White Paper
®
Using APEX II Differential I/O Standards in the Quartus II Software
Introduction
The APEXTM II device high-speed interface includes four I/O banks, each of which is comprised of 18 channels,
offering 36 differential input and 36 differential output channels, each running at up to 1 gigabit per second (Gbps).
The 72 input and output channels combine to offer 366-Gbps throughput. APEX II devices combine serialization,
deserialization, and frequency multiplication into one package, which allows them to transmit multiple bits of data
through a reduced number of differential transmission lines spanning large distances.
As demand for high-speed applications grows, the interface between systems becomes critical. The APEX II
high-speed interface offers four types of commonly applied high-speed I/O standards: LVDS, HyperTransportTM
technology, LVPECL, and PCML. This white paper will demonstrate how to use the Altera® Quartus® II software
version 1.1 to assign I/O standards to each I/O pin.
The following Altera documents provide information on APEX II device high-speed I/O standard features and
functions. These documents also explain how to take advantage of these standards to increase system efficiencies and
bandwidth.
■
■
■
Application Note 157 (Using CDS in APEX II Devices) describes the most common topologies, and how you can
apply the APEX II device’s unique clock-data synchronization (CDS) feature.
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices) provides information on the
APEX II device’s high-speed I/O standard features and functions.
Application Note 167 (Using Flexible-LVDS in APEX II Devices) describes the function, capabilities, and
implementation of the Flexible-LVDSTM buffer.
High-Speed Differential I/O Interface Operation
The APEX II device high-speed interface receives and transmits many bits of data through a reduced number of
differential transmission lines over distances greater than those that can be achieved with a single-ended (e.g., TTL or
CMOS) interface. The system receives the serial data and clock at its input pins. The high-frequency clock (internal)
shifts the serial data through the receiver’s deserializer shift register. The data is then driven out in parallel with the
low-frequency data clock. This same low-frequency clock can drive a global clock line to clock internal logic
elements (LEs). Figure 1 shows an example of an APEX II high-speed interface.
Figure 1. APEX II High-Speed Interface in ×10 Mode
Transmitter Circuit
Receiver Circuit
Serial
Register
Parallel
Register
Parallel
Register
Serial
Register
TrueDiff_TX01P
TrueDiff_TX01N
TrueDiff_RX01P
TrueDiff_RX01N
RXCLK_InP
RXCLK_InN
+
_
+
_
APEX II
Logic Array
xW
PLL
xW/J
X1
xW
PLL
G1
G2
G3
xW/J
X1
A-WP-APEXII/IOS-1.0
November 2001, ver. 1.0
1
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
High-Speed Differential I/O Pin Naming Convention
Table 1 helps you identify the differential I/O pin names. The receiver and transmitter channel names have a prefix of
TrueDiff followed by a receiver (RX) or transmitter (TX) designation. A range of numbers from 1 to 36 represents the
dual-purpose channels followed by a “p” (positive polarity) or a “n” (negative polarity).
Table 1. Differential Pin Naming Conventions
Pin Name
Function
TrueDiff_RX[1..36]p (1)
Positive receiver data pin
TrueDiff_RX[1..36]n (1)
Negative receiver data pin
TrueDiff_TX[1..36]p (1)
Positive transmitter data pin
TrueDiff_TX[1..36]n (1)
Negative transmitter data pin
RXCLK_IN1p
Positive clock input pin for receiver PLL1
RXCLK_IN1n (2)
Negative clock input pin for receiver PLL1
RXCLK_IN2p
Positive clock input pin for receiver PLL2
RXCLK_IN2n (2)
Negative clock input pin for receiver PLL2
TXCLK_OUT1P
Positive clock output pin for transmitter PLL1
TXCLK_OUT1n (2)
Negative Clock output pin for transmitter PLL1
TXCLK_OUT2p
Positive clock output pin for transmitter PLL2
TXCLK_OUT2n (2)
Negative clock output pin for transmitter PLL2
CLK[1..8]p
Positive dedicated terminal input for differential global clock
CLK[1..8]n (2)
Negative dedicated terminal input for differential global clock
CLKLK_FB[1..2]
Dual-purpose external feedback pin for general-purpose PLL1
CLKLK_OUT[1..2]
Dual-purpose external clock output pin for general-purpose PLL1
Notes to Table 1:
(1) Dual-purpose channels 1 through 36. If not used, these pins are regular I/O pins.
(2) Regular I/O pin when not used as a PLL input pin.
The dedicated clock pins (RXCLK_IN1p and RXCLK_IN2p) support the differential I/O pins and have negative
polarity pins (RXCLK_IN1n and RXCLK_IN2n) associated with them. Because the RXCLK_IN1n and
RXCLK_IN2n pins are dual-purpose, you can use them as general-purpose I/O pins when they are not used as
phase-locked loop (PLL) clock input pins. The PLL output pins (TXCLK_OUT1p and CLKTX_OUT2p) also support
the same convention as the dedicated clock pins.
Similar to other pins that have secondary functions (e.g., INIT_DONE), information on the dual-purpose differential
pins are displayed in the Quartus II Floorplan Editor. Figure 2, shows the differential clock pin naming convention.
Figure 2. Differential Clock Pin Naming Convention in the Quartus II Software
2
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Figure 3 shows the LVDS receiver in the Quartus II Floorplan Editor. The receiver data channel, represented by
TrueDiff_RX01p and TrueDiff_RX01n, feeds the dedicated serial-to-parallel converter.
Figure 3. Differential Pin Naming Convention in the Quartus II Software
The serial-to-parallel converter is shown by the filled rectangle adjacent to the input/output element (IOE) register
associated with each positive polarity LVDS data and clock pin.
The altlvds Megafunction
The altlvds megafunction implements a receiver (deserializer) or a transmitter (serializer). You can implement all
the differential I/O standards supported by APEX II devices using this megafunction. The differential I/O standards
use two wires carrying differential values to create a single channel. These wires are connected to two pins on an
APEX II device to create a single differential channel. The altlvds megafunction uses LVDS PLL circuitry for a
serializater/deserializer (SERDES).
Figures 4 and 5 show the symbols for the altlvds megafunction receiver and transmitter for one channel in 8×
mode with an input reference clock. Each module represents dedicated silicon present in APEX II devices as well as
the dedicated PLL that is used for clock multiplication and division.
Figure 4. The altlvds Megafunction Receiver Module Symbol
LVDS Receiver
rx_in[1..0]
rx_inclock
Inst 1
rx_out[15..0]
2 Channels, ×8
125 MHz
rx_outclock
rx_locked
APEX II Device
3
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Figure 5. The altlvds Megafunction Transmitter Module Symbol
LVDS Transmitter
tx_in[15..0]
2 Channels, ×8
100 MHz
tx_out[1..0]
tx_outclock
tx_locked
tx_inclock
Inst 1
CENTER_ALIGN: OFF
APEX II Device
The Quartus II software allows users to create VHDL or Verilog HDL design files with the Quartus II Text Editor (or
another standard text editor) and save them in the appropriate project directory. For both the receiver and transmitter,
AHDL function prototype (port name and order also apply to Verilog HDL) and VHDL component declaration
sample scripts are shown in Figures 6 through 8.
Figure 6. AHDL Function Prototype (Receiver)
FUNCTION altlvds_rx (rx_in[NUMBER_OF_CHANNELS-1..0], rx_inclock,
rx_CDS_EN, rx_pll_enable)
WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, REGISTERED_OUTPUT,
INCLOCK_PERIOD, CDS_MODE, INTENDED_DEVICE_FAMILY)
RETURNS (rx_out[DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1..0],
rx_outclock, rx_locked);
Figure 7. VHDL Component Declaration (Receiver)
COMPONENT altlvds_rx
GENERIC(NUMBER_OF_CHANNELS: NATURAL;
DESERIALIZATION_FACTOR: NATURAL;
REGISTERED_OUTPUT: STRING := "ON";
INCLOCK_PERIOD: NATURAL;
CLOCK_SETTING: STRING := "UNUSED";
CDS_MODE: STRING := "UNUSED";
INTENDED_DEVICE_FAMILY: STRING := "APEX20KE");
PORT (rx_in: IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
rx_inclock: IN STD_LOGIC;
rx_CDS_EN: IN STD_LOGIC := ’0’;
rx_pll_enable: IN STD_LOGIC := ’1’;
rx_out: OUT
STD_LOGIC_VECTOR(DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
rx_outclock, rx_locked: OUT STD_LOGIC);
END COMPONENT;
4
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Figure 8. AHDL Function Prototype (Transmitter)
FUNCTION altlvds_tx (tx_in[DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1..0], tx_inclock,
sync_inclock, tx_pll_enable) WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR,
REGISTERED_INPUT, MULTI_CLOCK, INCLOCK_PERIOD, OUTCLOCK_DIVIDE_BY, CENTER_ALIGN_MSB,
INTENDED_DEVICE_FAMILY) RETURNS (tx_out[NUMBER_OF_CHANNELS-1..0], tx_outclock, tx_coreclock,
tx_locked);
VHDL Component Declaration ( Transmitter )
COMPONENT altlvds_tx
GENERIC (NUMBER_OF_CHANNELS: NATURAL;
DESERIALIZATION_FACTOR: NATURAL;
OUTCLOCK_DIVIDE_BY: NATURAL := 0;
REGISTERED_INPUT: STRING := "ON";
MULTI_CLOCK: STRING := "OFF";
INCLOCK_PERIOD: NATURAL;
CLOCK_SETTING: STRING := "UNUSED";
CENTER_ALIGN_MSB: STRING := "UNUSED";
INTENDED_DEVICE_FAMILY: STRING := "APEX20KE");
PORT (tx_in: IN STD_LOGIC_VECTOR (DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
tx_inclock: IN STD_LOGIC;
sync_inclock: IN STD_LOGIC := ’0’;
tx_pll_enable: IN STD_LOGIC := ’1’;
tx_out: OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
tx_outclock, tx_coreclock, tx_locked: OUT STD_LOGIC);
END COMPONENT;
The altlvds megafunction receiver and transmitter input and output port parameters are described in
Tables 2 and 3. Table 4 lists the parameters that are used to configure the altlvds megafunction.
Table 2. Receiver Input & Output Ports
Port Name
Required
Description
LVDS input data port
Comments
rx_in[ ]
Yes
The input port is [NUMBER_OF_CHANNELS-1..0] wide. After
deserialization, rx_in[n-1] is the first bit received and
rx_in[0] is the last bit received for channel one; for channel
two, rx_in[2n-1] is the first bit received and rx_in[n] is
the last bit received. For more information on bit order, see
Application Note 166 (Using High speed I/O Standards in
APEX II Devices). For APEX II devices, you can apply the
CDS Clock Phase logic option to the input pins that drive the
rx_in port.
rx_inclock
Yes
LVDS reference input clock
rx_cds_ena
No
Specifies whether to activate
calibration mode
rx_pll_enable
No
Enable control for the LVDS PLL This pin enables the LVDS PLLs.
rx_out[ ]
Yes
Deserialized data signal
rx_outclock
No
Internal reference clock
rx_locked
No
Gives the status of the LVDS
PLL
CDS enables the pin. For more information on the
rx_cds_ena port, refer to Application Note 157 (Using CDS
in APEX II Devices).
The output port is [DESERIALIZATION_FACTOR ×
NUMBER_OF_CHANNELS-1..0] wide.
When the PLL is locked, this signal is VCC. When the PLL fails
to lock, this signal is GND.
5
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Table 3. Transmitter Input & Output Ports
Port Name
Required
Description
Comments
Input port is [DESERIALIZATION_FACTOR ×
NUMBER_OF_CHANNELS-1..0] wide.
tx_in[ ]
Yes
Input data
tx_pll_enable
No
Enables control for the LVDS
PLL
tx_out []
Yes
Serialized LVDS data signal
rx_locked
No
Provides the status of the LVDS When the PLL is locked, this signal is VCC. When the PLL fails
PLL
to lock, this signal is GND.
Output port is [NUMBER_OF_CHANNELS-1..0] wide. After
deserialization, tx_out[n-1] is the first bit transmitted and
tx_out[0] is the last bit transmitted for channel one; for
channel two, tx_out[2n-1] is the first bit transmitted and
tx_out[n] is the last bit transmitted. For more information on
bit order, see Application Note 166 (Using High-Speed I/O in
APEX II Devices).
Table 4. The altlvds Megafunction Parameters
Parameter
Type
Required
Description
Integer
Yes
Specifies the number of LVDS channels.
DESERIALIZATION_FACTOR Integer
Yes
Specifies the number of bits per channel. The values are 4-10 for APEX II
devices. The value of the INCLOCK_PERIOD parameter is between
125 MHz and 1,000 MHz/DESERIALIZATION_FACTOR.
NUMBER_OF_CHANNELS
REGISTERED_INPUT
String
No
Indicates whether the tx_in[] and tx_outclock ports should be
registered. The values are "ON" and "OFF". If omitted, the default is "ON".
INCLOCK_PERIOD
Integer
Yes
Specifies the period or frequency of the input clock. The default time unit is
picoseconds (ps), however you can use other time units. In AHDL designs
only, strings (such as 50.5 MHz) are acceptable.
INCLOCK_BOOST
Integer
No
The effective clock period used to sample output data. The values are
1, 2, and 4 through 10.
INTENDED_DEVICE_FAMILY String
No
This parameter is used for modeling and behavioral simulation purposes.
Create the PLL with the MegaWizard® Plug-in Manager (Tools menu) to
calculate the value for this parameter.
CENTER_ALIGN_MSB
String
No
Aligns the most significant bit (MSB) to the falling edge of the clock instead
of the rising edge. You can use this parameter to generate a
center-aligned clock. The values are "ON", "OFF", and "UNUSED". If
omitted, the default is "UNUSED". This parameter is available for APEX II
devices only.
CDS_MODE
String
No
The values are "SINGLE_BIT", "MULTIPLE_BIT", and "UNUSED". If
omitted, the default is "UNUSED". When this parameter is set to
"SINGLE_BIT", the CDS circuitry will expect a bit pattern of 00001111,
which can correct for clock skew up to 50% of one clock edge. When this
parameter is set to MULTIPLE_BIT, the deskew circuitry expects a pattern
of 01010101, which can correct for any clock skew but requires circuitry
to align data. This parameter is available for APEX II devices only.
The MegaWizard Interface
The MegaWizard Plug-In Manager helps create or modify design files containing custom megafunction variations
that you can then instantiate in a design file. These custom megafunction variations are based on Altera-provided
megafunctions, including library of parameterized module (LPM) functions. The MegaWizard Plug-In Manager
prompts you for the values you want to set for parameters or which optional ports you want to use.
You can start the MegaWizard Plug-In Manager in one of the following ways:
■
■
■
6
Choose the MegaWizard Plug-In Manager command (Tools menu).
Click MegaWizard Plug-In Manager in the Symbol dialog box (Insert menu) when working in the Block Editor.
Start the stand-alone version of the MegaWizard Plug-In Manager by typing the following at the command
prompt: qmegawiz r
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
The MegaWizard Plug-In Manager takes a step-by-step approach to generating customized differential transmitter
and receiver modules. Each page of the MegaWizard Plug-In Manager allows you to select from a set of customizable
features that tailor the modules to the needs of the design.
Figure 9 shows the third page of the altlvds megafunction when instantiating an LVDS transmitter.
Figure 9. Page 3 of the altlvds Transmitter the MegaWizard Plug-In Manager
Figure 10 shows the third page of the altlvds megafunction when instantiating an LVDS receiver.
Figure 10. Page 3 of the altlvds Receiver MegaWizard Plug-In Manager
The option descriptions for Figures 9 and 10 are listed below:
■
■
■
Device family – Select the device type from the list.
Number of channels – Specify the number of differential channels used in the design by either typing or selecting
from the list (up to a maximum of 18 channels for APEX II devices). This feature simplifies the complexity of
the design because you only need to instantiate one transmitter or receiver module to represent multiple differential channels.
Deserialization factor – This option specifies the number of bits per channel. You can either type or select 4, 5, 6,
7, 8, 9, or 10 from the list.
7
Altera Corporation
■
■
Using APEX II Differential I/O Standards in the Quartus II Software
Inclock Boost Factor (W) – This option is the effective clock period used to sample output data. You can either
type or select 1, 2, 4, or 10 from the list.
Clock frequency or clock period – This option specifies either the clock frequency or period of the LVDS input
clock.
Figure 11 displays the fourth page of the altlvds megafunction when instantiating an LVDS transmitter.
Figure 11. Page 4 of the altlvds Transmitter MegaWizard Plug-In Manager
The option descriptions for Figure 11 are listed below:
■
■
■
■
Use a synchronization clock – Activates the synchronization clock for the transmitter. If this option is activated,
the synchronization clock must have the same frequency and phase as the transmitter clock to avoid hold-time
violations. To use the synchronization clock, set the registered _input option by turning on Register inputs and
Use a synchronization clock.
Use the tx_pll_enable input port – Enables optional input port for the transmitter, allowing control of the LVDS
PLL.
Register inputs – If the signals are not registered in the adjacent MegaLABTM structure, then turn on register
inputs.
Use the tx_locked output port – Enables the use of the locked pin for the transmitter. When the PLL locks onto
the incoming clock and generates an internal clock, the locked signal is driven high. The signal remains high as
long as the input clock remains within specification.
Figure 12 displays the fourth page of the altlvds megafunction when instantiating an LVDS receiver.
8
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Figure 12. Page 4 of the altlvds Receiver MegaWizard Plug-In Manager
The option descriptions for Figure 12 are listed below:
■
■
■
■
■
■
Use the rx_pll_enable input port – Enables optional input port for the receiver, allowing control of the LVDS
PLL.
Register outputs – If the signals are not registered in the adjacent MegaLAB structure, then turn on register
outputs.
Use the rx_locked output port – Enables the use of the locked pin for the receiver. When the PLL locks onto the
incoming clock and generates an internal clock, the locked signal is driven high. The signal remains high as long
as the input clock remains within specification.
Do not use CDS or use pre-programmed CDS – The default clock phase will be used. You can change the setting
to -180°, -90°, 90°, or 180° from the assignment organizer for each receiver differential pair. Figure 13 shows
how to set the pre-programmed CDS.
Use Single-Bit mode – The deskew circuitry will expect a bit pattern of 00001111, which can correct for clock
skew up to 50% of one clock edge.
Use Multi-Bit mode – The CDS circuitry will expect a pattern of 01010101, which can correct for any clock
skew and requires circuitry to align data.
1The CDS section allows the user to select one of the three types of CDS.
Figure 13. Assignment Organizer Page Option for Individual Nodes Assignment
9
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
MegaWizard Example
Figure 14 shows an altlvds receiver module, including two channels generated by the MegaWizard Plug-In
Manager, with an input frequency of 100 MHz and a deserialization and boost factor (W) of 10. The rx-out signals
are 20 bits wide (two channels × SERDES factor of 10). In this example, inputs are registered and rx_locked is
utilized for simulation verification. Also, you cannot connect rx_outclock directly to an output pin.
Figure 14. altlvds Receiver Module with Two Channels
LVDS Receiver
rx_in[1..0]
rx_inclock
rx_out[19..0]
2 Channels, ×10
100 MHz
Inst 1
rx_outclock
rx_locked
APEX II Device
Figure 15 shows an altlvds transmitter module, including two channels generated by the MegaWizard Plug-In
Manager, with an input frequency of 100 MHz and a deserialization and boost factor (W) of 10. The tx_in signals
are 20 bits wide (two channels × SERDES factor of 10). In this example, inputs are registered and rx_locked is
utilized for simulation verification.
Figure 15. altlvds Transmitter Module with Two Channels
LVDS Transmitter
tx_in[19..0]
2 Channels, ×10
100 MHz
tx_out[1..0]
tx_outclock
tx_locked
tx_inclock
Inst 1
CENTER_ALIGN: OFF
APEX II Device
HDL Files
Figure 16 shows the transmitter and receiver VHDL example code. These examples instantiate the LVDS modules
and connect them to input and output pins. You can generate these Verilog HDL files directly from the Quartus II
software by performing the following steps:
1.
With the project open in the Quartus II software, choose Create HDL Design for Current Design (Tools menu).
2.
Select VHDL or Verilog HDL and click OK.
The Quartus II software automatically generates the required files and places them in the project directory.
The LVDS receiver is a two-channel module operating in ×10 mode with an input clock of 100 MHz. The receiver’s
output clock is fed out of the module in ×10 mode through the tx_outclock pin. You can monitor the PLL status
from the tx_locked pin.
The LVDS transmitter is a two-channel module operating in ×10 mode with an input clock of 100 MHz. The
transmitter’s output clock is fed out of the module in ×10 mode through the tx_outclock pin. You can monitor the
status of the PLL from the tx_locked pin.
10
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Figure 16. Transmitter & Receiver VHDL Example Code
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Tx2Rx IS
port
(
rx_inclock : IN STD_LOGIC;
rx_in : IN STD_LOGIC_VECTOR(1 downto 0);
tx_in : IN STD_LOGIC_VECTOR(19 downto 0);
rx_locked : OUT STD_LOGIC;
tx_outclock : OUT STD_LOGIC;
tx_locked : OUT STD_LOGIC;
rx_out : OUT STD_LOGIC_VECTOR(19 downto 0);
tx_out : OUT STD_LOGIC_VECTOR(1 downto 0)
);
END Tx2Rx;
ARCHITECTURE bdf_type OF Tx2Rx IS
component tx
PORT(tx_inclock : IN STD_LOGIC;
tx_in : IN STD_LOGIC_VECTOR(19 downto 0);
tx_outclock : OUT STD_LOGIC;
tx_locked : OUT STD_LOGIC;
tx_out : OUT STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component rx
PORT(rx_inclock : IN STD_LOGIC;
rx_in : IN STD_LOGIC_VECTOR(1 downto 0);
rx_outclock : OUT STD_LOGIC;
rx_locked : OUT STD_LOGIC;
rx_out : OUT STD_LOGIC_VECTOR(19 downto 0)
);
end component;
signal rx_outclock : STD_LOGIC;
b2v_inst : tx
PORT MAP(tx_inclock => rx_outclock,
tx_in => tx_in,
tx_outclock => tx_outclock,
tx_locked => tx_locked,
tx_out => tx_out);
b2v_inst1 : rx
PORT MAP(rx_inclock => rx_inclock,
rx_in => rx_in,
rx_outclock => rx_outclock,
rx_locked => rx_locked,
rx_out => rx_out);
END;
11
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Quartus II Reports
The Quartus II software reports differential usage in the compilation report file (.rpt). The report file documents all
information pertaining to LVDS resource usage and placement in the APEX II device under the following categories:
■
■
■
■
■
All Package Pins
Control Signals
Global & Other Fast Signals
LVDS
ClockLockTM Circuitry
All Package Pins
The All Package Pins category of the report file indicates the function and location of all package pins. LVDS pins
are displayed with their names and pin numbers.
The Quartus II software adheres to the previously discussed banking rules and will not place non-LVDS outputs in
LVDS-enabled banks. In such configurations, the design yields a no-fit, indicating that these non-LVDS outputs are
illegally placed.
f For more information on using I/O standards, refer to Application Note 117 (Using Selectable I/O Standards
in APEX 20KE, APEX 20KC & MAX 7000B Devices).
Control Signals
The Control Signals category reports the LVDS control signals that are present in the design, such as input clocks
and PLL output clocks. PLL output clocks are denoted as either lvdspllrx_1 or lvdspllrx_2.
Global & Other Fast Signals
The Global & Other Fast Signals category displays the globally routed signals in the design. When LVDS is used,
only the PLL-generated clocks and the synchronization clocks are routed globally. The number of fan-out nodes for
the global signal is also displayed.
LVDS
The LVDS category reports LVDS usage in the design. The instance name is displayed along with its function and
deserialization factor. Both PLL output clocks for the LVDS modules are also shown. The LVDS category is omitted
when LVDS is not used in the APEX II device.
ClockLock Category
The ClockLock category of the report file gives the specifications of each PLL used. The input frequency is
indicated, as well as the various resulting clock frequencies, after multiplication by the deserialization factor.
Synthesis with Third-Party Tools
To synthesize the design successfully in third-party tools such as Synplify®, FPGA Compiler II, FPGA Express, and
LeonardoSpectrumTM, the you must treat the LVDS design component as a black box. By declaring the module a
black box, synthesis tools will refrain from synthesizing the module. However, the EDIF Output File (.edo) or
Verilog Quartus II mapping file (.vqm) will make the correct port connections. When the netlist file is brought into
the Quartus II software, native synthesis on the black-boxed module is automatically performed. The MegaWizard
Plug-In Manager must first generate the LVDS module, which involves specifying the name of the module and the
ports that are used.
The Quartus II software must be configured so that it recognizes the EDO or VQM netlist file from the third-party
synthesis tool. The synthesis tool can be selected from the EDA Tool Settings dialog box (Project menu) in the
12
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Quartus II software. For more information regarding the Quartus II software’s integration with third-party tools, see
the Altera web site at http://www.altera.com.
Simulation in the Quartus II Software
The Quartus II development tools help you to conveniently and efficiently simulate the LVDS design. You can also
create vector waveform files (.vwf), which are used as inputs to the native simulation tool.
The simulation model for the LVDS receiver is essentially a serialization shift register that is driven by an LVDS data
channel and clocked by an LVDS PLL multiplied by the multiplication value. The shift register drives a bank of data
registers clocked by the original clock.
Figure 17 shows the results of an example functional simulation of an LVDS receiver. The receiver is operating at
100 MHz with the synchronization clock activated and a deserialization factor of 10. The parallel data assigned to the
input pins are varied to simulate real-world data transmission.
Figure 17. Example Functional Simulation Waveform of LVDS Receiver
The LVDS transmitter module is the inverse of the LVDS receiver. A data register is driven by internal parallel data
signals and clocked by the original LVDS clock. It then loads a shift-register that drives the LVDS output pin and is
clocked by the multiplied output of the LVDS PLL. For more information on simulation in the Quartus II software,
see Quartus II Help.
Figure 18 shows the results of an example functional simulation of an LVDS transmitter. The transmitter is operating
at 100 MHz with the synchronization clock activated and a serialization factor of 10. The parallel data assigned to the
input pins were varied to simulate real-world data transmission.
Figure 18. Example Functional Simulation Waveform of the LVDS Transmitter
The locked pin Tx_Lock remains high as long as the input frequency is valid. The input clock Tx_In_CLK and the
synchronization clock must have identical phase and frequency for the module to function correctly. The clocks must
also have the same frequency specified in the design files, or the simulator will warn that the PLL was unable to lock
onto the incoming clocks.
The incoming data Tx_IN is synchronized with the input clock Tx_In_CLK. The output data TX_OUT_Serial is
synchronized with the output clock Tx_CLK_OUT that has the same frequency as the input clock. The output clock
has the same frequency as the input clock (not the internally multiplied clock) because only the one version of the
PLL-generated clock is fed out. The output data transitions 10 times within one period of the one clock, indicating
that the deserialization factor is 10.
13
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Synthesis with Third-Party Tools
To synthesize the design successfully in third-party tools such as Synplify, FPGA Compiler II, FPGA Express, and
LeonardoSpectrum, you must treat the LVDS design component as a black box. By declaring the module a black box,
synthesis tools will refrain from synthesizing the module. However, the EDO or VQM will make the correct port
connections. When the netlist file is brought into the Quartus II software, native synthesis on the black-boxed module
is automatically performed. The MegaWizard Plug-In Manager must first generate the LVDS module, which involves
specifying the name of the module and the ports that are used.
Clock Data Synchronization
Clock-to-data skew is generally due to trace layout, capacitive loading of traces, variations in threshold voltages, or
transmission-line terminations. The APEX II high-speed interface offers a unique solution for clock-to-data
synchronization. The CDS solution incorporated in the APEX II device family gives you superior design flexibility.
CDS synchronizes the incoming data stream to the system clock regardless the skew between the clock signal and
data stream. It can compensate for as much as 50% of skew one in single-bit mode and for unlimited skew in multi-bit
mode. For more details about CDS in the APEX II device family, refer to Application Note 157 (Using CDS in APEX
II Devices).
The APEX II device family offers three types of clock-to-data synchronization solutions:
■
■
■
Fixed or Pre-Programmed
Single-Bit
Multi-Bit
The following sections describe how to apply these synchronization modes in the Quartus II software.
Pre-Programmed CDS in the Quartus II Software
In the pre-programmed CDS mode, you may select one of five phases of the clock. You can change the default clock
phase setting to -180°, -90°, 90°, or 180° from the Assignment Organizer (Processing menu) for each receiver
differential pair. The pre-programmed CDS design corrects clock-data skew of up to +/- 50% of the input bit period.
Single- & Multi-Bit CDS in the Quartus II Software
In single-bit synchronization, a known data pattern is transmitted to the receiver device(s) for the minimum of three
clock cycles, while the CDS-enable pin is held high. The single-bit CDS design also corrects clock-data skew of up to
+/-50% of the input bit period, and byte alignment is determined automatically when single-bit CDS is performed.
When using multi-bit synchronization, an alternating one and zero data pattern is transmitted to the receiver device(s)
for a minimum of three clock cycles while the CDS-enable pin is held high. The multi-bit CDS function corrects for
any clock-data skew; however, an additional byte-alignment circuit is required to determine the byte boundaries.
The following step-by-step instructions show how to implement the single- and multi-bit CDS feature in APEX II
devices using the Quartus II software. The example steps show an LVDS receiver configured for single- and multi-bit
CDS receiving 8-bit serial data at 800 megabits per second (Mbps) with a 100-MHz input clock. The process is
separated into three steps:
■
■
■
14
Open the New Project Wizard
Build an LVDS Receiver with the MegaWizard Plug-In Manager
Compile the Design
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
Open the New Project Wizard
1.
Choose New Project Wizard (File menu), and specify a new file name and directory.
2.
Ensure that the EP2A15F672C7 device is selected by using the following steps:
a.
Choose Compiler Settings (Processing menu) and click the Chips & Devices tab. The Compiler Settings
dialog box is shown in Figure 19.
Figure 19. Compiler Settings Dialog Box.
b.
c.
Select APEX II from the family list. Click Yes if you get a warning message that the device family has
changed.
Under Target device, select Specific device selected in ‘Available Devices’ list. In the Available devices
list, select EP2A15F672C7. Click Apply and OK.
Build an LVDS Receiver with the MegaWizard Plug-In Manager
3.
Choose New (File menu), and select Block Diagram/Schematic File, as shown in Figure 20. Click OK.
Figure 20. New File Selection Window
15
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
4.
Choose MegaWizard Plug-In Manager (Tools menu) then select Create a new custom megafunction
variation. Click Next.
5.
In the MegaWizard Plug-In Manager window, expand the gates folder and highlight ALTLVDS. Select AHDL
output and specify the output file name. Click Next.
6.
Set a single channel LVDS receiver which will deserialize by a factor of 8 to generate 8-bit words to the internal
logic. Set the input reference clock to 100 MHz by performing the following steps (see Figure 21):
a.
b.
c.
d.
e.
f.
Under This module acts as an, select LVDS receiver.
In the device family list, select APEX II.
Select or type 1 in the number of channels list.
To deserialize, set the deserialization factor to 8.
To match the deserialization factor of 8, set the inclock boost factor (W) to 8.
Under Specify the input clock rate by, select clock frequency and type 100 in the MHz box.
Figure 21. MegaWizard Plug-In Manager Page 1 of 3
7.
Click Next to proceed to Page 2 of the of the MegaWizard Plug-In Manager (see Figure 22). In this dialog box,
select the following ports:
a.
b.
c.
Under Output Ports, turn on Register outputs.
For Single-Bit CDS, turn on the Use Single-bit mode under CDS. For Multi-Bit CDS, turn on the Use
Multi-bit mode under Clock Data Synchronization (CDS).
Notice that the required rx_cds_ena signal has appeared in the symbol on the left because you have
chosen to use CDS.
Figure 22. MegaWizard Plug-In Manager page 2 of 3
16
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
8.
Click Next, then click Finish.
9.
Click OK. Instantiate and connect cds_rx in yourfilename.bdf by double-clicking the schematic diagram and
selecting it from the project library. Click the left mouse button to put down the symbol. Figure 23 shows the
receiver function configured for Multi-Bit CDS and connected to the byte alignment circuit.
Figure 23. Receiver Configured for Multi-Bit CDS and Connected to the Byte-Alignment Circuit.
Output (For Simulation Purposes)
CDS Receiver
rx_in[0]
rx_cds_ena
rx_inclock
Single Channel, ×8
100 MHz
byte_align
rx_out[7..0]
rx_outclock
received_data[7..0]
aligned_data[7..0]
clk
byte_align_done
core[7..0]
byte_align_done
align
reset
Inst 1 DDS SINGLE_BIT
APEX II Device
inst 1
Byte-Alignment Logic
Align
Reset
10. Save the file.
Compile the design
11. Click the right-arrow button to compile design.
Byte-Alignment Implementation
The multi-bit byte alignment circuit is responsible for finding the byte boundaries of the parallel data at the output of
the SERDES circuit. The circuit utilizes hex A1 (10100001Binary) as its alignment pattern. Thus, the circuit is
implemented in logic elements.
The byte alignment circuit is available on the Altera web site at http://www.altera.com in both VHDL and Verilog
HDL format. A detailed description of the circuit is also available in Application Note 157 (Using CDS in APEX II
Devices).
To implement the byte-alignment circuit in a design, a systematic approach, such as the following, is recommended.
1.
Use Altera’s Quartus II MegaWizard Plug-In Manager to build a receiver block, as described in “Build an LVDS
Receiver with the MegaWizard Plug-In Manager” on page 15.
2.
Perform multi-bit CDS by asserting the CDS enable pin to a high state for minimum of three clock cycles, and
then de-assert the pin.
The system design is now ready for byte alignment. With the device programmed with the byte alignment module,
perform the following steps:
3.
Set the module’s reset input pin to high. This pin is the module’s input pin which clears the byte-alignment logic.
4.
Assert the align pin to high for one clock cycle. This signal commands the byte-alignment logic to look for
hexadecimal pattern A1 to perform byte alignment. An output signal from the byte-alignment circuit goes high
when the hexadecimal pattern A1 is found.
17
Altera Corporation
Using APEX II Differential I/O Standards in the Quartus II Software
The byte-alignment circuit is designed to detect the incoming A1 pattern and reconstruct the misaligned data pattern.
Upon completion of this procedure, an align_done signal changes state. You can use the low-to-high transition of
align_done signal as a flag for the system logic to begin receiving user data.
Byte-Alignment Simulation
Figure 24 shows the output of the Quartus II vector simulation. For simulation purposes, the hex A1 and the
proceeding data were misaligned by 4 bits, then the byte-align signal was asserted high for one clock cycle. The
circuit detected the hexadecimal A1 misalignment, corrected for the misalignment, and reported the alignment
completion by setting the output byte_align_done to a high state. You may repeat the alignment at any time
during the operation by asserting the align pin to high.
Figure 24. Output of the Quartus II Vector Simulation using Byte-Alignment Circuit.
Conclusion
The Quartus II software enhances the APEX II device’s high-speed I/O and high-performance PLL capability.
Working together, APEX II devices and the Quartus II software not only increase system efficiency and bandwidth,
they provide a high-performance system solution in a fraction of the time required by an application-specific
integrated circuit (ASIC). APEX II devices and the Quartus II software minimize the risks associated with ASICs,
speed time-to-market, and maximize system functionality and performance.
®
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Copyright © 2001 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific
device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the
trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of
their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights,
and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard
warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing
by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services
18