HardCopy Stratix Overview
Introduction
Altera’s HardCopy™ devices are the industry’s only low-cost mask-programmed devices with
ASIC-level performance, price, and features that customers can take to production virtually riskfree. Following the successful introduction of the HardCopy APEX™ devices, Altera’s secondgeneration HardCopy device family is based on the high-performance Stratix™ FPGAs. Altera’s
HardCopy Stratix™ devices maintain the same features as the successful Stratix FPGAs, but
offer on average a 50 percent performance increase and an on-average 40 percent decrease in
power consumption compared to equivalent Stratix FPGAs. In addition, the Quartus® II version
3.0 design software supports all HardCopy devices, enabling design engineers to leverage the
increase in performance and lower power consumption with the same easy-to-use tools used to
design their FPGA.
Traditionally, ASICs have been the ideal solution for system architects designing high-volume,
high-performance applications. However, designing ASICs requires expensive design tools,
results in high development costs, and involves significant overall risk when bringing products to
market in a timely manner. With Altera® HardCopy devices, customers use the same FPGA
design tools to migrate their FPGA designs to HardCopy devices. Non-recurring engineering
(NRE) charges are minimal, and production devices are available in approximately 18 weeks
once the design is final.
HardCopy Devices—ASIC Gain without the Pain
Altera’s HardCopy devices preserve the architecture of the FPGA with the programmability
removed. As a result, the die size of a HardCopy device is 60 to 70 percent smaller than the
equivalent FPGA. This enables Altera to provide a lower cost, higher performance, and lower
power mask-programmed device. HardCopy devices are built on the same process technology
and include all of the same embedded features as their FPGA counterparts, enabling seamless
migration of the FPGA designs.
HardCopy Stratix Key Features
Altera’s HardCopy Stratix devices take the industry-leading Stratix device family to highvolume production in the shortest possible time with guaranteed first-time success. With the
perfect mix of features, density, and performance, Altera’s HardCopy Stratix devices are ideal
for high-performance, high-volume applications in the networking, wireless communication,
high-end consumer electronics, and industrial markets. Notable HardCopy Stratix features
include:
•
•
•
An average 50 percent increase in performance and 40 percent lower power consumption
compared to Stratix FPGAs.
Density range from 25,660 to 79,040 logic elements and up to 5.6 Mbits of embedded
memory to support highest density FPGA designs
Built on the same 0.13-µm, all-layer copper process technology as Stratix FPGA at the
same 1.5-V core voltage
•
Pin compatibility with Stratix FPGAs to support drop-in replacement for seamless
migration
For a complete description of HardCopy Stratix device features, please visit the Altera web site
at www.altera.com.
Relentless Attention to Cost
Based on customer feedback, Altera has refined the HardCopy Stratix offering and made careful
trade-offs to minimize die size and cost. Select HardCopy Stratix devices have slightly fewer MRAM blocks than their FPGA counterparts (as highlighted in Table 1). HardCopy Stratix devices
are only offered in packages that best fit the profile for high-volume, cost-sensitive applications.
Table 1: HardCopy Stratix Device Features
Logic
Elements
(LEs)
M512
Blocks
M4K
Blocks
M-RAM
Blocks
Total
RAM
Bits
DSP
Blocks
PLLs
Max.
User
I/Os
HC1S25F672
25,660
224
138
2
1,944,576
10
6
473
HC1S30F780
32,470
295
171
2
2,137,536
12
6
597
HC1S40F780
41,250
384
183
2
2,244,096
14
6
615
HC1S60F1020
57,120
574
292
6
5,215,104
18
12
773
HC1S80F1020
79,040
767
364
6
5,658,048
22
12
773
Device
Package
672-pin
FineLine BGA®
780-pin
FineLine BGA
780-pin
FineLine BGA
1,020-pin
FineLine BGA
1,020-pin
FineLine BGA
Quartus II Design Software
Altera’s Quartus II version 3.0 design software is the industry’s only design tool to offer a
unified design flow for the development of both FPGAs and mask-programmed devices.
For the first time, design engineers can now use the same low-cost, easy-to-use FPGA design
tools to design all low-cost, high-performance HardCopy devices. With the Quartus II design
software, system architects can predict the HardCopy Stratix device performance and power
consumption to fully leverage these two important benefits in their design. In addition, the
Quartus II software includes many features for the HardCopy devices:
• HardCopy Stratix Timing Models and Floorplan – Provides the best estimation of the
design’s performance in a HardCopy device by giving designers a view of the actual design
placement in the HardCopy device.
• HardCopy Design Assistant – Checks that the design satisfies industry-standard design
rules to facilitate the seamless migration of the FPGA design to equivalent HardCopy device.
• HardCopy Files Wizard – Generates the entire design database, at the push of a button, as
required by Altera’s migration process.
For a complete description of Quartus II version 3.0 design software features, please visit the
Altera web site at www.altera.com.
Pricing, Packaging, & Availability
The HardCopy Stratix device family includes five members ranging in density from 25,660 to
79,040 LEs. All devices are available in FineLine BGA® packages. Customer designs will be
accepted starting in Q3. Pricing is a function of package option, device performance, and volume.
Future volume pricing will range from $25 to $120.