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Reed Solomon Decoder Minicore
Introduction
The Altera® Reed-Solomon decoder minicore creates a very small, area efficient implementation for lower
throughput applications. The core remains relatively constant with different parameters, which are supported by the
parameterized microcode that is generated by an included utility.
The Reed-Solomon decoder minicore requires about 400 LCs, and has a typical throughput of 2 to 10 Mbps.
Ports and Parameters
The parameters are all entered into the RSMINIAB.EXE utility. This is described further in the section, RSMINIAB
Core Complilation.
Table 1 describes the parameters.
Table 1. Parameters
Parameter
Description
(M-1)
N
The number of symbols in the codeword. This can range from 5 to a maximum of 2
greater than R.
R
The number of check symbols in the codeword, which can range from 4 to N – 1, with a maximum of 40.
M
The number of bits per symbol, which can range from 4 to 8.
Field
The core can support any valid field polynomial for M. Valid field polynomials can be found using the
FIELD.EXE utility.
Genstart
Defines the first root of the generator polynomial. It can range from 0 to N – R – 1.
, but must always be
Table 2 descibes the input signals and Table 3 describes the output signals.
Table 2. Input Signals
Signal
Description
SYSCLK
The main system clock.
RESET
The entire decoder is asynchronously reset when RESET is asserted high, and decoding of a new block can
start.
ENABLE
The operation of the decoder is enabled when ENABLE is asserted high. When it is low, all processing is
stopped. This signal must be kept low when the core is being loaded with the input codeword. Once loading is
complete, it is asserted high to begin the decoding process.
LOAD
When high, the value on the RSIN[] bus is written to the internal data space addressed by the RSADD[] bus.
It must be kept low unless the RSIN[] and RSADD[] busses contain valid load data.
RSIN[8..1]
This 8-bit bus is the input bus for the symbols of the input codeword when they are written into the core. If M is
less than 8, the input values must occupy the lower M bits of the RSIN[] bus.
RSADD[8..1]
This 8-bit bus is used to address the internal data memory, for both reading and writing of the received and
decoded codewords, respectively.
WP-RSDECODER-1.0
Date: June 2002
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Reed-Solomon Decoder Minicore
Table 3. Output Signals
Signal
Description
RSOUT[8..1]
This bus contains the output data
DONE
This signal is asserted when the core has completed decoding of the codeword, after which the decoded data
can be read out of the core.
DECFAIL
This signal is asserted when the core has detected that there are too many errors in the received codeword,
and a decode is not possible.
RSMINIAA Core Compilation
The parameters for the core, which specify the code supported and therefore the throughput, are entered with the
RSMINIAB.EXE utility. If the utility is called without a parameter list, or an incomplete one, it responds with a list
of expected parameters:
>RSMINIAB <return>
Decoder Parameters
N : (message length)
R : (number of check symbols)
M : (field size)
Field : (field polynomial)
Genstart : (first root of the generator polynomial)
When run with a complete and correct parameter list, the utility generates the following files:
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DRSA.MIF
PXAA.MIF
INV.MIF
EVNUM.MIF—(these four files are used to specify the core behavior)
RSMINI.INC — (sets compile time parameters of the core)
RSMINI.VEC—(Altera simulation file for the core)
The core will be in the range of 400 LCs, for particular compilation options setting. For identical field widths (the M
parameter), the core size remains the same size, although the performance changes.
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Reed-Solomon Decoder Minicore
Compiling the Core
The core is at its smallest size and best performance when it is compiled with Register Packing set to on in the
MAX+PLUS® II software. Also set Global Project Logical Synthesis to normal, with Carry Chains set to
manual and Cascade Chains set to manual.
With the parameters N = 177, R = 12, M = 8, field = 285, and genstart = 0, the core compiles to 435 LCs and 3
EABs in an Altera EPF10K30ETC144-1 device. The fMAX is 50 MHz.
Reducing the field size to 6 bits, the core is compiled again with N = 55, R = 16, M = 6, field = 91, and genstart
= 0, results in 402 LCs and 3 EABs in the same device.
RSMINIAA Core Performance
As the decoding operation is microcoded for a relatively constant architecture, the throughput of the core depends on
N and R.
As a rough guide, the number of clock cycles required for a decoding operation is:
Cycles = (71+6.5N)R + 6.6R 2
The throughput can then be calculated:
Throughput = (N * M)/Cycles * fMAX Mbps
Taking the DVB standard (204,188) as an example at 50 MHz, gives:
Cycles = 24041
Throughput = 3.4 Mbps.
RSMINIAA Core Verification
The core can very easily be verified in the Altera environment, by using the testcase generated by the
RSMINIAB.EXE utility.
The testcase is in the form of an Altera vector file. To simulate, open the MAX+PLUS II software, in the simulator
window select Inputs/Outputs (File menu) to point to the RSMINI.VEC file that was created in the directory where
RSMINIAB.EXE is. The simulator converts the *.VEC file into a *.SCF file.
The simulator file starts with inputing an error free Reed-Solomon codeword into the core. The symbols can be
edited to insert errors, if desired. When the core simulation is run, the decoder asserts DONE, when it has completed
decoding. If the decoding was unsuccessful (i.e. too many errors received for the number of check symbols in the
code), it also asserts DECFAIL.
The testcase will already have the read addresses on the RSADD[] bus, so the core will write out the decoded
codeword.
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Reed-Solomon Decoder Minicore
Appendix A—Top Level Wrappers
An unencrypted top-level wrapper is provided for the core. As the top-level wrapper is in source form, it can also be
used to create symbol (*.SYM) and include files (*.INC).
The source code for TOP_LEVEL_RSMINIAA is shown below:
FUNCTION rsminiaa (sysclk, reset, enable, load, rsadd[8..1], rsin[8..1])
RETURNS (rsout[8..1], done, decfail);
subdesign top_level_rsminiaa
(
sysclk, reset, enable : INPUT;
load : INPUT;
rsadd[8..1] : INPUT;
rsin[8..1] : INPUT;
rsout[8..1] : OUTPUT;
done, decfail : OUTPUT;
)
BEGIN
(rsout[8..1], done, decfail) = rsminiaa (sysclk, reset, enable, load,
rsadd[8..1], rsin[8..1]);
END;
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