White Paper
®
Excalibur Backgrounder
Table of Contents
Introduction
Page 1
The Advent of Embedded Processor Programmable Logic Solutions
Page 2
Excalibur Embedded Processor Solutions
Page 4
Excalibur Workflow and Development Kit
Page 9
Altera’s Open Business Model
Page 9
Summary
Page 10
Introduction
Since their inception, digital systems have progressed towards higher levels of integration. Higher
integration offers several benefits to the system designer, including lower development costs, shorter design
cycles, increased performance and generally lower power consumption. At the device level, this integration
has been achieved by the accumulation of functions once performed by multiple, individual devices into
more capable, higher density devices. Additionally, the need for design flexibility has increased due to more
challenging time-to-market pressures and changes in system specifications. In particular, two types of
programmable, off-the-shelf components have carried most of the burden of maintaining flexibility and
increasing system integration: microprocessors and programmable logic.
Microprocessors have most notably evolved in two directions: towards higher performance, and towards
greater ease of use. The path to higher performance has produced microprocessors with wider data paths
and longer instructions. Greater integration has also improved speed, as many microprocessors now
incorporate on-board structures such as memory for caching. Finally, like all semiconductors,
microprocessors have benefited from architectural and process enhancements, allowing higher speed
through better clock rates and more efficient logic operations.
Accompanying the increased size and capability of microprocessors has been a corresponding increase in
their complexity, creating a need for improved ease of use. In design development, programming languages
have moved towards higher levels of abstraction, from microcode through assembly, to C, C++, and Java.
Likewise, to streamline the verification of these designs, microprocessors have become supplemented with
on-chip debugging tools such as Background Debug Mode, Enhanced JTAG, and N-Wire.
Programmable logic devices (PLDs) have also matured over their lifetime to meet the needs of systems
designers. Demands for greater capacity and performance are met with larger devices, architecture changes,
and process improvements. As with processors, the road to greater integration also led to memory structures
being incorporated into PLD architectures. With larger, more capable devices has come greater design
June 2000, ver. 1
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complexity, and subsequently, high-level hardware description languages (HDLs) have become the de facto
means of developing designs. Finally, as programmable devices and associated end applications have grown
larger and more intricate, the means to verify their functionality has been supplemented with on-chip
debugging tools.
It should come as no surprise that both microprocessors and programmable logic have evolved in a similar
fashion, as illustrated in the timeline in Figure 1. This parallelism arises from the fact that both types of
devices fundamentally address the same “problem space”—the space in which logical operations are
required to solve a set of problems, but where the exact combination or configuration of operations changes
with the user’s requirements. Within this space, however, performance requirements vary. The operations
that require the best performance will need direct hardware implementation (i.e., programmable logic),
while those with less stringent performance requirements can be satisfied with the slower, sequential
functioning of a microprocessor. As a result, the natural evolution of system-level integration is towards
components that combine the functionality of both microprocessors and programmable logic devices.
Figure 1: Timeline of Processor & PLD Evolution
Microprocessor Evolution
Processor
Created
Embedded
Memory
(cache)
Use of
C Code
On-Chip
Debug
Tools
Programmable Logic Evolution
PLD
Created
Embedded
Memory
(EAB)
Use of
HDLs
On-Chip
Debug
Tools
The Advent of Embedded Processor Programmable Logic Solutions
The traditional approach to system design involves combining a microprocessor and other off-the-shelf
devices on a board, while partitioning the board’s functions into the components that are best suited to
perform them. While this method seems to be straightforward, it ignores the advantages to be gained by
higher device-level integration. With higher device-level integration, the elimination of on-chip/off-chip
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delays enhances performance. Power consumption is often improved as well. Finally, the smaller die,
reduced packaging, and decreased manufacturing expenses associated with lower inventory and testing
requirements lower overall cost.
System Integration at the Component Level
Since the processor is common to nearly all systems, it makes sense to combine it with other functions into
a single device. Stand-alone embedded processors take this approach, as well as custom ASICs and
application-specific standard products (ASSPs). However, each of these approaches has drawbacks.
Stand-Alone Embedded Processors
While stand-alone embedded processors achieve a desirable combination of familiar processor instructions
and additional functional blocks to meet specific system needs, they suffer from a lack of flexibility. As a
result, designers are faced with a perplexing array of stand-alone embedded processor products, each with a
slightly different architectural mode, peripheral selection, and package option. Customers may experience a
long delivery lead time due to a mismatch between the order and the manufacturer’s inventory, which is
driven by total market demand. Finally, stand-alone embedded processors may also contain features unused
in the customer application, leading to cost inefficiency.
ASICs
Custom ASICs allow designers to choose exactly which set of functions will be present in the device, and
are a more likely means of achieving the desired system performance. However, they require many up-front
commitments from the designer, including high non-recurring engineering charges (e.g., mask charges) and
large volume orders. These barriers often prevent the use of custom ASICs in any but the most high-volume
products. Additionally, even under the best of circumstances, custom ASICs take several weeks to fabricate,
delaying their time-to-market when compared to off-the-shelf components. Even when built, they are
inflexible and cannot be modified to fix errors or meet changing specifications.
ASSPs
Because they are standard products, ASSPs are readily available, making them attractive from a time-tomarket point of view. They also provide lower total cost when compared to custom ASIC solutions. For
leading-edge technologies, however, standards must be fixed before ASSPs can be developed to meet them,
meaning that products that rely on standards will suffer a severe time-to-market penalty. Because of their
fixed nature, ASSPs are a viable choice for only a small range of uses. Applications that fall outside of their
range will require additional components, eliminating much of the device integration advantages and often
forcing the designer to pay for unused functions. To address these shortcomings, new types of ASSPs that
attempt to add programmability have recently been developed. Unfortunately, the additional flexibility
provided in these devices has only broadened their applicability by a small amount; these devices are still
targeted at a narrow range of applications (such as data path communications), making them unsuitable for
uses outside their range.
Reconfigurable Processors
On the speculative front, new microprocessor technologies that offer reconfigurable architectures and/or
instruction sets are being researched and developed. While ambitious in their goals of providing optimized
operation for a range of applications, these approaches are problematic in several ways. Changing
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microprocessor architecture means that the boot code must also change. Most systems rely upon a fixed
boot code to recover from instability or glitches. Introducing a changing boot code may result in a system
that cannot recover from problems during operation. In the case of custom or changing instruction sets, the
user of such a microprocessor will be dependent upon a specific set of (usually proprietary) software
development tools, eliminating their code’s portability, making their system architecture processor-specific,
and limiting their overall development options. Finally, introducing a changing architecture and/or
instruction set adds many layers of complexity to the verification process of such a system.
Embedded Processor Programmable Logic Solutions
Given the inadequacies of the other offerings, the next step in the evolution of system integration must be
the combination of embedded processors and programmable logic. In addition to offering all of the
traditional benefits of higher integration, embedded processor PLD solutions also provide unique advantages
to the system designer due to the extreme flexibility of programmable logic. With the integration of
embedded processors within PLDs, a designer can fully realize, in hardware, several iterations of a system
within a fraction of the amount of time required to implement either a custom ASIC, or a board-level design
that relies on an ASSP. This flexibility allows a designer to not only develop a product in a shorter amount
of time, but also to explore different options for partitioning to deliver the best possible combination in that
product. Embedded processor PLDs give the system designer unprecedented freedom in determining which
functions should be executed in software and which would benefit the most from dedicated hardware
implementation in the form of custom peripherals or coprocessor elements. The table in Figure 2 compares
the capabilities of embedded processor PLDs to the other component-level solutions for system integration.
Figure 2. Component-Level Solutions for System Integration
ASICs
ASSPs
Embedded
Processor PLDs
Level of System
Integration
High
Moderate
High
Development Cost
High
Low
Low
Unit Cost
Low
Low
Moderate
Volume Requirement
High
Low
Low
Design Flexibility
Low
Low
High
Time to Market
Slow
Moderate
Fast
Excalibur Embedded Processor Solutions
Altera Corporation has a long and proven history of providing system designers with elements necessary to
achieve high levels of system integration in the shortest amount of time. Continuing in this tradition, Altera
set out to provide the best and most complete offering of embedded processor programmable logic solutions
to the design community. One of the biggest challenges in providing embedded processor PLDs is the
extraordinarily wide range of potential applications. On the lower end, systems may require less than 10
MIPS; at the higher end, the more demanding systems require hundreds of MIPS, each one needing various
degrees of flexibility. A solution that fully covers this range needs to provide both the configurability of
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programmable devices and the performance and user familiarity of embedded processors. The Altera
Excalibur™ embedded processor solutions are the result.
Excalibur embedded processor solutions comprise the first RISC processors to be optimized specifically for
programmable logic. Altera’s Excalibur solutions include both soft core and hard core embedded
processors, each of which are combined with a programmable logic core. By offering both soft core and
hard core implementations, Altera is able to meet the needs of applications requiring the maximum amount
of flexibility, as well as those applications requiring the highest performance. Furthermore, the Excalibur
solutions are supported by a complete design workflow that automates system design, incorporating familiar
hardware and software (C/C++ code) methodologies.
The Nios Family of Soft Core Embedded Processors
The Nios™ embedded processor is a configurable RISC soft core processor with a 16-bit instruction set,
user-selectable 32- or 16-bit datapath, and configurable register file and barrel shifter size. As the first RISC
processor soft core to be developed specifically for programmable logic, Nios can provide up to 50 MIPS
performance while being optimized for area in a PLD. Initially targeted for the APEX device family, a Nios
embedded processor occupies only 12% of a 200,000-gate EP20K200E, a device which costs about $80 in
prototyping quantities, yielding a processor cost of $10. In high-volume production quantities, the cost of an
EP20K200E can be as low as $40, resulting in a processor cost of $5. With APEX devices ranging up to the
1.5-million-gate EP20K1500E, an abundance of device resources remain for the user to develop the rest of
the system. Figure 3 shows a block diagram of the Nios embedded processor.
Figure 3. Nios Embedded Processor Block Diagram
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Several peripherals are available and in development for Nios, including timer/counters, UART, PIO, SPI,
PWM, IDE disk controller, 10/100 Ethernet MAC and SDRAM controller. In addition, any of the multitude
of intellectual property (IP) cores offered by Altera and its IP partners can be used as custom peripherals.
Finally, users can develop their own custom peripherals to perform any desired digital logic function,
making the Nios embedded processor ideal for a wide range of applications in the 8-bit, 16-bit and lower
end of the 32-bit range. To provide software development support for the Nios embedded processor, Altera
has partnered with Red Hat, Inc. to provide a powerful, yet familiar coding environment. The result is a Ccode methodology supported through embedded processor development tools, created by Cygnus Software,
a division of Red Hat. This tool suite includes the GNUPro compiler, assembler, and debugger optimized
for the Nios instruction set.
The possibilities for the Nios embedded processor are quite broad; with the addition of items such as FIR
filters, oscillators, and/or FFTs, complete DSP systems can be developed. Designers can easily create
industrial or automotive controllers by combining the Nios embedded processor with time processing units.
When connected to media access controllers, error correction, and/or packet processing modules, etc.,
complete network processing systems can be realized. Also, the device utilization efficiency of the Nios
embedded processor means that multiple instantiations can be used in performance-intensive applications
requiring multi-processor implementation, as shown in Figure 4.
Figure 4. Flexibility and Scalability of Nios Embedded Processors
MIPS-Based and ARM-Based Hard Core Excalibur Device Families
®
The Excalibur hard core device families are based on processor technology from ARM Limited and MIPS
Technologies, Inc. These two processor vendors supply a large segment of embedded systems designers,
allowing Altera to serve the broadest possible market with competitive processor solutions. These Excalibur
device families feature hard core implementations of ARM and MIPS processors optimized for and
integrated with the APEX programmable logic architecture. As a result, they can deliver processor
performance in the range of hundreds of MIPS, complementing the range of applications covered by the
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Nios embedded processor. They are also fully compatible with all third-party debug tools that support
ARM-based and MIPS-based™ processors.
A block diagram of an Excalibur device with the embedded processor hard core is shown in Figure 5. In
addition to the embedded processor core itself, the devices also include optimized implementations of onchip RAM, cache, an external bus interface, and a UART. With these on-chip elements in place, these
devices can run software and interface to external components prior to configuration of the programmable
logic core. This feature eases and shortens design cycles by allowing software to be written for these
devices in advance of the development of the programmable logic portion of the design.
Figure 5. Block Diagram of ARM- and MIPS-Based Excalibur Devices
Soft Cores and Hard Cores Provide Complete Solution
There are convincing arguments for both soft and hard implementation of processors in PLDs. Soft cores
offer immense flexibility and scalability as well as surprising performance and low cost. They fit well for
many applications that require moderate performance. Finally, they benefit immediately from process
enhancements of their target hardware platform. On the other hand, hard core processors offer maximum
performance and cost effectiveness, primarily for applications at the high performance end of the market.
Altera recognizes the strengths of each approach and gives the designer maximum choice by offering both
hard and soft core processor capability.
The Nios processor can be parameterized, allowing the user to make the performance/cost tradeoff quickly
and robustly, without needing to be an expert in processor design. Regardless of the configuration, the
instruction set remains the same, allowing Altera to deliver fully verified cores and industry-standard
software development tools such as C/C++ compilers. The ARM- and MIPS-based device families offer
leading-edge 32-bit RISC processor performance and substantial system RAM integrated with industry7
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leading programmable logic architectures. These products bring the performance, memory capacity and gate
density normally associated with ASICs within the reach of every software or hardware designer. The table
in Figure 6 outlines the differences between the soft core and hard core Excalibur product families.
Figure 6. Soft Core and Hard Core Excalibur Product Comparison
Flexibility
Performance
Multi-processor Implementation
Process Enhancement Benefit
Nios Soft Core
ARM-Based and MIPS-Based Hard Cores
High
Moderate
Moderate
High
Yes
No
Immediate
Requires Mask Change
Future of Excalibur Solutions
Altera plans to continue developing Excalibur products to meet the changing needs of systems designers.
The table in Figure 7 shows that a version of the Nios embedded processor will be developed for the lowcost ACEX PLD family, resulting in even lower priced solutions. The Nios embedded processor will also be
supported in future Altera device architectures, paving the way for higher speed implementations. All
Excalibur embedded processor solutions will benefit from process enhancements, resulting in higher
performance and lower cost. Altera will also maintain its reputation as the largest supplier of IP for
programmable logic by expanding its IP portfolio to include more functions in the communications and DSP
space, as well as covering emerging bus and interface standards. Finally, Altera will partner with providers
of leading real-time operating systems (RTOS) to further expand the capability of Excalibur products.
Figure 7. Future Excalibur Product Enhancements
Feature
Higher Performance
Future Enhancements
64-bit processor cores
Nios embedded processor optimization for future PLD families
Enhanced process technology
Lower Cost
Nios embedded processor optimization for ACEX architecture
Enhanced process technology for MIPS-based and ARM-based families
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Greater System Integration
Expanded IP portfolio, including communications, DSP, and emerging
buses & interfaces
Increased System Capability
Real-time operating systems, including eCos, Linux, and pSOS
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Excalibur Workflow and Development Kit
Altera provides all of the tools necessary for development of Excalibur designs, including C/C++ compiler
and debugger, peripherals and drivers, the Quartus™ software for PLD design development, and download
cables for device programming and verification. These tools provide a system-centric approach to
development, allowing hardware and software to be created in unison. Figure 8 illustrates the Excalibur
workflow. Altera’s graphical MegaWizard™ Plug-Ins guide the user through the process of configuring the
processor and peripherals, and automate much of the design development, such as generation of code to
handle the interrupts and wait states associated with the peripherals. SignalTap™ Plus provides debugging
capability, including the capture of run-time data at system speeds as well as PC trace.
Figure 8. Excalibur Workflow Diagram
The Excalibur Development Kit featuring the Nios embedded processor includes the Red Hat GNUPro
embedded processor development tools, peripherals and drivers, Quartus PLD development software,
ByteBlaster™ MV download cable, a development board populated by an APEX device, reference design,
and complete documentation for all kit components.
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Altera’s Open Business Model
In addition to providing the technical means to design the next generation of system-level products, Altera
offers a unique value proposition to its customers. The Excalibur solutions are pre-licensed, royalty-free,
off-the-shelf products. Altera has absorbed the intellectual property costs associated with Excalibur
products, allowing each of its customers to use leading-edge technology without the burden of the heavy
investment and complex terms and conditions typically required for core licensing.
The fact that Excalibur solutions provide low-cost access to embedded processor core technology is only
one aspect of Altera’s open business model. Altera customers also gain easy access to other technologies,
including: EDA tools from Synopsys and Mentor Graphics, advanced semiconductor fabrication process
(currently 0.18-micron), a broad portfolio of IP cores from both Altera and its partners, and advanced
packaging options such as Fineline BGA™ packages. In contrast, these advanced technologies are typically
limited only to those companies that are able to make up-front, significantly risky investments.
As an example, the self-limiting ASIC business model precludes access to a broad customer base. Because
the wafer foundry seeks to maximize revenue per mask set, the ASIC customer is limited by high (and
increasing) initial investments in the form of NREs, large minimum order commitments, and costly core
licenses. Coupled with the long development times and the associated higher risks, these conditions make
fixed ASICs a less attractive platform for system-level integration. Conversely, the wide-open nature of the
Altera business model not only provides low-cost access to advanced technology for the entire marketplace,
but it also provides both Altera and the wafer foundry with a very high return per mask set.
Summary
The combination of programmable logic and embedded processors provides the system designer with the
highest degree of freedom and capability for system integration. By including both soft core and hard core
embedded processor options, the Excalibur embedded processor solutions offer both the flexibility and
performance to address the broad scope of problems in today’s system-level designs. In addition, the
Excalibur product roadmap includes enhancements that will bring better performance, lower cost options,
and greater capabilities. These system-on-a-programmable-chip (SOPC) solutions, when combined with
Altera’s open business model, guarantee that Altera’s customers will continue to have easy, low-cost access
to advanced technology that will be crucial to bringing about the next generation of system design.
Altera, APEX, ACEX, Excalibur, Nios, Quartus, SignalTap, ByteBlaster, ByteBlasterMV, FineLine BGA, MegaWizard, The
Programmable Solutions Company, and specific device designations are trademarks and/or service marks of Altera Corporation in
the United States and other countries. ARM and the ARM Powered logo are registered trademarks of ARM Limited. MIPS-based
and the MIPS logo are trademarks of MIPS Technologies, Inc. Other brands or products are trademarks of their respective holders.
The specifications contained herein are subject to change without notice. All rights reserved.
Copyright © 2000, Altera Corporation. All rights reserved.
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