UTOPIA Level 2 Master
MegaCore Function
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
Document Version:
Document Date:
2.1.2
2.1.2 rev1
June 2003
UTOPIA Level 2 Master MegaCore Function User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
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UG-UTOPIA_MASTER-2.3
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
UTOPIA Level 2 Master MegaCore® function.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the features, including
new features in this release
Refer to the readme file for late-breaking information that is not
available in this user guide
Table 1 shows the user guide revision history.
Table 1. Revision History
Date
How to Find
Information
June 2003
Quartus II version 3.0 information added.
January 2003
Device family support table added.
July 2002
Stratix™ device information added. Using Visual IP models
section added.
June 2001
Atlantic™ interface now supported.
Dec 2000
Version 1.2 updates incorporated.
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Altera Corporation
Description
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a PDF file. Click on the binoculars icon in the top toolbar to open the
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Bookmarks serve as an additional table of contents.
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Numerous links, shown in green text, allow you to jump to related
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iii
About this User Guide
How to Contact
Altera
UTOPIA Level 2 Master MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The UTOPIA Level 2 Master MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 2.1.0 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
Performance ....................................................................................................................................11
Getting Started ............................................................................................................................................13
Software Requirements .................................................................................................................13
Design Flow ....................................................................................................................................13
Download & Install the Function ................................................................................................13
Obtaining the UTOPIA Level 2 Master MegaCore Function ..........................................13
Installing the UTOPIA Level 2 Master Files ......................................................................14
UTOPIA Level 2 Master Directory Structure .....................................................................15
Set Up Licensing .............................................................................................................................16
Append the License to Your license.dat File ......................................................................16
Specify the Core’s License File in the Quartus II Software ..............................................17
UTOPIA Level 2 Master Walkthrough .......................................................................................18
Create a New Quartus II Project ..........................................................................................19
Launch the IP Toolbench ......................................................................................................19
Step 1: Parameterize ..............................................................................................................21
Step 2: Generate ......................................................................................................................24
Simulate the Design .......................................................................................................................25
Set Up the ModelSim Simulation Tool for the VHDL Model ..........................................25
Set Up the ModelSim Simulation Tool for the Verilog HDL Model ..............................26
Simulate with the Visual IP Model ......................................................................................26
Using the Sample VHDL Testbench ....................................................................................27
Configure a Device ........................................................................................................................28
Specifications ..............................................................................................................................................29
Functional Description ..................................................................................................................29
Signal Definitions ...................................................................................................................30
UTOPIA Transmit Interface .................................................................................................37
Local Transmit Interface .......................................................................................................37
Altera Corporation
vii
Contents
Atlantic Slave Transmit Interface ........................................................................................38
UTOPIA Receive Interface ....................................................................................................39
Local Receive Interface ..........................................................................................................40
Atlantic Slave Receive Interface ...........................................................................................41
Atlantic Interface ....................................................................................................................42
Address Translation ..............................................................................................................45
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Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the UTOPIA Level 2
Master MegaCore function.
Table 4. UTOPIA Level 2 Master Release Information
Item
Version
Device Family
Support
2.1.2
Release Date
June 2003
Ordering Code
IP-UTOPIA2MS
Product ID(s)
0017
Vendor ID(s)
6AF7
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
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Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software
9
About this Core
UTOPIA Level 2 Master MegaCore Function User Guide
Table 5 shows the level of support offered by the UTOPIA Level 2
Master MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Stratix GX
™
Support
Full
Cyclone
Full
Stratix™
Full
Mercury™
Full
™
Excalibur
Full
HardCopy™
Full
®
ACEX 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera UTOPIA Level 2 Master MegaCore function is is designed
for use in asynchronous transfer mode (ATM) layer devices that
transfer data to and from PHY devices using the standard UTOPIA
bus.
New in Version
2.1.2
■
Support for the Quartus II software version 3.0
Features
■
■
■
Conforms to the UTOPIA Level 2, Version 1.0 specification
8- or 16-bit UTOPIA bus operation
Single physical layer (SPHY) operation, with both octet- and
cell-level handshaking
Multi-PHY (MPHY) operation, with single clav signal
Logical-to-physical address translation via programmable lookup table
Parity generation and detection
Atlantic interface—packet-based interface that is compatible
with other Altera cell and packet MegaCore functions
Easy-to-use IP Toolbench that generates a parameterized
MegaCore function
Simulation models for the ModelSim simulation tool
OpenCore® feature allows you to instantiate and simulate
designs in the Quartus II software prior to purchase
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Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
The UTOPIA Level 2 Master MegaCore function is designed for use
in asynchronous transfer mode (ATM) layer devices that transfer
data to and from PHY devices using the standard UTOPIA bus. The
UTOPIA Level 2 Master MegaCore function comprises a separate
transmitter and receiver; both support SPHY and MPHY operation
modes. SPHY mode supports octet- or cell-level handshake; MPHY
mode supports cell-level handshake with up to 31 PHY devices.
The transmitter polls the PHYs in a round-robin fashion to determine
which are ready to receive data transfers, and outputs the poll status
to the ATM layer. The transmitter accepts cells from the ATM layer
and sends them to the PHY devices via the UTOPIA bus interface.
There is an option to generate parity information for the UTOPIA
bus.
The receiver polls the PHYs in a round-robin fashion to determine
which are ready to send data transfers, and outputs the poll status to
the ATM layer. The receiver accepts cells from the PHY devices via
the UTOPIA bus interface and sends them to the ATM layer. There is
an option to check for parity errors on the UTOPIA bus.
Figure 1 shows the UTOPIA MegaCore function block diagram.
Figure 1. UTOPIA MegaCore Function Block Diagram
Port 0
PHY
UTOPIA
Slave
Function
ATM Layer
UTOPIA
Master
Function
Port N
PHY
SAR/
Switch
UTOPIA
Slave
Function
The Atlantic interface allows a consistent interface between all Altera
cell and packet MegaCore functions. The Atlantic interface is only
designed to support a point-to-point connection. You must choose
whether you use the local or Atlantic interface. Figure 2 shows
examples of the Atlantic interface. The core supports a slave Atlantic
interface only.
Altera Corporation
11
1
About this Core
General
Description
About this Core
About this Core
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 2. Atlantic Interface
Atlantic Interface
UTOPIA
Interface
Cell
Processor
UTOPIA
Interface
ATM
Processor
Atlantic Interface
Performance
Tables 6 and 7 show push-button performance with the Quartus II
software version 2.1 and APEX 20KE devices. All MPHY figures use
the complete address range and RAM for the translation tables.
1
Use the LogicLock™ incremental design capability for
greater performance.
Table 6. Transmitter Performance
Parameters
LEs
ESBs Performance
(MHz)
Device
16-bit UTOPIA width, 52 bytes local cell size, MPHY mode.
473
2
83
EP20K30EFC208-1
16-bit UTOPIA width, 54 bytes local cell size, MPHY mode. 465
2
88
EP20K30EFC324-1
8-bit UTOPIA width, 52 bytes local cell size, MPHY mode.
452
2
80
EP20K30EFC144-1
8-bit UTOPIA width, 53 bytes local cell size, MPHY mode.
442
2
89
EP20K30EFC144-1
Table 7. Receiver Performance
Parameters
LEs
ESBs Performance
(MHz)
Device
16-bit UTOPIA width, 52 bytes local cell size, MPHY mode. 441
2
95
EP20K30EQC208-1
16-bit UTOPIA width, 54 bytes local cell size, MPHY mode. 439
2
77
EP20K30EQC208-1
8-bit UTOPIA width, 52 bytes local cell size, MPHY mode.
431
2
88
EP20K30EQC208-1
8-bit UTOPIA width, 53 bytes local cell size, MPHY mode.
429
2
93
EP20K30EQC208-1
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Altera Corporation
Getting Started
Software
Requirements
This section requires the following software:
■
■
A PC running the Windows 98/NT/2000 operating system
Quartus II version 2.1 or higher
Design Flow
This walkthrough involves the following steps:
1.
Download and install the MegaCore function.
2.
Generate a custom MegaCore function using the IP Toolbench.
3.
Implement your system using AHDL, VHDL, or Verilog HDL.
4.
Compile your design.
5.
Simulate your design to confirm the operation of your system.
6.
License the MegaCore function and configure the devices.
1
Download &
Install the
Function
This document assumes that you are using a PC with the
Windows operating system. However, you can also use the
UTOPIA Level 2 Master MegaCore function on UNIX platforms.
The IP Toolbench is a toolbar from which you can quickly and
easily view documentation, specify core parameters, set up
third-party tools, and generate all files necessary for integrating
the parameterized core into your design.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining the UTOPIA Level 2 Master MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at www.altera.com. Follow the instructions below to
obtain the UTOPIA Level 2 Master via the Internet. If you do not have
Internet access, you can obtain the UTOPIA Level 2 Master from your
local Altera representative.
Altera Corporation
13
Getting Started
1
2
Getting Started
UTOPIA Level 2 Master MegaCore Function User Guide
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Type UTOPIA in the Keyword Search box.
4.
Click Go.
5.
Click the link for the Altera UTOPIA Level 2 Master MegaCore
function in the search results table. The product description web
page displays.
6.
Click the Free Test Drive graphic on the top right of the product
description web page.
7.
Fill out the registration form, read the license agreement, and click
I Agree at the bottom of the page.
8.
Follow the instructions on the UTOPIA Level 2 Master download
and installation page to download the function and save it to your
hard disk.
Installing the UTOPIA Level 2 Master Files
For Windows, perform the following steps:
14
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The UTOPIA Level 2 Master Installation dialog box
appears. Follow the on-line instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the directory in which you installed them
(e.g., <path>/utopia2_master-<version>\lib) as a user library in the
Quartus II software. Search for “User Libraries” in Quartus II Help
for instructions on how to add these libraries.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Getting Started
UTOPIA Level 2 Master Directory Structure
Figure 1 shows the directory structure for the UTOPIA Level 2 Master.
Figure 1. UTOPIA Level 2 Master Directory Structure
megacore
utopia2_master-<version>
Contains the UTOPIA Master MegaCore function files and documentation.
2
doc
Contains the documentation for the core.
sim_lib
Contains the simulation models provided with the core.
modelsim_verilog
Contains the pre-compiled Verilog HDL model for the ModelSim simulation tool.
modelsim_vhdl
Contains the pre-compiled VHDL model for the ModelSim simulation tool.
testbench
Contains the sample VHDL testbench and configuration files for the models.
vip_models
Contains the Visual IP models.
Altera Corporation
15
Getting Started
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
Getting Started
Set Up
Licensing
UTOPIA Level 2 Master MegaCore Function User Guide
You can use Altera’s OpenCore feature to compile and simulate the
UTOPIA Level 2 Master MegaCore function, allowing you to evaluate it
before purchasing a license. You can simulate your design in the Quartus
II software using the OpenCore feature. However, you must obtain a
license from Altera before you can generate programming files or EDIF,
VHDL, or Verilog HDL gate-level netlist files for simulation in third-party
EDA tools.
After you purchase a license for the UTOPIA Level 2 Master core, you can
request a license file from the Altera web site at
http://www.altera.com/licensing and install it on your PC. When you
request a license file, Altera e-mails you a license.dat file. If you do not
have Internet access, contact your local Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the UTOPIA Level 2 Master core,
you must already have the Quartus II software installed on your
PC with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the UTOPIA Level 2 Master core license file in a text editor.
The file should contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the UTOPIA Level 2 Master core
license file and paste it into the Quartus II license file.
1
16
Do not delete any FEATURE lines from the Quartus II license
file.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
5.
Getting Started
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Altera Corporation
2
Create a text file with the FEATURE line and save it to your hard disk.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
17
Getting Started
1.
Getting Started
UTOPIA Level 2
Master
Walkthrough
UTOPIA Level 2 Master MegaCore Function User Guide
This walkthrough explains how to create a custom core using the Altera
UTOPIA Level 2 Master IP Toolbench and the Quartus II software. As you
go through the IP Toolbench, each page is described in detail. When you
are finished generating a custom core, you can incorporate it into your
overall project.
This walkthrough consists of the following steps:
■
■
■
■
“Create a New Quartus II Project” on page 18
“Launch the IP Toolbench” on page 19
“Step 1: Parameterize” on page 20
“Step 2: Generate” on page 23
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the UTOPIA Level 2 Master user library. To create a
new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction does not display if
you turned it off previously).
4.
Specify the working directory for your project. This walkthrough
uses the directory d:\temp\example
5.
Specify the name of the project. This walkthrough uses example.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\utopia2_master-<version>\lib\ into the Library
name box, where <path> is the directory in which you installed the
UTOPIA Level 2 Master. The default installation directory is
c:\megacore.
9.
Click Add.
10. Click OK.
18
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Getting Started
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the IP Toolbench
The MegaWizard Plug-In Manager allows you to run the IP Toolbench
that helps you easily specify options for the UTOPIA Level 2 Master. To
launch the IP Toolbench, perform the following steps:
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
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Altera Corporation
Refer to the Quartus II Help for more information on how to use
the MegaWizard Plug-In Manager.
2.
Specify that you want to create a new custom megafunction and
click Next.
3.
Select UTOPIA Level 2 Master-<version> in the Communications >
UTOPIA directory.
4.
Choose the output file type for your design; the wizard supports
AHDL, VHDL, and Verilog HDL.
5.
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 2 shows the wizard after you have made
these settings.
<variation name> and <directory name> must be the same name and the
same directory that your Quartus II project uses.
19
Getting Started
1.
2
Getting Started
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 2. Selecting the MegaCore Function
Step 1: Parameterize
To parameterize your core, perform the following steps:
1.
Click Step 1: Parameterize in the IP Toolbench (see Figure 3).
Figure 3. IP Toolbench
20
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Getting Started
2.
Choose the device family (see Figure 4).
3.
Select whether you wish to create a transmitter or receiver (see
Figure 4). Click Next.
4.
If you require an Atlantic local interface, turn on the Atlantic Local
Interface check box.
Figure 4. Select a Transmitter or Receiver
2
Getting Started
5.
Altera Corporation
Choose the parameters that define the specific UTOPIA master
MegaCore function you wish to implement (see Figure 5). See Table 1
on page 29 for a description of the parameters. The IP Toolbench
allows you to select only legal combinations of parameters. Click
Next when you are finished.
21
Getting Started
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 5. Select the Parameters
22
6.
When you select the MPHY mode, you can implement an address
translation table in ROM or RAM. To implement the address
translation table in RAM, click Set Address Translation Table. The
Set Address Translation Table dialog box appears.
7.
Click on a logical address, and physical address, and then click Link
(see Figure 6). Continue until all logical addresses have been linked
to the required physical addresses. Click Done.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Getting Started
Figure 6. Setting the Address Translation Tables
2
Getting Started
Step 2: Generate
To generate your core, perform the following steps:
1.
Click Step 2: Generate in the IP Toolbench (see Figure 7).
Figure 7. IP Toolbench—Generate
2.
Altera Corporation
The generation report lists the design files that the IP Toolbench
creates (see Figure 8). Click Exit IP Toolbench.
23
Getting Started
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 8. IP Toolbench-Generated Files
When you have created a custom megafunction, you can integrate it into
your system design and compile.
Simulate the
Design
Altera provides ModelSim VHDL and Verilog HDL models that you can
use to simulate the MegaCore function in your system. Altera also
provides a Visual IP model in the sim_lib\vip_models directory, which
you can use with the Visual IP software and is supported by other Verilog
HDL and VHDL simulators. The models are supplied as pre-compiled
libraries for the ModelSim simulator and are installed in the
sim_lib\modelsim_vhdl and sim_lib\modelsim_vhdl directories. You
can integrate these models into your system, speeding simulation.
Set Up the ModelSim Simulation Tool for the VHDL Model
The pre-compiled VHDL model that is provided with the MegaCore
function is installed in the sim_lib\modelsim_vhdl directory. To set up
your system to use the UTOPIA master model, perform the following
steps.
1
24
You can also use the ModelSim graphical user interface (GUI) to
create a logical map. Refer to the ModelSim online Help for
details.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
1.
Getting Started
Run the ModelSim software and create a logical map called altutm
to the folder containing the compiled library by typing the following
command in the ModelSim software:
vmap altutm <Drive:>/<MegaCore Path>
/sim_lib/modelsim_vhdl/altutm
2.
You must refresh the compiled library by typing the command:
vcom -work altutm -refresh
2
The pre-compiled Verilog HDL model is provided with the MegaCore
function and is installed in the sim_lib\modelsim_verilog folder. To set
up your system to use the UTOPIA master model, perform the following
steps.
1
1.
You can also use the ModelSim graphical user interface (GUI) to
create a logical map. Refer to the ModelSim online Help for
details.
Run the ModelSim software and create a logical map called altutm
to the folder containing the compiled library by typing the following
command in the ModelSim software:
vmap altutm <Drive:>/<MegaCore Path>
/sim_lib/modelsim_verilog/altutm
2.
You must refresh the compiled library by typing the command:
vlog -work altutm -refresh
Simulate with the Visual IP Model
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
Altera Corporation
1.
Point your web browser at
https://www.altera.com/support/software/download/eda_softw
are/visualip/dnl-visualip.jsp.
2.
Follow the on-line instructions to download the Innoveda Visual IP
software and save it to your hard disk.
25
Getting Started
Set Up the ModelSim Simulation Tool for the Verilog HDL Model
Getting Started
UTOPIA Level 2 Master MegaCore Function User Guide
To use the Visual IP model, perform the following steps:
1.
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Compile the wrapper for the core model.
The Verilog HDL version of the wrapper is in the
sim_lib\vip_models\<model name>\interface\pli directory;
the corresponding VHDL version is in the
sim_lib\vip_models\<model name>\interface\mti directory.
1
3.
Where <model_name> is masterrx, masterrx_atlantic, mastertx,
mastertx_atlantic. For Stratix devices use <model name>_sba.
Compile the wizard-generated wrapper <variation name>.vhd,
<variation name>.v.
The Visual IP model is now ready for use in your simulator.
Using the Sample VHDL Testbench
In addition to the models, Altera provides a sample VHDL testbench (in
the sim_lib\testbench folder). This VHDL testbench provides you with
the ability to easily simulate several different configurations (e.g., single
slave vs. multiple slaves). To use the models, you must first instantiate
them in your system. The testbench is master_tb. It comprises a master
(receiver and transmitter), and a configurable number of slaves (receivers
and transmitters). The testbench includes some simple stimulus to control
the user interfaces of the MegaCore functions and to transfer ATM cells
across the UTOPIA bus. Various parameters may be set to control the
testbench operating mode, including PHY mode, UTOPIA bus width,
operating frequencies, and number of slaves. To compile these files in the
ModelSim software, follow the steps below:
1
26
To use the sample VHDL testbench, the UTOPIA master and
slave MegaCore functions must be available and both setup for
ModelSim. See “Set Up the ModelSim Simulation Tool for the
VHDL Model” on page 24, and the UTOPIA Level 2 Slave
MegaCore Function User Guide.
1.
Choose Change Directory (Design menu).
2.
Select Create a New Library (Design Menu). Select a new library and
a logical mapping to it. In the Library Box type work.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Getting Started
3.
In the Compile HDL Source Files dialog box, select the library work
in the Library drop-down list box. Also select the
\sim_lib\vhdl\testbench folder in the Look In drop-down list box.
4.
Select master_tb_pack.vhd and click Compile. Select
slave_user_if.vhd and click Compile. Select master_tb.vhd and
click Compile.
5.
When the compilation finishes, click Done. You are now ready to run
the simulation.
vsim -GPHYMode=\”SPHYCellHandshake\” -Gnum_slaves=1
-GUserCellSize=52 master_tb
You can also use the ModelSim graphical user interface to load the
configuration. Refer to the ModelSim online Help for details.
To instantiate the Verilog HDL model in your system, you can instantiate
the parameterized models by using the sample testbench as a template.
Configure a
Device
Altera Corporation
2
Getting Started
You can load a configuration from the command line in the ModelSim
simulation tool, for example:
After you have compiled and analyzed your design, you are ready to
configure your target Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must obtain a license from
Altera. You can then generate output files (.edo, .vho, .vo, or .sdo) or a
netlist for use in your third-party EDA tool for post-route, device-level,
and system-level simulation.
27
Notes:
Specifications
Table 1 shows the MegaCore function’s parameters.
Table 1. Parameters
Parameter
Values
Description
bus_width
8 or 16
Width of the UTOPIA and local data bus. The local data bus width
is always the same as the UTOPIA bus width.
address_translation
Yes or no
Determines whether logical-to-physical address translation is
performed. If address translation is not enabled, logical
addresses are mapped directly to physical addresses.
address_range
0 to 30
Determines the range of logical addresses that is polled.
parity_check
Yes or no
Determines whether UTOPIA bus parity is checked. This
parameter controls the creation of parity logic in the receive
direction.
parity_generate
Yes or no
Determines whether UTOPIA bus parity is generated. This
parameter controls the creation of parity logic in the transmit
direction.
sphy_mode
Yes or no
Determines whether operation is in UTOPIA 1 compatibility mode
(i.e., interfacing with a single PHY).
53/54_byte_cells
Yes or no
Determines whether operation is with cells of 53 bytes (54 bytes
in 16-bit mode), or cells of 52 bytes on the local interface side. In
52 byte cells the user defined (UDF) field has been removed.
octet_handshake
Yes or no
When in SPHY mode, this parameter determines whether the
interface supports octet- or cell-level handshaking.
pipeline_user_interface Yes or no
Determines whether operation is in pipelined or non-pipelined
mode. (1)
3
Specifications
Note:
(1)
Pipelined is the recommended mode; however, the non-pipelined mode is provided.
Signals
The MegaCore function uses the following signals:
■
■
Input—Standard input-only signal.
Output—Standard output-only signal.
The signal block diagram is shown in Figure 1.
Altera Corporation
29
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 1. Signal Block Diagram
UTOPIA Bus
transmit
receive
Local Bus
UTOPIA
Master
Function
transmit
receive
parameters
Table 2 shows the UTOPIA transmit interface signal definitions.
Table 2. UTOPIA Transmit Interface
Name
Type
Description
tx_data[15/7:0]
Output
Transmit data. When in 8-bit mode, tx_data[7:0] is used.
tx_soc
Output
Start of cell indicator. Active-high signal asserted when tx_data contains
the first word of the cell.
tx_enb
Output
Enable. Active-low signal asserted when tx_data contains valid data.
tx_clav
Input
Cell available. Active-high signal asserted from the PHY devices when they
are ready to receive another cell.
tx_prty
Output
Parity. tx_prty is the parity bit over tx_data[7:0] in 8-bit mode, and
tx_data[15:0] in 16-bit mode.
tx_addr[4:0]
Output
Address. Five-bit-wide address used in MPHY mode to poll and select the
various connected PHY devices.
tx_clk_in
Input
Transmit clock. All signals on the UTOPIA and local transmit interface are
synchronous to it.
30
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Table 3 shows the local transmit interface signal definitions.
Table 3. Local Transmit Interface
Name
Type
Description
Input
Data input for transmit data. When in 8-bit mode,
atm_tx_data[7:0] is used.
atm_tx_soc
Input
Active-high signal asserted when atm_tx_data contains the first
word of the cell.
atm_tx_valid
Input
Active-high signal asserted when valid cell data is present on
atm_tx_data.
atm_tx_enb
Output
Active-high signal asserted when ready to accept cell data.
atm_tx_port_stat[30:0]
Output
Port status of polled PHYs. Represents the tx_clav status of the
corresponding PHYs.
atm_tx_port[4:0]
Input
Port address for next cell transfer.
atm_tx_port_load
Input
Active-high enable pulse. Loads the port address for the next cell
transfer.
atm_tx_port_wait
Output
Active-high signal. Indicates that the local interface must wait before
loading the next port address with atm_tx_port.
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31
3
Specifications
atm_tx_data[15/7:0]
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Table 4 shows the Atlantic transmit interface signal definitions.
Table 4. Atlantic Transmit Interface
Name
Type
Description
atm_tx_dat[15/7:0]
Input
Data bus.
This bus carries the packet octets that are transferred across the
interface.
The data is transmitted in big endian order on atm_tx_dat. The
data is sent most significant bit (MSB) first and all valid bits are
contiguous with the MSB.
atm_tx_sop
Input
Start of packet signal.
atm_tx_sop is used to delineate the packet boundaries on the
atm_tx_dat bus. When atm_tx_sop is high, the start of the
packet is present on the atm_tx_dat bus.
atm_tx_sop is required to be present at the beginning of every
packet.
atm_tx_eop
Input
End of packet signal.
atm_tx_eop is used to delineate the packet boundaries on the
atm_tx_dat bus. When atm_tx_eop is high, the end of the packet
is present on the atm_tx_dat bus.
atm_tx_eop is required to be present at the end of every packet.
atm_tx_ena
Input
Enable signal.
atm_tx_ena is driven by a master interface, and used to control the
flow of data across the interface.
atm_tx_ena behaves as a write enable from master to slave.
When ena is sampled asserted, the Atlantic data interface signals
are valid and are transferred across the interface on the following
rising edge of clk.
atm_tx_dav
Output
Data available signal.
If atm_tx_dav is high, the FIFO has enough space for another word
to be written. If more than one word of data is written after
atm_tx_dav transitions low, data is lost.
atm_tx_adr_stat[30:0]
Output
Port status of polled PHYs. Represents the tx_clav status of the
corresponding PHYs.
atm_tx_adr[4:0]
Input
Port address for next cell transfer.
32
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Table 5 shows the UTOPIA receive interface signal definitions.
Table 5. UTOPIA Receive Interface
Name
Type
Description
rx_data[15/7:0]
Input
Receive data. When in 8-bit mode, rx_data[7:0]is used.
rx_soc
Input
Start of cell indicator. Active-high signal asserted when rx_data
contains the first word of the cell.
rx_enb
Output
Enable. Active-low signal asserted to enable the PHY device to drive
data on rx_data.
rx_clav
Input
Cell available. Active-high signal asserted from the PHY devices
when they are ready to send another cell.
rx_clk_in
Input
Receive clock. All signals on the UTOPIA/local receive interface are
synchronous to it.
rx_prty
Input
Parity. rx_prty is the parity bit over rx_data[7:0]in 8-bit mode,
and rx_data[15:0] in 16-bit mode.
rx_addr[4:0]
Output
Address. Five-bit-wide address used in MPHY mode to poll and
select the various connected PHY devices.
rx_prty_pulse
Output
Active-high one-cycle pulse, indicating a parity error has been
detected on rx_prty input.
rx_cell_pulse
Output
Active-high one-cycle pulse, indicating a cell has been received.
rx_cell_err_pulse
Output
Active-high one-cycle pulse, indicating an illegal-length cell has
been received.
3
Specifications
Table 6 shows the local receive interface signal definitions.
Table 6. Local Receive Interface
Name
Type
Description
atm_rx_data[15/7:0]
Output
Data output for receive data.
atm_rx_soc
Output
Asserted when atm_rx_data contains the first word of the cell.
atm_rx_valid
Output
Asserted when valid cell data is present on atm_rx_data.
atm_rx_enb
Input
Asserted when ready to accept cell data.
atm_rx_port_stat[30:0]
Output
Port status of polled PHYs. Represents the rx_clav status of the
corresponding PHYs.
atm_rx_port[4:0]
Input
Port address for the next cell transfer.
atm_rx_port_load
Input
Active-high enable pulse, which loads the port address for the next
cell transfer.
atm_rx_port_wait
Output
Active-high signal asserted to indicate that the local interface must
wait before loading the next port address with atm_rx_port_load.
Altera Corporation
33
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Table 7 shows the Atlantic receive interface signal definitions.
Table 7. Atlantic Receive Interface (Part 1 of 2)
Name
Type
Description
atm_rx_dat[15/7:0]
Output
Data bus.
This bus carries the packet octets that are transferred across the
interface.
The data is transmitted in big endian order on atm_rx_dat. The data
is sent most significant bit (MSB) first and all valid bits are contiguous
with the MSB.
atm_rx_sop
Output
Start of packet signal.
atm_rx_sop is used to delineate the packet boundaries on the
atm_rx_dat bus. When atm_rx_sop is high, the start of the packet
is present on the dat bus.
atm_rx_sop is required to be present at the beginning of every
packet.
atm_rx_eop
Output
End of packet signal.
atm_rx_eop is used to delineate the packet boundaries on the
atm_rx_dat bus. When atm_rx_eop is high, the end of the packet
is present on the atm_rx_dat bus.
atm_rx_eop is required to be present at the end of every packet.
atm_rx_val
Output
Data valid signal.
atm_rx_val indicates the validity of the data signals.
atm_rx_val is updated on every clock edge where atm_rx_ena is
sampled asserted, and holds it’s current value along with the
atm_rx_dat bus where ena is sampled de-asserted.
When atm_rx_val is asserted, the Atlantic data interface signals are
valid.
When atm_rx_val is de-asserted, the Atlantic data interface signals
are invalid and must be disregarded.
To determine whether new data has been received, the master must
qualify the atm_rx_val signal with the previous state of the
atm_rx_ena signal.
atm_rx_ena
Input
Enable signal.
atm_rx_ena is driven by an Atlantic master interface, and used to
control the flow of data across the interface.
atm_rx_ena behaves as a read enable from Atlantic master to
Atlantic slave.
When atm_rx_ena is sampled asserted, the Atlantic data interface
signals contain new data during the following clock edge. atm_rx_val
indicates the validity of the data.
The Atlantic data interface signals get new data on every clock cycle,
if atm_rx_ena is asserted.
34
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UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Table 7. Atlantic Receive Interface (Part 2 of 2)
Name
atm_rx_dav
Type
Output
atm_rx_adr_stat[30:0] Output
Description
Data available signal.
If atm_rx_dav is high, the slave FIFO has at least one word available
to be read.
Port status of polled PHYs. Represents the rx_clav status of the
corresponding PHYs.
atm_rx_req_adr[4:0]
Input
Port address for the next cell transfer.
atm_rx_req_adr_load
Input
Active-high enable pulse, which loads the port address for the next cell
transfer.
atm_rx_req_adr_wait
Output
Active-high signal asserted to indicate that the local interface must wait
before loading the next port address with atm_rx_req_adr_load.
atm_rx_adr[4:0]
Output
Address Bus. atm_rx_adr carries the associated address information
for each packet in multi-port implementations.
The atm_rx_adr bus is valid at the same time as the atm_rx_dat
bus and remains constant throughout a complete packet.
3
Specifications
Altera Corporation
35
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Table 8 shows the configuration interface signal definitions.
Table 8. Configuration Interface
Name
Type
Description
tx_phy_mode[1:0]
Input
Bit 0: 0 = MPHY mode; 1 = SPHY mode.
Bit 1: (SPHY mode only) 0 = octet-level handshaking, 1 = cell-level
handshaking.
atm_tx_pipe_mode
Input
0 = Non-pipelined mode; 1 = pipelined mode.
tx_width
Input
0 = 8-bit UTOPIA transmit and local bus width.
1 = 16-bit UTOPIA transmit and local bus width.
tx_user_bytes
Input
Defines the size of the cells at the local transmit interface.
8-bit local transmit bus: 0 = 52 bytes; 1 = 53 bytes.
16-bit local transmit bus: 0 = 52 bytes; 1 = 54 bytes.
tx_parity_generate
Input
Enables parity generation on the UTOPIA bus when high.
tx_addr_range[4:0]
Input
The range of transmit ports polled in MPHY mode is from 0 to
tx_addr_range.
tx_tt_en
Input
Enables the logical-to-physical translation table.
tx_tt_mode
Input
Selects the logical-to-physical translation table: 0 = RAM; 1 = ROM.
tx_tt_write
Input
Write enable for logical-to-physical translation table (active high).
tx_tt_addr[4:0]
Input
Address for logical-to-physical translation table.
tx_cell_adjust[3:0] Input
Cell size adjustement. Default is 0, other modes are not supported.
tx_tt_data[4:0]
Input
Data for logical-to-physical translation table.
rx_phy_mode[1:0]
Input
Bit 0: 0 = MPHY mode; 1 = SPHY mode.
Bit 1: (SPHY mode only) 0 = octet-level handshaking, 1 = cell-level
handshaking.
atm_rx_pipe_mode
Input
0 = Non-pipelined mode; 1 = pipelined mode.
rx_width
Input
0 = 8-bit UTOPIA receive and local bus width.
1 = 16-bit UTOPIA receive and local bus width.
rx_user_bytes
Input
Defines the size of the cells at the local receive interface.
8-bit local receive bus: 0 = 52 bytes; 1 = 53 bytes.
16-bit local receive bus: 0 = 52 bytes; 1 = 54 bytes.
rx_parity_check
Input
Enables parity checking on the UTOPIA bus when high.
rx_addr_range[4:0]
Input
The range of receive ports polled in MPHY mode is from 0 to
rx_addr_range.
rx_cell_adjust[3:0] Input
Cell size adjustement. Default is 0, other modes are not supported.
rx_tt_en
Input
Enables the logical-to-physical translation table.
rx_tt_mode
Input
Selects the logical-to-physical translation table: 0 = RAM; 1 = ROM.
rx_tt_write
Input
Write enable for logical-to-physical translation table (active high).
rx_tt_addr[4:0]
Input
Address for logical-to-physical translation table.
rx_tt_data[4:0]
Input
Data for logical-to-physical translation table.
reset
Input
System reset.
36
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Interfaces
Specifications
This section describes the following interfaces:
■
■
■
■
■
■
■
UTOPIA transmit
Local transmit
Atlantic slave transmit
UTOPIA receive
Local receive
Atlantic slave receive
Atlantic
UTOPIA Transmit Interface
The UTOPIA transmit interface transmits ATM cell data to a
UTOPIA level 2 slave transmitter. The interface supports 8- or 16-bit
transmit data buses, and SPHY or MPHY modes of operation.
f
The UTOPIA Level 2, Version 1.0 specification is available from
http://www.atmforum.com
In SPHY mode, the slave indicates that it can accept a cell by
asserting the tx_clav output. The master subsequently transmits a
cell to the slave by asserting tx_enb low. This behavior is described
in section 3 of the UTOPIA Level 2, Version 1.0 specification.
Altera Corporation
37
3
Specifications
In MPHY mode, the master polls the various slaves using tx_addr.
It polls the logical addresses ranging from address 0 to the
programmed value of tx_addr_range. The slaves respond by
driving their tx_clav output to allow the master to determine
whether the slaves can accept a cell. The atm_tx_port_stat and
atm_tx_port_stat outputs store the polling result for each slave
address, which allows the local transmit interface to determine
which slaves can accept cells. The master then selects a slave and
transfers a complete cell. This behavior is described in section 4.2 of
the UTOPIA Level 2, Version 1.0 specification.
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Local Transmit Interface
The local transmit interface provides the ability to transmit ATM cell
data along with its associated port (slave) address, ready for
transmission on the UTOPIA bus. To avoid stalling the UTOPIA
transmit interface, a new ATM cell transmission should be initiated
only when the relevant bit of atm_tx_port_stat is active. The
data path (atm_tx_data) can operate in either 8- or 16-bit mode,
but it always has the same bus width as the UTOPIA transmit
interface. The cell size can be 52, 53, or 54 bytes long. The local
transmit interface indicates that it can accept data on atm_tx_data
by asserting atm_tx_enb high. Before you transmit a cell, you must
load a new port using atm_tx_port_load. With the cell’s first data
word, you should assert atm_tx_soc high. The master asserts the
atm_tx_port_wait signal for a number of clock cycles after
atm_tx_port_load until the cell starts transmission on the
UTOPIA interface. While it is high, you must not load the port for the
next cell. You can load a new port, and start the cell transfer
simultaneously (see Figure 2).
The local side controls the transfer of data across this interface by
asserting atm_tx_valid high when it is ready to accept data. In
non-pipelined mode, data is transferred when atm_tx_enb and
atm_tx_valid are high. In pipelined mode, data is transferred
when atm_tx_valid is high and the previous value of
atm_tx_enb is high.
Figure 2. Local Transmit Interface Timing Diagram
tx_clk_in
atm_tx_data
H1
H2
H3
P46
XX
P47
P48
H1
H2
atm_tx_soc
atm_tx_enb
atm_tx_enb
(pipelined mode)
atm_tx_valid
atm_tx_port
Address
Address
atm_tx_port_load
38
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Atlantic Slave Transmit Interface
The Atlantic slave transmit interface provides the ability to transmit
ATM cell data along with its associated port (slave) address, ready
for transmission on the UTOPIA bus. To avoid stalling the UTOPIA
transmit interface, a new ATM cell transmission should be initiated
only when the relevant bit of atm_tx_adr_stat is active. The data
path (atm_tx_dat) can operate in either 8- or 16-bit mode, but it
always has the same bus width as the UTOPIA transmit interface.
The cell size can be 52, 53, or 54 bytes long. The Atlantic slave
transmit interface indicates that it can accept data on atm_tx_dat
by asserting atm_tx_dav high. With the cell’s first data word, you
should assert atm_tx_sop high.
The Atlantic slave controls the transfer of data across this interface by
asserting atm_tx_dav high when it is ready to accept data. Data is
transferred when atm_tx_ena is high. To avoid the FIFO buffer
overflowing, the Atlantic master must stop transfering data the clock
cycle after dav transistions low.
Figure 3 shows the Atlantic slave transmit interface timing diagram.
Specifications
Figure 3. Atlantic Slave Transmit Interface Timing Diagram
clk
atm_tx_dat
H1
H2
H3
XX
H4
H5
XX
P47
P48
H1
atm_tx_sop
atm_tx_eop
atm_tx_ena
atm_tx_dav
atm_tx_adr
UTOPIA Receive Interface
The UTOPIA receive interface receives ATM cell data from a
UTOPIA level 2 slave receiver. The interface supports 8- or 16-bit
receive data buses, and SPHY or MPHY modes of operation.
Altera Corporation
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39
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
In MPHY mode, the master polls the various slaves using the
rx_addr bus. It polls the logical addresses ranging from address 0
to the programmed value of rx_addr_range. The slaves respond
by driving their rx_clav output to allow the master to determine
whether they have any cells ready for transfer. The
atm_rx_port_stat and atm_rx_adr_stat output stores the
polling result for each slave address to allow the local transmit
interface to determine which slaves can accept cells. The master then
selects a slave and transfers a complete cell. This behavior is
described in section 4.2 of the UTOPIA Level 2, Version 1.0
specification.
In SPHY mode, the slave indicates that it has a cell ready for transfer
by asserting the rx_clav output. The master subsequently initiates
the transfer of a cell from the slave by asserting rx_enb low. This
behavior is described in section 3 of the UTOPIA Level 2, Version 1.0
specification.
Local Receive Interface
The local receive interface provides the ability to receive ATM cell
data from its associated port (slave) address across the UTOPIA bus.
To avoid stalling the UTOPIA receive interface, a new ATM cell
request should be initiated only when the relevant bit of
atm_rx_port_stat is active. The data path (atm_rx_data) can
operate in either 8- or 16-bit mode, but it always has the same bus
width as the UTOPIA receive interface. The cell size can be 52, 53, or
54 bytes long. Before a cell is received, a new port must be loaded
using atm_rx_port_load. This starts a cell transfer across the
UTOPIA bus when a cell is available. The UTOPIA master asserts the
atm_rx_port_wait signal for a number of clock cycles after
atm_rx_port_load until the cell starts being received across the
UTOPIA interface. While it is high, the port for the next cell should
not be loaded. The local receive interface indicates that cell data is
available on atm_rx_data by asserting atm_rx_valid high;
atm_rx_soc is asserted high when the first data word of the cell is
on atm_rx_data.
The local side controls the transfer of data across this interface by
asserting atm_rx_enb high when it is ready to accept data. In
non-pipelined mode, data is transferred when both atm_rx_enb
and atm_rx_valid are high. In pipelined mode, data is transferred
when atm_rx_valid is high and the previous value of
atm_rx_enb is high.
Figure 4 shows the local receive interface timing diagram.
40
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Figure 4. Local Receive Interface Timing Diagram
rx_clk_in
atm_rx_data
H1
H2
H3
P46
XX
P47
P48
H1
H2
atm_rx_soc
atm_rx_enb
atm_rx_enb
(pipelined mode)
atm_rx_valid
atm_rx_port
Next Port
atm_rx_port_wait
atm_rx_port_load
3
The Atlantic slave receive interface provides the ability to receive
ATM cell data from its associated port (slave) address across the
UTOPIA bus. To avoid stalling the UTOPIA receive interface, a new
ATM cell request should be initiated only when the relevant bit of
atm_rx_adr_stat is active. The data path (atm_rx_dat) can
operate in either 8- or 16-bit mode, but it always has the same bus
width as the UTOPIA receive interface. The cell size can be 52, 53, or
54 bytes long. Before a cell is received, a new port must be loaded
using atm_rx_req_adr_load. This starts a cell transfer across the
UTOPIA bus when a cell is available. The UTOPIA master asserts the
atm_rx_req_adr_wait signal for a number of clock cycles after
atm_rx_adr_load until the cell starts being received across the
UTOPIA interface. While it is high, the port for the next cell should
not be loaded.
The Atlantic slave indicates that it has data available by asserting
atm_rx_dav high. The Atlantic master controls the transfer of data
across this interface by asserting atm_rx_ena high when it is ready
to accept data. When atm_rx_ena is sample asserted, the data
interface signals contains new data during the following clock edge.
atm_rx_val indicates the validity of the data. atm_rx_sop is
asserted high when the first data word of the cell is on atm_rx_dat.
Figure 5 shows the Atlantic slave receive interface timing diagram.
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Specifications
Atlantic Slave Receive Interface
Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 5. Atlantic Slave Receive Interface Timing Diagram
clk
atm_rx_dat
H1
H2
H3
P47
P48
XX
H1
atm_rx_sop
atm_rx_eop
atm_rx_ena
atm_rx_val
atm_rx_dav
atm_rx_adr
XX
atm_rx_req_adr_wait
atm_rx_req_adr_load
atm_rx_req_adr
Atlantic Interface
On the UTOPIA Level 2 MegaCore function the Atlantic interface is
configured to be a slave control interface only.
■
■
A slave sink interface responds to write commands from a
master source interface and behaves like a synchronous FIFO
A master sink interface generates read commands to a slave
source interface and behaves like a synchronous FIFO controller
Figure 6 shows the four different Atlantic interface control options:
■
■
■
■
42
Master source
Slave sink
Master sink
Slave source
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Specifications
Figure 6. Atlantic Interface Control Options
DATA
Atlantic
Interface
Master
(Source)
ENA
Atlantic
Interface
Slave
(Sink)
DAV
Atlantic Interface
DATA
Atlantic
Interface
Master
(Sink)
ENA
VAL
Atlantic
Interface
Slave
(Source)
3
Specifications
DAV
Compatibility
To ensure that individual implementations of an Atlantic interface
are compatible they must have:
■
■
■
■
The same data bus width
Compatible data directions (data source connecting to data sink)
Compatible control interfaces (master interface connecting to
slave interface)
Compatible FIFO threshold levels (slave sink can overflow, and
slave source can operate inefficiently if thresholds are
incorrectly set)
Timing
Figure 7 shows the timing of the Atlantic interface when in master
mode. Figure 8 shows the timing of the Atlantic interface when in
slave mode.
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Specifications
UTOPIA Level 2 Master MegaCore Function User Guide
Figure 7. Atlantic Interface Timing—Slave Source
(1)
(2)
(3)
(4)
(5)
(6)
(7)
clk
dav
ena
val
sop
eop
dat
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Slave (source) indicates that data is available (at least 1 word).
Master (sink) begins reading data.
Master (sink) decides to stop reading the data for one clock cycle. val remains asserted.
Slave (source) indicates that it has less than 1 word available.
Master (sink) continues to read data, validates data with val.
Slave (source) cannot supply any more data, so deasserts val.
Master (sink) goes idle until dav is re-asserted.
Figure 8. Atlantic Interface Timing—Slave Sink
(1)
(2)
(3)
(4)
(5)
(6)
(7)
clk
dav
ena
sop
eop
dat
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Slave (sink) indicates it has space for at least 2 words.
Master (source) begins writing data to the slave (sink).
Slave (sink) indicates it does not have space for 2 words. Master (source) must stop sending data, on the next clock
cycle to ensure that the slave (sink) FIFO does not overflow.
Master (source) stops sending data
Slave (sink) indicates it has space for at least 2 words.
Master (source) begins writing data to the slave (sink).
Slave (sink) indicates it still has space, but the master (source) has run out of data.
44
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Address
Translation
Specifications
The receiver and the transmitter have the option of using a logicalto-physical address translation table. The master, when in MPHY
mode, always polls logical addresses from zero up to
address_range. The address_translation signal can be used
if the master must poll physical addresses that are not contiguous, or
do not start at zero.
When you select address_translation, the IP Toolbench allows
you to map any logical address to any physical address.
Additionally, the address translation table can be implemented
either in ROM or in RAM. If you know what the mappings are, the
IP Toolbench allows the table to be setup and generates ROM.
However, if you want to specify the mappings after using the IP
Toolbench (e.g., if the slave addresses change regularly),
implementing the address translation table in RAM is an option.
When implementing the address translation table in RAM, a
waveform must be generated that loads data into the address
translation table (see Figure 9).
3
Specifications
Figure 9. Translation Table Programming Interface Timing Diagram
tx_clk_in
tx_tt_addr
XXXX
Addr1
Addr2
XXXXX
Addr3
tx_tt_data
XXXX
Data1
Data2
XXXXX
Data3
tx_tt_write
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