UTOPIA Level 2 Slave
MegaCore Function
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Core Version:
Document Version:
Document Date:
2.2.2
2.2.2 rev1
June 2003
UTOPIA Level 2 Slave MegaCore Function User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
UG-UTOPIA_SLAVE-2.3
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
UTOPIA Level 2 Slave MegaCore® function.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the features, including
new features in this release
Refer to the readme file for late-breaking information that is not
available in this user guide
Table 1 shows the user guide revision history.
Table 1. Revision History
Date
How to Find
Information
June 2003
Quartus II version 3.0 information added..
February 2003
Device family support information added.
August 2002
Stratix™ device information added. Using Visual IP models
section added.
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Altera Corporation
Description
®
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
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Numerous links, shown in green text, allow you to jump to related
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About this User Guide
How to Contact
Altera
UTOPIA Level 2 Master MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
UTOPIA Level 2 Master MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The UTOPIA Level 2 Slave MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 2.2.0 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
Performance ....................................................................................................................................12
Getting Started ............................................................................................................................................13
Software Requirements .................................................................................................................13
Design Flow ....................................................................................................................................13
Download & Install the Function ................................................................................................13
Obtaining the UTOPIA Level 2 Slave MegaCore Function .............................................13
Installing the UTOPIA Level 2 Slave Files .........................................................................14
UTOPIA Level 2 Slave Directory Structure ........................................................................15
Set Up Licensing .............................................................................................................................16
Append the License to Your license.dat File ......................................................................16
Specify the Core’s License File in the Quartus II Software ..............................................17
UTOPIA Level 2 Slave Walkthrough ..........................................................................................18
Create a New Quartus II Project ..........................................................................................19
Launch the IP Toolbench ......................................................................................................19
Step 1: Parameterize ..............................................................................................................21
Step 2: Generate ......................................................................................................................23
Simulate the Design .......................................................................................................................25
Set Up the ModelSim Simulation Tool for the VHDL Model ..........................................25
Set Up the ModelSim Simulation Tool for the Verilog HDL Model ..............................25
Simulate with the Visual IP Model ......................................................................................26
Using the Sample VHDL Testbench ....................................................................................27
Configure a Device ........................................................................................................................28
Specifications ..............................................................................................................................................29
Signals ..............................................................................................................................................30
Interfaces .........................................................................................................................................36
UTOPIA Transmit Interface .................................................................................................37
Local Transmit Interface .......................................................................................................37
Altera Corporation
vii
Contents
UTOPIA Receive Interface ....................................................................................................38
Local Receive Interface ..........................................................................................................38
Atlantic Interface ....................................................................................................................39
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 1 provides information about this release of the UTOPIA Level 2
Slave MegaCore function.
Table 1. UTOPIA Level 2 Slave Release Information
Item
Version
Device Family
Support
2.2.2
Release Date
June 2003
Ordering Code
IP-UTOPIA2SL
Product ID(s)
0016
Vendor ID(s)
6AF7
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software
9
About this Core
UTOPIA Level 2 Slave MegaCore Function User Guide
Table 2 shows the level of support offered by the UTOPIA Level 2 Slave
MegaCore function to each of the Altera device families.
Table 2. Device Family Support
Device Family
™
Stratix GX
™
Support
Full
Cyclone
Full
Stratix™
Full
Mercury™
™
Full
Excalibur
Full
HardCopy™
Full
®
ACEX 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera UTOPIA Level 2 Slave MegaCore function is is designed for
use PHY devices that transfer data to and from asynchronous transfer
mode (ATM) devices using the standard UTOPIA bus.
New in Version
2.2.2
■
Support for the Quartus II software version 3.0
Features
■
■
■
Conforms to the UTOPIA Level 2, Version 1.0 specification
8- or 16-bit UTOPIA bus operation and local bus widths of 8 or 16 bits
Single physical layer (SPHY) operation, with both octet- and cell-level
handshaking
Multi-PHY (MPHY) operation, with a single clav signal
Parity generation and detection
Optional cell discard on parity error detection
Internal 4-cell first-in first-out (FIFOs) buffers supported for both
transmit and receive
Atlantic™ interface—packet-based interface that is compatible with
other Altera cell and packet MegaCore functions
Includes simulation models for the ModelSim simulation tool
OpenCore® feature allows designers to instantiate and simulate
designs in the Quartus® II software prior to purchase
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Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
The UTOPIA Level 2 Slave MegaCore function comprises a separate
transmitter and receiver; both support SPHY and MPHY operation
modes. SPHY mode supports octet- or cell-level handshake; MPHY mode
supports cell-level handshake.
The transmitter is polled by the ATM layer to determine whether it is
ready to receive data transfers. The transmitter accepts cells from the ATM
layer via the UTOPIA bus interface, and sends them to the PHY devices.
It detects and discards cells that are too short, and discards excess bytes
from cells that are too long. It also checks for parity errors on the UTOPIA
bus, and there is an option to discard cells with detected parity errors.
The receiver is polled by the ATM layer to determine whether it is ready
to transfer data. The receiver accepts cells from the PHY, and sends them
to the ATM layer device via the UTOPIA bus interface. There is an option
to generate parity information for the UTOPIA bus.
Figure 1 shows the UTOPIA MegaCore function block diagram.
Figure 1. UTOPIA MegaCore Function Block Diagram
Port 0
PHY
UTOPIA
Slave
Function
ATM Layer
UTOPIA
Master
Function
Port N
PHY
SAR/
Switch
UTOPIA
Slave
Function
The Atlantic interface allows a consistent interface between all Altera cell
and packet MegaCore functions. The Atlantic interface is only designed to
support a point-to-point connection. You must choose whether you use
the local or Atlantic interface. Figure 2 shows examples of the Atlantic
interface.
Altera Corporation
11
1
About this Core
General
Description
About this Core
About this Core
UTOPIA Level 2 Slave MegaCore Function User Guide
Figure 2. Atlantic Interface
Atlantic Interface
UTOPIA
Interface
Cell
Processor
UTOPIA
Interface
ATM
Processor
Atlantic Interface
f
Performance
For more information on the Atlantic interface, refer to the Atlantic
Interface Functional Specification.
The performance information in Tables 3 and 4 was generated with the
Quartus II software version 2.1, for APEX 20K and Stratix devices..
Table 3. Transmitter Performance
Parameters
LEs
Memory Performance
(1)
(MHz)
Device
16-bit local/UTOPIA width, 54 bytes local cell size, MPHY
mode, using parity_check and
pipeline_user_interface.
252
1
136
EP20K30E7C144-1
8-bit local/UTOPIA width, 52 bytes local cell size, MPHY
mode, using parity_check and discard_on_error.
286
1
115
EP20K30E7C144-1
16-bit local/UTOPIA width, 54 bytes local cell size, MPHY
mode, using parity_check and
pipeline_user_interface.
217
1
233
EP1S25B672C6
8-bit local/UTOPIA width, 52 bytes local cell size, MPHY
mode, using parity_check and discard_on_error.
250
1
205
EP1S25B672C6
Note:
(1)
12
M4K RAM blocks for Stratix devices; ESBs for all other devices.
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
About this Core
1
Parameters
LEs
Memory Performance
(1)
(MHz)
Device
16-bit local/UTOPIA width, 54 bytes local cell size, MPHY
mode, using parity_check and
pipeline_user_interface.
238
1
106
EP20K30E7C144-1
8-bit local/UTOPIA width, 52 bytes local cell size, MPHY
mode, using parity_check and discard_on_error.
258
1
92
EP20K30E7C144-1
16-bit local/UTOPIA width, 54 bytes local cell size, MPHY
mode, using parity_check and
pipeline_user_interface.
201
1
167
EP1S25B672C6
8-bit local/UTOPIA width, 52 bytes local cell size, MPHY
mode, using parity_check and discard_on_error.
253
1
153
EP1S25B672C6
Note:
(1)
M4K RAM blocks for Stratix devices; ESBs for all other devices.
Altera Corporation
13
About this Core
Table 4. Receiver Performance
Notes:
Getting Started
Software
Requirements
This section requires the following software:
■
■
A PC running the Windows 98/NT/2000 operating system
Quartus II version 2.1 or higher
Design Flow
This walkthrough involves the following steps:
1.
Download and install the MegaCore function.
2.
Generate a custom MegaCore function using the IP Toolbench.
3.
Implement your system using AHDL, VHDL, or Verilog HDL.
4.
Compile your design.
5.
Simulate your design to confirm the operation of your system.
6.
License the MegaCore function and configure the devices.
1
Download &
Install the
Function
This document assumes that you are using a PC with the
Windows operating system. However, you can also use the
UTOPIA Level 2 Slave MegaCore function on UNIX platforms.
The IP Toolbench is a toolbar from which you can quickly and
easily view documentation, specify core parameters, set up
third-party tools, and generate all files necessary for integrating
the parameterized core into your design.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining the UTOPIA Level 2 Slave MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at www.altera.com. Follow the instructions below to
obtain the UTOPIA Level 2 Slave via the Internet. If you do not have
Internet access, you can obtain the UTOPIA Level 2 Slave from your local
Altera representative.
Altera Corporation
13
Getting Started
1
2
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Type UTOPIA in the Keyword Search box.
4.
Click Go.
5.
Click the link for the Altera UTOPIA Level 2 Slave MegaCore
function in the search results table. The product description web
page displays.
6.
Click the Free Test Drive graphic on the top right of the product
description web page.
7.
Fill out the registration form, read the license agreement, and click
I Agree at the bottom of the page.
8.
Follow the instructions on the UTOPIA Level 2 Slave download and
installation page to download the function and save it to your hard
disk.
Installing the UTOPIA Level 2 Slave Files
For Windows, perform the following steps:
14
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The UTOPIA Level 2 Slave Installation dialog box
appears. Follow the on-line instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the directory in which you installed them
(e.g., <path>/utopia2_slave-<version>\lib) as a user library in the
Quartus II software. Search for “User Libraries” in Quartus II Help
for instructions on how to add these libraries.
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
UTOPIA Level 2 Slave Directory Structure
Figure 1 shows the directory structure for the UTOPIA Level 2 Slave.
Figure 1. UTOPIA Level 2 Slave Directory Structure
megacore
utopia2_slave-<version>
Contains the UTOPIA Slave MegaCore function files and documentation.
2
doc
Contains the documentation for the core.
sim_lib
Contains the simulation models provided with the core.
modelsim_verilog
Contains the pre-compiled Verilog HDL model for the ModelSim simulation tool.
modelsim_vhdl
Contains the pre-compiled VHDL model for the ModelSim simulation tool.
testbench
Contains the sample VHDL testbench and configuration files for the models.
vip_models
Contains the Visual IP models.
Altera Corporation
15
Getting Started
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
Getting Started
Set Up
Licensing
UTOPIA Level 2 Slave MegaCore Function User Guide
You can use Altera’s OpenCore feature to compile and simulate the
UTOPIA Level 2 Slave MegaCore function, allowing you to evaluate it
before purchasing a license. You can simulate your design in the Quartus
II software using the OpenCore feature. However, you must obtain a
license from Altera before you can generate programming files or EDIF,
VHDL, or Verilog HDL gate-level netlist files for simulation in third-party
EDA tools.
After you purchase a license for the UTOPIA Level 2 Slave core, you can
request a license file from the Altera web site at
www.altera.com/licensing and install it on your PC. When you request a
license file, Altera e-mails you a license.dat file. If you do not have
Internet access, contact your local Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the UTOPIA Level 2 Slave core,
you must already have the Quartus II software installed on your
PC with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the UTOPIA Level 2 Slave core license file in a text editor. The
file should contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the UTOPIA Level 2 Slave core license
file and paste it into the Quartus II license file.
1
16
Do not delete any FEATURE lines from the Quartus II license
file.
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
5.
Getting Started
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Altera Corporation
2
Create a text file with the FEATURE line and save it to your hard disk.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
17
Getting Started
1.
Getting Started
UTOPIA Level 2
Slave
Walkthrough
UTOPIA Level 2 Slave MegaCore Function User Guide
This walkthrough explains how to create a custom core using the Altera
UTOPIA Level 2 Slave IP Toolbench and the Quartus II software. As you
go through the IP Toolbench, each page is described in detail. When you
are finished generating a custom core, you can incorporate it into your
overall project.
This walkthrough consists of the following steps:
■
■
■
■
18
“Create a New Quartus II Project” on page 19
“Launch the IP Toolbench” on page 19
“Step 1: Parameterize” on page 21
“Step 2: Generate” on page 23
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the UTOPIA Level 2 Slave user library. To create a
new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction does not display if
you turned it off previously).
4.
Specify the working directory for your project. This walkthrough
uses the directory d:\temp\example
5.
Specify the name of the project. This walkthrough uses example.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\utopia2_slave-<version>\lib\ into the Library
name box, where <path> is the directory in which you installed the
UTOPIA Level 2 Slave. The default installation directory is
c:\megacore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the IP Toolbench
The MegaWizard Plug-In Manager allows you to run the IP Toolbench
that helps you easily specify options for the UTOPIA Level 2 Slave. To
launch the IP Toolbench, perform the following steps:
Altera Corporation
19
Getting Started
2.
2
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
1.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
f
Refer to the Quartus II Help for more information on how to use
the MegaWizard Plug-In Manager.
2.
Specify that you want to create a new custom megafunction and
click Next.
3.
Select UTOPIA Level 2 Master-<version> in the Communications >
UTOPIA directory.
4.
Choose the output file type for your design; the wizard supports
AHDL, VHDL, and Verilog HDL.
5.
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 2 shows the wizard after you have made
these settings.
<variation name> and <directory name> must be the same name and the
same directory that your Quartus II project uses.
Figure 2. Select the MegaCore Function
20
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
Step 1: Parameterize
To parameterize your core, perform the following steps:
1.
Click Step 1: Parameterize in the IP Toolbench (see Figure 3).
Figure 3. IP Toolbench
2
Getting Started
Altera Corporation
2.
Choose the device family (see Figure 4).
3.
Select whether you wish to create a transmitter or receiver (see
Figure 4). Click Next.
4.
If you require an Atlantic local interface, turn on the Atlantic Local
Interface check box.
21
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
Figure 4. Select a Transmitter or Receiver
5.
22
Choose the parameters that define the specific UTOPIA master
MegaCore function you wish to implement (see Figure 5). See Table 1
on page 29 for a description of the parameters. The IP Toolbench
allows you to select only legal combinations of parameters. Click
Next when you are finished.
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
Figure 5. Select the Parameters
2
Getting Started
Step 2: Generate
To generate your core, perform the following steps:
1.
Altera Corporation
Click Step 2: Generate in the IP Toolbench (see Figure 6).
23
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
Figure 6. IP Toolbench—Generate
2.
The generation report lists the design files that the IP Toolbench
creates (see Figure 7). Click Exit IP Toolbench.
Figure 7. IP Toolbench-Generated Files
24
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
When you have created a custom megafunction, you can integrate it into
your system design and compile.
Simulate the
Design
Altera provides ModelSim VHDL and Verilog HDL models that you can
use to simulate the MegaCore function in your system. The models are
supplied as pre-compiled libraries for the ModelSim simulator and are
installed in the sim_lib\modelsim_vhdl and sim_lib\modelsim_vhdl
directories. Altera also provides a Visual IP model in the
sim_lib\vip_models directory, which you can use with the Visual IP
software and is supported by other Verilog HDL and VHDL simulators.
You can integrate these models into your system, speeding simulation.
The pre-compiled VHDL model that is provided with the MegaCore
function is installed in the sim_lib\modelsim_vhdl directory. To set up
your system to use the UTOPIA slave model, perform the following steps.
1.
Run the ModelSim software and create a logical map called altuts to
the folder containing the compiled library by typing the following
command in the ModelSim software:
vmap altuts <Drive:>/<MegaCore Path>
/sim_lib/modelsim_vhdl/altuts
1
2.
You can also use the ModelSim graphical user interface (GUI) to
create a logical map. Refer to the ModelSim online Help for
details.
You must refresh the compiled library by typing the command:
vcom -work altuts -refresh
Set Up the ModelSim Simulation Tool for the Verilog HDL Model
The pre-compiled Verilog HDL model is provided with the MegaCore
function and is installed in the sim_lib\modelsim_verilog folder. To set
up your system to use the UTOPIA slave model, perform the following
steps.
1.
Run the ModelSim software and create a logical map called altuts to
the folder containing the compiled library by typing the following
command in the ModelSim software:
vmap altuts <Drive:>/<MegaCore Path>
/sim_lib/modelsim_verilog/altuts
Altera Corporation
25
Getting Started
Set Up the ModelSim Simulation Tool for the VHDL Model
2
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
1
2.
You can also use the ModelSim graphical user interface (GUI) to
create a logical map. Refer to the ModelSim online Help for
details.
You must refresh the compiled library by typing the command:
vlog -work altuts -refresh
Simulate with the Visual IP Model
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
1.
Point your web browser at
https://www.altera.com/support/software/download/eda_softw
are/visualip/dnl-visualip.jsp.
2.
Follow the on-line instructions to download the Innoveda Visual IP
software and save it to your hard disk.
To use the Visual IP model, perform the following steps:
1.
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Compile the wrapper for the core model.
The Verilog HDL version of the wrapper is in the
sim_lib\vip_models\<model name>\interface\pli directory;
the corresponding VHDL version is in the
sim_lib\vip_models\<model name>\interface\mti directory.
1
3.
Where <model_name> is slaverx, slaverx_atlantic, slavetx, or
slavetx_atlantic. For Stratix devices use <model name>_sba.
Compile the wizard-generated wrapper <variation name>.vhd,
<variation name>.v.
The Visual IP model is now ready for use in your simulator.
26
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Getting Started
Using the Sample VHDL Testbench
1
To use the sample VHDL testbench, the UTOPIA master and
slave MegaCore functions must be available and both setup for
ModelSim. See “Set Up the ModelSim Simulation Tool for the
VHDL Model” on page 25, and the UTOPIA Level 2 Master
MegaCore Function User Guide.
1.
Choose Change Directory (Design menu).
2.
Select Create a New Library (Design Menu). Select a new library and
a logical mapping to it. In the Library Box type work.
3.
In the Compile HDL Source Files dialog box, select the library work
in the Library drop-down list box. Also select the
\sim_lib\vhdl\testbench folder in the Look In drop-down list box.
4.
Select master_tb_pack.vhd and click Compile. Select
slave_user_if.vhd and click Compile. Select master_tb.vhd and
click Compile.
5.
When the compilation finishes, click Done. You are now ready to run
the simulation.
You can load a configuration from the command line in the ModelSim
simulation tool, for example:
vsim -GPHYMode=\”SPHYCellHandshake\” -Gnum_slaves=1
-GUserCellSize=52 master_tb
You can also use the ModelSim graphical user interface to load the
configuration. Refer to the ModelSim online Help for details.
Altera Corporation
27
2
Getting Started
In addition to the models, Altera provides a sample VHDL testbench (in
the sim_lib\testbench folder). This VHDL testbench provides you with
the ability to easily simulate several different configurations (e.g., single
slave vs. multiple slaves). To use the models, you must first instantiate
them in your system. The testbench is master_tb. It comprises a master
(receiver and transmitter), and a configurable number of slaves (receivers
and transmitters). The testbench includes some simple stimulus to control
the user interfaces of the MegaCore functions and to transfer ATM cells
across the UTOPIA bus. Various parameters may be set to control the
testbench operating mode, including PHY mode, UTOPIA bus width,
operating frequencies, and number of slaves. To compile these files in the
ModelSim software, follow the steps below:
Getting Started
UTOPIA Level 2 Slave MegaCore Function User Guide
To instantiate the Verilog HDL model in your system, you can instantiate
the parameterized models by using the sample testbench as a template.
Configure a
Device
28
After you have compiled and analyzed your design, you are ready to
configure your target Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must obtain a license from
Altera. You can then generate output files (.edo, .vho, .vo, or .sdo) or a
netlist for use in your third-party EDA tool for post-route, device-level,
and system-level simulation.
Altera Corporation
Specifications
Table 1 shows the MegaCore function’s parameters.
Table 1. Parameters
Parameter
Values
Type
Description
8 or 16
Fixed or
programmable
Width of the UTOPIA data bus.
user_bus_width
8 or 16
Fixed or
programmable
Width of the local data bus.
discard_on_error
Yes or no
Fixed or
programmable
Determines whether cells with errors are
discarded on reception. Cells that are
received with parity errors on the UTOPIA
transmit interface are discarded.
3
Specifications
utopia_bus_width
parity_check
Yes or no
Fixed or
programmable
Determines whether UTOPIA bus parity is
checked. This parameter controls the
creation of parity logic in the transmit
direction.
parity_generate
Yes or no
Fixed or
programmable
Determines whether UTOPIA bus parity is
generated. This parameter controls the
creation of parity logic in the receive
direction.
sphy_mode
Yes or no
Fixed or
programmable
Determines whether operation is in UTOPIA
1 compatibility mode (i.e., interfacing with a
single PHY).
slave_address
0 to 30
Fixed or
programmable
Determines the address of the UTOPIA
slave.
52/53/54_byte_cells
52, 53, or 54
Fixed or
programmable
Determines whether operation is with cells of
52, 53 (1), or 54 bytes on the local interface
side. In 52-byte cells, the user defined (UDF)
field has been removed.
Fixed
Determines whether operation is in pipelined
or non-pipelined mode. (2)
pipeline_user_interface Yes or no
Notes:
(1)
(2)
53-byte cells only supported in 8-bit local bus mode.
Pipelined is the recommended mode; however, the non-pipelined mode is provided.
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29
Specifications
Signals
UTOPIA Level 2 Slave MegaCore Function User Guide
The MegaCore function uses the following signals:
■
■
■
Input—Standard input-only signal.
Output—Standard output-only signal.
Tri-state—Tri-state input/output signal.
Figure 1 shows the MegaCore function’s signal block diagram.
Figure 1. Signal Block Diagram
UTOPIA Bus
transmit
receive
Local Bus
UTOPIA
Slave
Function
transmit
receive
parameters
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Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
Table 2 shows the UTOPIA transmit interface signal definitions.
Table 2. UTOPIA Transmit Interface
Name
Type
Description
Input
Transmit data. When in 8-bit mode, tx_data[7:0] is used.
tx_soc
Input
Start of cell indicator. Active-high signal asserted when tx_data
contains the first word of the cell.
tx_enb
Input
Enable. Active-low signal asserted when tx_data contains valid data.
tx_clav
Output
Cell available. Active-high signal asserted when the slave interface is
ready to receive another cell.
tx_clav_enb
Output
Output enable signal for tx_clav. When high, the tx_clav output
buffer should be enabled. When low, the output buffer should be
tri-stated.
tx_prty
Input
Parity. The parity bit over tx_data[7:0] in 8-bit mode, and
tx_data[15:0] in 16-bit mode (optional).
tx_addr[4:0]
Input
Address. Five-bit-wide address used in MPHY mode to poll and select
the correct PHY device.
tx_prty_pulse
Output
Active-high 1 cycle pulse, indicating a parity error has been detected.
tx_cell_pulse
Output
Active-high 1 cycle pulse, indicating a cell has been received.
tx_cell_err_pulse
Output
Active-high 1 cycle pulse, indicating an illegal length cell has been
received.
tx_cell_disc_pulse
Output
Active-high 1 cycle pulse, indicating a cell has been discarded due to
the detection of a parity error or an incorrect length (short) cell.
tx_clk
Input
Transmit clock. All signals on this interface are synchronous to it.
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31
3
Specifications
tx_data[15/7:0]
Specifications
UTOPIA Level 2 Slave MegaCore Function User Guide
Table 3 shows the local transmit interface signal definitions.
Table 3. Local Transmit Interface
Name
Type
Description
phy_tx_data[15/7:0]
Output
Data output for transmit data. When in 8-bit mode,
phy_tx_data[7:0] is used.
phy_tx_soc
Output
Active-high signal asserted when phy_tx_data contains the first
word of the cell.
phy_tx_valid
Output
Active-high signal asserted when valid cell data is present on
phy_tx_data.
phy_tx_enb
Input
Active-high signal asserted when the local interface is ready to accept
cell data.
phy_tx_fifo_full
Output
Active-high signal asserted when the receive FIFO buffer is full.
phy_tx_clav
Output
Active high signal asserted when there is at least one more complete
cell in the FIFO. Valid four cycles after the start of a cell.
phy_tx_clk
Input
Local transmit interface clock. All signals on this interface are
synchronous to it.
Table 4 shows the Atlantic transmit interface signal definitions.
Table 4. Atlantic Transmit Interface (Part 1 of 2)
Name
Type
Description
phy_tx_dat[15/7:0]
Output
Data bus.
This bus carries the packet octets that are transferred across the
interface.
The data is transmitted in big endian order on phy_tx_dat. The data
is sent most significant bit (MSB) first and all valid bits are contiguous
with the MSB.
phy_tx_sop
Output
Start of packet signal.
phy_tx_sop is used to delineate the packet boundaries on the
phy_tx_dat bus. When phy_tx_sop is high, the start of the packet
is present on the dat bus.
phy_tx_sop is required to be present at the beginning of every
packet.
phy_tx_eop
Output
End of packet signal.
phy_tx_eop is used to delineate the packet boundaries on the
phy_tx_dat bus. When phy_tx_eop is high, the end of the packet
is present on the phy_tx_dat bus.
phy_tx_eop is required to be present at the end of every packet.
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UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
Table 4. Atlantic Transmit Interface (Part 2 of 2)
Name
Type
Description
Output
Error indicator signal.
phy_tx_err is used to indicate that the current packet is aborted and
should be discarded. phy_tx_err can be asserted at any time during
the current packet, but when asserted it can only be de-asserted on the
clock cycle after phy_tx_eop is asserted.
phy_tx_val
Output
Data valid signal.
phy_tx_val indicates the validity of the data signals.
phy_tx_val is updated on every clock edge where phy_tx_ena is
sampled asserted, and holds it’s current value along with the
phy_tx_dat bus where ena is sampled de-asserted.
When phy_tx_val is asserted, the Atlantic data interface signals are
valid.
When phy_tx_val is de-asserted, the Atlantic data interface signals
are invalid and must be disregarded.
To determine whether new data has been received, the master must
qualify the phy_tx_val signal with the previous state of the
phy_tx_ena signal.
phy_tx_ena
Input
Enable signal.
phy_tx_ena is driven by a master interface, and used to control the
flow of data across the interface.
phy_tx_ena behaves as a read enable from master to slave.
When phy_tx_ena is sampled asserted, the Atlantic data interface
signals contain new data during the following clock edge. phy_tx_val
indicates the validity of the data.
The Atlantic data interface signals get new data on every clock cycle,
if phy_tx_ena is asserted.
phy_tx_dav
Output
Data available signal.
If phy_tx_dav is high, the slave FIFO has at least one cell available
to be read, or the data can be read up to an end of packet without risk
of underflow.
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3
Specifications
phy_tx_err
Specifications
UTOPIA Level 2 Slave MegaCore Function User Guide
Table 5 shows the UTOPIA receive interface signal definitions.
Table 5. UTOPIA Receive Interface
Name
Type
Description
rx_data[15/7:0]
Output
Receive data. When in 8-bit mode, rx_data[7:0]is used.
rx_soc
Output
Start of cell indicator. Active-high signal asserted when rx_data
contains the first word of the cell.
rx_prty
Output
Parity. The parity bit over rx_data[7:0]in 8-bit mode, and
rx_data[15:0]in 16-bit mode (optional).
rx_bus_enb
Output
Output enable signal for the rx_data, rx_soc, and rx_prty signals.
When high, the output buffers should be enabled. When low, the output
buffers should be tri-stated.
rx_enb
Input
Enable. Active-low signal asserted to enable the PHY device to drive
data on rx_data.
rx_clav
Output
Cell available. Active-high signal asserted when another cell is ready
to be sent.
rx_clav_enb
Output
Output enable signal for rx_clav. When high, the rx_clav output
buffer should be enabled. When low, the output buffer should be
tri-stated.
rx_addr[4:0]
Input
Address. Five-bit-wide address used in MPHY mode to poll and select
the correct PHY device.
rx_clk
Input
Receive clock. All signals on this interface are synchronous to it.
Table 6 shows the local receive interface signal definitions.
Table 6. Local Receive Interface
Name
Type
Description
phy_rx_data[15/7:0]
Input
Data input for receive data. When in 8-bit mode,
phy_rx_data[7:0]is used.
phy_rx_soc
Input
Active-high signal asserted when phy_rx_data contains the first
word of the cell.
phy_rx_valid
Input
Active-high signal asserted when valid cell data is present on
phy_rx_data.
phy_rx_enb
Output
Active-high signal asserted when the local interface is ready to accept
cell data. This signal goes low when the receive FIFO buffer is full.
phy_rx_clav
Output
Active high signal asserted when there is space for at least one more
complete cell in the FIFO. Valid four cycles after the start of a cell.
phy_rx_clk
Input
local receive interface clock. All signals on this interface are
synchronous to it.
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Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
Table 7 shows the Atlantic receive interface signal definitions.
Table 7. Atlantic Receive Interface
Name
Type
Description
Input
Data bus.
This bus carries the packet octets that are transferred across the
interface.
The data is transmitted in big endian order on phy_rx_dat. The data is
sent most significant bit (MSB) first and all valid bits are contiguous with
the MSB.
phy_rx_sop
Input
Start of packet signal.
phy_rx_sop is used to delineate the packet boundaries on the
phy_rx_dat bus. When phy_rx_sop is high, the start of the packet is
present on the phy_rx_dat bus.
phy_rx_sop is required to be present at the beginning of every packet.
phy_rx_eop
Input
End of packet signal.
phy_rx_eop is used to delineate the packet boundaries on the
phy_rx_dat bus. When phy_rx_eop is high, the end of the packet is
present on the phy_rx_dat bus.
phy_rx_eop is required to be present at the end of every packet.
phy_rx_err
Input
Error indicator signal.
phy_rx_err is used to indicate that the current packet is aborted and
should be discarded. phy_rx_err can be asserted at any time during
the current packet, but when asserted it can only be de-asserted on the
clock cycle after phy_rx_eop is asserted.
Conditions that can cause phy_rx_err to be set can be, but are not
limited to, FIFO overflow and abort sequence detection.
phy_rx_ena
Input
Enable signal.
phy_rx_ena is driven by a master interface, and used to control the flow
of data across the interface.
phy_rx_ena behaves as a write enable from master to slave.
When ena is sampled asserted, the Atlantic data interface signals are
valid and are transferred across the interface on the following rising edge
of clk.
The Atlantic data interface signals get new data on every clock cycle, if
ena is asserted.
phy_rx_dav
Output
Data available signal.
If phy_rx_dav is high, the slave FIFO has enough space for another one
cell to be written.
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35
3
Specifications
phy_rx_dat[15/7:0]
Specifications
UTOPIA Level 2 Slave MegaCore Function User Guide
Table 8 shows the configuration interface signal definitions.
Table 8. Configuration Interface
Name
Type
Description
tx_phy_mode
Input
0 = MPHY mode; 1 = SPHY mode.
phy_tx_pipe_mode
Input
0 = Non-pipelined mode; 1 = pipelined mode.
tx_ut_width
Input
1 = 16-bit UTOPIA transmit bus width.
0 = 8-bit UTOPIA transmit bus width.
tx_user_width
Input
1 = 16-bit local transmit bus width.
0 = 8-bit local transmit bus width.
tx_user_bytes[1:0]
Input
Defines the size of the cells at the local transmit interface.
8-bit local transmit bus: 00 = 52 bytes; 01 = 53 bytes; 1x = 54 bytes.
16-bit local transmit bus: 0x = 52 bytes; 1x = 54 bytes.
tx_address[4:0]
Input
Transmit port address in MPHY mode.
tx_discard_on_error
Input
0 = Transmit cells not discarded on detecting a parity error.
1 = Transmit cells discarded on detecting a parity error.
tx_parity_check
Input
Enables parity checking on the UTOPIA bus when high.
rx_parity_generate
Input
Enables parity generation on the UTOPIA bus when high.
rx_phy_mode
Input
0 = MPHY mode; 1 = SPHY mode.
phy_rx_pipe_mode
Input
0 = Non-pipelined mode; 1 = pipelined mode.
rx_ut_width
Input
1 = 16-bit UTOPIA receive bus width.
0 = 8-bit UTOPIA receive bus width.
rx_user_width
Input
1 = 16-bit local receive bus width.
0 = 8-bit local receive bus width.
rx_user_bytes[1:0]
Input
Defines the size of the cells at the local receive interface.
8-bit local receive bus: 00 = 52 bytes; 01 = 53 bytes; 1x = 54 bytes.
16-bit local receive bus: 0x = 52 bytes; 1x = 54 bytes.
rx_address[4:0]
Input
Receive port address in MPHY mode.
rx_parity_generate
Input
Enables parity generation on the UTOPIA bus when high.
reset
Input
System reset. Active-low.
Interfaces
This section describes the following interfaces:
■
■
■
■
■
36
UTOPIA transmit
Local transmit
UTOPIA receive
Local receive
Atlantic
Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
UTOPIA Transmit Interface
The UTOPIA transmit interface receives ATM cell data from a
UTOPIA level 2 master transmitter. The interface supports 8- or
16-bit transmit data buses, and SPHY or MPHY modes of operation.
Any cells that are too short are discarded, and any cells that are too
long have their excess bytes discarded. If discard_on_error is
enabled, any parity errors detected on tx_data causes the cell to be
discarded. The interface contains several statistic ‘pulse’ outputs,
which can be used to count parity errors, cells received, illegal length
cells, and discarded cells.
In MPHY mode, a UTOPIA master polls the various UTOPIA slaves
using tx_addr. The slaves respond by driving their tx_clav
output to allow the master to determine whether they can accept a
cell transfer. The master then selects a slave and transfers a complete
cell. This behavior is described in section 4.2 of the UTOPIA Level 2,
Version 1.0 specification.
The received ATM cell data is written into the rate-matching fourcell deep transmit FIFO buffer ready to be accessed by the local
transmit interface.
Local Transmit Interface
The local transmit interface provides access to read the received
ATM cell data from the transmit FIFO buffer in a variety of different
cell formats. The data path (phy_tx_data) can operate either in 8or 16-bit mode. The cell size can be 52, 53, or 54 bytes long. The local
transmit interface indicates that cell data is available on
phy_tx_data by asserting phy_tx_valid high. phy_tx_soc is
also asserted high with the first data word of the cell.
The local side controls the transfer of data across this interface by
asserting phy_tx_enb high when it is ready to accept data. In
non-pipelined mode, data is transferred when both phy_tx_enb
and phy_tx_valid are high. In pipelined mode, data is transferred
when phy_tx_valid is high and the previous value of
phy_tx_enb is high.
If further cells remain in the transmit FIFO buffer, back-to-back cells
may be transferred by keeping phy_tx_enb high (see Figure 2).
Altera Corporation
37
3
Specifications
In SPHY mode, the slave indicates that it can accept a cell transfer by
asserting tx_clav. The master subsequently transmits a cell to the
slave by asserting tx_enb low. This behavior is described in section
3 of the UTOPIA Level 2, Version 1.0 specification.
Specifications
UTOPIA Level 2 Slave MegaCore Function User Guide
Figure 2. local Transmit Interface Timing
phy_clk
phy_tx_data
H1
H2
H3
P47
P48
XX
XX
H1
H2
phy_tx_soc
phy_tx_enb
phy_tx_enb
(pipelined mode)
phy_tx_valid
UTOPIA Receive Interface
The UTOPIA receive interface transmits ATM cell data to a UTOPIA
level 2 master receiver. The interface supports 8- or 16-bit receive
data buses, and SPHY or MPHY modes of operation.
In MPHY mode, a UTOPIA level 2 master polls the various UTOPIA
level 2 slaves using rx_addr. The slaves respond by driving their
rx_clav output, to allow the master to determine whether they
have any cells ready for transfer. The master then selects a slave and
transfers a complete cell. This behavior is described in section 4.2 of
the UTOPIA Level 2, Version 1.0 specification.
In SPHY mode, the slave indicates that it has a cell ready for transfer
by asserting rx_clav. The master subsequently initiates the transfer
of a cell from the slave by asserting rx_enb low. This behavior is
described in section 3 of the UTOPIA Level 2, Version 1.0 specification.
Local Receive Interface
The local receive interface provides access to fill the receive FIFO
buffer with ATM cell data that is ready to be transmitted on the
UTOPIA bus. The data path (phy_rx_data) can operate either in 8or 16-bit mode. The cell size can be 52, 53, or 54 bytes long. The local
receive interface is notified that cell data is available on
phy_rx_data by asserting phy_rx_valid high. phy_rx_soc
should also be asserted high with the first data word of the cell.
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Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
The local receive interface controls the transfer of data across this
interface by asserting phy_rx_enb high when it is ready to accept
data. In non-pipelined mode, data is transferred when both
phy_rx_enb and phy_rx_valid are high. In pipelined mode, data
is transferred when phy_rx_valid is high and the previous value
of phy_rx_enb is high.
If further space for cells remains in the receive FIFO buffer (i.e.,
phy_rx_enb is high), back-to-back cells may be transferred by
keeping phy_rx_valid high and supplying continuous cell data
(see Figure 3).
Figure 3. local Receive Interface Timing
rx_clk_in
phy_rx_data
H1
H2
XX
H3
P47
P48
XX
H1
H2
phy_rx_soc
3
phy_rx_enb
Specifications
phy_rx_enb
(pipelined mode)
phy_rx_valid
Atlantic Interface
On the UTOPIA level 2 MegaCore function the Atlantic interface is
configured to be a slave control interface.
■
■
A slave sink interface responds to write commands from a
master source interface and behaves like a synchronous FIFO
A master sink interface will generate read commands to a slave
source interface and behaves like a synchronous FIFO controller
Figure 4 shows the four different Atlantic interface control options:
■
■
■
■
Altera Corporation
Master source
Slave sink
Master sink
Slave source
39
Specifications
UTOPIA Level 2 Slave MegaCore Function User Guide
Figure 4. Atlantic Interface Control Options
DATA
Atlantic
Interface
Master
(Source)
ENA
Atlantic
Interface
Slave
(Sink)
DAV
Atlantic Interface
DATA
Atlantic
Interface
Master
(Sink)
ENA
VAL
Atlantic
Interface
Slave
(Source)
DAV
Compatibility
To ensure that individual implementations of an Atlantic interface
are compatible they must have:
■
■
■
■
The same data bus width
Compatible data directions (data source connecting to data sink)
Compatible control interfaces (master interface connecting to
slave interface)
Compatible FIFO threshold levels (slave sink can overflow, and
slave source can operate inefficiently if thresholds are
incorrectly set)
Timing
Figure 5 shows the timing of the Atlantic interface when in master
mode. Figure 6 shows the timing of the Atlantic interface when in
slave mode.
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Altera Corporation
UTOPIA Level 2 Slave MegaCore Function User Guide
Specifications
Figure 5. Atlantic Interface Timing—Slave Source
(1)
(2)
(3)
(4)
(5)
(6)
(7)
clk
dav
ena
val
sop
eop
dat
Notes:
(1)
(2)
(3)
(4)
Figure 6. Atlantic Interface Timing—Slave Sink
(1)
(2)
(3)
(4)
(5)
(6)
(7)
clk
dav
ena
sop
eop
dat
Notes:
(1)
(2)
(3)
(4)
Slave (sink) indicates it has space for at least 1 cell.
Master (source) begins writing data to the slave (sink).
Slave (sink) indicates it does not have space for 1 cell. Master (source) may continue to send data, but must ensure
that the slave (sink) FIFO does not overflow. By setting the slave (sink) threshold to a suitable value, the requirement
on the master (source) to stop immediately is removed. Setting a small threshold can be used to counter for pipeline
delays; setting a large threshold may be useful if the master (source) is capable of transferring data in bursts.
Master (source) stops sending data
Altera Corporation
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3
Specifications
(5)
(6)
(7)
Slave (source) indicates that data is available (at least 1 cell).
Master (sink) begins reading data.
Master (sink) decides to stop reading the data for one clock cycle. VAL remains asserted.
Slave (source) indicates that it has less than 1 cell available. The master (sink) cannot tell which, nor can it deassert
ENA quick enough to prevent a potential underflow, but this is desirable if it is also to be able to transfer back to back
packets.
Master (sink) continues to read data, validates data with VAL.
Slave (source) cannot supply any more data, so deasserts VAL.
Master (sink) goes idle until DAV is re-asserted.
Specifications
(5)
(6)
(7)
42
UTOPIA Level 2 Slave MegaCore Function User Guide
Slave (sink) indicates it has space for at least 1 cell.
Master (source) begins writing data to the slave (sink).
Slave (sink) indicates it still has space, but the master (source) has run out of data.
Altera Corporation