Viterbi Compiler
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
3.2.0
Document Version:
3.2.0 rev 1
Document Date: January 2003
Viterbi Compiler MegaCore Function User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
UG-VITERBI-3.2
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
Viterbi Compiler MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
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See “Features” on page 10 for a complete list of the core features.
Refer to the readme file for late-breaking information that is not
available in this user guide.
Table 1. User Guide Revision History
Date
Description
January 2003
Device family support table added. Performance figures
updated.
August 2002
Stratix™ device support information added.
DSP Builder support information added.
OpenCore® Plus hardware evaluation information added.
December 2001
Changed formula in “Product Options” on page 44.
November 2001
Version 3.0 updates incorporated.
June 2001
Version 2.1 updates incorporated.
March 2001
Version 2.0 updates incorporated.
September 2000 Initial release.
How to Find
Information
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Altera Corporation
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Bookmarks serve as an additional table of contents.
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Numerous links, shown in green text, allow you to jump to related
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About this User Guide
How to Contact
Altera
Viterbi Compiler User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
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Viterbi Compiler User Guide
Typographic
Conventions
About this User Guide
The Viterbi Compiler MegaCore Function User Guide uses the typographic
conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 3.2.0 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
DSP Builder Support .............................................................................................................11
OpenCore & OpenCore Plus Hardware Evaluation .........................................................12
Product Options .............................................................................................................................13
Getting Started ............................................................................................................................................15
Software Requirements .................................................................................................................15
Design Flow ....................................................................................................................................15
Download & Install the Function ................................................................................................15
Obtain the Viterbi Compiler MegaCore Function .............................................................16
Install the MegaCore Files ....................................................................................................16
Directory Structure ................................................................................................................17
Set Up Licensing .............................................................................................................................18
Append the License to Your license.dat File ......................................................................18
Specify the Core’s License File in the Quartus II Software ..............................................19
Generate a Custom Viterbi Core ..................................................................................................19
Create a New Quartus II Project ..........................................................................................20
Launch the MegaWizard Plug-In Manager .......................................................................20
Architecture and Options .....................................................................................................22
Parameters ...............................................................................................................................23
Code Set Information (hybrid architecture only) ..............................................................26
Integrated Depuncturing Option .........................................................................................27
Test Data Settings ...................................................................................................................28
Completing the Custom Function .......................................................................................29
Apply the LogicLock Script ..........................................................................................................31
Simulate the VHDL Model in the ModelSim Simulation Tool ...............................................32
Simulate using the Visual IP Model ............................................................................................33
Configure a Device ........................................................................................................................34
Altera Corporation
vii
Contents
Specifications ..............................................................................................................................................35
Functional Description ..................................................................................................................35
DSP Builder Feature & Simulation Support .......................................................................36
OpenCore Plus Time-Out Behavior ....................................................................................36
Signals ......................................................................................................................................37
Hybrid Architecture ..............................................................................................................40
Parallel Architecture ..............................................................................................................43
Product Options .....................................................................................................................44
Soft Symbol Inputs .................................................................................................................47
Puncturing Scheme ................................................................................................................47
Encoding Scheme ...................................................................................................................49
Performance ....................................................................................................................................49
Core Verification ............................................................................................................................54
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 1 provides information about this release of the Viterbi Compiler.
Table 1. Viterbi Compiler Release Information
Item
Version
Release Date
Ordering Code (Product ID)
Vendor ID(s)
Device Family
Support
3.2.0
January 2003
IP-VITERBI/HS (0037)
IP-VITERBI/SS (0038)
6AF7 (Standard)
6AFA (Time-Limited)
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
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Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
About this Core
Table 2 shows the level of support offered by the Viterbi MegaCore
function to each of the Altera device families.
Table 2. Device Family Support
Device Family
™
Support
Stratix GX
Full
Cyclone™
Full
™
Stratix
Full
Mercury™
™
Full
Excalibur
Full
HardCopy™
Full
®
ACEX 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera® high-performance, soft-decision Viterbi Compiler MegaCore®
function implements a wide range of standard Viterbi decoders.
New in Version
3.2.0
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Support for Stratix™ GX and Cyclone™ devices
Support for Quartus® II integrated synthesis
Improved LogicLock™ script, which works for any configuration
Optional BER estimator pipelined for maximum performance
Features
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High-performance, area-optimized, soft-decision Viterbi decoders
for error correction
High-speed parallel architecture with:
–
Pure logic implementation or memory based traceback
–
Performance up to 190 Mbps
–
Fully parallel operation
–
Integral configurable depuncturing rate
Low to medium-speed, hybrid architecture
–
Configurable number of add compare and select (ACS) units
–
Memory based architecture
–
Wide range of performance
–
Wide range of logic area
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Viterbi Compiler User Guide
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General
Description
Fully parameterized Viterbi core, including:
–
Number of coded bits
–
Constraint length
–
Number of soft bits
–
Traceback depth or maximum block length
–
Polynomial for each coded bit
Efficient RTL models for use in VHDL and Verilog HDL simulators
VHDL testbenches to verify the decoder
Flexible licensing—use only the features you require
Easy-to-use MegaWizard® Plug-In
Support for OpenCore and OpenCore Plus hardware evaluation
OpenCore feature allows designers to instantiate and simulate
designs in the Quartus II software prior to purchasing a license
Has the DSP Builder Ready certification
Support for DSP Builder v2.1.0
Support for MATLAB version 6.5 and Simulink version 5.0
Viterbi decoding (also known as maximum likelihood decoding or
forward dynamic programming) is the most common way of decoding
convolutional codes by using an asymptotically optimum decoding
technique. In its basic form, Viterbi decoding is an efficient, recursive
algorithm that performs an optimal exhaustive search.
A convolutional encoder and Viterbi decoder can be used together to
provide error correction over a noisy channel, e.g., a communications
channel. A convolutional encoder adds redundancy (i.e., extra bits) to a
data stream before transmission.
The rate and the generating polynomials describe the convolutional code,
hence they describe the convolutional encoder. The rate is the number of
transmitted bits per input bit, e.g., a rate 1/2 encodes 1 bit and produces 2
bits for transmission. Similarly, a rate 2/3 encodes 2 bits and produces 3
bits for transmission. A code can be punctured to increase its rate, by
deleting some of the encoded bits according to a deterministic pattern.
The generating polynomials denote the convolutional encoder state bits,
which are mathematically combined to produce an encoded bit. There is
one generating polynomial per encoded bit. The length in bits of the
generating polynomial is called the constraint length; systems with higher
constraint lengths are generally more robust. However, the complexity of
the Viterbi decoder increases exponentially with the constraint length, so
it is unusual to find constraint lengths greater than nine.
Altera Corporation
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1
About this Core
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About this Core
About this Core
Viterbi Compiler User Guide
A noisy transmission channel causes bit errors at the receiver. The Viterbi
algorithm finds the most likely sequence of bits that is closest to the actual
received sequence. The Viterbi decoder uses the redundancy, which the
convolutional encoder imparted, to decode the bit stream and remove the
errors.
The receiver can deliver either hard or soft symbols to the Viterbi decoder.
A hard symbol is equivalent to a binary ±1. A soft symbol is multi-leveled
to represent the confidence in the bit being positive or negative. For
instance, if the channel is non-fading and Gaussian, the output of a
matched filter quantized to a given number of bits is a suitable soft input.
In both cases 0 is used to represent a punctured bit. The Viterbi algorithm
has better performance with soft input symbols.
The Viterbi decoder works on blocks of data, or continuous streams. It
takes in n symbols at a time for processing, where n is the number of
encoded symbols. The traceback length is the number of trellis states
processed before the decoder makes a decision on a bit. For blocks of data,
the best performance is achieved if decoding decisions are delayed until
all input symbols have been processed. For continuous streams this is not
possible, and there is no benefit in increasing the traceback length beyond
several times the constraint length.
The function is capable of a throughput (decoded bits output) up to 190
Mbps; for relatively large constraint lengths, such as 7, 165 Mbps is
achievable. The function can support many different puncturing rates,
based on a mother code of 1/2.
DSP Builder Support
DSP system design in Altera programmable logic devices requires both
high-level algorithms and HDL development tools. The Altera DSP
Builder, which you can purchase as a separate product, integrates the
algorithm development, simulation, and verification capabilities of The
MathWorks MATLAB and Simulink system-level design tools with
VHDL synthesis and simulation of Altera development tools.
DSP Builder allows system developers, algorithm implementers, and
hardware engineers to share a common development platform. The DSP
Builder shortens DSP design cycles by helping you create the hardware
representation of a DSP design in an algorithm-friendly development
environment. You can combine existing MATLAB functions and Simulink
blocks with Altera DSP Builder blocks to link system-level design and
implementation with DSP algorithm development. The DSP Builder
consists of libraries of blocks as shown in Figure 1.
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Altera Corporation
Viterbi Compiler User Guide
About this Core
Figure 1. DSP Builder Blocks in Simulink Library Browser
1
About this Core
DSP Builder version 2.1.0 and higher provides modular support for Altera
DSP cores, including the Viterbi Compiler. The MATLAB software
automatically detects cores that support DSP Builder, and the cores
appear in the Simulink library browser.
f
For more information on using DSP Builder with the Viterbi Compiler, see
“DSP Builder Feature & Simulation Support” on page 36.
OpenCore & OpenCore Plus Hardware Evaluation
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus® II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed before making a purchase decision. However, you cannot generate
device programming files.
Altera Corporation
13
About this Core
Viterbi Compiler User Guide
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that includes Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
1
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Product
Options
If you are simulating a time-limited MegaCore function using
the DSP Builder and Simulink, i.e., in software, the core
operation does not time out and the done pin stays low.
For more information on OpenCore Plus hardware evaluation using the
Viterbi Compiler, see “OpenCore Plus Time-Out Behavior” on page 36
and AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
There are two Viterbi decoder products within the Viterbi Compiler
MegaCore function; for each you can specify a number of options. With
Altera flexible licensing, you only need to license the product that you
require. Table 3 shows the product options.
Table 3. Product Options
Options
BER Estimator
Multiple Code set
Node Synchronization
Architecture
Hybrid
Parallel
v
v
v
v(1)
v
v(1)
Integrated Depuncturing
Continuous Decoding
v
v
Block Decoding
v
v
Note:
(1)
14
Available with the continuous decoding option, not with the block decoding
option.
Altera Corporation
Getting Started
Software
Requirements
The instructions in this section require the following hardware and
software:
1
Design Flow
Download &
Install the
Function
Altera Corporation
2
Microsoft Windows 98 or higher operating system
Quartus® II, version 2.2 or higher
DSP Builder version 2.1.0 or higher (optional)
This section assumes you are using a PC with the Windows
operating system. However, the core also works with UNIX
platforms. If you are using UNIX, you must install the Java
Runtime Environment version 1.3. Refer to the core’s readme file
for more information on UNIX support.
The Viterbi Compiler design flow involves the following steps:
1.
Download and install the Viterbi Compiler MegaCore function.
2.
Set up licensing. This step is not required if you are test-driving the
core using the OpenCore feature, however, you do need to obtain
and install an OpenCore Plus license to test-drive the core using this
feature.
3.
Generate a custom MegaCore function.
4.
Implement your system using VHDL or Verilog HDL.
5.
Compile your design.
6.
Apply the LogicLock™ script.
7.
Simulate your design to confirm the operation of your system.
8.
License the Viterbi Compiler MegaCore function and configure the
devices.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
15
Getting Started
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Getting Started
Viterbi Compiler User Guide
Obtain the Viterbi Compiler MegaCore Function
1.
Point your web browser to http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Signal Processing (DSP) from the Technology drop-down
list box.
4.
Type Viterbi Compiler in the Keyword Search box.
5.
Click Go.
6.
Click the link for the Altera Viterbi Compiler MegaCore function in
the search results table. The product description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
I Agree at the bottom of the page.
9.
Follow the instructions on the Viterbi Compiler download and
installation page to download the function and save it to your hard
disk.
Install the MegaCore Files
To install the MegaCore files, follow the instructions below:
16
1.
Click Run (Start menu).
2.
Type <path name>\<filename>, where <path name> is the location of
the downloaded MegaCore function and <filename> is the file name
of the core. Click OK.
3.
Follow the on-line instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the MegaCore function’s library directory
(<path>\viterbi-<version>\lib) as a user library in the Quartus II
software. Search for “User Libraries” in Quartus II Help for
instructions on how to add a library.
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
Directory Structure
Figure 2 shows the directory structure for the Viterbi Compiler.
Figure 2. Directory Structure
MegaCore
viterbi-<version>
Contains the Viterbi Compiler MegaCore function files and documentation.
2
doc
Contains the documentation for the core.
dspbuilder
Contains the files for DSP Builder functionality.
lib_time_limited
Contains encrypted lower-level design files for OpenCore Plus hardware evaluation.
After installing the MegaCore function, you should set a user library in the
Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
dspbuilder
Contains the files for DSP Builder functionality.
sim_lib
Contains the simulation models provided with the core.
modelsim
Contains the precompiled libraries and the testbenches for the ModelSim
simulation tool.
vhdl
Contains the VHDL precompiled libraries and the VHDL testbenches.
testbench
Contains the VHDL testbench directories.
viterbi
Contains the precompiled libraries.
visualip
Contains the precompiled models for the Visual IP software.
Altera Corporation
17
Getting Started
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
Getting Started
Set Up
Licensing
Viterbi Compiler User Guide
You can use the Altera OpenCore feature to compile and simulate the
Viterbi Compiler MegaCore function, allowing you to evaluate the it
before purchasing a license. You can simulate your Viterbi design in the
Quartus II software using the OpenCore feature. However, you must
obtain a license from Altera before you can generate programming files or
EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in
third-party EDA tools.
After you purchase a license for Viterbi Compiler, you can request a
license file from the Altera web site at http://www.altera.com/licensing
and install it on your PC. When you request a license file, Altera e-mails
you a license.dat file. If you do not have Internet access, contact your local
Altera representative.
1
If you want to use the OpenCore Plus feature, you must request
a license file from the licensing page of the Altera web site
(http://www.altera.com/licensing) to enable it. Your license file
is sent to you via e-mail; follow the instructions below to install
the license file.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the Viterbi Compiler, you must
already have the Quartus II software installed on your PC with
licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
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18
Quartus II
MAX+PLUS® II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the Viterbi Compiler license file in a text editor. The file should
contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the Viterbi Compiler license file and
paste it into the Quartus II license file.
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
1
5.
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
2
Specify the Core’s License File in the Quartus II Software
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Generate a
Custom Viterbi
Core
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
This section describes the design flow using the Altera Viterbi Compiler
MegaCore function and the Quartus II development system. Altera
provides a MegaWizard Plug-In Manager with the Viterbi Compiler
MegaCore function. The MegaWizard Plug-In Manager, which you can
use within the Quartus II software, lets you create or modify design files
to meet the needs of your application. You can then instantiate the custom
megafunction in your design file.
You can use the Altera OpenCore feature to compile and simulate the
MegaCore functions in the Quartus II software, allowing you to evaluate
the functions before deciding to license them.
Altera Corporation
19
Getting Started
To specify the core’s license file, perform the following steps:
Getting Started
Viterbi Compiler User Guide
Create a New Quartus II Project
Before you begin creating a core, you must create a new Quartus II project.
With the New Project wizard, you specify the working directory for the
project, assign the project name, and designate the name of the top-level
design entity. You will also specify the Viterbi Compiler user library. To
create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software if you prefer.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\viterbi-<version>\lib\ into the Library name box,
where <path> is the directory in which you installed the Viterbi
Compiler. The default installation directory is c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You are finished creating your new Quartus II project.
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the Viterbi Compiler. To launch the wizard,
perform the following steps:
20
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
1.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
Specify that you want to create a new custom megafunction and
click Next.
3.
Select Viterbi Compiler-<version> in the DSP > Error
Correction/Detection directory.
4.
Choose the output file type for your design; the wizard supports
VHDL and Verilog HDL.
5.
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 3 shows the wizard after you have made
these settings.
2
Getting Started
2.
1
Altera Corporation
Refer to the Quartus II Help for more information on how to use
the MegaWizard Plug-In Manager.
<variation name> and <directory name> must be the same name
and the same directory that your Quartus II project use.
21
Getting Started
Viterbi Compiler User Guide
Figure 3. Selecting the Megafunction
6.
Click Next.
Architecture and Options
Select the architecture and options that you require (see Figure 4). Click
Next.
22
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
Figure 4. Selecting the Architecture
2
Getting Started
You can select a hybrid block, hybrid continuous, parallel block, or
parallel continuous architecture. You can select the bit error rate (BER),
multiple code set, or node synchronization options; if an option is greyed
out, it is not available for your architecture.
Parameters
The next wizard page shows the parameters that you can specify.
1
The MegaWizard Plug-In only allows you to select legal
combinations of parameters, and warns you of any invalid
configurations. Press F1 at anytime for on-line help.
Hybrid Architecture
Select the parameters that define the specific Viterbi code you wish to
implement (see Figure 5).
The throughput calculator calculates throughput for specified frequencies
and block size.
Altera Corporation
23
Getting Started
Viterbi Compiler User Guide
Figure 5. Selecting the Parameters—Hybrid Architecture
Constraint Length
The constraint length, constraint_length, which can take any integer
value from 5 to 9; selecting less than 9 limits the acs_units range.
ACS Units
The number of ACS units, which adds a degree of parallelism and can take
the values of 1, 2, 4, 8, or 16 depending on the value of
constraint_length.
Traceback
Traceback length is the number of stages in the trellis that are traced back
to obtain a decoded bit. It is typically set to 5 × constraint_length for
unpunctured codes, up to 15 × constraint_length for highly punctured
codes, and is >10.
Softbits
The number of soft decision bits per symbol, softbits. When softbits
is set to 2 bits, the decoder acts as a hard decision decoder and still allows
for erased symbols to be entered as binary ‘00’. softbits can take any
integer value from 2 to 16.
Bmgwide
The precision of the state metric accumulation. The MegaWizard Plug-In
selects and displays the optimum value, which depends on n,
constraint_length and, softbits.
24
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
Throughput Calculator
The throughput calculator uses the following formulae:
fMAX
Hybrid continuous throughput =
2L – 1 – log2A
fMAX
Hybrid block throughput =
2
V
V+L–1
Parallel continuous throughput =
{
× fMAX
Getting Started
Parallel block throughput =
2L – 1 – log2A + 1 + 6/V
fMAX for unpunctured code
fMAX × m/n (for punctured codes)
where:
L is the constraint length
A is ACS units
V is traceback length or the block size for the block decoders
m/n is the punctured rate.
When you have specified your parameters click Next.
Parallel Architecture
Select the parameters that define the specific Viterbi code you wish to
implement (see Figure 6).
Altera Corporation
25
Getting Started
Viterbi Compiler User Guide
Figure 6. Selecting the Parameters—Parallel Architecture
Constraint Length
The constraint length, constraint_length, which can take any integer
value from 3 to 9.
Softbits
The number of soft decision bits per symbol, softbits. When softbits
is set to 2 bits, the decoder acts as a hard decision decoder, and still allows
for erased symbols to be entered as binary ‘00’. softbits can take any
integer value from 2 to 16.
Traceback
Traceback length is the number of stages in the trellis that are traced back
to obtain a decoded bit. It is typically set to 5 × constraint_length for
unpunctured codes, up to 15 × constraint_length for highly punctured
codes, and is >10. Traceback length can have a large impact on the number
of logic elements (LEs) used for the parallel continuous decoder with
logic-based traceback.
Bmgwide
The precision of the state metric accumulation. The MegaWizard Plug-In
selects and displays the optimum value, which depends on n,
constraint_length and, softbits.
26
Altera Corporation
Viterbi Compiler User Guide
GettingGetting Started
N
The number of coded bits, n. For every bit to be encoded, n bits are output.
n can take any integer value from 2 to 4.
Traceback Type
Traceback type—logic- or memory-based.
When you have specified your parameters click Next.
2
Code Set Information (hybrid architecture only)
Getting Started
You can select the code set information that you require (see Figure 7).
Figure 7. Code Set Configuration (Hybrid Architecture)
GA, GB, GC, GD, GE, GF, GG
The generator polynomials. If the multiple code set option is used, a
different set of polynomials is entered in the respective gi group. The
MegaWizard Plug-In provides default values that can be overwritten by
any valid polynomial (the wizard does not check whether the entered
values are valid). The wizard writes them as decimal base, but you have
the option of entering in either decimal or octal base.
N
The number of coded bits, n. For every bit to be encoded, n bits are output.
If you have specified the multiple code set option, there are up to 5
different n parameters, which can be in any order. n can take any integer
value from 2 to 7.
Altera Corporation
27
Getting Started
Viterbi Compiler User Guide
When you have specified the code set information, click Next.
Integrated Depuncturing Option
The parallel continuous architecture offers you the option of integrated
depuncturing.
Select the number of rates and the puncturing rate that you require (see
Figure 8).
Figure 8. Puncturing (Parallel Architecture)
Number of Rates
This is set to 1.
Punctured Rate
You can select no puncturing or a value x/y, where x < y and x/y > 1/2.
Puncturing Pattern
The pattern for the selected puncturing rate. A 1 marks the puncturing
position. You can change the wizard-specified value.
28
Altera Corporation
Viterbi Compiler User Guide
GettingGetting Started
Test Data Settings
The MegaWizard Plug-In generates a VHDL testbench, which can be used
in any simulator. It also generates a Tcl script for the ModelSim software
(see “Simulate the VHDL Model in the ModelSim Simulation Tool” on
page 33). This script maps the provided ModelSim library and compiles
the provided testbench and the wrapper. You can use the script to
initialize a simulation with your parameters. Enter the test data settings
for the testbench (see Figure 9).
2
Figure 9. Test Data Settings
Getting Started
Number of Test Bits
The number of test bits, minimum value constraint_length.
Noise Ratio dB
The signal to noise ratio.
Block Size to Simulate (Block Architectures only)
The size of the block, which must be less than the traceback length.
Code Set to Simulate (Multiple Code Set Option only)
Specify which code set you want to simulate.
Altera Corporation
29
Getting Started
Viterbi Compiler User Guide
Puncturing Pattern
For the hybrid architecture you can specify punctured data for testing. For
the parallel architecture the wizard takes the previously specified
puncturing pattern.
Test Target
Select either test BER or test node sync (node synchronization option
only), to test the BER or node synchronization feature.
When you have finished entering your test data settings, click Next.
Completing the Custom Function
To complete your custom function, perform the following steps.
1.
The wizard selects the product order code for your chosen Viterbi
core (see Figure 10). Click Next.
Figure 10. Product Order Code
2.
30
The final screen lists the design files that the wizard creates (see
Figure 11). Click Finish.
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
The wizard generates the following files:
■
■
■
■
■
■
■
■
■
■
■
1
Altera Corporation
<variation name> is the variation name you chose for the core.
31
2
Getting Started
■
■
One of the following files (depending on your selection), which are
used to used to instantiate an instance of the function in your design:
–
A VHDL Design File (.vhd)
–
Verilog Design File (.v)
Symbol Files (.bsf) used to instantiate the function into a schematic
design
<variation name>_quartus_script.tcl, which you must execute in the
Quartus Tcl console to configure your project (see step 4 on page 32).
An example of the instantiation of the core <variation name> _inst
A blackbox Verilog HDL model, <variation name>_bb (Verilog HDL
only)
A component declaration file <variation name>.cmp (VHDL only);
transbit.txt, which contains the bits that have been used to generate
the test data
a_txsym.txt, which contains the encoded bits
a_rcvsym.txt, which contains the received bits that are corrupted
with a signal to noise ratio you specify in the MegaWizard Plug-In.
a_rcvsym.txt is input to the bench when testing the core
BER_report.txt, which contains the number of errors, the BERs and
their location for the test data
A VHDL testbench <variation name>__testbench.vhd), which is used
in the ModelSim software to simulate the core
<variation name>__vsim_script.tcl, which is used in the ModelSim
software to start the core simulation
<variation name>__logiclock_script.tcl, which is used in the Quartus
software to provide some constraints that improve the performance
of the decoder
Getting Started
Viterbi Compiler User Guide
Figure 11. Design Files
3.
The wizard reminds you that you must execute <variation
name>_quartus_script.tcl to configure your project (see Figure 12).
Click OK on the message.
Figure 12. Message
4.
To execute <variation name>_quartus_script.tcl, choose Utility
Windows > Tcl Console (View menu), and in the Tcl console type the
following command:
source <variation name>_quartus_script.tcl
You can now integrate your custom megafunction into your system
design and compile.
Apply the
LogicLock
Script
The MegaWizard Plug-In generates a LogicLock script (<variation
name>__logiclock_script.tcl). Executing the script provides some
constraint files that significantly improve the performance of any
configuration on the APEX device families.
1
32
LogicLock incremental design capability provides a way of
controlling the floorplanning of the Viterbi Compiler in your
system.
Altera Corporation
Viterbi Compiler User Guide
f
GettingGetting Started
For more information on LogicLock incremental design capability, refer to
Application Note 161: Using the LogicLock Methodology in the Quartus II
Design Software.
To execute the script and use the constraint files, perform the following
steps:
1.
Choose Utility Windows > Tcl Console (View menu).
2.
In the Tcl console type the following command:
2
source <variation name>_logiclock_script.tcl
Altera Corporation
The following steps explain how to simulate the VHDL model of your
design in the ModelSim simulation tool.
1.
Open the ModelSim simulation tool. Select Change Directory (File
menu) and change the directory to <directory name>.
2.
Select Execute Macro (Macro menu). Select the file <variation
name>_vsim_script.tcl (see Figure 13) and click Open.
33
Getting Started
Simulate the
VHDL Model in
the ModelSim
Simulation Tool
Getting Started
Viterbi Compiler User Guide
Figure 13. Selecting wizard_vsim.tcl
This Tcl script performs the following functions:
■
■
■
■
Maps the provided Viterbi library
Creates a working library vit_work
Compiles your design wrapper, the provided bench and the top-level
testbench with your parameters into vit_work
Executes vsim and opens a wave window with the bench signals
When the simulation is finished the decoded bits are output to the file
decoded.txt. The bits originally transmitted are in the file tranbits.txt. If
you selected the BER test option, a comparison between the decoded.txt
bits and transbit.txt show the performance of the core.
If you selected node synchronization option, the wave form display
shows how the core regains node synchronization.
Simulate using
the Visual IP
Model
Altera provides a Visual IP model with the Viterbi Compiler MegaCore
function, which you can use with the Visual IP software.
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
1.
34
Point your web browser at
http://www.altera.com/products/ip/altera/visual_ip.html.
Altera Corporation
GettingGetting Started
Viterbi Compiler User Guide
2.
Follow the online instructions to download the software and save it
to your hard disk.
To use the Visual IP model, perform the following steps:
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Compile the wrapper for the core model.
The Verilog version of the wrapper is in the
$VIP_MODELS_DIR\<model_name>\interface\pli directory;
the corresponding VHDL version is in the
$VIP_MODELS_DIR \<model_name>\interface\mti directory.
1
<model_name> is aukv_hyb_top_cnt, aukv_hyb_top_blk,
aukv_par_top_blk, or aukv_par_top_cnt.
3.
Compile the wrapper for the testbench model.
4.
Compile the MegaWizard wrapper.
5.
Compile the top-level testbench, which is generated by the
MegaWizard Plug-In and is called <variation name>_testbench.vhdl.
1
Verilog HDL users must create their own version of the toplevel testbench.
The Visual IP model is now ready for use in your simulator.
Configure a
Device
Altera Corporation
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must license the function before
you can generate configuration files.
35
2
Getting Started
1.
Notes:
Specifications
Functional
Description
Table 3 shows the function’s parameters, which can only be set in the
MegaWizard Plug-In and are described in detail in “Generate a Custom
Viterbi Core” on page 19.
Table 3. Parameters
Parameter
Description
n
The number of coded bits. For every bit to be encoded, n bits are output. With the
multiple code set option there are up to 5 different n parameters, which can be in any
order.
constraint_length
The constraint length. Defines the number of states in the convolutional encoder,
where number of states = 2 (constraint_length – 1). Selecting less than 9 limits the
acs_units range.
acs_units
The number of add compare and subtract (ACS) units, which adds a degree of
parallelism (hybrid architecture only). The range of values available depends upon the
value of constraint_length.
softbits
The number of soft decision bits per symbol. When softbits is set to 2 bits, the
decoder acts as a hard decision decoder, and still allows for erased symbols to be
entered as binary ‘00’.
bmgwide
The precision of the state metric accumulation. The MegaWizard Plug-In selects and
displays the optimum value, which depends on n, constraint_length and,
softbits.
v
Traceback length, which is typically set to 5 × constraint_length for unpunctured
codes, and up to 15 × constraint_length for highly punctured codes.
GA, GB, GC, GD,
GE, GF, GG
The generator polynomials. If the multiple code set option is used, a different set of
polynomials is entered in the respective gi group. The MegaWizard Plug-In provides
default values that can be overwritten by any valid polynomial. The wizard writes them
as decimal base, but you have the option of entering in either decimal or octal base.
35
Specifications
Altera Corporation
3
Specifications
Viterbi Compiler User Guide
DSP Builder Feature & Simulation Support
You can create Simulink Model Files (.mdl) using the Viterbi Compiler
and DSP Builder blocks. DSP Builder supports the following Viterbi
Compiler options:
■
Parallel continuous (except the node synchronization and the internal
depuncturing options)
DSP Builder does not support the following Viterbi Compiler options:
■
■
■
Hybrid block
Hybrid continuous
Parallel block
1
The MegaWizard Plug-In allows you to select supported options
only.
After you create your model, you can perform simulation. DSP Builder
supports the simulation files shown in Table 4 for the Viterbi Compiler.
Table 4. Viterbi Compiler Simulation File Support in DSP Builder
Simulation Type
Simulation Flow
Precompiled ModelSim model
for RTL functional simulation
The DSP Builder Signal Compiler block generates a ModelSIm Tcl script and
a VHDL testbench on-the-fly.
VHDL Output File (.vho) models You can generate a .vho after you have purchased a license for your
for timing simulation
MegaCore function. Refer to the “VHDL Output File (.vho)” topic in Quartus II
Help for more information.
Visual IP Models
Not Supported
Quartus II simulation
The DSP Builder SignalCompiler block generates a Quartus II simulation
vector file on-the-fly.
f
For more information on DSP Builder, see “DSP Builder Support” on page
12.
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
36
The decbits signal remains low
The timed_out signal is driven from low to high
Altera Corporation
Viterbi Compiler User Guide
Specifications
A time-limited the Viterbi Compiler runs for approximately 30 minutes
for a 150 MHz clock (exactly 2.7 × 1011 clock cycles).
f
For more information on OpenCore Plus hardware evaluation, see
“OpenCore & OpenCore Plus Hardware Evaluation” on page 13 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
Signals
Table 5 shows the input signals.
Table 5. Input Signals (Part 1 of 2)
Signal Name
Description
sysclk is the main system clock. the whole core operates on the
rising edge of sysclk.
reset
Reset. The entire decoder is asynchronously reset when reset is
asserted high. The reset signal is used to reset the entire system. The
reset signal must be deasserted asynchronously with respect to
sysclk.
enable
Enable. The decoder is enabled, when enable is asserted high. When
it is low, the entire operation of the core is suspended.
load (1)
When high, load latches the rr[] bus into the decoder on the rising
edge of sysclk. load must be asserted when the core asserts the
output ready (assuming input data is ready), otherwise enable must
be deasserted.
rr[(n_max*softbits):1]
rr[(softbits):1] (2)
Data input. This takes in n symbols, each softbits wide per clock.
“Encoding Scheme” on page 49 describes the correspondence of the
input symbols with the output of a convolutional encoder. Erased
(depunctured) symbols are equal to zero. An encoded ‘1’ is negative
(i.e., ‘1XX:’) and an encoded ‘0’ is positive (i.e. ‘0XX:’). n_max is
max(n).
sync_rot
External node synchronization. When sync_rot is asserted high for
one clock cycle, a state transition occurs where the n incoming signals
are rotated.
sel_code[log2(ncodes):1] (3)
Selects the codeword—’0’ selects the first codeword, ‘1’ selects the
second, etc. The bus size increases according to the number of codes
specified.
tb_length[] (3)
Block size length. After the number of symbol sets set by
tb_length[]is received, further inputs to the decoder are ignored
and the traceback starts. The width of tb_length[]is automatically
set to handle the maximum value of v. tb_length[]must remain
stable before the decoder is reset and until the traceback starts.
Altera Corporation
37
3
Specifications
sysclk
Specifications
Viterbi Compiler User Guide
Table 5. Input Signals (Part 2 of 2)
Signal Name
Description
tb_type (3)
When tb_type is low, the decoder uses the state containing the best
metric state to start the traceback from. When tb_type is high, the
decoder uses the state specified in
tr_init_state[(constraint_length-1):1].
tr_init_state
[(constraint_length-1):1] (3)
Specifies the state to start the traceback from, when tb_type is
asserted high.
period_ber[24:1] (4), (5)
Period for BER estimation. Specifies the number of decoded symbols
over which the BER measurement is made. After the specified number
of symbols is reached, the bererr[16:1] output bus is latched with
the number of errors estimated during the previous measurement
period, and the numerr_ber[16:1] bus is reset to zero. A new
measurement period then begins.
period_ns[8:1] (3), (6)
Period for node synchronization. Specifies the number of decoded
symbols over which the BER measurement is made, to decide whether
the decoder has achieved node synchronization or not. Output signals
in_sync and out_sync are flagged, and the numerr_ns[8:1] bus
is reset to zero. A new measurement period then begins.
threshold_ns[8:1] (3), (6)
Specifies the number of errors’ threshold over the period period_ns,
to decide whether the decoder is in node synchronization or not.
bm_init_state
Specifies the state with which to initialize, with the value from the
[(constraint_length-1):1] (3), bm_init_value[] bus. All other state metrics are set to zero.
(7)
bm_init_state[(constraint_length-1):1] must be stable
before reset, and remain stable until after the third symbol set is read in.
bm_init_value
Specifies the value of the metric that initializes the start state. All other
[(constraint_length-1):1] (3), metrics are set to 0. bm_init_value[(constraint_length(7)
1):1]must be larger than
(constraint_length × 2(softbits – 1)).
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
38
Not used with parallel architectures.
Used only when internal depuncturing is enabled.
Used only when you select the block decoding option.
Used only when you select the BER option.
Used only when you select the continuous decoding option.
Used only when you select the node synchronization option.
Hybrid architecture only.
Altera Corporation
Viterbi Compiler User Guide
Specifications
Table 6 shows the output signals.
Table 6. Output Signals (Part 1 of 2)
Signal
Description
ready (1)
ready is asserted when the decoder requires another n symbols
on the rr[] bus on the next rising edge. If the input symbols are
not available, the decoder must be disabled immediately until they
are available (using the enable signal).
valid
valid is an internal enable signal that is applied to the decoder.
valid indicates when internal depuncturing is used and indicates
when the core is enabled or not enabled.
decbits[bitsout:1] (2), (4)
decbit (5)
The decbits[] bus or the decbit signal contains output bits
when outvalid is asserted.
outvalid
outvalid is asserted high for one clock cycle, whenever there is
a valid output on the decbits[] bus, or decbit signal.
normalize
normalize is asserted high for one clock cycle, whenever the
state metrics are normalized.
in_sync (6)
in_sync is asserted high when the number of errors are less
than threshold_ns, after monitoring the BER output for
period_ns symbols.
out_sync (6)
out_sync is asserted high when the number of errors are equal
or higher than threshold_ns, after monitoring the BER output
for period_ns symbols.
numerr[] (4), (7), (8)
The numerr[] bus contains the number of errors detected during
a block. It is updated each time an error is detected, making it
possible to see the location of individual errors. It is reset at the
end of each measurement period. The width of this bus is
automatically set to handle the maximum value of v.
numerr_ber[] (4), (8), (9)
The numerr_ber[] bus contains the number of errors detected
during period_ber. It is updated each time an error is detected,
making it possible to see the location of individual errors.
numerr_ns[] (4), (6), (9)
The numerr_ns[] contains the number of errors detected during
period_ns. This value is then compared against
threshold_ns to decide whether the decoder is in node
synchronization or not.
bererr[16:1] (8), (9)
The bererr[16:1] contains the number of errors detected
during the previous measurement period. It is updated at the end
of each measurement period.
bestmet[bmgwide:1] (7)
The best metric, which is the value contained in the trellis at the
end of a block.
bestadd[(constraint_length-1):1]
(7)
The best address state. The address corresponding to the best
metric.
39
Specifications
Altera Corporation
3
Specifications
Viterbi Compiler User Guide
Table 6. Output Signals (Part 2 of 2)
Signal
Description
bitnum[] (7)
bitnum[] contains the decoded bit position within the block,
starting with position ‘0’ and ending with position
tb_length[] – 1. The width of this bus is automatically set to
handle the maximum value of v.
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Hybrid architectures only.
Hybrid architectures with continuous decoding option only.
Held at a constant value.
The MegaWizard Plug-In sets the width of this bus.
Parallel architectures only.
Used only when you select the node synchronization option.
Used only when you select the block decoding option.
Used only when you select the BER estimator option.
Used only when you select continuous decoding option.
Hybrid Architecture
Figures 14 and 15 are timing diagrams for hybrid continuous decoding,
and show the relationship between ready and load. Figure 16 shows a
timing diagram for hybrid block decoding.
Figure 14. Continuous Decoding (Hybrid Architecture) (data ready)
sysclk
reset
enable
ready
load
rr[20..1]
40
76747
76675
Altera Corporation
Viterbi Compiler User Guide
Specifications
Figure 15. Continuous Decoding (Hybrid Architecture) (Data not Ready)
sysclk
reset
enable
ready
load
76675
rr[20:1]
Data not ready
Data ready
Figure 16. Block Decoding (Hybrid Architecture)
Period of 2 (constraint_length - 1)
3
Specifications
sysclk
enable
reset
rr[66..1]
00000000122600400
000000000FFEE0052D
load
ready
normalize
sel_code
1
bm_init_state
0
bm_init_value
0
tb_type
tr_init_state
tb_length[9..1]
0
300
outvalid
bitnum[9..1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
decbits
numerr[12..1]
0
bestadd[23..1]
3
bestmet[23..1]
1820686
Altera Corporation
41
Specifications
Viterbi Compiler User Guide
For hybrid continuous decoding, the output bus is
decbits[bitsout:1], where bitsout is a parameter that depends
upon the constraint_length, acs_units and v, as shown in the
following equations:
log2cc = constraint_length – 1 – log2(acs_units)
bitsout = ceil ( (v + 1) / (2log2cc ) )
For example, when
constraint_length = 5
acs_units = 2
v = 29
therefore bitsout = 4
Another parameter dictates, on the first outvalid pulse, how many bits
have to be skipped and is given by:
skipbit = (v + 2) mod bitsout.
Figure 17 shows hybrid continuous decoding and illustrates skipbit.
For the given parameters, skipbit = 3. On the first outvalid pulse, the
first three bits are not valid or have to be skipped. The first three bits are
decbits (1) = 0, decbits (2) = 0, and decbits (3) = 0; decbits (4) = 1
is the first valid bit. The following valid bit is decbits (1) = 1 at the next
outvalid pulse.
42
Altera Corporation
Viterbi Compiler User Guide
Specifications
Figure 17. Hybrid Continuous Decoding—Illustrating Skipbit
First Outvalid Pulse
sysclk
reset
enable
load
rr
78
88
A5
87
77
78
87
77
sel_code
87
88
77
87
77
78
77
78
0
outvalid
normalize
ready
decbits[0] 0000
0000
0000
0000
0000
0000
decbits[4]
decbits[3]
decbits[2]
decbits[1]
17408
period_ber
bererr
0
1
numerr_ber
0
1
3
Parallel Architecture
You can specify traceback type (parallel architecture only) as memorybased or logic-based. Memory-based traceback implements the traceback
mechanism using RAM to store the survivors information; logic-based
traceback uses logic (flip-flops) to store the survivors information.
Memory-based requires less LEs, but it uses a number of ESBs.
Logic-based requires more LEs, but no ESBs are deployed on the traceback
operation.
Figures 18 and 19 show the timing diagrams for the parallel architecture.
Altera Corporation
43
Specifications
You may want to select values of v that force skipbit to be zero
(constraint_length and, to some degree, acs_units are dictated by
the application and the required throughput). When skipbit is zero,
after a reset, the first outvalid pulse indicates a set of decbits that are
all valid, which makes the core easier to use in your system.
Specifications
Viterbi Compiler User Guide
Figure 18. Parallel Continuous Decoding
sysclk
enable
rr
F
8
6
7
B
C
1
A
7
B
8
4
8
7
8
7
D
8
decbit
valid
outvalid
Outvalid asserted and
valid asserted for valid data
Figure 19. Parallel Block Decoding
sysclk
enable
outvalid
ready
bestmet
154
141
bestadd
12
3
decbit
tb_length
30
bitnum
0
numerr
rr
1
2
3
0
46 D8 8D
76
4
5
6
7
8
9 10 11 12 13 14 15
1
24 25 88 68 58 B3 24 78 7D
68
89 94 34 78 C8 5D 9B 7C 88 87 69
The performance of any parallel architecture is improved by using the
MegaWizard Plug-In provided LogicLock script.
Product Options
The BER estimator option uses a re-encode and compare approach for
estimating the number of errors in the input data. In cases where the
signal-to-noise ratio is sufficiently high to allow the decoder to decode an
error-free output, the BER estimation is very close to the actual channel
BER. When the decoder is not decoding an error-free output, the
estimated BER is higher and more random than the actual channel BER,
which introduces a degree of uncertainty directly proportional to the
output errors (see Figure 20).
44
Altera Corporation
Viterbi Compiler User Guide
Specifications
Figure 20. Graph comparing Actual BER with Estimated BER
1.00e-01
BER 1.00e-02
Actual BER
Estimated BER
1.00e-03
3.00
3.50
4.00
4.50
5.00
5.50
6.00
Signal-to-Noise Ratio
The multiple code set option allows up to five code sets, where a code set
comprises a code rate and associated generating polynomials.
You should aim for b/a to be in the range 0.25 to 0.4. This mechanism
trades-off two known characteristic figures of any detection mechanism:
the probability of undetection against the probability of a false alarm.
If b/a is greater than 0.4, you are entering the region of higher probability
of undetection at the expense of no or an extremely low probability of a
false alarm.
If b/a is less than 0.25, you are entering the region of higher probability of
a false alarm at the expense of no or an extremely low probability of
undetection.
However both regions overlap—you must set the right values for the
duration and threshold.
Figure 21 shows the node synchronization timing diagram.
Altera Corporation
45
Specifications
The node synchronization option relies on the BER to detect if the two
incoming symbols are in the correct order. If they are not, the decoded bits
are approximately 50% erroneous, i.e., the communications link is broken.
By setting the values of period_ns (a) and threshold_ns (b), you can
control the decision mechanism. period_ns clock cycles after outvalid
is asserted, the output on numerr_ns is compared to threshold_ns. If
the output numerr_ns is greater, the decoder is out of synchronization.
To find the node synchronization, you must rotate the incoming symbols
by using the input sync_rot.
3
Specifications
Viterbi Compiler User Guide
Figure 21. Node Synchronization Timing Diagram
sysclk
enable
reset
outvalid
threshold_ns
15
period_ns
42
in_sync
out_sync
numerr_ns
0
5
19
21
0
1
2
5
0
5
19
21
0
1
2
5
sync_rot
rr
numerr_ber
21 errors, threshold is 15 errors.
21>15, therefore out_sync is asserted
When the Viterbi decoder is used as a continuous decoder, it processes
bits from a continuous data stream. The block decoding option allows the
decoder to start and end in a given run-time state, allowing optimum
decoding of a data block framed with tail bits.
The block decoding option comprises:
■
■
■
■
46
Run-time selection of start state in a block (hybrid only)
Run-time selection of either an end state that you specify, or the state
with the best metric (from this state the traceback starts its operation
for the block)
Run-time selection of block length (up to the value of the traceback
parameter)
An output providing the best metric per decoded block
Altera Corporation
Viterbi Compiler User Guide
Specifications
Soft Symbol Inputs
Table 7 shows an example of the soft symbol input representation, for
softbits = 4.
Table 7. Soft Symbol Input Representation
Soft Symbol
Meaning
Strongest ‘0’
0110
Stronger ‘0’
0101
Strong ‘0’
0100
Medium ‘0’
0011
Weak ‘0’
0010
Weaker ‘0’
0001
Weakest ‘0’
0000
Erased Symbol
1111
Weakest ‘1’
1110
Weaker ‘1’
1101
Weak ‘1’
1100
Medium ‘1’
1011
Strong ‘1’
1010
Stronger ‘1’
1001
Strongest ‘1’
1000
Stronger ‘1’ (internally clipped to 1001 for maximum ‘1’)
3
Specifications
0111
Puncturing Scheme
All architectures support external puncturing. All punctured codes
shown are based on a mother code of rate 1/2. For external depuncturing
you must depuncture the received data stream external to the decoder,
and input the data into the decoder n symbols at a time. If you are using
a parallel decoder with an externally punctured code, you need two clocks
in the system—a faster received-bits clock and a slower decoder clock. If
you use one clock, you must operate the enable signal. Even if the code
is unpunctured, you must still combine n symbols into a parallel symbol
vector and present the symbol vector data samples to the decoder with
every decoder clock. When testing this decoder with a depunctured code,
erased symbols are entered as zero.
Altera Corporation
47
Specifications
Viterbi Compiler User Guide
Only the parallel architectures (with n = 2) support internal depuncturing.
The decoder receives input symbols one at a time and depunctures the
data internally. The punctured rates supported are given by:
Punctured rate = ‘x/y’ or ‘unpunctured’
where x<y, x/y>1/2
(x = information symbols, y – x = parity symbols).
Puncturing rate = mother code rate/punctured rate,
i.e.,
1/2
punctured rate
Table 8 shows some possible puncturing schemes, which can be defined,
and their rate.
Table 8. Some Puncturing Schemes
Punctured Rate
2/3
Puncturing
Rate
3/4
3/4
4/6
4/5
5/8
5/6
6/10
6/7
7/8
7/12
8/14
Puncturing Scheme
Bit (1)
Multiplier
CA
1
0
CB
1
1
CA
1
0
1
CB
1
1
0
CA
1
0
0
0
CB
1
1
1
1
CA
1
0
1
0
1
CB
1
1
0
1
0
CA
1
0
0
1
0
1
CB
1
1
1
0
1
0
CA
1
0
0
0
1
0
1
CB
1
1
1
1
0
1
0
Note:
(1)
48
CA refers to the most significant (first transmitted bit, first received symbol); CB
refers to the least significant (last transmitted bit, last received symbol).
Altera Corporation
Viterbi Compiler User Guide
Specifications
Encoding Scheme
Figure 22 shows a convolutional encoder with parameters
constraint_length = 5, n = 2 and polynomials GA = 19 and GB = 29. GA
in decimal is 19 is equal to 10011 in binary. The most significant bit of the
binary representation is the connection at the input data bit; the least
significant bit represents the connection at the end of the shift register
chain. The XOR function implements the modulo-2 adding operation.
Figure 22 also shows the correspondence with the RR input port of the
Viterbi decoder and its DSP Builder model. Once the encoded bits are
quantified and sent through the channel, the symbol generated by the GA
polynomial is assigned to the most significant bits of the port rr and the
symbol generated by GB is assigned to the least significant bits. This is still
true for code rates n = 3 or n = 4.
Figure 22. Encoding Scheme
DSP
Builder
MSB
R2
LSB
R1
ga_xor
gb_xor
Performance
Tables 10 through 16 show typical expected performance for different
architectures and constraint_length combinations, and acs_units,
for various devices. Performance largely depends on
constraint_length. Results were generated using the Quartus II
software, version 2.2.
The tables for the hybrid continuous architectures use the BER option and
the following parameters:
v = 6 × constraint_length
softbits = 3
n=2
Altera Corporation
49
3
Specifications
RR
Port
Specifications
Viterbi Compiler User Guide
The tables for the parallel continuous architectures do not use the BER
option or the LogicLock script, and use n = 2.
Table 9. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 1
Device
constraint_length
LEs
Memory (1)
fMAX
(MHz)
Throughput
(Mbps)
Cyclone (EP1C6T144C6)
5
452
4
98
6.1
Stratix (EP1S20F780C5)
5
469
4+0
124
7.7
Cyclone (EP1C6T144C6)
7
650
5
101
1.5
Stratix (EP1S20F780C5)
7
674
3+2
120
1.8
Cyclone (EP1C6T144C6)
9
1,376
11
99
0.3
Stratix (EP1S20F780C5)
9
1,399
2+9
119
0.4
Notes:
(1)
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Table 10. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 2
Device
constraint_length
LEs
Memory (1)
fMAX
(MHz)
Throughput
(Mbps)
Any
5
Not Possible
Cyclone (EP1C6T144C6)
7
824
5
100
3.1
Stratix (EP1S20F780C5)
7
857
3+2
115
3.6
Cyclone (EP1C6T144C6)
9
1,536
11
101
0.7
Stratix (EP1S20F780C5)
9
1,570
2+9
122
0.9
Notes:
(1)
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Table 11. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 4
Device
constraint_length
LEs
Memory (1)
fMAX
(MHz)
Throughput
(Mbps)
Any
5
Cyclone (EP1C6T144C6)
7
1,148
5
Not Possible
105
6.5
Stratix (EP1S20F780C5)
7
1,193
1+4
122
7.6
Cyclone (EP1C6T144C6)
9
1,865
11
101
1.5
Stratix (EP1S20F780C5)
9
1,907
2+9
121
1.8
Notes:
(1)
50
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Altera Corporation
Viterbi Compiler User Guide
Specifications
Table 12. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 8
Device
constraint_length
LEs
Memory (1)
fMAX
(MHz)
Throughput
(Mbps)
Any
5
Not Possible
Any
7
Cyclone (EP1C6T144C6)
9
2,528
13
100
3.1
Stratix (EP1S20F780C5)
9
2,604
2 + 11
121
3.7
Not Possible
Notes:
(1)
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Table 13. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 16
Device
constraint_length
LEs
Memory (1)
fMAX
(MHz)
Throughput
(Mbps)
3
5
Not Possible
Any
7
Cyclone (EP1C6T144C6)
9
3,838
17
98
6.1
Stratix (EP1S20F780C5)
9
3,981
2 + 15
140
8.7
Not Possible
Notes:
(1)
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Altera Corporation
51
Specifications
Any
Specifications
Viterbi Compiler User Guide
Table 14. Performance & Area Utilization for Parallel Continuous Architecture (Memory-based Traceback)
Device
constraint_
length
softbits
v (1)
LEs
Memory
(2)
MHz
Throughput
(Mbps)
Cyclone (EP1C6T144C6)
3
2
5L
232
3
178
178
Stratix (EP1S20F780C5)
3
2
5L
232
3+0
188
188
Cyclone (EP1C6T144C6)
5
2
5L
537
3
169
149
Stratix (EP1S20F780C5)
5
2
5L
544
1+2
176
176
Cyclone (EP1C6T144C6)
7
2
5L
1,738
9
148
148
Stratix (EP1S20F780C5)
7
2
5L
1,741
1+8
165
165
Stratix (EP1S20F780C5)
9
2
5L
6,478
1 + 30
130
130
Cyclone (EP1C6T144C6)
7
3
6L
1,960
9
145
145
Stratix GX
(EP1SGX10DF672C6)
7
3
6L
1,961
1+8
145
145
Stratix GX
(EP1SGX10CF672C6)
7
3
6L
1,961
1+8
146
146
Stratix (EP1S20F780C5)
7
3
6L
1,961
1+8
159
159
Stratix (EP1S25F780C6)
7
3
6L
1,961
1+8
146
146
Stratix (EP1S10F780C5)
7
3
6L
1,961
1+8
152
152
Stratix (EP1S10F780C6)
7
3
6L
1,961
1+8
146
146
APEX II (EP2A15F672C7)
7
3
6L
1,972
9
129
129
APEX II (EP2A15F672C7) (3)
7
3
6L
2,090
9
146
146
Note:
(1)
(2)
(3)
Where L = constraint_length.
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
With the LogicLock script applied.
Table 15. Performance & Area Utilization for Parallel Continuous Architecture (Logic-based Traceback)
Device
constraint_
length
softbits
v (1)
LEs
Memory MHz
(2)
Throughput
(Mbps)
Cyclone (EP1C6T144C6)
3
2
5L
168
0
178
178
Stratix (EP1S20F780C5)
3
2
5L
169
0
192
192
Cyclone (EP1C6T144C6)
5
2
5L
692
0
169
169
Stratix (EP1S20F780C5)
5
2
5L
693
0
179
179
Cyclone (EP1C6T144C6)
7
2
5L
3,126
0
151
151
Stratix (EP1S20F780C5)
7
2
5L
3,126
0
159
159
Note:
(1)
(2)
52
Where L = constraint_length.
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other devices.
Altera Corporation
Viterbi Compiler User Guide
Specifications
Table 16. Performance & Area Utilization for Parallel Block Architecture
Device
constraint_
length
softbits
v (1)
LEs
Memory fMAX Throughput
(MHz)
(2)
(Mbps)
Cyclone (EP1C6T144C6)
3
2
10L
415
3
177
166
Stratix (EP1S20F780C5)
3
2
10L
426
3+0
188
176
Cyclone (EP1C6T144C6)
5
2
10L
840
3
159
147
Stratix (EP1S20F780C5)
5
2
10L
861
2+1
175
162
Cyclone (EP1C6T144C6)
7
2
10L
2,517
4
144
133
Stratix (EP1S20F780C5)
7
2
10L
2,589
2+2
159
146
Stratix (EP1S20F780C5)
9
2
5L
9,278
3+7
138
127
Note:
(1)
(2)
Where L = constraint_length.
M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices; ESBs for all other device.
Core
Verification
The core’s verification strategy included an automated regression test
suite, which is described in the following paragraphs.
3
The test script defined sets of tests that covered a comprehensive set of
parameters on RTL VHDL simulation.
The first tests were carried out with noiseless data. Then tests using a
subset of parameters, which used data with noise and performing millions
of bits at different signal-to-noise ratios, were carried out to evaluate the
BER performance. The BER performance matches the theoretical behavior
of a Viterbi decoder (see Figure 23). Another subset of parameters was
tested with noiseless data using post-synthesis Vital VHDL netlist.
Altera Corporation
53
Specifications
Tcl scripts drove the simulation at RTL level. Data was randomly
generated and encoded. The original transmitted bits were stored in a file
transbit.txt. Optionally, Gaussian noise was added as a channel model
and the data was formatted for use by the decoder’s testbench. The file
that fed the testbench was a_rcvsym.txt. The testbench collected the
decoder’s decoded bits and stored them in decoded.txt. Those bits were
compared with the original in transbit.txt.
Specifications
Viterbi Compiler User Guide
Figure 23. Graph of Actual BER vs. Signal-to-Noise Ratio for various Values of Rate
1.00e-01
Rate 1/2, 3 softbits
Rate 2/3, 3 softbits
Rate 3/4, 3 softbits
Rate 7/8, 3 softbits
Unencoded BPSK
1.00e-02
1.00e-03
BER 1.00e-04
1.00e-05
1.00e-06
1.00e-07
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
7.00
Signal-to-Noise Ratio
The set of test parameters that were chosen were comprehensive and
should detect any malfunction in any of the features or parameter sets of
the four core architectures.
54
Altera Corporation