UTOPIA Level 3 Master
MegaCore Function
UTOPIA3MS
User Guide
November 2001
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
A-UG-IPUTOPIA3MS-1.00
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Copyright
Copyright © 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device
designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise,
the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are
the property of their respective holders. Altera Corporation acknowledges the trademarks of other organizations for their
respective products or services mentioned in this document, including the following: Verilog is a registered trademark of Cadence
Design Systems, Incorporated. Java is a trademark of Sun Microsystems Inc. Microsoft is a registered trademark and Windows is
a trademark of Microsoft Corporation. ModelSim is a registered trademark of Model Technology Inc. Altera products are
protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s
standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services. All rights reserved
ii
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About this User Guide
User Guide
This user guide provides comprehensive information about the Altera®
UTOPIA Level 3 Master MegaCore® function (UTOPIA3MS).
Table 1 shows the user guide revision history.
B
Go to the following sources for more information:
■
Refer to the UTOPIA3MS readme file for late-breaking information
that is not available in this user guide.
Table 1. User Guide Revision History
Date
November 2001
How to Find
Information
■
■
■
■
Altera Corporation
Description
Initial release.
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About this User Guide
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Access
USA & Canada
All Other Locations
Altera Literature
Services
Electronic mail
[email protected] (1)
[email protected] (1)
Non-technical
customer service
Telephone hotline
(800) SOS-EPLD
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Fax
(408) 544-7606
(408) 544-7606
Telephone hotline
(800) 800-EPLD
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Fax
(408) 544-6401
(408) 544-6401 (1)
On-line
http://www.altera.com/mysupport http://www.altera.com/mysupport
FTP site
ftp.altera.com
ftp.altera.com
Telephone
(408) 544-7104
(408) 544-7104 (1)
Technical support
General product
information
World-wide web site http://www.altera.com
http://www.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Typographic
Conventions
About this User Guide
The UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User
Guide uses the typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Quartus II and MAX+PLUS II
Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX
8000 Device with the BitBlaster™ Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
L
Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
H
The hand points to information that requires special attention.
B
The feet direct you to more information on a particular topic.
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The angled arrow indicates you should press the Enter key.
v
About this User Guide
Abbreviations
and Acronyms
vi
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
AHDL
ATM
CPU
EDA
EOP
ERR
ESB
FIFO
Gbps
HDL
I/O
IP
LE
LSB
LSByte
Mbps
MPHY
MSB
MSByte
OC-12
OC-48
OSI
PC
PHY
PLD
RX
SOC
SOP
SPHY
TX
UTOPIA
VHDL
VHSIC
Altera hardware description language
asynchronous transfer mode
central processing unit
electronic design automation
end of packet
error
embedded system block
first-in first-out
gigabits per second
hardware description language
input/output
intellectual property
logic element
least significant bit
least significant byte
megabits per second
multi-PHY
most significant bit
most significant byte
optical carrier level 12
optical carrier level 48
open system interconnection
personal computer
OSI physical layer
programmable logic device
receive
start of cell
start of packet
single-PHY
transmit
universal test & operations physical interface for ATM
VHSIC hardware description language
very high speed integrated circuit
Altera Corporation
Contents
About this User Guide
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Abbreviations and Acronyms ...................................................................................................... vi
About this Core
General Description .........................................................................................................................9
Features .............................................................................................................................................9
Getting Started
Design Walkthrough .....................................................................................................................11
Obtaining & Installing the UTOPIA3MS ....................................................................................12
Downloading the MegaCore Function ...............................................................................12
Installing the MegaCore Files ...............................................................................................12
Generating a Custom UTOPIA3MS ............................................................................................13
Implementing the System .............................................................................................................14
Simulating Your Design ................................................................................................................14
Using the Verilog HDL Demo Testbench ...........................................................................14
Using the Visual IP Software ................................................................................................15
Synthesis, Compilation & Place & Route ...................................................................................15
Using Third-Party EDA Tools for Synthesis ......................................................................15
Using the Quartus II Development Tool for Compilation & Place-and-Route ............15
Licensing for Configuration .........................................................................................................16
Performing Post-Routing Simulation ..........................................................................................16
Specifications
Performance ....................................................................................................................................18
Interfaces & Protocols ....................................................................................................................19
UTOPIA Level 3 Interface .....................................................................................................19
Atlantic Interface ....................................................................................................................19
Functional Description ..................................................................................................................20
Data Flow (DIR) .....................................................................................................................20
TXUTOPIA3MS ..............................................................................................................20
RXUTOPIA3MS ..............................................................................................................21
UTOPIA Level 3 Block ..................................................................................................23
FIFO Buffer .....................................................................................................................23
Bus Parity (PRTY) ..................................................................................................................23
Altera Corporation
vii
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Contents
Interface Bus Width ...............................................................................................................24
UTOPIA Data Width (UDAT) ......................................................................................24
Atlantic Data Width (ADAT) .......................................................................................24
FIFO Buffer (FIFO) .........................................................................................................24
Cell Length (CLEN) ...............................................................................................................25
PHY Configuration ................................................................................................................28
Multi-PHY (MPHY) .......................................................................................................28
Number of Ports (NPORTS) .........................................................................................28
Multi-PHY Address Translation (ATRANS) .............................................................28
Direct Status Indication Mode (DSTAT) .....................................................................28
I/O Signals ......................................................................................................................................29
Typical Configurations ..................................................................................................................32
AC Timing .......................................................................................................................................36
viii
Altera Corporation
About this Core
1
General
Description
The UTOPIA Level 3 Master MegaCore® function (UTOPIA3MS) is
designed for use in asynchronous transfer mode (ATM) devices that
transfer data to and from physical layer (PHY) devices using the UTOPIA
Level 3 interface, as defined by the ATM Forum.
The UTOPIA level 3 interface specifies an operating frequency of up to
104 MHz, and a data path width of 8, 16, or 32 bits resulting in data
transfer rates of up to 832 Mbps, 1.6 Gbps, or 3.2 Gbps, respectively.
Typical applications for the UTOPIA3MS include: OC-48, quad OC-12, or
16 × OC-3 line rates.
The UTOPIA3MS is compliant with all applicable standards, including:
■
Features
Altera Corporation
■
ATM Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy0136.000, November 1999.
Altera® Corporation, AtlanticTM Interface Specification.
■
■
■
■
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■
■
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■
Configurable for receive or transmit directions
Supports single-PHY (SPHY) and multi-PHY(MPHY) operation
Configurable for up to 31 devices in MPHY mode
Optional configuration of port/address map
Configurable UTOPIA data width of 8, 16, or 32 bits
Configurable Atlantic slave interface data width of 8, 16, 32, or 64 bits
Configurable cell transfer length
Optional parity error detection
Optional direct status indication
9
About this Core
User Guide
Notes:
Getting Started
User Guide
2
You can test-drive a UTOPIA3MS using the Altera® OpenCore® feature—
within the Quartus® II software—to instantiate it, to perform place-androute, to perform static timing analysis, and to simulate it using a thirdparty simulator, within your custom logic. You only need licenses when
you are ready to generate programming files.
Getting
GettingStarted
Started
Design
Walkthrough
This section describes how to obtain a variant from the UTOPIA Level 3
Master MegaCore® function (UTOPIA3MS). It explains how to install the
UTOPIA3MS on your PC, and walks you through the process of
implementing the variant in a design.
This design walkthrough involves the following steps:
1.
Obtaining and installing the UTOPIA3MS MegaCore function.
2.
Generating a custom UTOPIA3MS for your system using the Altera
MegaWizard® Plug-In.
3.
Implementing the rest of your system using AHDL, VHDL, or
Verilog HDL.
4.
Simulating the UTOPIA3MS within your design.
5.
Synthesis, compilation, and place-and-route.
6.
Licensing the UTOPIA3MS to configure the device.
7.
Performing post-routing simulation.
The instructions assume that:
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Altera Corporation
You are using a PC
You are familiar with the Quartus II software.
The Quartus II software (the newest version) is installed in the default
location.
You are using the OpenCore feature to test-drive a UTOPIA3MS, or
you have licensed it.
11
Getting Started
Obtaining &
Installing the
UTOPIA3MS
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
To start using the UTOPIA3MS, you need to obtain the MegaCore
package, which includes the following:
■
■
■
■
■
■
Data sheet
User guide
Atlantic interface functional specification
MegaWizard Plug-In
–
Encrypted gate-level netlist
–
Place-and-route constraints (where necessary)
–
Secure RTL simulation model
Demo testbench
Access to problem reporting system
Downloading the MegaCore Function
If you have Internet access, you can download the UTOPIA Level 3
MegaCore function from the Altera web site. Follow the instructions
below to obtain the core via the Internet. If you do not have Internet
access, you can obtain the core from your local Altera representative.
1.
Point your web browser at http://www.altera.com/IPmegastore.
2.
In the IP MegaSearch keyword field type UTOPIA.
3.
Click the link for the UTOPIA Level 3 Master MegaCore function.
4.
On the product page, click the Free Test-Drive icon.
5.
Follow the on-line instructions to download the function and save it
to your hard disk.
Installing the MegaCore Files
Use the MegaWizard Plug-In to generate the files and install them on your
PC. The following instructions describe this process.
For UNIX systems, you must have Java runtime environment version 1.3
before you can use the MegaWizard Plug-In. You can download this file
from the Java web site at http://www.java.sun.com.
For Windows, follow the instructions below:
1.
12
Click Run (Start menu).
Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Generating a
Custom
UTOPIA3MS
GettingGetting Started
2.
Type <path name>\<filename>.exe, where <path name> is the location
of the downloaded UTOPIA3MS and <filename> is the filename of
the UTOPIA3MS. Click OK.
3.
The MegaCore Installer dialog box appears. Follow the
MegaWizard Plug-In instructions to finish the installation.
To create a custom UTOPIA3MS using the MegaWizard Plug-In, follow
these steps:
1.
Refer to Quartus II Help for detailed instructions on how to use
the MegaWizard Plug-In Manager.
2.
Specify that you want to create a new custom variant and click Next.
3.
On the second page of the MegaWizard Plug-In, open the
Communications folder, and select the UTOPIA3MS from the
UTOPIA folder.
4.
Choose the type of output files (language), specify the folder and
name for the files the MegaWizard Plug-In creates, and click Next.
5.
Select the optional parameters and choices that you require.
6.
Altera Corporation
Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In
Manager command (Tools menu) in the Quartus II software. The
MegaWizard Plug-In Manager dialog box is displayed.
If your chosen variant (configuration) is not included as part of
the downloaded package, the MegaWizard Plug-In generates the
necessary text to request this variant. Forward this text to
[email protected] for processing.
The final screen lists the design files created by the MegaWizard
Plug-In, and indicates the location of the simulation models for the
selected variant. Click Finish.
13
2
Getting Started
This section describes the design flow using the UTOPIA Level 3 Master
MegaCore function and the Quartus II development system. A
MegaWizard Plug-In is provided with the UTOPIA3MS. The
MegaWizard Plug-In Manager—used within the Quartus II software—
allows you to create or modify design files to meet the needs of your
application. You can then instantiate the UTOPIA3MS in your design file.
Getting Started
Implementing
the System
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Once you have created/obtained your custom UTOPIA3MS, you are
ready to implement it. You can use the files generated by the MegaWizard
Plug-In, and use the Quartus II software or other EDA tools to create your
design. Table 1 lists the generated files.
Table 1. MegaWizard Plug-In Files
Description
Verilog HDL
VHDL
Design File Wrapper
.v
.vhd
Sample Instantiation
_inst.v
_inst.vhd
Black Box Module
_bb.v
–
.bsf
.bsf
.e.vqm.v
.e.vqm.v
Symbol files for the Quartus II software used to instantiate the
UTOPIA3MS into a schematic design
An encrypted HDL netlist file
Note:
(1) AHDL output file creation is not supported in the UTOPIA3MS v1.0.0 MegaWizard Plug-In. If AHDL output
files are required, please file a request through http://www.altera.com/mysupport.
Simulating
Your Design
Altera provides three models to be used for functional verification of the
UTOPIA3MS within your design. A Verilog HDL demo testbench,
including scripts to run it, is also provided. This demo testbench used
with the ModelSim-Altera simulation tool demonstrates how to
instantiate a model in a design.
To find the simulation models for your selected variant, refer to the last
page of the MegaWizard Plug-In Manager. These models and the demo
testbench are located on your hard drive, the paths are:
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■
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sim_lib/<variant>/modelsim_verilog/
sim_lib/<variant>/modelsim_vhdl/
sim_lib/<variant>/visual_ip/
sim_lib/<variant>/test/
<variant> is a unique code (aotXXXX_#_utopia3ms) assigned to
the specific configuration requested through the MegaWizard
Plug-In.
Using the Verilog HDL Demo Testbench
The demo testbench includes some simple stimulus to control the user
interfaces of the UTOPIA3MS. Each UTOPIA3MS variant includes scripts
to compile and run the demo testbench using a variety of simulators and
models.
14
Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
GettingGetting Started
Using the Visual IP Software
The Visual IP software facilitates the use of Visual IP simulation models
with third-party simulation tools. To view a simulation model, you must
have the Visual IP software installed on your system. To download the
software, or for instructions on how to use the software, refer to the Altera
web site at http://www.altera.com, and search for Visual IP. For
examples of how to use the provided Visual IP model, refer to the sample
scripts included with the demo testbench.
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
1.
Create your custom design instantiating a UTOPIA3MS.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the UTOPIA3MS instantiation as a black box by
either setting attributes or ignoring the instantiation.
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Placeand-Route
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
Altera Corporation
1.
Select Compile mode (Processing menu).
2.
Specify the compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Specify the input settings for the project. Choose EDA Tool Settings
(Project menu). Select Custom EDIF in the Design entry/synthesis
tool list. Click Settings. In the EDA Tool Input Settings dialog box,
make sure that the relevant tool name or option is selected in the
Design Entry/Synthesis Tool list.
15
2
Getting Started
Synthesis,
Compilation &
Place & Route
Getting Started
B
Licensing for
Configuration
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
4.
Add your third-party EDA tool-generated netlist file to your project.
5.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
6.
Add the pre-synthesized and encrypted .e.vqm.v file from your
working directory, created by the MegaWizard Plug-In Manager.
7.
Constrain your design as required.
8.
Compile your design. The Quartus II compiler synthesizes and
performs place-and-route on your design.
Refer to Quartus II Help for further instructions on performing
compilation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera PLD. If you are evaluating the
UTOPIA3MS with the OpenCore feature, you must license the function
before you can generate programming files. To obtain licenses contact
your local Altera sales representative.
Performing
Post-Routing
Simulation
16
All current UTOPIA3MS variants use a single license, with
ordering code: PLSM-UTOPIA3MS.
After you have licensed the UTOPIA3MS, you can generate EDIF, VHDL,
Verilog HDL, and Standard Delay Output Files from the Quartus II
software and use them with your existing EDA tools to perform functional
modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, refer to the
“Using the Quartus II Development Tool for Compilation & Placeand-Route”section. The Quartus II software generates output and
programing files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
Altera Corporation
Specifications
User Guide
Customized variants of the UTOPIA Level 3 Master MegaCore function
(UTOPIA3MS) can be generated/requested using the MegaWizard® PlugIn within the Quartus® II software.
Table 1 shows the optional features available to generate all variants.
Table 1. Optional Features
Options
Parameters
Choices
Data flow
DIR
Bus parity
PRTY
Yes / No
Include FIFO buffer
FIFO
Yes / No
UTOPIA data width
UDAT
8 / 16 / 32
Atlantic data width (1)
ADAT
8 / 16 / 32 / 64
Cell length
CLEN
52
53 (n/a for UTOPIA data width of 16 or 32)
54 (n/a for UTOPIA data width of 8 or 32)
56 (n/a for UTOPIA data width of 8 or 16)
MPHY
Yes / No
3
Number of ports (2)
NPORTS
2 - 31 (only valid when MPHY = Yes)
Multi-PHY address
translation (2)
ATRANS
Direct (No translation)
Custom (Port to address mapping)
Direct status mode (3)
DSTAT
Yes / No
Notes:
(1)
(2)
(3)
B
Altera Corporation
FIFO buffer required, otherwise Atlantic data width must be equal to UTOPIA data
width.
Only applicable for multi-PHY configuration.
Only available for multi-PHY configuration with up to 4 ports.
For detailed instructions on generating a custom UTOPIA3MS, refer to the
“Generating a Custom UTOPIA3MS” section in the “Getting Started”
chapter.
17
Specifications
Multi-PHY
RX / TX
Specifications
Performance
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Tables 2 to 4 show the estimated resource utilization and performance for
these sample configurations. The utilization and performance information
was generated with the Quartus II version 1.1 software, for an APEX
20K400E-1 device
Table 2 lists the estimated resources and speed of a one port
RXUTOPIA3MS and TXUTOPIA3MS.
Utilization
Table 2. One Port Configuration
Direction
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3MS
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=No
318
3
144
TXUTOPIA3MS
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=No
340
3
138
Table 3 lists the estimated resources and speed of a four port
RXUTOPIA3MS and TXUTOPIA3MS.
Utilization
Table 3. Four Port Configuration
Direction
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3MS
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
1,215
12
106
TXUTOPIA3MS
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
1,329
12
116
Table 4 lists the estimated resources and speed of an RXUTOPIA3MS and
a TXUTOPIA3MS without FIFO buffers.
Table 4. Four Port No FIFO Buffer Configuration
Direction
Utilization
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3MS
PRTY=No, FIFO=No, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
364
–
125
TXUTOPIA3MS
PRTY=No, FIFO=No, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
241
–
116
18
Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Interfaces &
Protocols
GettingSpecifications
Two interfaces, described below, support the UTOPIA3MS.
UTOPIA Level 3 Interface
The UTOPIA level 3 interface is an external protocol defined by the ATM
Forum. Depending on the variant chosen (see Table 1), the UTOPIA3MS
uses this interface to support: a data width of 8, 16, or 32 bits, SPHY or
MPHY operation, bus parity, 52, 53, 54, or 56 octet cells, and direct status
or polling mode.
If MPHY = No, the utxaddr[4:0]/urxaddr[4:0] address lines are
not present. If DSTAT = No, the utxclav[3:1]/urxclav[3:1] ports
are not present. If PRTY = No, the utxprty/urxprty ports are not
present.
B
For further information on this interface, refer to the ATM Forum,
UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November
1999, available at http://www.atmforum.com.
3
Atlantic Interface
If the chosen variant of the UTOPIA3MS is configured to include a multicell first in first out (FIFO) buffer for crossing the clock domain, the
Atlantic interface operates as a slave, otherwise it operates as a master.
B
Altera Corporation
For further information on this interface, refer to the Atlantic Interface
Functional Specification, available at http://www.altera.com.
19
Specifications
The AtlanticTM interface is a full-duplex synchronous bus protocol. The
UTOPIA3MS supports data widths of 8, 16, 32, and 64 bits on the Atlantic
interface. If PRTY = No, the arxpar/atxpar ports are not present.
Specifications
Functional
Description
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
This section describes the various optional features available to generate
a UTOPIA3MS, and their respective functions. Some of these options are
inter-dependent, and are therefore grouped and described accordingly.
Data Flow (DIR)
The UTOPIA3MS functions either as a transmitter (TXUTOPIA3MS)
where data flows from the ATM device to the PHY device, or as a receiver
(RXUTOPIA3MS) where data flows from the PHY device to the ATM
device. Both the TXUTOPIA3MS and RXUTOPIA3MS have control
signals for handshaking.
In order for the UTOPIA3MS to act as a full-duplex, bidirectional
transceiver, you need to instantiate two variants: a
TXUTOPIA3MS and a RXUTOPIA3MS.
TXUTOPIA3MS
The TXUTOPIA3MS polls the PHY layer device to determine whether it is
ready to receive data transfers. Polling is achieved when the
TXUTOPIA3MS outputs the port address on the utxaddr bus. If the port
can accept one or more complete ATM cells, the PHY device accepts the
data transfer by driving the utxclav signal high, in accordance with the
UTOPIA level 3 interface specification. Thus the TXUTOPIA3MS accepts
cells from the Atlantic interface and sends them to the PHY layer device
via the UTOPIA Level 3 interface. Figure 1 shows the TXUTOPIA3MS
block diagram.
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
GettingSpecifications
Figure 1. TXUTOPIA3MS Block Diagram
FIFO Port 0 Clock Domain
UTOPIA Clock Domain
arxclk_0
arxreset_n_0
arxena_0
Atlantic
Interface
FIFO
arxdav_0
Port 0
arxdat_0[63/31/15/7:0]
arxpar_0
arxsop_0
arxerr_0
soc_0
Global Signals
soc_err_0
UTOPIA
oflw_err_0
Level 3
Block
FIFO Port N* Clock Domain
utxclk
utxreset_n
utxenb_n
utxaddr[4/3/2/1/0:0]
utxclav[3/0:0]
utxdata[31/15/7:0]
utxprty
utxsoc
prty_err
UTOPIA
Level 3
Interface
Global Signal
3
arxclk_N*
arxreset_n_N*
FIFO
Specifications
arxena_N*
arxdav_N*
Atlantic
Interface arxdat_N*[63/31/15/7:0]
Port N* (1)
arxpar_N*
arxsop_N*
arxerr_N*
soc_N*
Global Signals
soc_err_N*
oflw_err_N*
Note:
(1)
N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
RXUTOPIA3MS
The RXUTOPIA3MS polls the PHY layer device to determine whether it is
ready to transfer data. Polling is achieved when the RXUTOPIA3MS
outputs the port address on the urxaddr bus. If the port is ready to send
one or more complete ATM cells, the PHY device completes the data
transfer by driving its urxclav signal high, in accordance with the
UTOPIA level 3 interface specification. Thus the RXUTOPIA3MS accepts
cells from the PHY layer device via the UTOPIA Level 3 interface, and
sends them to the Atlantic interface. Figure 2 shows the RXUTOPIA3MS
block diagram.
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 2. RXUTOPIA3MS Block Diagram
FIFO Port 0 Clock Domain
Atlantic
Interface
atxclk_0
atxreset_n_0
atxena_0
atxdav_0
atxdat_0[63/31/15/7:0]
atxval_0
atxpar_0
atxsop_0
atxeop_0
atxerr_0
Global Signals
UTOPIA Clock Domain
FIFO
Port 0
soc_0
soc_err_0
uflw_err_0
UTOPIA
Level 3
Block
FIFO Port N* Clock Domain
atxclk_N*
atxreset_n_N*
atxena_N*
atxdav_N*
Atlantic atxdat_N*[63/31/15/7:0]
Interface
atxval_N*
atxpar_N*
atxsop_N*
atxeop_N*
atxerr_N*
Global Signals
urxclk
urxreset_n
urxenb_n
urxaddr[4/3/2/1/0:0]
urxclav[3/0:0]
urxdata[31/15/7:0]
urxprty
urxsoc
prty_err
UTOPIA
Level 3
Interface
Global Signal
FIFO
Port N* (1)
soc_N*
soc_err_N*
uflw_err_N*
Note:
(1)
N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
B
For further details on the transmitter or receiver functions, including
timing information, refer to the ATM Forum, UTOPIA 3 Physical Layer
Interface Specification, af-phy-0136.000, November 1999.
Both variants, TXUTOPIA3MS and RXUTOPIA3MS, are further divided
into sub-blocks: the UTOPIA block and the FIFO buffer, as illustrated in
Figures 1 and 2.
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UTOPIA Level 3 Block
The UTOPIA block is the Input/Output (I/O) port for the UTOPIA level
3 interface. This block’s primary function is address polling and port
selection. The following is a summary list of functions.
■
■
■
■
Round-robin address polling
Back-to-back cell transfer
Cell-based handshaking
UTOPIA data bus parity checking
–
Parity error indication
FIFO Buffer
The FIFO buffer is used for clock decoupling between the internal clock
and the UTOPIA clock. The following is a summary list of functions.
■
■
■
3
Specifications
■
■
■
■
Data width conversion
Cell-based handshaking
Start of packet (SOP) error detection
–
SOP indication
–
Spurious or missing SOP error indication
End of packet (EOP) generation
Error (ERR) signal generation
Overflow indication
Underflow indication
For both UTOPIA and FIFO buffer sub-blocks, functionality is largely
dependent on the chosen variant, see Table 1.
Bus Parity (PRTY)
The UTOPIA level 3 interface specifies that odd parity be passed.
In the transmit direction, where data flows from the Atlantic interface to
the UTOPIA level 3 interface, the user must insert the parity (arxpar)
lines for the correct parity to be placed on the utxprty line. The data bus
(arxdat) and parity (arxpar) are monitored for errors. When an error is
detected, the prty_err signal is asserted for one clock cycle.
In the receive direction, where data flows from the UTOPIA level 3
interface to the Atlantic interface, the data bus (urxdata) and parity
(urxprty) lines are monitored for errors. When a parity error is detected,
the prty_err signal is asserted for one clock cycle. The error signal
(atxerr) on the Atlantic bus is asserted upon detecting the parity error
until the end of the current cell.
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Interface Bus Width
UTOPIA Data Width (UDAT)
This feature sets the UTOPIA data bus width. In accordance with UTOPIA
level 3 interface handshaking, the UTOPIA3MS supports the three
following options:
■
■
■
8-bit UTOPIA data bus
16-bit UTOPIA data bus
32-bit UTOPIA data bus
The UTOPIA data bus width can differ from the Atlantic data
bus width.
Atlantic Data Width (ADAT)
This feature sets the Atlantic data bus width. Four choices are available: 8,
16, 32, or 64 bits.
If the Atlantic data width chosen is not equal to the UTOPIA data
bus width, the user MUST also choose the “Include FIFO buffer”
option.
FIFO Buffer (FIFO)
The user has the option to include, or not include a FIFO buffer. If the user
chooses the “Include FIFO buffer” option, one FIFO buffer is included for
each port. The FIFO buffer is large enough to store at least four full cells.
If the FIFO is not included, the Atlantic interface signals are on the same
clock domain as the UTOPIA clock.
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GettingSpecifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Three global signals: soc_N*, soc_err_N*, and oflw_err_N* or
uflw_err_N* are also included, and intended as additional optional
logic to be used as required by the user. The soc_N* signal indicates a cell
has been written to the FIFO buffer from either the UTOPIA level 3
interface via the RXUTOPIA3MS, or the Atlantic interface via the
TXUTOPIA3MS. The soc_err_N* signal is asserted to indicate a start of
cell (soc) error condition. A soc error indicates a start of packet (SOP) is
incorrectly positioned. The oflw_err_N* indicates that a cell transfer has
been initiated with the arxdav (TXUTOPIA3MS) deasserted thus
indicating that the FIFO buffer cannot accept a full cell. This overflowtype condition causes the cell to be discarded. The uflw_err_N*
indicates an underflow condition exists in the FIFO buffer. The
uflw_err_N* signal is asserted when a read from the FIFO buffer is
attempted and no data is available.
In the TXUTOPIA3MS, the soc_N*, soc_err_N*, and oflw_err_N*
signals are synchronous to the arxclk_N*. The soc_N* signal is asserted
when the arxsop_N* signal is sampled asserted on the Atlantic interface.
The soc_err_N* signal is asserted when an error is detected on the
arxsop_N* signal on the Atlantic interface.
soc_err_N*
In the RXUTOPIA3MS, the
and
signals are
synchronous to the urxclk. The uflw_err_N* is synchronous to the
arxclk. The soc_N* signal is asserted two clock cycles after the urxsoc
signal is sampled asserted. The soc_err_N* signal is asserted one clock
cycle after an error is detected on the utxsoc signal.
Cell Length (CLEN)
The UTOPIA level 3 interface specifies a standard cell structure of 52
octets for all UTOPIA data widths. The following cell structures are also
supported:
■
■
■
53 octets for the 8-bit UTOPIA data bus
54 octets for the 16-bit UTOPIA data bus
56 octets for the 32-bit UTOPIA data bus
The UTOPIA3MS converts cells formatted for the Atlantic into a cell
structure used by the UTOPIA level 3 interface. Figures 3 to 7 show the cell
structures used to transport data across the Atlantic interface.
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3
Specifications
soc_N*,
Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 3. 8-Bit Atlantic Interface, 52-and 53-Octet Cell Structures
7
DAT
0 SOP
EOP
7
DAT
0
SOP
EOP
H1
1
0
H1
1
0
H2
0
0
H2
0
0
H3
0
0
H3
0
0
H4
0
0
H4
0
0
P1
0
0
HEC
0
0
P2
0
0
P1
0
0
P2
0
0
P48
0
1
P48
0
1
52 octets
53 octets
Figure 4. 16-Bit Atlantic Interface, 52 and 54 Octet Cell Structures
EOP
DAT
15
0 SOP
EOP
H1
H2
1
0
H1
H2
1
0
H3
H4
0
0
H3
H4
0
0
P1
P2
0
0
HEC
UDF
0
0
P1
P2
0
0
P48
0
1
P47
P48
52 octets
26
0 SOP
DAT
15
0
1
P47
54 octets
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 5. 32-Bit Atlantic Interface, 52 and 56 Octet Cell Structures
31
0 SOP
DAT
EOP
31
DAT
0 SOP
EOP
H1
H2
H3
H4
1
0
H1
H2
H3
H4
1
0
P1
P2
P3
P4
0
0
HEC
UDF
UDF
UDF
0
0
P1
P2
P3
P4
0
0
P45
P46
P47
P48
0
1
P45
P46
P47
P48
0
1
52 octets
56 octets
Figure 6. 64-Bit Atlantic Interface, 56 Octet Cell Structure
0 SOP
DAT
63
EOP
H2
H3
H4
HEC
UDF
UDF
UDF
1
0
P1
P2
P3
P4
P5
P6
P7
P8
0
0
P41
P42
P43
P44
P45
P46
P47
P48
0
1
3
Specifications
H1
56 octets with HEC
Figure 7. 64-Bit Atlantic Interface, 52 Octet Cell Structure
63
0 SOP
DAT
H3
H4
X
X
P1
P2
P3
P4
P5
P6
P41
P42
P43
P44
P45
P46
P47
(1)
EOP
X
H2
(1)
X
H1
1
0
P7
P8
0
0
P48
0
1
(1)
(1)
56 octet without HEC
Note:
(1)
In the case of a 52-octet cell, DAT [31:0] is discarded
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
PHY Configuration
The UTOPIA3MS can be configured for one of two modes of operation:
SPHY or MPHY.
The SPHY configuration is a single data path, point-to-point connection
between the ATM device and PHY device. Only one Atlantic interface
port is included.
Multi-PHY (MPHY)
The MPHY configuration is a multi data path, point-to-point connection
between the ATM device and PHY device. A dedicated Atlantic interface
is included for each port.
Number of Ports (NPORTS)
If the chosen UTOPIA3MS variant includes the MPHY option, the user
can select the number of ports, up to 31.
Multi-PHY Address Translation (ATRANS)
This feature offers two options for translation: Direct or Custom.
■
■
Direct implies no translation. Ports are assigned in a sequential order,
starting at zero.
Custom implies port to address mapping. The user specifies an
address for each port via the MegaWizard Plug-In.
Direct Status Indication Mode (DSTAT)
The UTOPIA3MS can be configured to operate in direct, or polling status
mode.
For polling status mode, in the TXUTOPIA3MS, a single UTOPIA Clav
(utxclav[0]) signal is polled to determine whether the PHY device can
accept at least one entire cell; in the RXUTOPIA3MS, a single UTOPIA
Clav (urxclav[0]) signal is polled to determine whether the PHY device
can transmit at least one entire cell. This applies for any number of ports,
from 2 to 31.
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
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For direct status indication mode, in the TXUTOPIA3MS, four UTOPIA
Clav (utxclav[3:0]) signals, one for each port, are polled to determine
whether the PHY device can accept at least one entire cell; in the
RXUTOPIA3MS, four UTOPIA Clav (urxclav[3:0]) signals, one for
each port, are polled to determine whether the PHY device can accept at
least one entire cell. The DSTAT mode is only possible when the chosen
variant is an MPHY device with up to four ports.
I/O Signals
Tables 5 to 9 list the I/O signals used in the UTOPIA3MS The active low
signals are indicated by _n.
Table 5. UTOPIA Level 3 Transmit Interface
Signal
Direction
Description
Configuration
Requirement
utxclk
Input
Transfer/Interface clock
None
utxreset_n
Input
Active low synchronous reset
None
utxenb_n
ATM to PHY
Active low signal. Enables port selection in
MPHY mode
None
utxaddr[n:0]
ATM to PHY
Address for MPHY device being selected
MPHY = Yes
utxclav[0]
PHY to ATM
Cell buffer may accept at least one entire cell None
utxclav[3:1]
PHY to ATM
Cell buffer may accept at least one entire cell NPORTS <=4, DSTAT
utxdata
[31/15/7:0]
ATM to PHY
Data bus
UDAT = 32, 16, 8
utxprty
ATM to PHY
Odd parity calculated across data bus
PRTY = Yes
utxsoc
ATM to PHY
Start of cell
None
3
Specifications
Table 6. UTOPIA Level 3 Receive Interface (Part 1 of 2)
Signal
Direction
Description
Configuration
Requirement
urxclk
Input
Transfer/Interface clock
None
urxreset_n
Input
Active low synchronous reset
None
urxenb_n
ATM to PHY
Enables port selection in MPHY mode
None
urxaddr[4:0]
ATM to PHY
Address for MPHY device being selected
MPHY = Yes
urxclav[0]
PHY to ATM
At least one entire cell is available in the
FIFO buffer
None
urxclav[3:1]
PHY to ATM
At least one entire cell is available in the
FIFO buffer
NPORTS <=4, DSTAT
urxdata
[31/15/7:0]
PHY to ATM
Data bus
UDAT = 32, 16, 8
urxprty
PHY to ATM
Odd parity calculated across data bus
PRTY = Yes
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Table 6. UTOPIA Level 3 Receive Interface (Part 2 of 2)
Signal
urxsoc
Direction
PHY to ATM
Description
Start of cell
Configuration
Requirement
None
Table 7. Atlantic Receive Interface
Signal
Direction
Description
Configuration
Requirement
arxclk
Input
Clock
FIFO = Yes
arxreset_n
Input
Active low synchronous reset
FIFO = Yes
arxena
Master to Slave Enables port selection in MPHY mode
None
arxdat
[63/31/15/7:0]
Input
ADAT = 64, 32, 16, 8
arxval
Slave to Master Data valid
arxdav
Slave to Master Cell buffer may accept at least one entire cell None
arxpar
Input
Odd parity calculated across data bus
PRTY = Yes
arxsop
Input
Start of packet
None
arxerr
Input
Data error
None
Data bus
FIFO = No
Table 8. Atlantic Transmit Interface
Signal
Direction
Description
Configuration
Requirement
atxclk
Input
Clock
FIFO = Yes
atxreset_n
Input
Active low synchronous reset
FIFO = Yes
atxena
Master to Slave Enables port selection in MPHY mode
atxdav
Slave to Master Cell buffer may accept at least one entire cell None
atxdat
[63/31/15/7:0]
Output
atxval
Slave to Master Data valid
FIFO = Yes
atxpar
Output
Odd parity calculated across data bus
PRTY = Yes
atxsop
Output
Start of packet
None
atxeop
Output
End of packet
None
atxerr
Output
Data error. Current cell contains a soc or prty None
error and should be discarded.
30
Data bus
None
ADAT = 64, 32, 16, 8
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
GettingSpecifications
Table 9. Global Signals
Signal
Direction
Description
Configuration Requirement
prty_err
Output
Parity error in current cell
PRTY = Yes
soc[n-1:0]
Output
Start of cell has been written to the FIFO. FIFO = Yes
soc_err[n-1:0]
Output
Start of cell error.
FIFO = Yes
oflw_err[n-1:0] Output
FIFO overflow. Current cell is discarded. FIFO=Yes, DIR=TX
uflw_err[n-1:0] Output
FIFO underflow
FIFO=Yes, DIR=RX
3
Specifications
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Typical
Configurations
This section shows some common example configurations, illustrated in
Figures 8 to 12.
Figure 8 shows an RXUTOPIA3MS and a TXUTOPIA3MS configured for
one port, and for full-duplex operation.
Figure 8. One Port Configuration.
RXUTOPIA3MS
FIFO Port 0 Clock Domain
UTOPIA Clock Domain
atxclk_0
atxreset_n_0
urxclk
atxena_0
Atlantic
Interface
atxdav_0
FIFO
UTOPIA
atxdat_0[31:0]
Port 0
Level 3
atxval_0
Block
atxsop_0
urxreset_n
urxenb_n
urxclav[0:0]
urxdata[31:0]
UTOPIA
Level 3
Interface
urxsoc
atxeop_0
atxerr_0
Global Signals
soc_0
soc_err_0
uflw_err_0
TXUTOPIA3MS
FIFO Port 0 Clock Domain
UTOPIA Clock Domain
arxclk_0
arxreset_n_0
arxena_0
Atlantic
Interface
arxdav_0
arxdat_0[31:0]
arxsop_0
utxclk
utxreset_n
FIFO
UTOPIA
Port 0
Level 3
Block
utxenb_n
utxclav[0:0]
UTOPIA
Level 3
Interface
utxdata[31:0]
utxsoc
arxerr_0
soc_0
Global Signals
soc_err_0
oflw_err_0
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
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Figure 8 shows an RXUTOPIA3MS configured for four ports.
Figure 9. RXTUOPIA3MS Four Port Configuration
UTOPIA Clock Domain
FIFO Port 0 Clock Domain
Atlantic
Interface
Global Signals
atxclk_0
atxreset_n_0
atxena_0
atxdav_0
atxdat_0[31:0]
atxval_0
atxsop_0
atxeop_0
atxerr_0
FIFO
Port 0
soc_0
soc_err_0
uflw_err_0
FIFO Port 1 Clock Domain
Atlantic
Interface
FIFO
Port 1
soc_1
soc_err_1
uflw_err_1
UTOPIA
Level 3
Block
FIFO Port 2 Clock Domain
Atlantic
Interface
Global Signals
atxclk_2
atxreset_n_2
atxena_2
atxdav_2
atxdat_2[31:0]
atxval_2
atxsop_2
atxeop_2
atxerr_2
3
urxclk
urxreset_n
urxenb_n
urxaddr[1:0]
urxclav[0:0]
urxdata[31:0]
urxsoc
Specifications
Global Signals
atxclk_1
atxreset_n_1
atxena_1
atxdav_1
atxdat_1[31:0]
atxval_1
atxsop_1
atxeop_1
atxerr_1
UTOPIA
Level 3
Interface
FIFO
Port 2
soc_2
soc_err_2
uflw_err_2
FIFO Port 3 Clock Domain
Atlantic
Interface
Global Signals
Altera Corporation
atxclk_3
atxreset_n_3
atxena_3
atxdav_3
atxdat_3[31:0]
atxval_3
atxsop_3
atxeop_3
atxerr_3
FIFO
Port 3
soc_3
soc_err_3
uflw_err_3
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Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 10 shows a TXUTOPIA3MS configured for four ports.
Figure 10. TXUTOPIA3MS Four Port Configuration
FIFO Port 0 Clock Domain
UTOPIA Clock Domain
arxclk_0
arxreset_n_0
Atlantic
Interface
arxena_0
FIFO
arxdav_0
Port 0
arxdat_0[31:0]
arxsop_0
arxerr_0
Global Signals
soc_0
soc_err_0
oflw_err_0
FIFO Port 1 Clock Domain
arxclk_1
arxreset_n_1
Atlantic
Interface
arxena_1
FIFO
arxdav_1
Port 1
arxdat_1[31:0]
arxsop_1
arxerr_1
Global Signals
soc_1
soc_err_1
oflw_err_1
UTOPIA
Level 3
FIFO Port 2 Clock Domain
arxclk_2
Block
utxclk
utxreset_n
utxenb_n
utxaddr[1:0]
utxclav[3/0:0]
utxdata[31:0]
utxsoc
UTOPIA
Level 3
Interface
arxreset_n_2
Atlantic
Interface
arxena_2
FIFO
arxdav_2
Port 2
arxdat_2[31:0]
arxsop_2
arxerr_2
Global Signals
soc_2
soc_err_2
oflw_err_2
FIFO Port 3 Clock Domain
arxclk_3
arxreset_n_3
Atlantic
Interface
arxena_3
FIFO
arxdav_3
Port 3
arxdat_3[31:0]
arxsop_3
arxerr_3
Global Signals
34
soc_3
soc_err_3
oflw_err_3
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
GettingSpecifications
Figure 11 shows an RXUTOPIA3MS configured for four ports, without
FIFO buffers.
Figure 11. RXUTOPIA3MS No FIFO Buffer Configuration.
atxclk_0
atxclk_0
atxreset_n_0
atxreset_n_0
atxena_0
atxena_0
atxdav_0
Atlantic
atxdav_0
Atlantic
atxdat_0[31:0]
Interface
atxdat_0[31:0]
Interface
atxsop_0
atxsop_0
atxeop_0
atxeop_0
atxerr_0
atxerr_0
atxclk_1
atxclk_1
atxreset_n_1
atxreset_n_1
atxena_1
atxena_1
atxdav_1
Atlantic
atxdav_1
Atlantic
atxdat_1[31:0]
Interface
Interface atxdat_1[31:0]
atxsop_1
atxsop_1
atxeop_1
atxeop_1
atxerr_1
atxerr_1
Block Block
uclk uclk
ureset_n
ureset_n
urxenb_n
urxenb_n UTOPIA
UTOPIA
urxaddr[1:0]
urxaddr[1:0]
Level Level
3
3
urxclav[0:0]
urxclav[0:0]
Interface
Interface
urxdata[31:0]
urxdata[31:0]
urxsoc
urxsoc
3
Specifications
atxclk_2
atxclk_2
atxreset_n_2
atxreset_n_2
atxena_2
atxena_2
atxdav_2
Atlantic
atxdav_2
Atlantic
atxdat_2[31:0]
Interface
atxdat_2[31:0]
Interface
atxsop_2
atxsop_2
atxeop_2
atxeop_2
atxerr_2
atxerr_2
UTOPIA
UTOPIA
Level Level
3
3
atxclk_3
atxclk_3
atxreset_n_3
atxreset_n_3
atxena_3
atxena_3
atxdav_3
Atlantic
atxdav_3
Atlantic
atxdat_3[31:0]
Interface
atxdat_3[31:0]
Interface
atxsop_3
atxsop_3
atxeop_3
atxeop_3
atxerr_3
atxerr_3
Note:
(1)
The Atlantic interface signals are intended to be on the same clock domain as the UTOPIA clock.
Altera Corporation
35
Specifications
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 12 shows a TXUTOPIA3MS configured for four ports, without
FIFO buffers.
Figure 12. TXUTOPIA3MS No FIFO Buffer Configuration.
arxclk_0
arxreset_n_0
arxena_0
Atlantic
Interface
arxdav_0
arxdat_0[31:0]
arxsop_0
arxerr_0
arxclk_1
arxreset_n_1
arxena_1
Atlantic
Interface
arxdav_1
arxdat_1[31:0]
arxsop_1
arxerr_1
UTOPIA
Level 3
arxclk_2
Block
arxreset_n_2
uclk
ureset_n
utxenb_n
utxaddr[1:0]
utxclav[0:0]
utxdata[31:0]
utxsoc
UTOPIA
Level 3
Interface
arxena_2
Atlantic
Interface
arxdav_2
arxdat_2[31:0]
arxsop_2
arxerr_2
arxclk_3
arxreset_n_3
arxena_3
Atlantic
Interface
arxdav_3
arxdat_3[31:0]
arxsop_3
arxerr_3
Note:
(1)
The Atlantic interface signals are intended to be on the same clock domain as the UTOPIA clock.
AC Timing
36
For timing information on the UTOPIA level 3 interface, refer to the ATM
Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000,
November 1999, available at http://www.atmforum.com.
Altera Corporation