SONET/SDH Compiler
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Core Version:
Document Version:
Document Date:
2.1.0
2.1.0 rev1
June 2003
Copyright
SONET/SDH Complier User Guide
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-SONET/SDH-2.1
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
SONET/SDH Compiler.
Table 1 shows the user guide revision history.
Table 1. User Guide Revision History
Date
How to Find
Information
June 2003
Added STS-12c/4×AU-4-4c channelization support for
OC-48/STM-16. Added Stratix™ GX device family support,
including integrated clock-data recovery (CDR) hardware
module for OC-12/STM-4 and OC-48/STM-16 configurations.
October 2002
Added OC-192c level support, STS-3c/AU-4 channelization
support, Stratix device family support, and SDH terminology.
May 2002
First release of the user guide.
■
■
■
■
Altera Corporation
Description
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a PDF file. Click the binoculars toolbar icon to open the Find dialog
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Bookmarks serve as an additional table of contents.
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Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
SONET/SDH Compiler User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For technical support on this product, go to www.altera.com/mysupport.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
About this User Guide
Typographic
Conventions
SONET/SDH Compiler User Guide
The SONET/SDH Compiler User Guide uses the typographic conventions
shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
About this User Guide
Abbreviations
& Acronyms
vi
SONET/SDH Compiler User Guide
AHDL
AIS-L
AIS-P
APS
ATM
AU
BER
BIP-8
CDR
CRC
DCC
EDA
ERDI-P
FIFO
GFP
IP
LCD-P
LE
LOF
LOP
LOPC
LOS
LSB
LSByte
Mbps
MSB
MSByte
NDF
OSI
PC
PHY
PLM-P
POH
PPP
PTE
RDI-L
RDI-P
REI-L
REI-P
RSOH
RX
SD
SDH
SEF
SF
SOH
Altera hardware description language
alarm indication signal–line
alarm indication signal–path
automatic protection switching
asynchronous transfer mode
administrative unit
bit error rate
bit interleaved parity 8
clock data recovery
cyclic redundancy code
data communication channel
electronic design automation
enhanced remote defect indicator–path
first-in first-out
generic framing procedure
intellectual property
loss of cell delineation–path
logic element
loss of frame
loss of pointer
loss of optical carrier
loss of signal
least significant bit
least significant byte
megabits per second
most significant bit
most significant byte
new data flag
open system interconnection
personal computer
OSI physical layer
payload label mismatch–path
path overhead
point-to-point protocol
path terminating equipment
remote defect identification–line
remote defect indication–path
remote error identification–line
remote error indication–path
regeneration section overhead
receive
signal degrade
synchronous digital hierarchy
severely errored frame
signal fail
section overhead
Altera Corporation
About this User Guide
SONET/SDH Compiler User Guide
SONET
SPE
SRDI-P
STM
STS
TC
TCL
TDM
TIM-P
TOH
TU
TX
UNEQ-P
UTOPIA
VC
VHDL
VHSIC
Altera Corporation
synchronous optical network
synchronous payload envelope
single-bit RDI-P
synchronous transport module
synchronous transport signal
transmission convergence
tool command language
time division multiplexed
trace identifier mismatch–path
transport overhead
tributary unit
transmit
unequipped–path
universal test & operations physical interface for ATM
virtual container
VHSIC hardware description language
very high speed integrated circuit
vii
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Abbreviations & Acronyms .......................................................................................................... vi
About this Core ............................................................................................................................................13
Release Information .......................................................................................................................13
Device Family Support ..................................................................................................................13
Introduction ....................................................................................................................................14
New in Version 2.1.0 ......................................................................................................................15
Features ...........................................................................................................................................15
Typical Applications ......................................................................................................................15
Performance ....................................................................................................................................17
OpenCore Evaluation ....................................................................................................................26
Getting Started ............................................................................................................................................27
Hardware & Software Requirements ..........................................................................................27
Download & Install the Core ........................................................................................................28
Downloading the SONET/SDH Compiler ........................................................................28
Installing the SONET/SDH Compiler Files .......................................................................28
SONET/SDH Compiler Walkthrough ........................................................................................29
Create a New Quartus II Project ..........................................................................................30
Launch the IP Toolbench ......................................................................................................31
Configuration Parameters ............................................................................................33
Device Family .........................................................................................................33
Optical Carrier (OC) Level ...................................................................................34
Path Configuration ................................................................................................34
SFI-4.1 Mode ...........................................................................................................34
Stratix GX Clock & Data Recovery (CDR) ..........................................................34
Data Width ..............................................................................................................35
Clock Enable ...........................................................................................................35
Transport Overhead Buffer Size ..........................................................................35
SONET/SDH Overhead Processor Enable ........................................................35
Step 1: Select Configuration .................................................................................................36
Step 2: Set Up Simulation ......................................................................................................40
Step 3: Generate ......................................................................................................................40
Implementing the System .....................................................................................................41
Altera Corporation
ix
SONET/SDH Compiler User Guide
Contents
Instantiating a Design File in AHDL ...........................................................................43
Simulate the Design .......................................................................................................................43
SONET/SDH Framer Demonstration Testbench ..............................................................43
Synthesize, Compile & Place & Route ........................................................................................45
Using Third-Party EDA Tools for Synthesis ......................................................................45
Using the Quartus II Development Tool for Compilation & Place-and-Route ............45
Setting Constraints .................................................................................................................46
Set Up Licensing .............................................................................................................................47
Append the License to Your license.dat File ......................................................................48
Specify the Core’s License File in the Quartus II Software ..............................................48
Perform Post-Route Simulation ...................................................................................................49
Specifications ..............................................................................................................................................51
Functional Description ..................................................................................................................51
SONET/SDH Receiver Data Path Features (SSRX_DATA) ............................................53
SONET/SDH Transmitter Data Path Features (SSTX_DATA) .......................................53
SONET/SDH Receiver Processor Features (SSRX_PROC) .............................................54
SONET/SDH Transmitter Processor Features (SSTX_PROC) ........................................54
SONET/SDH Receiver (SSRX_DATA) Description .................................................................55
Receiver Transport Overhead (RXT) ...................................................................................55
Framing & Alignment (without the GXCDR parameter enabled) ............................56
Framing & Alignment (with the GXCDR parameter enabled) ..................................56
LOS Monitoring .............................................................................................................58
Descrambling ..................................................................................................................58
B1 Monitoring .................................................................................................................58
B2 Monitoring .................................................................................................................58
TOH Capture Memory ..................................................................................................59
AIS-L Insertion ...............................................................................................................59
Receiver Path Overhead (RXP) ............................................................................................59
H1/H2 Pointer Processing ...........................................................................................59
POH Capture Memory ..................................................................................................61
B3 Monitoring .................................................................................................................61
AIS-P Insertion ...............................................................................................................61
Downstream AIS Insertion ...........................................................................................61
SONET/SDH Transmitter (SSTX_DATA) Description ............................................................62
Transmitter Path Overhead (TXP) .......................................................................................64
Pointer Adjustments (H1 H2 Generation) ..................................................................64
B3 Generation .................................................................................................................64
AIS-P Insertion ...............................................................................................................64
Transmitter Transport Overhead (TXT) .............................................................................64
A1/A2/Z0 Generation ..................................................................................................64
B1 Generation .................................................................................................................65
B2 Generation .................................................................................................................65
AIS-L Insertion ...............................................................................................................65
LOS Insertion ..................................................................................................................65
Scrambling ......................................................................................................................65
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Altera Corporation
Contents
SONET/SDH Compiler User Guide
SONET/SDH Processor (SSPROC) Description .......................................................................65
Receiver Transport Trace (RXT) ...........................................................................................66
J0 Section Trace ...............................................................................................................66
B1 Accumulation ............................................................................................................67
Bit Error Rate Monitoring .............................................................................................67
RDI-L and AIS-L (K2) Monitoring ...............................................................................70
K1/K2 Monitoring .........................................................................................................70
Synchronization Monitoring (S1) ................................................................................70
REI-L Accumulation ......................................................................................................70
Receiver Path Trace (RXP) ....................................................................................................71
J1 Path Trace ...................................................................................................................71
B3 Accumulation ............................................................................................................71
Signal Label (C2) Monitor .............................................................................................72
RDI-P Monitoring ..........................................................................................................73
REI-P Accumulation ......................................................................................................74
Transmitter Transport Trace (TXT) .....................................................................................74
Section Trace (J0) Generation .......................................................................................74
Automatic RDI-L Generation .......................................................................................75
REI-L Generation (M0/M1) ..........................................................................................75
Automatic AIS-P Generation ........................................................................................75
Transmitter Path Trace (TXP) –Per Path .............................................................................75
J1 Path Trace Generation ...............................................................................................75
RDI-P (G1) Generation ..................................................................................................76
REI-P (G1) Generation ...................................................................................................76
Automatic Downstream AIS Insertion Control .........................................................77
Interfaces & Protocols ....................................................................................................................77
Physical Interface ...................................................................................................................77
SFI-4 Phase 1 (SFI-4.1) Interface ...........................................................................................77
Stratix GX Clock & Data Recovery (CDR) ..........................................................................80
Midbus Interface ....................................................................................................................81
Strobes .............................................................................................................................82
DAT ..................................................................................................................................84
Timing Information .......................................................................................................88
AIRbus interface .....................................................................................................................93
Signals ..............................................................................................................................................94
Software Interface ..........................................................................................................................99
AIRbus Shadow Register ......................................................................................................99
Memory Maps ......................................................................................................................100
RXT_REG Memory Map .....................................................................................................101
RXT_REG Register Description .................................................................................102
RXT_PRC Memory Map .....................................................................................................106
RXT_PRC Register Description ..................................................................................109
RXP_REG Memory Map .....................................................................................................127
RXP_REG Register Description .................................................................................128
RXP_PRC Memory Map .....................................................................................................131
RXP_PRC Register Description ..................................................................................132
Altera Corporation
xi
SONET/SDH Compiler User Guide
Contents
TXT_REG Memory Map .....................................................................................................143
TXT_REG Register Description ..................................................................................143
TXT_PRC Memory Map ......................................................................................................145
TXT_PRC Register Description ..................................................................................145
TXP_REG Memory Map .....................................................................................................147
TXP_REG Register Description ..................................................................................147
TXP_PRC Memory Map ......................................................................................................149
TXP_PRC Register Description ..................................................................................150
xii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the SONET/SDH
Compiler.
Table 4. SONET/SDH Compiler Release Information
Item
Version
Device Family
Support
2.1.0
Release Date
June 2003
Ordering Code
IP-STSFRM
Product IDs
0092
Vendor ID
6AF7
Every Altera MegaCore® function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
13
SONET/SDH Compiler User Guide
About this Core
Table 5 shows the level of support offered by the SONET/SDH Compiler
to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Support
Cyclone (1)
Full
Stratix GX
Preliminary
Stratix
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
Other device families
No support
Note for Table 5:
(1)
Introduction
The Cyclone device family is not supported for OC-192 configurations.
The SONET/SDH Compiler generates configurations of a SONET/SDH
Framer MegaCore function for termination applications up to OC-192
levels, including full-overhead processing. Table 6 shows the possible
configurations.
Table 6. SONET/SDH Framer Configurations
Optical Carrier SONET Synchronous Transport
(OC) Level
Signal (STS) Level
SDH Synchronous Transport
Module (STM) Level
OC-1
STS-1
STM-0 (AU-3)
OC-3
STS-3c
3×STS-1
STM-1 (AU-4)
STM-1 (3×AU-3)
OC-12
STS-12c
4×STS-3c
12×STS-1
STM-4 (AU-4-4c)
STM-4 (4×AU-4)
STM-4 (12×AU-3)
OC-48
STS-48c
4×STS-12c (1)
16×STS-3c
48×STS-1
STM-16
STM-16
STM-16
STM-16
OC-192
STS-192c
STM-64 (AU-4-64c)
(AU-4-16c)
(4×AU-4-4c)(1)
(16×AU-4)
(48×AU-3)
Note for Table 6:
(1) STS-12c/4×AU-4-4c channelization is only available for 32-bit OC-48
configurations.
14
Altera Corporation
About this Core
■
■
■
■
Features
■
■
■
■
■
■
■
■
■
■
■
■
Stratix GX device family support
–
Including integrated clock-data recovery (CDR) hardware
module for OC-12 and OC-48 configurations
Cyclone device family support for OC levels of OC-48 or smaller
Supports STS-12c/4×AU-4-4c channelization (only supported in 32bit OC-48/STM-16 configurations)
Improvements:
–
Metastable hardening between the receiver clock domain and
the processor clock domain
–
Accurate loss of frame (LOF) functionality in framing state
machine
–
Data path alignment for OC-192 configurations
Supports data rates at OC levels of 1, 3, 12, 48, and 192
Supports single-path (concatenated), STS-1/AU-3 (channelized),
STS-3c/AU-4 (channelized), and STS-12c/4×AU-4-4c (channelized)
frame structures
Performs frame alignment (A1/A2 bytes)
Generates and monitors B1/B2/B3 bytes
Terminates section, line, and path overhead
Scrambles and descrambles
Performs pointer processing (H1/H2 bytes)
Inserts and extracts payload
Supports full-duplex operation
Configurable Midbus interface data widths of 8, 16, 32, or 64 bits,
depending on OC level and operating frequency
Access to internal registers via AIRbus interface
Supports 10 Gigabit Ethernet (10 GE) applications as the Wide Area
Network (WAN) Interface Sublayer (WIS), used in conjunction with
64B/66B Physical Coding Sublayer (PCS) and Media Access
Controller (MAC) functions from AMPPSM partner MorethanIP
Typical
Applications
Figure 1 on page 16 shows an asynchronous transfer mode (ATM), pointto-point protocol (PPP), or generic framing procedure (GFP) delineation
over SONET/SDH application using an Altera SONET/SDH Framer
MegaCore function.
Altera Corporation
15
1
About this Core
New in Version
2.1.0
SONET/SDH Compiler User Guide
SONET/SDH Compiler User Guide
About this Core
Figure 1. ATM, Packet, or GFP Delineation over SONET/SDH Application
Midbus
Interface
Integrated
Fiber Optic
Transponder
External
CPU
ATM Cell
PPP Packet
or
GFP
Delineation
SONET/SDH
Framer
Processor
Interface
Atlantic
Interface
Atlantic
Interface
UTOPIA
POS-PHY
or
CSIX-L1
Interface
Traffic
Manager
AIRbus
Interface
FPGA
Figure 2 shows a 10 GE WAN-PHY layer application using an Altera
OC-192c SONET/SDH Framer MegaCore function connected to AMPP
partner MorethanIP’s PCS 64B66B and 10 GE MAC functions.
Figure 2. 10 GE WAN-PHY Application
SFI-4
Interface
Integrated
Optics,
SERDES,
CDR
Midbus
Interface
OC-192
SONE T
Framer
XGMII
Interface
PCS
64B66B
Atlantic
Interface
10 GE
MAC
POS-PHY
Level 4
Interface
Atlantic
Interface
Optional
User
Logic
PL4
FPGA
The SONET/SDH Compiler uses the IP Toolbench launchpad within the
Quartus II software to generate configurations of a SONET/SDH Framer
MegaCore function (STSFRM) in VHDL, or Verilog HDL, which you can
instantiate into your design. The IP Toolbench is a toolbar from which you
can quickly and easily view documentation, specify core parameters, set
up third-party tools, and generate all files necessary for integrating the
parameterized core into your design. You can launch the IP Toolbench
from within the Quartus II software. For detailed instructions on
generating a custom SONET/SDH framer, refer to the “Getting Started”
chapter.
Table 7 on page 17 shows the configuration options available to generate
all SONET/SDH framer configurations. Some of the available
configuration parameters are interdependent; for example, an OC-192
configuration is only available for the Stratix device family.
16
Altera Corporation
About this Core
SONET/SDH Compiler User Guide
1
Table 7 does not capture all of the parameter
interdependencies. Altera recommends that you run the
IP Toolbench to select your parameters.
1
About this Core
Table 7. Configuration Options
Option
Device family
Description
Parameter
Specifies the device family base architecture.
FAMILY
Stratix includes Stratix, Stratix GX, and Cyclone
devices.
APEX includes APEX 20K, APEX 20KE, APEX 20KC,
and APEX II devices.
Choices
Stratix or
APEX/APEX II
Optical carrier level Signal rate for transmitting digital signals on optical
fiber.
OCLEVEL
1, 3, 12, 48, or 192
Path configuration
Concatenated, or channelized (1) STS-1/AU-3,
STS-3c/AU-4, and STS-12c/4×AU-4-4c paths (2)
PATH
concatenated or
channelized
SFI-4 mode
Specifies the txclk mode, in accordance with the
SFI-4
SFI-4 Phase 1 (SFI-4.1) standard. Only applicable for
OC-192 configurations.
311 or 622 MHz
Stratix GX clock
and data recovery
(CDR)
Optimizes the SONET/SDH framer to take advantage GXCDR
of dedicated CDR pattern detection and word
alignment provided in Stratix GX devices for OC-12
and OC-48 configurations.
Yes/No
Data width
Internal data bus width (2)
DATW
8, 16, 32, or 64
Clock enable
Allows the core to run on a faster clock.(2)
CLKEN
Yes/No
Transport overhead Option to exclude TOH bytes that are undefined in the TOHBUF
buffer size
standards (see Figure 17 on page 52). (2)
All/Defined
SONET/SDH
Full–implements all features listed under
overhead processor SSRX_DATA, SSTX_DATA, SSRX_PROC, and
SSTX_PROC.
Partial–implements only the features listed under
SSRX_DATA and SSTX_DATA.
See pages 53 and 54.
Full/Partial
SSPROC
Notes for Table 7:
(1)
(2)
Selecting a channelized configuration involves choosing one of three paths: STS-1/AU-3, STS-3c/AU-4, or STS12c/4×AU-4-4c.
Available choices depend on the optical carrier level chosen as a parameter.
Performance
Altera Corporation
Tables 8 through 14 list the resource utilization and performance of some
SONET/SDH MegaCore function configurations. These results were
obtained using the Quartus II software version 2.2, for Cyclone
EP1C20F400C6, Stratix EP1S25F780C6, and Stratix GX
EP1SGX25CF672C6 devices.
17
SONET/SDH Compiler User Guide
About this Core
1
The logic elements (LEs) column only appears once per table
because the logic element utilization is the same across all
devices, per configuration.
1
For Stratix and Stratix GX devices, M-Ram is always zero,
therefore it was left out of the tables. Cyclone devices use only
M4K memory.
Table 8 shows OC-1 configurations. The required fMax for rxclk and
txclk is 6.48 MHz. The fMax required for prcclk is path dependent,
refer to Table 15 on page 34.
Table 8. OC-1 SONET/SDH Framer Utilization & Performance
Parameters
LEs
Cyclone
Memory
M4K
fMAX
(MHz)
rxclk
txclk
prcclk
Stratix
Memory
M512 M4K
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=1,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Partial
1,880
5
134
126
5
0
142
131
5
0
137
120
OCLEVEL=1,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=Yes, TOHBUF=All,
SSPROC=Full
5,452
9
95
88
141
6
3
90
81
137
6
3
83
79
134
18
Altera Corporation
About this Core
SONET/SDH Compiler User Guide
Table 9. OC-3 SONET/SDH Framer Utilization & Performance
Parameters
LEs
Cyclone
Memory
M4K
fMAX
(MHz)
rxclk
txclk
prcclk
Stratix
Memory
M512 M4K
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=3,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Partial
2,366
14
168
145
10
4
195
165
10
4
189
174
OCLEVEL=3,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=Yes, TOHBUF=All,
SSPROC=Full
6,041
19
120
117
141
11
8
128
114
133
11
8
117
107
131
OCLEVEL=3,
PATH=Concatenated,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Partial
2,063
8
194
169
6
2
176
170
6
2
192
161
OCLEVEL=3,
PATH=Concatenated,
GXCDR=No, DATW=8,
CLKEN=Yes, TOHBUF=All,
SSPROC=Full
5,610
12
111
100
146
7
5
120
104
134
7
5
113
90
137
Altera Corporation
19
1
About this Core
Table 9 shows OC-3 configurations. The required fMax for rxclk and
txclk is 19.44 MHz. The fMax required for prcclk is path dependent,
refer to Table 15 on page 34.
SONET/SDH Compiler User Guide
About this Core
Table 10 shows OC-12 configurations. The required fMax for rxclk and
txclk is 77.76 MHz. The fMax required for prcclk is path dependent,
refer to Table 15 on page 34.
Table 10. OC-12 SONET/SDH Framer Utilization & Performance
Parameters
LEs
Cyclone
Memory
M4K
fMAX
(MHz)
rxclk
txclk
prcclk
Stratix
Memory
M512 M4K
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=12,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
2,650
17
199
177
8
9
190
171
8
9
181
179
OCLEVEL=12,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Full
5,940
31
136
130
136
9
22
124
135
126
9
22
141
136
121
OCLEVEL=12,
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
2,599
18
201
165
12
6
184
190
12
6
185
174
OCLEVEL=12,
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Full
5,838
23
142
148
144
13
10
152
140
134
13
10
157
136
133
OCLEVEL=12,
PATH=Concatenated,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
2,287
8
184
176
6
2
183
176
6
2
175
174
OCLEVEL=12,
PATH=Concatenated,
GXCDR=No, DATW=8,
CLKEN=No, TOHBUF=All,
SSPROC=Full
5,370
12
157
147
148
7
5
143
134
134
7
5
146
134
135
20
Altera Corporation
About this Core
SONET/SDH Compiler User Guide
Table 11. OC-12 Stratix GX CDR SONET/SDH Framer Utilization & Performance
Parameters
Stratix GX
LEs
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=12, PATH=Channelized STS-1/AU-3, GXCDR=Yes, DATW=8,
CLKEN=No, TOHBUF=Defined, SSPROC=Partial
2,392
8
9
183
175
OCLEVEL=12, PATH=Channelized STS-1/AU-3, GXCDR=Yes, DATW=8,
CLKEN=No, TOHBUF=All, SSPROC=Full
5,715
9
22
125
141
127
OCLEVEL=12, PATH=Channelized STS-3c/AU-4, GXCDR=Yes, DATW=8,
CLKEN=No, TOHBUF=Defined, SSPROC=Partial
2,345
12
6
180
174
OCLEVEL=12, PATH=Channelized STS-3c/AU-4, GXCDR=Yes, DATW=8,
CLKEN=No, TOHBUF=All, SSPROC=Full
5,572
13
10
145
145
129
OCLEVEL=12, PATH=Concatenated, GXCDR=Yes, DATW=8, CLKEN=No,
TOHBUF=Defined, SSPROC=Partial
2,020
6
2
204
171
OCLEVEL=12, PATH=Concatenated, GXCDR=Yes, DATW=8, CLKEN=No,
TOHBUF=All, SSPROC=Full
5,097
7
5
179
138
139
Altera Corporation
21
1
About this Core
Table 11 shows OC-12 configurations using the Stratix GX CDR. The
required fMax for rxclk and txclk is 77.76 MHz. The fMax required for
prcclk is path dependent, refer to Table 15 on page 34
SONET/SDH Compiler User Guide
About this Core
Table 12 shows OC-48 configurations. The required fMax for rxclk and
txclk is 77.76 MHz for 32-bit configurations (DATW=32), and
155.52 MHz for 16-bit configurations (DATW=16). The fMax required for
prcclk is path dependent, refer to Table 15 on page 34.
Table 12. OC-48 SONET/SDH Framer Utilization & Performance (Part 1 of 3)
Parameters
LEs
Cyclone
Memory
M4K
fMAX
(MHz)
rxclk
txclk
prcclk
Stratix
Memory
M512 M4K
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=48,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
4,068
26
203
174
9
17
185
163
9
17
189
172
OCLEVEL=48,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=All,
SSPROC=Full
7,578
0
(1)
8
73
162
158
112
8
73
175
174
116
OCLEVEL=48,
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
3,962
24
170
175
10
14
178
168
10
14
184
174
OCLEVEL=48,
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=All,
SSPROC=Full
7,509
44
177
170
130
11
33
191
170
118
11
33
182
168
123
OCLEVEL=48,
PATH=Concatenated,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
3,012
8
202
179
4
4
196
157
4
4
184
170
OCLEVEL=48,
PATH=Concatenated,
GXCDR=No, DATW=16,
CLKEN=No, TOHBUF=All,
SSPROC=Full
5,899
18
197
175
130
5
13
187
178
126
5
13
195
164
128
22
Altera Corporation
About this Core
SONET/SDH Compiler User Guide
1
Table 12. OC-48 SONET/SDH Framer Utilization & Performance (Part 2 of 3)
LEs
Cyclone
Memory
M4K
fMAX
(MHz)
rxclk
txclk
prcclk
Stratix
Memory
M512 M4K
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=48,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
6,262
42
161
142
9
33
151
153
9
33
154
155
OCLEVEL=48,
PATH=Channelized STS-1/AU-3,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=All,
SSPROC=Full
10,410
0
(1)
10
88
136
139
124
10
88
124
133
124
OCLEVEL=48,
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
6,149
39
156
151
19
20
157
153
19
20
150
141
OCLEVEL=48,
10,070
PATH=Channelized STS-3c/AU-4,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=All,
SSPROC=Full
59
122
145
139
20
39
118
140
127
20
39
127
133
130
OCLEVEL=48,
PATH=Channelized
STS-12c/4×AU-4-4c, GXCDR=No,
DATW=32, CLKEN=No,
TOHBUF=Defined,
SSPROC=Partial
4,368
20
163
167
10
10
160
168
10
10
153
164
OCLEVEL=48,
PATH=Channelized
STS-12c/4×AU-4-4c, GXCDR=No,
DATW=32, CLKEN=No,
TOHBUF=All, SSPROC=Full
7,674
31
147
150
148
11
20
138
138
135
11
20
131
142
137
OCLEVEL=48,
PATH=Concatenated,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
4,028
10
158
157
3
7
160
157
3
7
157
152
Altera Corporation
23
About this Core
Parameters
SONET/SDH Compiler User Guide
About this Core
Table 12. OC-48 SONET/SDH Framer Utilization & Performance (Part 3 of 3)
Parameters
LEs
Cyclone
Memory
M4K
OCLEVEL=48,
PATH=Concatenated,
GXCDR=No, DATW=32,
CLKEN=No, TOHBUF=All,
SSPROC=Full
6,935
20
fMAX
(MHz)
rxclk
txclk
prcclk
149
144
151
Stratix
Memory
M512 M4K
4
16
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
138
133
142
Memory
M512 M4K
4
16
fMAX
(MHz)
rxclk
txclk
prcclk
126
133
144
Note:
(1)
This configuration does not fit the Cyclone device.
Table 13 shows OC-48 configurations using the Stratix GX CDR.
Table 13. OC-48 Stratix GX CDR SONET/SDH Framer Utilization & Performance
Parameters
Stratix GX
LEs
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
OCLEVEL=48, PATH=Channelized STS-1/AU-3, GXCDR=Yes, DATW=16,
CLKEN=No, TOHBUF=Defined, SSPROC=Partial
3,497
9
17
171
152
OCLEVEL=48, PATH=Channelized STS-1/AU-3, GXCDR=Yes, DATW=16,
CLKEN=No, TOHBUF=All, SSPROC=Full
7,139
10
72
148
166
114
OCLEVEL=48, PATH=Channelized STS-3c/AU-4, GXCDR=Yes, DATW=16,
CLKEN=No, TOHBUF=Defined, SSPROC=Partial
3,398
10
14
189
175
OCLEVEL=48, PATH=Channelized STS-3c/AU-4, GXCDR=Yes, DATW=16,
CLKEN=No, TOHBUF=All, SSPROC=Full
6,923
11
33
176
165
108
OCLEVEL=48, PATH=Concatenated, GXCDR=Yes, DATW=16, CLKEN=No,
TOHBUF=Defined, SSPROC=Partial
2,443
4
4
202
174
OCLEVEL=48, PATH=Concatenated, GXCDR=Yes, DATW=16, CLKEN=No,
TOHBUF=All, SSPROC=Full
5,541
5
13
190
170
124
24
Altera Corporation
About this Core
SONET/SDH Compiler User Guide
Table 14. OC-192 SONET/SDH Framer Utilization & Performance
Parameters
LEs
Stratix
Memory
M512 M4K
OCLEVEL=192, PATH=Concatenated, GXCDR=No,
DATW=64, CLKEN=No, TOHBUF=Defined,
SSPROC=Partial
Stratix GX
fMAX
(MHz)
rxclk
txclk
prcclk
Memory
M512 M4K
fMAX
(MHz)
rxclk
txclk
prcclk
6,501
2
18
163
152
2
18
174
153
OCLEVEL=192, PATH=Concatenated, GXCDR=No, 9,418
DATW=64, CLKEN=No, TOHBUF=All, SSPROC=Full
3
45
175
156
122
3
45
176
154
121
The SONET/SDH Framer MegaCore function complies with all
applicable standards, including:
■
■
■
■
■
■
■
■
■
Altera Corporation
American National Standards Institute (ANSI), Synchronous Optical
Network (SONET) –Basic Description including Multiplex Structure,
Rates, and Formats, ANSI T1-105–1995.
American National Standards Institute (ANSI), Synchronous Optical
Network (SONET) –Payload Mappings, ANSI T1-105.02–1995.
International Telecommunication Union, Network node interface for the
synchronous digital hierarchy (SDH), ITU-T Recommendation G. 707,
March 1996
International Telecommunication Union, Characteristics of
synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T
Recommendation G. 783, January 1994
Optical Internetworking Forum, SFI-4 Phase 1 (OC-192 Serdes-Framer
Interface) - Proposal for a common electrical interface between SONET
framer and serializer/deserializer parts for OC-192 interfaces, OIF-SFI401.0, September 2000.
Telcordia, Synchronous Optical Network (SONET) Transport Systems:
Common Generic Criteria, GR-253-CORE, Issue 3, September 2000.
Telcordia, Synchronous Optical Network (SONET) Transport Systems:
Common Generic Criteria Issue List Report, GR-253-ILR, Issue 3A,
October 2000.
Altera Corporation, AIRbus Interface Functional Specification
Altera Corporation, Midbus Interface Functional Specification
25
1
About this Core
Table 14 shows OC-192 configurations. The required fMax for rxclk and
txclk is 155.52 MHz. The fMax required for prcclk is path dependent,
refer to Table 15 on page 34.
SONET/SDH Compiler User Guide
About this Core
The SONET/SDH standards use a bit naming convention, where bit 1 is
the most significant bit (MSB) of the byte. This SONET/SDH Compiler
user guide uses a bit naming convention where bit 7 is the MSB of the byte,
see Figure 3.
Figure 3. Naming Conventions
SONET Bit Naming Convention
MSB
1
LSB
2
3
4
5
6
7
8
Bit Naming Convention for this user guide
MSB
7
OpenCore
Evaluation
26
LSB
6
5
4
3
2
1
0
The OpenCore® feature lets you test-drive Altera MegaCore functions for
free using the Quartus II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
Altera Corporation
Getting Started
Hardware &
Software
Requirements
The instructions in this section require the following hardware and
software:
■
■
The SONET/SDH Compiler design flow involves the following steps:
Altera Corporation
1.
Obtain and install the SONET/SDH Compiler.
2.
Create a custom configuration of a SONET/SDH Framer MegaCore
function using the IP Toolbench.
3.
Implement the rest of your system using VHDL, Verilog HDL, or
schematic entry.
4.
Use the SONET/SDH Framer IP Toolbench-generated simulation
models to confirm your custom core’s operation.
5.
Use the SONET/SDH Framer encrypted netlists to perform static
timing analysis of your customized core in the Quartus II software.
6.
Compile your design and perform place-and-route.
7.
License the SONET/SDH Compiler.
27
2
Getting Started
■
A PC running the Windows 98/NT/2000/XP operating system; or a
SUN workstation running the Solaris operating system
Quartus II development tool, version 2.2 service pack 1 (SP1) or
higher
Model Technology™ ModelSim®-Altera simulation software, version
5.6a or higher; or Innoveda Visual IP RTL simulation software,
version 4.3 or higher
SONET/SDH Compiler User Guide
Download &
Install the Core
Getting Started
8.
Perform post-route simulation (optional).
9.
Configure or program Altera devices with the design.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC or workstation. The
following instructions describe this process.
Downloading the SONET/SDH Compiler
You can download MegaCore functions from Altera’s web site at
www.altera.com. Follow the instructions below to obtain the
SONET/SDH Compiler via the Internet. If you do not have Internet
access, you can obtain the SONET/SDH Compiler from your local Altera
representative.
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Type SONET or SDH in the Keyword Search box.
3.
Click Go.
4.
Click the link for the Altera SONET/SDH Compiler in the search
results table. The product description web page displays.
5.
Click the Download Free Evaluation OpenCore graphic on the top
right of the product description web page.
6.
Follow the online instructions to download the core and save it.
Installing the SONET/SDH Compiler Files
For Windows, perform the following steps:
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The SONET/SDH Compiler Installation dialog box
appears. Follow the on-line instructions to finish installation.
1
28
You may be prompted to remove older versions of the
SONET/SDH Compiler or MegaCore functions that exist on
your system.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
For Solaris systems, perform the following steps:
Download the core, see “Downloading the SONET/SDH Compiler”
on page 28.
2.
Decompress/untar the package, using the following commands:
gunzip xxx.tar.gz; tar xvf xxx.tar
3.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically
<path>/stsfrmv2.1.0/lib) as a user library in the Quartus II software
to access the core in the MegaWizard® Plug-In Manager. Search for
“User Libraries” in Quartus II Help for instructions on how to add
these libraries.
Figure 4 shows the directory structure for the SONET/SDH Framer
MegaCore function.
Figure 4. SONET/SDH Framer MegaCore Function Directory Structure
<path>/stsfrmv2.1.0
The default path is c:/MegaCore
doc
Contains the core documentation.
lib
Contains the core files.
SONET/SDH
Compiler
Walkthrough
This walkthrough explains how to create a SONET/SDH Framer
MegaCore function using the Altera IP Toolbench within the Quartus II
software. As you go through the IP Toolbench, each page is described in
detail. When you are finished generating a SONET/SDH framer, you can
incorporate it into your overall project.
This walkthrough consists of the following steps:
■
■
■
■
■
Altera Corporation
“Create a New Quartus II Project” on page 30
“Launch the IP Toolbench” on page 31
“Step 1: Select Configuration” on page 36
“Step 2: Set Up Simulation” on page 40
“Step 3: Generate” on page 40
29
2
Getting Started
1.
SONET/SDH Compiler User Guide
Getting Started
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You must also specify the SONET/SDH Compiler user library. To create
a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
1
Stratix GX configurations require version 2.2 SPI or higher.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
1
Steps 7 to 10 only apply to Solaris systems.
7.
Click User Library Pathnames.
8.
Type <path>\stsfrmv.2.1.0\lib\ into the Library name box,
where <path> is the directory in which you installed the
SONET/SDH Compiler. The default installation directory is
c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
30
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
Launch the IP Toolbench
To launch the IP Toolbench from within the Quartus II software, perform
the following steps:
Choose MegaWizard Plug-In Manager (Tools menu).
2.
Select Create a new custom megafunction variation (default).
3.
Click Next.
4.
Expand the Communications folder under Installed Plug-Ins by
clicking the + next to the name.
5.
Expand the SONET/SDH folder under Communications.
6.
Click stsfrm-v2.1.0.
7.
Choose the output file type for your design; the IP Toolbench
supports VHDL, and Verilog HDL. This walkthrough uses
Verilog HDL, however, you can use either language.
1
8.
For Altera hardware description language (AHDL)
instructions, refer to “Instantiating a Design File in AHDL”
on page 43.
Type the name of the output file. Figure 5 on page 32 shows the page
after you have made these settings.
1
Altera Corporation
2
Getting Started
1.
The screen captures shown in this user guide are representative
examples of the IP Toolbench. The wizard windows displayed in
your project may differ from these examples.
31
SONET/SDH Compiler User Guide
Getting Started
Figure 5. MegaWizard Plug-In Manager
9.
32
Click Next. The IP Toolbench for SONET/SDH Compiler launches.
See Figure 6 on page 33.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
Figure 6. IP Toolbench
2
Getting Started
You are now ready to configure your SONET/SDH framer core.
Configuration Parameters
The following subsections describe the optional parameters available to
configure a SONET/SDH Framer MegaCore function.
Device Family
The SONET/SDH Compiler is targeted for the following device
architectures:
Altera Corporation
■
Stratix device family, including:
–
Stratix
–
Stratix GX
–
Cyclone
1
Cyclone devices are not supported for OC-192
configurations.
■
APEX device family, including:
–
APEX 20K
–
APEX 20KE
–
APEX 20KC
–
APEX II
33
SONET/SDH Compiler User Guide
Getting Started
Optical Carrier (OC) Level
The optical carrier levels: 1, 3, 12, 48, or 192 correspond to the basic
module in SONET (STS-n), or in SDH (STM-n/AU-n).
Path Configuration
This parameter optimizes the architecture for different path
configurations.
This parameter affects the required fMax for prcclk. Table 15 lists the
minimum required frequency for this clock domain. Since every AIRbus
access causes this minimum to increase, it is recommended that you run
this clock domain as fast as your data path allows.
Table 15. Path Configuration
Number of Paths
Required fMAX (MHz)
for prcclk
1
4.44
3
8.52
4
10.56
12
26.88
16
35.04
48
100.32
This parameter also affects signals included as part of the Midbus
interface if the data width is greater than eight. See Table 25 on page 84
through Table 31 on page 92 for examples.
SFI-4.1 Mode
This parameter allows the txclk of the SFI-4.1 standard to be set to either
311 or 622 MHz.
Stratix GX Clock & Data Recovery (CDR)
This parameter optimizes the core for use with the Stratix GX CDR.
34
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
Data Width
This parameter determines the width of the data path throughout the
whole core.
Table 16. Data Width
OCLEVEL
DATW
Required fMAX (MHz)
(rxclk/txclk)
8
6.48
OC-3
8
19.44
OC-12
8
77.76
OC-48
16
155.52
OC-48
32
77.76
OC-192
64
155.52
2
Getting Started
OC-1
Clock Enable
Allows the core to run on a faster clock. For example: running OC-1 on a
19.44 MHz clock, see Figure 7. The rxclk_en and txclk_en signals are
only present if this parameter is chosen.
Figure 7. Timing Diagram
clk (19.44 MHz)
clk_en (1/3)
stsfrm flops (6.48 MHz)
Transport Overhead Buffer Size
By dropping undefined bytes, the transport overhead buffer size can be
reduced. The exact memory resources required depend on the transport
overhead buffer size parameter, the OC level parameter, and the device
family chosen.
SONET/SDH Overhead Processor Enable
If the SONET/SDH overhead processor parameter is enabled, the
SSPROC block is instantiated in the design. If the SONET/SDH overhead
processor parameter is not enabled, the SSPROC block is not instantiated,
and all of its features are disabled. See “SONET/SDH Receiver Data Path
Features (SSRX_DATA)” and “SONET/SDH Transmitter Data Path
Features (SSTX_DATA)”on page 53.
Altera Corporation
35
SONET/SDH Compiler User Guide
Getting Started
Step 1: Select Configuration
Since the SONET/SDH framer core is highly configurable, a vast number
of configurations are possible. To reduce package sizes and download
time, this version of the IP Toolbench offers two possible methods of
obtaining the configuration(s) best suited to your design.
■
■
Select an installed configuration
–
Installed configurations are pre-packaged and installed with the
IP Toolbench
Request a custom configuration
–
Custom configurations are available by entering a MySupport
request (several days may be required to process a request)
This section describes how to select an installed configuration, or
customize one to suit your design. To select a configuration, perform the
following steps:
1.
Click the Step 1: Select Configuration button in the IP Toolbench.
2.
A window opens showing installed configurations. From the left
window pane, select the configuration that best meets your
requirements. A brief list of this configuration’s parameters appears
in the right pane. See Figure 8.
Figure 8. Installed Configurations
3.
36
Click the View/Configure button.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
4.
A parameterization window opens. Verify that all parameters meet
your requirements. Modify all parameters as required. See Figure 9.
Figure 9. Parameters
2
Getting Started
Altera Corporation
5.
When you are satisfied with your selection, click OK.
6.
If you have selected an installed configuration (see Figure 8 on
page 36)—and have not modified any parameters, you may proceed
to “Step 2: Set Up Simulation” on page 40.
7.
If you customized your own configuration, the next page that opens
is a Custom Configuration Request dialog box showing a list (text
format) of the parameters you chose for your customized
configuration. See Figure 10 on page 38. Select and copy all of this
text.
37
SONET/SDH Compiler User Guide
Getting Started
Figure 10. Custom Configuration Request
8.
Click Ok.
9.
Point your web browser to Altera’s technical on-line support system,
mySupport, at:www.altera.com/mysupport/
1
If this is your first time using this system, you must register
to obtain a login and password.
10. Log on, and click Create a Service Request.
11. Click Product Related Request.
12. Enter your project information, complete all fields as appropriate.
See Figure 11 on page 39.
13. Select Intellectual Property in the Category list.
14. Select Communications from the Megafunction Category list.
15. Select SONET/SDH Framer from the Megafunction Product list.
16. Paste the configuration parameters text—generated with the IP
Toolbench—into the Description field.
38
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
Figure 11. MySupport Product Related Request
2
Getting Started
17. Click Submit Product Related Request.
1
Altera e-mails your custom configuration to the address you
provided for your mySupport account. Requests take up to three
business days to process.
18. Click the × in the top corner of IP Toolbench to close the application,
or continue selecting configurations. Do not click Step 3: Generate.
Altera Corporation
39
SONET/SDH Compiler User Guide
Getting Started
Step 2: Set Up Simulation
Now that you have chosen your SONET/SDH framer configuration(s),
you are ready to set up the simulation outputs for your system.
1.
Click the Step 2: Set Up Simulation button in the IP Toolbench. (See
Figure 6 on page 33.)
2.
Turn on Generate Simulation Model. See Figure 12.
3.
Select the simulator of your choice.
Figure 12. Set Up Simulation
4.
Click Finish.
Step 3: Generate
Now that you have set up the outputs for your system, you are ready to
generate your system.
1.
Click Step 3: Generate in the IP Toolbench to begin generation. (See
Figure 6 on page 33.) The IP Toolbench performs the actions you
specified, and generates any resulting output files. See Figure 13 on
page 41.
1
40
If you generate files without parameterizing the core, the IP
Toolbench creates a default core.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
Figure 13. Generate
2
Getting Started
2.
Click Exit IP Toolbench when you are finished.
Implementing the System
Once you have generated your custom SONET/SDH framer, you are
ready to implement it. You can use the files generated by the IP
Toolbench, and use the Quartus II software or other electronic design
automation (EDA) tools to create your design. Figure 14 on page 42 shows
an example directory structure.
1
Altera Corporation
<configuration> is a unique code (aot###_<configuration>
#_stsfrm) assigned to the specific configuration requested
through the IP Toolbench.
41
SONET/SDH Compiler User Guide
Getting Started
Figure 14. SONET/SDH Framer Quartus II Directory Structure
<working directory>
Directory name selected by user in project wizard
db
Quartus II software-generated directory
<output file name>.v (or .vhd)
<output file name>.bsf
<output file name>.cmp
<output file name>.inc
<output file name>.log
IP Toolbench-generated files
aot####_<configuration>_stsfrm_top.v (or .vhd)
HDL top-level wrapper
aot####_<configuration>_altgxb-1x622_syn.v (or .vhd) (1)
aot####_<configuration>_altgxb-1x2488_syn.v (or .vhd) (2)
aot####_<configuration>_altlvds_rx-16x622_syn.v (or .vhd)
(3)
aot####_<configuration>_altlvds_tx-16x622_syn.v (or .vhd)
Clear-text I/O wrappers
aot####_<configuration>_stsfrm.e.vqm
Encrypted vqm Verilog HDL netlist for Quartus II development tool
aot####_<configuration>_airbus.v
AIRbus interface register 'define file
aot####_<configuration>_stsfrm-stratixgx.tcl (4)
Tool command language script for sample constraints in Quartus II
<output file name>_airbus
Contains the software interface descriptions (.html)
for aot####_<configuration>
<output file name>_sim
Contains the simulation model(s)
stsfrm-v2.1.0_base
Configuration based on parameter choices
sim_lib
aot####_<configuration>_stsfrm
test
Contains the scripts to run the simulation models
& demonstration testbench
aot####_<configuration>_airbus.v
aot####_<configuration>_alt*.v (or .vhd) (5)
aot####_<configuration>_stsfrm_top.v (or .vhd)
run_modelsim_verilog
run_modelsim_vhdl
run_modelsim_visual_ip
tb.v
readme (6)
<simulator db> (7)
Simulator database
Notes:
(1)
(2)
(3)
42
The altgxb-1×622 files are only present for OC-12 configurations with the GXCDR
parameter enabled.
The altgxb-1×2488 files are only present for OC-48 configurations with the GXCDR
parameter enabled.
The altlvds files are only present for OC-192 configurations.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
(4)
(5)
(6)
(7)
The .tcl script files are device and configuration dependent, thus the files may be
absent or their names may change.
Necessary I/O file(s) required to run the simulation. Though these files may have
the same names as the clear-text I/O wrapper files, they may differ slightly. Refer
to the readme for more information.
The readme file contains important information that should be reviewed prior to
using the model(s).
<simulator db> must be the same as the simulator chosen during parameterization.
Instantiating a Design File in AHDL
2
Simulate the
Design
1.
When the Verilog design file is open in Quartus II, create an AHDL
include file by choosing Create AHDL Include Files for Entities in
Current File (Tools menu).
2.
Add an Include statement to your AHDL file. The Include statement
allows you to import text from the AHDL include file into the
current file.
3.
Instantiate the Verilog design in the AHDL file as described in the
“Instance Declaration” section of the Quartus II Help.
4.
In the logic section of the AHDL design, connect the ports of the
instance to the rest of your design.
Altera provides models you can use for functional verification of the
SONET/SDH framer within your design. A Verilog HDL demonstration
testbench, including scripts to run it, is also provided. This demonstration
testbench, used with the ModelSim-Altera simulator, demonstrates how
to instantiate a model in a design. To find the simulation models for your
selected configuration, refer to Figure 14 on page 42.
SONET/SDH Framer Demonstration Testbench
The demonstration testbench, provided with the SONET/SDH framer
configurations, tests the following functions:
■
■
■
■
Altera Corporation
Reset
Framing
Pointer processing
Path overhead insertion and extraction
43
Getting Started
To instantiate a lower-level Verilog HDL design file in an AHDL file,
perform the following steps:
SONET/SDH Compiler User Guide
Getting Started
The demonstration testbench consists of two basic modules: a
SONET/SDH framer configuration, and an Airbus-master utility. The
line-side interface is looped back from the transmitter to the receiver. The
Midbus txdat signal is set to zero, and most output Midbus signals are
ignored.
Figure 15. SONET/SDH Framer Demonstration Testbench
Device Under Test
TX to RX
Loopback
SONET/SDH
Framer
Configuration
AIRbus-Master
Utility
clk_gen
The demonstration testbench begins by setting up various clocks, and
resetting each clock domain. The transmitter automatically starts sending
SONET/SDH frames upon coming out of reset. The AIRbus-master
disables scrambling so that the user can see the content of the
SONET/SDH frames being looped back. The AIRbus-master utility
inserts specific values for some of the path overhead (POH) bytes on up to
three paths (depending on the configuration) in the transmitter. The
receiver finds frame after two SONET/SDH frames. The severely errored
frame (SEF) pin is monitored to determine when frame is found. The
mrxffp signal is monitored, and when it is asserted, mrxdat is checked
to be sure it carries the A1 byte. The AIRbus-master utility inserts new
data flags (NDFs) on up to three paths with different offsets. The mrxffp
signal is monitored to determine when four (three for pointer lock, one to
reach offset) frames have passed so that the path overhead capture buffers
of the receiver contain the new overhead inserted at the beginning of the
test. The AIRbus-master utility reads out and checks that the value of the
POH bytes for up to three paths are captured correctly.
44
Altera Corporation
Getting Started
Synthesize,
Compile &
Place & Route
SONET/SDH Compiler User Guide
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar Logic™,
Mentor Graphics®, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
2
1.
Create your custom design instantiating a SONET/SDH framer.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the SONET/SDH framer instantiation as a black
box by either setting attributes or ignoring the instantiation.
Getting Started
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Placeand-Route
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
1.
2.
Altera Corporation
Specify the input settings for the project.
a.
Choose EDA Tool Settings (Assignments menu).
b.
Select Synplify in the Design entry/synthesis tool list.
c.
Click Settings.
d.
In the EDA Tool Input Settings dialog box, select Synplify from
the Design Entry/Synthesis Tool list.
Specify the netlist optimizations for the project in Settings >
Compiler Settings > Netlist Optimizations (Assignments menu).
a.
Click the Perform WYSIWYG primitive resynthesis check box.
b.
Click the Perform gate-level register retiming checkbooks.
45
SONET/SDH Compiler User Guide
Getting Started
c.
Click the Automatically duplicate logic elements check box.
d.
Click the Perform logic element level LUT resynthesis check
box.
1
f
Steps c) and d) are not applicable for APEX II devices.
3.
Add your third-party EDA tool-generated netlist file to your project.
4.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
5.
Add the pre-synthesized and encrypted .e.vqm file from your
project directory, created by the MegaWizard Plug-In Manager.
6.
If required, constrain your design.
7.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design.
Refer to the Quartus II Help for further instructions on performing
compilation.
Setting Constraints
The SONET/SDH framer configurations include a tool command
language (Tcl) script. The Tcl script is used to set example LogicLock™
regions from within the Quartus II software.
1
This script is intended for reference purposes only, and
should not be run within your project.
This Tcl script sets constraints for particular devices, i.e. APEX
EP2A25B724C7 or Stratix EP1S25F780C6. The constraints divide the entire
die into several regions, and places independent portions of the core into
each region. These regions are large, and intentionally fixed, so they can
accommodate most configurations. They are not optimized, or design
specific.
If you are experiencing timing issues in your design, you can run this
example script to see where important hierarchical boundaries can be
separated. Separating major blocks allows the placing tool to group
interconnected logic elements in a more efficient manner, thus improving
timing.
46
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
To set the LogicLock regions, perform the following steps:
Set Up
Licensing
Install the SONET/SDH Compiler core, see “Installing the
SONET/SDH Compiler Files” on page 28.
2.
Launch the Quartus II software.
3.
Launch the IP Toolbench, and recreate your configuration in a new
directory.
4.
In the View menu, under Auxiliary Windows, click Tcl Console. A
console window opens.
5.
Click into the Tcl Console window. Go to your new directory path,
using the cd command.
6.
Type source aot####_<configuration>_stsfrm.tcl r.
7.
Wait for script to finish. When the script ends, open the Timing
Closure Floorplan (Processing menu) to see how the Quartus II
software has assigned the LogicLock regions.
8.
Apply similar LogicLock regions to your design.
Refer to Quartus II Help for further instructions on using LogicLock
regions.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FPGA device. You can use Altera’s
OpenCore evaluation software to compile and simulate the SONET/SDH
Framer MegaCore function in the Quartus II software, allowing you to
evaluate it before purchasing a license. However, you must obtain a
license from Altera before you can generate programming files or EDIF,
VHDL, or Verilog HDL gate-level netlist files for simulation in third-party
EDA tools.
After you purchase a license for the SONET/SDH Framer, you can
request a license file from the Altera web site at
www.altera.com/licensing and install it on your PC. When you request a
license file, Altera e-mails you a license.dat file. If you do not have
Internet access, contact your local Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
Altera Corporation
47
2
Getting Started
f
1.
SONET/SDH Compiler User Guide
1
Getting Started
Before you set up licensing for the SONET/SDH Framer, you
must already have the Quartus II software installed on your PC
or workstation, with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC or
workstation:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrumTM
Synplify
ModelSim
2.
Open the SONET/SDH Framer license file in a text editor. The file
should contain one FEATURE line, spanning two lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the SONET/SDH Framer license file
and paste it into a new line in the Quartus II license file.
1
5.
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
48
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Run the Quartus II software.
Altera Corporation
Getting Started
SONET/SDH Compiler User Guide
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
Perform PostRoute
Simulation
Altera Corporation
Click OK to save your changes.
After you have licensed the SONET/SDH framer, you can generate EDIF,
VHDL, Verilog HDL, and Standard Delay Output (.sdo) files from the
Quartus II software and use them with your existing EDA tools to
perform functional modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, refer to the
“Using the Quartus II Development Tool for Compilation & Placeand-Route”section. The Quartus II software generates output and
programming files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
49
2
Getting Started
6.
Do not include any spaces either around the semicolon or in
the path/filename.
Specifications
Functional
Description
The SONET/SDH Framer MegaCore function (STSFRM) operates in fullduplex mode, and comprises three main blocks that are further divided
into sub-blocks. Figure 16 shows a block diagram of the SONET/SDH
framer.
■
■
■
■
SONET/SDH transmitter data path (SSTX_DATA) block
–
Transmitter transport sub-block (TXT)
–
Transmitter path sub-block (TXP)
SONET/SDH receiver data path (SSRX_DATA) block
–
Receiver transport sub-block
–
Receiver path sub-block
SONET/SDH transmitter processor (SSTX_PROC) block
SONET/SDH receiver processor (SSTX_PROC) block
3
STSFRM
SSTX_DATA
txclk
txclk_en (1)
txreset_n
TXT
TXP
stxdata
mtxdat
mtxslt
mtxffp
mtxfoh
mxtena
mtxefp
mtxeoh
mtxffr
mtxoho
mtxerr
mtxpos
mtxneg
mtxefr
Midbus
Interface
mrxval
mrxena
mrxffp
mrxfoh
mrxefp
mrxeoh
mrxais
Midbus
Interface
RX Clock Domain
prcclk (2)
prcreset_n (2)
lopc (2)
sel
read
addr
AIRbus
wdata
Interface
rdata
irq
dtack
SSTX_PROC
(2)
SSRX_PROC
(2)
Processor Clock Domain
(3)
TX Clock Domain
rxclk
rxclk_en (1)
rxreset_n
srxdata
srxval
srxfr
los
sef
lof
SSRX_DATA
RXT
RXP
Notes:
(1)
(2)
(3)
Depends on the CLKEN parameter.
Depends on the SSPROC parameter. The SSTX_PROC and SSRX_PROC blocks are collectively referred to as
SSPROC.
AIRbus interface signals are asynchronous.
Altera Corporation
51
Specifications
Figure 16. Block Diagram
SONET/SDH Compiler User Guide
Specifications
Figure 17 shows the SONET/SDH overhead byte standard names and
functions
Figure 17. SONET/SDH Overhead Byte Nomenclature
SONET Transport Overhead
Path Overhead
SDH Section Overhead
Trace/
Growth
(STS-ID)
J0/Z0
Framing
Framing
A1
A2
BIP-8 (2)
Orderwire
B1/
E1/
F1/
Undefined
Undefined
Undefined
Section
Data Com
Data Com
Data Com
Overhead
D1/
D2/
D3/
Undefined
Undefined
Undefined
Pointer
Pointer
Pointer Action
Path Status
H1
H2
H3
G1
APS
APS
K1/
K2/
Undefined
Undefined
Data Com
Data Com
Data Com
D4/
D5/
D6/
Undefined
Undefined
Undefined
SONET
Section
Overhead
SDH
Regeneration
BIP-8 (2)
B2
SONET
Line
Overhead
User
Trace J1
BIP-8 (3)
B3
Signal Label
C2
User Channel
F2
Indicator
H4
SDH
Data Com
Data Com
Data Com
Growth
Multiplex
D7/
D8/
D9/
Z3
Section
Undefined
Undefined
Undefined
F3
Data Com
Data Com
Data Com
Growth
Overhead
D10/
D11/
D12/
Z4
Undefined
Undefined
Undefined
K3
Sync Status/
REI-L/
Orderwire
Growth
Growth
E2/
Tandem
Connection
S1/Z1
M0 or M1/Z2
Undefined
Z5
N1
Notes:
(1)
(2)
52
The information for this figure was taken from the Telcordia GR-253_CORE
standard, Issue 3, September 2000, and the International Telecommunication Union
ITU-T Network Node Interface for the Synchronous Digital Hierarchy (SDH),
Recommendation G.707, March 1996.
Bit interleaved parity 8 (BIP-8) is always calculated using even parity.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
SONET/SDH Receiver Data Path Features (SSRX_DATA)
■
■
SONET/SDH Transmitter Data Path Features (SSTX_DATA)
■
■
Altera Corporation
Transmitter transport overhead (TXT)
–
A1/A2/Z0 generation with optional error insertion
–
B1, B2 generation and insertion with optional error mask
–
Scrambling
–
LOS insertion capabilities
–
Zero insertions for undefined and/or growth bytes
–
AIRbus or Midbus interface insertion of all transport overhead,
undefined, and fixed-stuff bytes.
Transmitter path overhead (TXP) (per path)
–
B3 generation and insertion with optional error mask
–
AIRbus or Midbus interface insertion of all path overhead,
undefined, and fixed-stuff bytes.
–
Pointer generation driven from AIRbus or Midbus interface:
insertion of NDF, positive stuff, negative stuff, arbitrary pointer
–
AIRbus interface insertion of AIS-P
–
Insertion of fixed-stuff columns
53
3
Specifications
Receiver transport overhead (RXT)
–
Frame and byte alignment with severely errored frame (SEF),
and loss of frame (LOF)
–
Loss of signal (LOS) detection
–
Remote defect indication–line (RDI-L) and alarm indication
signal–line (AIS-L) detection
–
Descrambling
–
Bit interleaved parity (BIP-8) (B1, B2) error checking, with single
frame accumulation
–
Full transport overhead capture capabilities
–
AIRbus interface insertion (AIS-L)
Receiver path overhead (RXP) –Per path
–
Bit interleaved parity (BIP-8) (B3) error checking, with single
frame accumulation
–
Pointer processor that supports new data flag (NDF), positive
stuff, and negative stuff
–
Alarm indication signal–path (AIS-P) and loss of pointer (LOP)
detection
–
Full path overhead capture capabilities
–
AIRbus interface insertion (AIS-P)
SONET/SDH Compiler User Guide
Specifications
SONET/SDH Receiver Processor Features (SSRX_PROC)
■
■
Receiver transport trace (RXT)
–
(J0) section trace buffer (16/64-byte message) with mismatch
detection and invalid message detection
–
32-bit saturating B1 BIP-8 error accumulation
–
32-bit saturating B2 BIP-8 error accumulation
–
(B2) fully programmable threshold detection for signal degrade
(SD) and signal fail (SF) conditions used for automatic protection
switching (APS)
–
K1K2 filter
–
K1 APS inconsistent monitor
–
S1 synchronization status filter
–
(M0M1) 32-bit saturating remote error indication–line (REI-L)
accumulation
–
Auto AIS-P insertion
Receiver path trace (RXP) (per path)
–
(J1) path trace buffer (16-/64-byte message) with trace identifier
mismatch–path (TIM-P) and invalid message detection
–
32-bit saturating B3 BIP-8 accumulation
–
(C2) signal label monitor with payload label mismatch (PLM)
detection
–
(G1) remote defect indication–path (RDI-P) filtering
–
(G1) 32-bit saturating REI-L accumulation
–
Auto AIS-Downstream
SONET/SDH Transmitter Processor Features (SSTX_PROC)
■
■
Transmitter transport trace (TXT)
–
(J0) section trace generation from buffer (16-/64-byte message)
–
(K1K2) automatic generation of AIS-L and RDI-L according to
receiver
–
(M0M1) automatic generation of REI-L according to receiver
Transmitter path trace (TXP) (per path)
–
(J1) path trace generation from buffer (16-/64-byte message)
–
(G1) automatic generation of RDI-P and remote error indication–
path (REI-P) signals according to receiver
1
54
If the SSPROC parameter is set to partial, you can still emulate
any SSRX_PROC or SSTX_PROC feature via software. However,
performance requirements may not allow an external processor
to perform all of the functions performed by the SSPROC.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
SONET/SDH
Receiver
(SSRX_DATA)
Description
The SSRX_DATA block processes a portion of the overhead at line rate.
The SSRX_DATA block is broken down into the RXT, and RXP sub-blocks.
This block consists of only one clock domain controlled by the rxclk,
rxclk_en (1), and rxreset_n signals.
Figure 18. SSRX_DATA Block Diagram
AIRbus Interface
dtack irq rdata wdata addr read sel
SSRX_DATA
AIRbus interface
rxclk
RXP
RXT
rxclk_en (1)
Registers
rxreset_n
rx_a1a2size (2)
rx_enacdet
Registers
POH
Capture
Memory
mrxval
3
mxrena
mrxffp
Framing
bit_slip (3)
LOS
Monitoring
los
B1
Monitoring
B2
Monitoring
sef
mrxfoh
H1/H2
Pointer
mrxefp
Strobe
Processing
B3
Monitoring
Midbus
Interface
mrxeoh
lof
srxdata
Alignment
(2)
mrxais
Descrambling
srxval
mrxslt
Pointer
Delay
srxfr
mrxdat
Notes:
(1)
(2)
(3)
Depends on CLKEN parameter.
Depends on GXCDR parameter.
Depends on SFI-4 Phase 1 (SFI-4.1) interface.
Receiver Transport Overhead (RXT)
This block processes a portion of the transport/section overhead at line
rate.
Altera Corporation
55
Specifications
TOH
Capture
Memory
SONET/SDH Compiler User Guide
Specifications
Framing & Alignment (without the GXCDR parameter enabled)
The SONET/SDH framer receives unaligned SONET/SDH data on
srxdata. The width of srxdata is determined by the DATW
parameter. This DATW value also determines the number of A1A2 byte
detection circuits. These circuits run in parallel, searching for valid A1A2
patterns using an AIRBus declared threshold. When a detection circuit
detects a valid A1A2 pattern, a counter is reset and the position is relayed
to a byte-alignment circuit that provides aligned data to the rest of the core
receiver.
1
OC-192 configurations use the data alignment feature, also
known as the bit-slip feature, of the Stratix deserializer.
If another valid A1A2 pattern is detected at the same bit position when the
counter indicates that one frame has passed, the severely errored frame
(SEF) signal is deasserted, and the framer is in frame. If a second valid
A1A2 pattern is detected after one frame, the search for a valid A1A2
pattern resumes.
Once the framer is in frame, the SEF signal is only asserted if four
consecutive frames contain bad A1A2 patterns, as determined by an
AIRbus declared threshold. This threshold is different from the threshold
used to find frame. When a SEF is declared, the byte alignment circuit
does not change its alignment until a good A1A2 pattern is detected at a
different bit position.
Framing & Alignment (with the GXCDR parameter enabled)
The SONET/SDH framer receives SONET/SDH data on srxdata. The
width of srxdata is determined by the DATW parameter. The
pattern_detect and word_align circuits of the Stratix GX CDR are used to
perform A1A2 detection and word alignment. An AIRBus register is used
to control the required pattern. The choices are: A1A2 and A1A1A2A2.
When the pattern_detect circuit detects the pattern, it automatically aligns
the incoming data to a word boundary and sets a flag. The framing FSM
detects the flag and disables further realignments, and a frame counter is
reset. If another valid A1A2 pattern is detected when the counter indicates
that one frame has passed (125 µs), the severely errored frame (SEF) signal
is deasserted, and the framer is in frame. If a second valid A1A2 pattern
is not detected, the search for a valid A1A2 pattern resumes and
realignment is again enabled. Once the framer is in frame, the SEF signal
is only asserted if four consecutive frames contain bad A1A2 patterns, as
determined by an AIRbus declared threshold. This threshold is different
from the threshold used to find frame. When a SEF is declared, the byte
alignment circuit does not change its alignment until a good A1A2 pattern
is detected at a different bit position.
56
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Figure 19 shows the state machine that performs this operation.
Figure 19. Framing and Alignment State Machine
Initial State
(four frames
SEF
with errored
A1A2)
OOF
A1A2 Not Detected Again After 125 µs
A1A2 Detected
PRE-SYNC
A1A2 Detected Again After 125 µs
3
The framer comprises a three millisecond (ms) integration timer. This
timer handles intermittent SEFs, while monitoring for loss of frame (LOF)
conditions. The timer operates as follows:
■
■
■
Altera Corporation
The in-frame timer accumulates when no SEF defect is present. It
stops accumulating and is reset to zero when a SEF defect is detected.
The SEF timer accumulates when a SEF defect is present. It stops
accumulating when the SEF defect is terminated. It is reset to zero
when the SEF defect is absent—continuously— for three ms (i.e.
when the in-frame timer reaches three ms).
A LOF defect is detected when the accumulated SEF timer reaches the
three ms threshold. Once detected, the LOF defect is terminated
when the in-frame timer reaches three ms.
57
Specifications
SYNC
SONET/SDH Compiler User Guide
Specifications
LOS Monitoring
The incoming scrambled data is monitored for the absence of ones.
Continuous zeros in the incoming data stream are used to trigger a loss of
signal (LOS) condition. The AIRbus interface is used to specify the
number of zero words (=DATW) needed to declare and terminate a LOS
condition. LOS can be configured for a large range, see Table 17 for
examples.
Table 17. Typical LOS_SET_THRESH Register Settings
Clock
Time (2.3 µs)
Time (100 µs)
Note (1)
Time (125 µs)
6.48 MHz
15
648
810
19.44 MHz
45
1,944
2,430
77.76 MHz
180
7,776
9,720
155.52 MHz
360
15,552
19,440
Note:
(1)
LOS_CLR_THRSH should be set to maximum (125 µs, 2.5 × LOS_SET_THRSH).
Descrambling
The incoming stream is descrambled by applying the polynomial
1+ x6 + x7 to all bytes except the A1, A2, J0, and Z0 bytes. The descrambler
is reset at the first byte following the last J0/Z0 byte. Descrambling can
be enabled/disabled by the AIRbus interface. Descrambling is
enabled/disabled at frame boundaries.
B1 Monitoring
The B1 byte contains the section bit interleaved parity 8 (BIP-8) code. This
BIP-8 code is calculated using even parity over all bytes of the previous
frame, after scrambling.
For each frame, B1 errors are accumulated for access by the AIRbus
interface. This is a single frame accumulation only. For multiple frame
accumulations, with a saturation accumulator, see “SONET/SDH
Processor (SSPROC) Description” on page 65.
B2 Monitoring
Each B2 byte is allocated a line BIP-8 code for error monitoring. Each code
is calculated over all bytes of the previous frame—except SONET section
or SDH regeneration section overhead (RSOH)—using even parity, before
scrambling.
58
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
For each frame, a sum of all of the B2 errors is accumulated for access by
the AIRbus interface. This is a single frame accumulation only. For
multiple frame accumulations with a saturation accumulator, as well as
bit-error rate monitoring functions, see “SONET/SDH Processor
(SSPROC) Description” on page 65.
TOH Capture Memory
The transport overhead (TOH)/section overhead (SOH) [SDH] is
captured and stored for access by the AIRbus interface, and the SSPROC
block. Each stored byte is preserved for one frame for access by the
AIRbus interface. An interrupt can be set to occur at the beginning of any
row to allow synchronization with an external processor. The set of bytes
captured is affected by the TOHBUF parameter.
AIS-L Insertion
Alarm indication signal–line (AIS-L) can be inserted downstream via the
AIRbus interface. AIS-L inserts 8’hFF into all bytes, except regenerator
section overhead [SDH].
This block performs receive path overhead processing at line rate. All
operations are performed per path. The number of paths is determined by
the PATH parameter.
H1/H2 Pointer Processing
The pointer bytes are used to locate the synchronous payload envelope
(SPE)/virtual container (VC) offset. The types of pointers are: normal,
new, AIS, NDF, increment, decrement, or invalid. The received pointer
type can be monitored via the AIRbus interface. Figure 20 and Table 18
show the pointer finite state machine operation.
Altera Corporation
59
Specifications
Receiver Path Overhead (RXP)
3
SONET/SDH Compiler User Guide
Specifications
Figure 20. Pointer Processing Finite State Machine
ndf_ptr
3 x new_ptr
inc_ptr
dec_ptr
NORM
_pt
r
new
tr
3x
r
_pt
ais
8x
nd
8x
f_p
tr
inv
ptr
w_
ne
_p
tr
3x
f_p
nd
3x
LOP
3 x ais_ptr
AIS
8 x inv_ptr
Table 18. SONET Pointer Event Types
Event
60
Description
norm_ptr
Disabled NDF + ss + offset value equal to active offset
ndf_ptr
Enabled NDF + ss + offset value in range of 0 to 782
ais_ptr
H1 = 8’hFF, H2 = 8’hFF
inc_ptr
Disabled NDF + ss+ majority of I bits inverted + no majority of D bits
inverted + previous ndf_ptr_ind, inc_ptr_ind, or dec_ptr_ind more
than three frames ago
dec_ptr
Disabled NDF + ss + majority of D bits inverted + no majority of I bits
inverted + previous ndf_ptr_ind, inc_ptr_ind, or dec_ptr_ind more
than three frames ago
inv_ptr
Not any of the above
new_ptr
Disabled NDF + ss + offset in range of 0 to 782 but not equal to
active offset
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
POH Capture Memory
The path overhead (POH) is captured and stored for access by the AIRbus
interface and SSPROC block. An interrupt can be set to occur at the
beginning of the SPE/VC to allow synchronization with an external
processor. Each stored byte is preserved for one frame for access by the
AIRbus interface.
B3 Monitoring
B3 BIP-8 is calculated, using even parity, over the SPE/VC of the previous
frame and compared with the B3 byte of the path overhead. For each
SPE/VC, a sum of the B3 errors are accumulated for access by the AIRbus
interface.
AIS-P Insertion
Alarm indication signal–path (AIS-P) can be inserted downstream via the
AIRbus interface, or by automatic generation by the SSPROC block. AISP inserts 8’hFF into H1H2H3 and all SPE/VC bytes for a particular path.
Downstream AIS can be inserted via the AIRbus interface, or by automatic
generation by the SSPROC block. Downstream AIS drives the mrxais pin
for a particular path.
Altera Corporation
61
Specifications
Downstream AIS Insertion
3
SONET/SDH Compiler User Guide
SONET/SDH
Transmitter
(SSTX_DATA)
Description
Specifications
The SSTX_DATA block processes a portion of the overhead at line rate.
The SSTX_DATA block is broken down into the TXP, and TXT sub-blocks.
This block consists of only one clock domain controlled by the txclk,
txclk_en (1), and txreset_n signals.
Figure 21. SSTX_DATA Block Diagram
SSTX_DATA
txclk
txclk_en (1)
txreset_n
stxdata
TXP
TXT
B1
Generation
B2
Generation
Scrambling
&
LOS Insertion
Registers
B3
Generation
TOH/SOH
Data
Multiplexer
&
A1/A2/Z0
Generation
Pointer
Adjustments
&
H1/H2
Generation
Path
Data
Multiplexer
TOH
Insertion
Memory
POH
Insertion
Memory
Registers
mtxffr
mtxefr
mtxpos
mtxneg
mtxoho
mtxerr
mtxdat
mxtena
mtxffp
mtxfoh
mtxefp
mtxeoh
mtxslt
Midbus
Interface
AIRbus Interface
dtack irq rdata wdata addr read sel
AIRbus Interface
Note:
(1)
62
Depends on CLKEN parameter.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
The transport overhead (TOH)/section overhead (SOH) and path data
multiplexer blocks perform functions described by the following pseudocode.
There are three sources for OH bytes:
1. generated_value = internally generated A1 A2 Z0 B1
B2 B3 H1 H2 bytes
2. ram_value = the value stored by AIRbus/SSPROC
interface.
1
SSPROC uses TOH/POH RAM to insert RDI-L (K2),
RDI-P (G1), REI-L (M0M1), REI-P (G1). If the
AIRbus interface writes to these bytes, it
may interfere with SSPROC functions.
3. mtxdat = the value sampled from the transmit Midbus
interface.
These three sources are muxed/masked in the following way (before
scrambling):
3
Altera Corporation
63
Specifications
if (TOH or POH)
if (A1 or A2 or Z0 or B1 or B2 or B3 or H1 or H2)
if (~mtxoho and ~mtxerr)
output <- generated_value XOR ram_value
else if (mtxoho and ~mtxerr)
output <- mtxdat
else if (~mtxoho and mtxerr)
output <- generated_value XOR mtxdat XOR ram_value
else if (mtxoho and mtxerr)
output = 0
else
if (~mtxoho and ~mtxerr)
output <- ram_value
else if (mtxoho and ~mtxerr)
output <- mtxdat
else if (~mtxoho and mtxerr)
output <- ram_value XOR mtxdat
else if (mtxoho and mtxerr)
output = 0
SONET/SDH Compiler User Guide
Specifications
Transmitter Path Overhead (TXP)
The TXP block accepts overhead and payload data from the Midbus
interface. It generates the H1/H2 pointer and POH bytes, and
transparently passes payload and transport overhead (TOH)/section
overhead (SOH) bytes to the TXT block.
Pointer Adjustments (H1 H2 Generation)
Pointer generation is determined by requests from the AIRbus or Midbus
interfaces. The user can request positive stuff, negative stuff, NDF, and
new pointer actions to be performed. In addition, the user can send an
arbitrary pointer value (H1/H2) without affecting the actual alignment of
the SPE/VC—for debugging purposes—by using the Midbus or AIRbus
interface (see pseudo-code).
B3 Generation
The TXP block calculates the B3 BIP-8 value, using even parity, over the
SPE/VC of the previous frame. Errors can be inserted into the B3 value
from the AIRbus or Midbus interface (see pseudo-code).
AIS-P Insertion
AIS-P can be inserted via the AIRbus interface, per path. AIS-P overrides
all sources with 8’hFF for H1H2H3 and SPE/VC.
Transmitter Transport Overhead (TXT)
The TXT block accepts SPE/VC (POH and payload), and the H1/H2
pointer from the TXP block. It generates all remaining TOH/SOH bytes,
and scrambles the transmitted frame.
A1/A2/Z0 Generation
The A1/A2/Z0 bytes are generated using the following values:
■
■
■
■
A1=8’hF6
A2=8’h28
Z0=the corresponding STS-1 slot number (for up to OC-48)
Z0=8’hCC (for OC-192)
Errors can be inserted into these bytes from the AIRbus or Midbus
interface (see pseudo-code).
64
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
B1 Generation
The TXT block calculates the B1 BIP-8 value, using even parity, over all
bytes of the previous frame, after scrambling. Errors can be inserted into
the B1 value from the AIRbus or Midbus interface (see pseudo-code).
B2 Generation
The TXT block calculates the B2 BIP-8 value over all bytes of the previous
frame—except SONET section or SDH (regeneration section overhead–
RSOH)—using even parity, before scrambling. Errors can be inserted into
the B2 value from the AIRbus or Midbus interface (see pseudo-code).
AIS-L Insertion
AIS-L can be inserted via the AIRbus interface. AIS-L overrides all sources
with 8’hFF for all bytes except SOH (RSOH). The AIS-L insertion is set or
cleared on frame boundaries.
3
LOS Insertion
Scrambling
The outgoing stream is scrambled by applying the polynomial
1+ x6 + x7 to all bytes except A1, A2, J0, and Z0. The scrambler is reset at
the first byte following the last J0/Z0. Scrambling can be
enabled/disabled by the AIRbus interface. Scrambling is
enabled/disabled at frame boundaries.
SONET/SDH
Processor
(SSPROC)
Description
Altera Corporation
This block performs all overhead processing that doesn’t require
processing at line rate.
1
Since this block uses a shared resource architecture, there is no
clear correlation between the blocks shown and the functions
described.
65
Specifications
A LOS condition can be inserted via the AIRbus interface. LOS is inserted
by setting all data bytes to zero after scrambling. LOS insertion, if
specified, overrides all other transmit frame data insertion schemes.
SONET/SDH Compiler User Guide
Specifications
Figure 22. SSPROC Block Diagram
TXT
TXP
SSPROC
SSTX_PROC
Processor TXTOH
Memory
sel
Processor TXPOH
Memory
Processor RXTOH
Memory
read
addr
AIRbus
Interface
SSRX_PROC
wdata
rdata
Processor RXPOH
Memory
irq
Processor Trace
dtack
Processor
Bit Error Rate Monitoring
Processor Accumulation
Processor Filtering
RXT
RXP
Receiver Transport Trace (RXT)
J0 Section Trace
The J0 byte is used for section trace. The J0 section trace message length
is set to 1, 16, or 64 bytes, via the AIRbus interface. The received trace is
preserved for one message, for access by the AIRbus interface. An
interrupt is generated when a new section trace message is accepted as
valid. A J0 mismatch flag is raised if the accepted message is not identical
to the expected message. The SSPROC block also implements a J0
unstable counter. The J0 unstable counter is incremented for each
message that differs from the previously received message. An invalid J0
condition is declared when the J0 unstable counter reaches eight. The J0
unstable counter is cleared to zero when a valid J0 message is accepted.
1
66
For SDH, the cyclic redundancy code (CRC) must be performed
by an external processor, and applied to the AIRbus interface.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
B1 Accumulation
A 32-bit saturation accumulator is used to accumulate an error count for
B1 BIP-8 errors over several frames. Bit or frame B1 error accumulation is
set via the AIRbus interface. If set for bit, the saturation accumulator is
incremented by each frame’s B1 error count. If set for frame, the saturation
accumulator is incremented by one for each frame containing a B1 error.
B2 Accumulation
A 32-bit saturation accumulator is used to accumulate an error count for
B2 BIP-8 errors over several frames. Bit or frame B2 error accumulation is
set via the AIRbus interface. If set for bit, the saturation accumulator is
incremented by each frame’s B2 error count. If set for frame, the saturation
accumulator is incremented by one for each frame containing a B2 error.
Bit Error Rate Monitoring
Figure 23. Set and Clear Conditions for Signal Degrade and Signal Fail
10 -2
10 -3
10 -4
SF_SET Threshold
10 -5
BER
10 -6
10 -7
SF_CLR Threshold
SD_SET Threshold
SD_CLEAR Threshold
10 -8
10 -9
t
SD
SF
Altera Corporation
67
3
Specifications
The B2 bytes are used to measure the bit error rate (BER) of the received
signal when monitoring for signal fail (SF) and signal degrade (SD)
conditions. There are four separate bit error rate monitors used to detect
set and clear conditions for SD and SF, as shown in Figure 23.
SONET/SDH Compiler User Guide
Specifications
Each bit error rate monitor is programmed separately. Each bit error rate
monitor uses a sliding window protocol in which the sliding window size
is decomposed into eight sub-windows. The length of the window is
programmable between (0..224) ×8 × 125 µs. SD and SF are set and cleared
when a total bit error count for the window reaches a programmable
threshold between (0..216). In addition, you can specify a burst tolerance
threshold between (0..216) for each sub-window. The bit error count for
each sub-window is saturated at the burst tolerance threshold. Samples of
these settings are shown in Table 19.
Table 19. Sample Bit Error Rate Monitoring Register Settings (Part 1 of 2)
Bit Error Rate
SUBWIN_SIZE (1)
ERR_THRSH (2)
Average Burst (3)
OC-1
1.00E-03
1,234
63,970
7,996
1.00E-04
6,172
31,995
3,999
1.00E-05
30,864
15,999
2,000
1.00E-06
154,320
7,999
1,000
1.00E-07
771,604
3,999
500
1.00E-08
2,885,802
1,495
187
1.00E-09
4,320,987
223
28
1.00E-03
411
63,918
7,990
1.00E-04
2,057
31,990
3,999
1.00E-05
10,288
15,999
2,000
1.00E-06
51,440
7,999
1,000
1.00E-07
257,201
3,999
500
1.00E-08
1,286,008
1,999
250
1.00E-09
6,430,041
999
125
1.00E-03
102
6,3452
7,932
1.00E-04
514
31,974
3,997
1.00E-05
2,572
15,999
2,000
1.00E-06
12,860
7,999
1,000
1.00E-07
64,300
3,999
500
OC-3
OC-12
1.00E-08
321,502
1,999
250
1.00E-09
1,607,510
999
125
1.00E-03
25
62,208
7,776
1.00E-04
128
31,850
3,981
OC-48
68
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 19. Sample Bit Error Rate Monitoring Register Settings (Part 2 of 2)
Bit Error Rate
SUBWIN_SIZE (1)
ERR_THRSH (2)
Average Burst (3)
1.00E-05
643
15,999
2,000
1.00E-06
3,215
7,999
1,000
1.00E-07
16,075
3,999
500
1.00E-08
80,375
1,999
250
1.00E-09
401,877
999
125
OC-192
1.00E-03
6
59,719
7,465
1.00E-04
32
31,850
3,981
1.00E-05
160
15,925
1,991
1.00E-06
803
7,992
999
1.00E-07
4,018
3,999
500
1.00E-08
20,093
1,999
250
1.00E-09
100,469
999
125
3
(1)
The SUBWIN_SIZE column refers to the following registers:
–
–
–
–
(2)
The ERR_THRSH column refers to the following registers:
–
–
–
–
(3)
“RXT_PRC_SD_SET_ERR_THRSH - Signal degrade set total
error threshold - 'h8E” on page 120
“RXT_PRC_SD_CLR_ERR_THRSH - Signal degrade clear total
error threshold - 'hAE” on page 122
“RXT_PRC_SF_SET_ERR_THRSH - Signal fail set total error
threshold - 'hCE” on page 124
“RXT_PRC_SF_CLR_ERR_THRSH - Signal fail clear total error
threshold - 'hEE” on page 126
The BURST_TOL register should be set to a value that is sufficiently greater than
the average burst, depending on your system’s requirements. To disable burst
tolerance, set the register to the maximum value of 16’hFFFF. The Average Burst
column refers to the following registers:
–
–
Altera Corporation
“RXT_PRC_SD_SET_SUB_WIN - Signal degrade set subwindow - 'h80” on page 118
“RXT_PRC_SD_CLR_SUB_WIN - Signal degrade clear subwindow - 'hA0” on page 120
“RXT_PRC_SF_SET_SUB_WIN - Signal fail set sub-window 'hC0” on page 122
“RXT_PRC_SF_CLR_SUB_WIN - Signal fail clear sub-window 'hE0” on page 124
“RXT_PRC_SD_SET_BURST_TOL - Signal degrade set burst
tolerance - 'h81” on page 118
“RXT_PRC_SD_CLR_BURST_TOL - Signal degrade clear burst
tolerance - 'hA1” on page 120
69
Specifications
Notes:
SONET/SDH Compiler User Guide
Specifications
–
“RXT_PRC_SF_SET_BURST_TOL - Signal fail set burst tolerance
- 'hC1” on page 122
“RXT_PRC_SF_CLR_BURST_TOL - Signal fail clear burst
tolerance - 'hE1” on page 124
–
RDI-L and AIS-L (K2) Monitoring
The K2 byte, in consecutive frames, is monitored for remote defect
identification–line (RDI-L) and alarm indication signal–line (AIS-L)
conditions.
For SONET, an AIS-L/RDI-L condition is declared after five consecutive
matches (frames) in the least significant bits (LSB) of the K2 byte.
For SDH, an AIS-L/RDI-L condition is declared after three consecutive
matches (frames) in the LSB of the K2 byte.
K1/K2 Monitoring
K1 and K2 are used for automatic protection switching (APS). Three
identical K1 and K2 bytes in consecutive frames replace the current APS
code. Flags are set to notify the AIRbus interface when a valid code or an
inconsistent byte has been received.
The K1 byte is also monitored for inconsistencies. These inconsistencies
are flagged when there are not three consecutive matching K1 bytes in 12
frames.
Synchronization Monitoring (S1)
The SSPROC block monitors the S1 byte for eight consecutive identical
values after which the new value is stored for access by the AIRbus
interface. The SSPROC blocks also implements an S1 unstable counter.
The S1 unstable counter is incremented for each byte that differs from the
previously received S1 byte. An invalid S1 condition is declared when the
S1 unstable counter reaches 32. The S1 unstable counter is cleared to zero
when eight consecutive identical S1 bytes are received. When it detects an
invalid S1 condition. An external processor sets up a 10 s timer for S1
reference failure.
REI-L Accumulation
An remote error indication-line (REI-L) value is considered valid if it is
between zero, and the minimum of OC × 8 or 255.
70
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
The M0/M1 byte contains the REI-L value, which conveys how many B2
BIP-8 errors were received at the far end. A 32-bit saturation accumulator
is used to accumulate the REI-L value over several frames.
Bit or frame REI-L accumulation is set via the AIRbus interface. If set for
bit, the saturation accumulator is incremented by a valid REI-L value. If
set for frame, the saturation accumulator is incremented by one for each
frame containing a valid non-zero REI-L value.
Receiver Path Trace (RXP)
J1 Path Trace
B3 Accumulation
A 32-bit saturation accumulator is used to accumulate an error count for
B3 BIP-8 errors over several frames. Bit or frame B3 error accumulation is
set via the AIRbus interface. If set for bit, the saturation accumulator is
incremented by each frame’s B3 error count. If set for frame, the saturation
accumulator is incremented by one for each frame containing a B3 error.
Altera Corporation
71
3
Specifications
The J1 byte is used for path trace. The length of the J1 path trace message
is set to 1, 16, or 64 bytes, via the AIRbus interface. The received trace is
preserved for one message for access by the AIRbus interface. An
interrupt is generated when a new path trace message is accepted as valid.
A trace identifier mismatch-path (TIM-P) flag is raised if the accepted
message is not identical to the expected message. The SSPROC block also
implements a J1 unstable counter. The J1 unstable counter is
incremented for each message that differs from the previously received
message. An invalid J1 condition is declared when the J1 unstable
counter reaches eight. The J1 unstable counter is cleared to zero when a
valid J1 message is accepted.
SONET/SDH Compiler User Guide
Specifications
Signal Label (C2) Monitor
The C2 byte is allocated to indicate the contents of the SPE/VC and is
treated as a signal label. Table 20 shows the signal label mismatch defect
conditions.
Table 20. STS Signal Label Mismatch Defect Conditions
Provisioned STS Path Terminating
Equipment (PTE) Functionality
Note (1)
Received Payload Label (C2 Byte, hexadecimal)
Defect
Any equipped functionality
(C2 = anything except H00)
Unequipped (00)
UNEQ-P
Any equipped functionality
Equipped–non specific (01)
none
(Matched)
Equipped–non specific (C2 = H01)
A value corresponding to any payload specific
functionality
none
(Matched)
Any payload specific functionality
(C2 = anything except H00 or H01)
A value corresponding to the same payload specific
functionality as the provisioned functionality
none
(Matched)
Any payload specific functionality
A value corresponding to a different payload specific
functionality as the provisioned functionality
PLM-P
Note:
(1)
The information for this table was taken from the Telcordia GR-253_CORE standard, Issue 3, September 2000.
The SSPROC block allows the AIRbus interface to specify the expected
signal label and compares it with the observed value. If the values don’t
match, a payload label mismatch (PLM) error is declared. If the observed
value is 8’h00, an unequipped (UNEQ) error is declared, and PLM is
cleared. If the observed value matches the expected value, PLM is cleared.
If the observed value changes, a flag is set for the AIRbus interface. For a
C2 label to be considered valid, it must be received in five consecutive
frames. The SSPROC block also implements a C2 unstable counter. The C2
unstable counter is incremented for each byte that differs from the
previously received byte. An invalid C2 condition is declared when the C2
unstable counter reaches five. The C2 unstable counter is cleared to zero
when five consecutive identical C2 bytes are received.
72
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
RDI-P Monitoring
The Telcordia SONET standards have two definitions for the path RDI
defect:
■
■
Enhanced remote defect indicator–path (ERDI-P)
Single-bit remote defect indication–path (SRDI-P)
Table 21. RDI-P Bit Conventions
G1 Field
REI-P
ERDI-P
SRDI-P
Undefined
Undefined
SONET Bit
Convention
1
2
3
4
5
6
7
8
Altera Bit
Convention
7
6
5
4
3
2
1
0
3
Specifications
Table 22. RDI-P Bit Settings and Interpretation
Note (1)
G1 Bits 5, 6 and 7
Priority of ERDI-P
Codes
Trigger
Interpretation
0xx
Not Applicable
No defects
No RDI-P defect
1xx
Not Applicable
AIS-P, LOP-P
SRDI-P or ERDI-P
Server defectc
001
4
No defects
No RDI-P defect
010
3
PLM-P, LCD-P
ERDI-P Payload defect
101
1
AIS-P, LOP-P
ERDI-P Server defect
110
2
UNEQ-P, TIM-P
ERDI-P Connectivity
defect
Note:
(1)
The information for this table was taken from Table 6-4. of the Telcordia GR-253_CORE standard, Issue 3, September
2000.
Altera Corporation
73
SONET/SDH Compiler User Guide
Specifications
The SSPROC block allows the AIRbus interface to specify the type of
RDI-P: single-bit or enhanced. The AIRbus interface also specifies the
number of consecutive consistent RDI-P codes (1 to 16) that must be
observed before it is accepted as valid. When a new valid RDI-P is
detected, a flag is set for the AIRbus interface, and the RDI-P code that
caused the condition is captured in a register. The SSPROC block also
implements an RDI-P unstable counter. The unstable counter is
incremented for each RDI-P code that differs from the previously received
RDI-P code. An invalid RDI-P condition is declared when the unstable
counter reaches the AIRbus interface specified threshold (1 to 16). The
unstable counter is cleared to zero when a valid RDI-P code is accepted.
REI-P Accumulation
A remote error indication–path (REI-P) value is considered valid if it is
between zero and eight.
The G1 byte contains the REI-P value, which conveys how many B3
BIP-8 errors were received at the far end. A 32-bit saturation accumulator
is used to accumulate the REI-P value over several frames.
Bit or frame REI-P accumulation is set via the AIRbus interface. If set for
bit, the saturation accumulator is incremented by a valid REI-P value. If
set for frame, the saturation accumulator is incremented by one for each
frame containing a valid non-zero REI-P value.
Transmitter Transport Trace (TXT)
Section Trace (J0) Generation
The length of the section trace is set to 16 or 64 bytes, via the AIRbus
interface. The message is stored in a separate memory and transmitted
one byte per frame by copying each byte to the J0 byte of the
transport/section memory, in the SSTX_DATA. Writing to the J0 byte, of
the transport/section memory in the SSTX_DATA block, from the AIRbus
interface can interfere with the operation of the SSPROC.
74
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Automatic RDI-L Generation
The three least significant bits of the K2 byte usually contain portions of
the transmitted APS code. However, these bits can be automatically
overwritten by the RDI-L pattern 3’b110 if any of the following AIRbus
interface programmable conditions occur: LOS, LOF and AIS-L. To
arbitrarily force the insertion of an RDI-L, write to the K2 byte in the
transport/section memory, with automatic RDI-L generation disabled.
Writing to the K2 byte, of the transport/section memory in the
SSTX_DATA block, from the AIRbus interface can interfere with the
operation of the SSPROC.
REI-L Generation (M0/M1)
Automatic AIS-P Generation
Any, or all, of the following conditions: AIS-L, LOS, LOF, LOPC, SD, SF,
J0 mismatch, or J0 unstable can be set via the AIRbus interface to
automatically insert AIS-P. When enabled, the SSPROC block sets and
clears the AIS-P condition by writing to an AIRbus interface accessible
register in the SSRX_DATA block.
Transmitter Path Trace (TXP) –Per Path
J1 Path Trace Generation
The length of the path trace can be set to 16 or 64 bytes, via the AIRbus
interface. The message is stored in a separate memory and transmitted
one byte per frame by copying each byte to the J1 byte of the POH
memory, in the SSTX_DATA block. Writing to the J1 byte, of the POH
memory in the SSTX_DATA block, from the AIRbus interface can
interfere with the operation of the SSPROC.
Altera Corporation
75
3
Specifications
REI-L can be automatically generated. SSPROC reads the number of B2
errors from the SSRX_DATA block at every received frame, and
accumulates them. For every transmitted frame, the REI-L value is
subtracted from the accumulation to a maximum of 255 or OCLEVEL × 8,
whichever is smaller. SSPROC writes to the M0/M1 byte of the TOH
Memory when automatically generating REI-L. Writing to the M0/M1
byte, of the TOH memory in the SSTX_DATA block, from the AIRbus
interface can interfere with the operation of the SSPROC.
SONET/SDH Compiler User Guide
Specifications
RDI-P (G1) Generation
The SSPROC block can automatically generate the RDI-P signal. To
support old and new definitions of RDI-P, the SSPROC block provides a
flexible scheme where the AIRbus interface can specify the RDI-P code
that is to be sent for each type of detected path alarm. The RDI-P codes are
generated according to the priority shown in Table 23.
1
If a higher priority alarm is detected before the current RDI-P
code has been generated for 20 frames, the higher priority code
is generated immediately for 20 frames.
Table 23. RDI-P Insertion Priority
Alarm Type
Priority (1 = highest priority)
Alarm indication signal–path (AIS-P)
Loss of pointer-path (LOP-P)
Unequipped–path (UNEQ-P)
Trace identifier mismatch–path (TIM-P)
Payload label mismatch–path (PLM-P)
Loss of cell delineation–path (LCD-P)
1
2
3
4
5
6
The SSPROC block writes to the G1 byte of the POH Memory when
automatically generating RDI-P. Writing to the G1 byte, of the POH
memory in the SSTX_DATA block, from the AIRbus interface can
interfere with the operation of the SSPROC.
REI-P (G1) Generation
The REI-P signal is transmitted in bits one to four of the G1 byte. REI-P can
be automatically generated. The SSPROC block reads the number of B3 bit
errors from the SSRX_DATA block at every received SPE/VC frame, and
accumulates them. For every transmitted SPE/VC frame, the REI-P value
is subtracted from the accumulation to a maximum of eight. The SSPROC
block writes to the G1 byte of the POH Memory when automatically
generating REI-P. Writing to the G1 byte, of the POH memory in the
SSTX_DATA block, from the AIRbus interface can interfere with the
operation of the SSPROC.
76
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Automatic Downstream AIS Insertion Control
Any, or all, of the following conditions: AIS-P, LOP-P, TIM-P, J1 unstable,
PLM-P, UNEQ-P, or C2 unstable can be set via the AIRbus interface to
automatically insert Downstream AIS. When enabled, the SSPROC block
sets and clears the Downstream AIS condition by writing to an AIRbus
interface accessible register in the SSRX_DATA block.
Interfaces &
Protocols
Physical Interface
1
Only configurations with the SFI-4 and GXCDR parameters
enabled have already-instantiated inputs and outputs (I/Os).
For all other chosen configurations, it is up to you to instantiate
the appropriate I/Os, and provide the required clocks for the
core.
SFI-4 Phase 1 (SFI-4.1) Interface
The SFI-4.1 interface, developed by the Optical Internetworking Forum
(OIF), is a 16-bit LVDS interface between an OC-192
serializer/deserializer (SERDES) and SONET/SDH framer. An aggregate
of 9953.28 megabits per second (Mbps) is transferred in each direction.
Table 24 on page 78 provides the data rates and clock frequencies
specified by SFI-4.1 specification.
1
Altera Corporation
The SFI-4.1 interface txclk signal is not equal to the core’s
txclk signal.
77
3
Specifications
The physical layer (PHY) side of the core is comprised of two data buses:
srxdata and stxdata. It also has two receiver inputs: srxval and
srxfr. The srxdata, srxval and srxfr signals are all sampled on the
positive edge of rxclk. The stxdata signal is driven on the positive
edge of txclk. The srxval signal must be asserted for the framer to
attempt framing. The srxfr signal forces the framer into a SEF condition,
effectively causing it to reframe.
SONET/SDH Compiler User Guide
Specifications
The modes of TXCLK are specified by the SFI-4.1 standard. In required
mode (622 MHz clock mode or ×1 mode), TXCLK should run at 622.08
MHz. In optional mode (311 MHz clock mode or ×2 mode), TXCLK should
run at 311.04 MHz.
Table 24. SFI-4.1 Interface Data Rates & Clock Frequencies
Signal
TXDATA[15..0]
TXCLK
Performance
622.08 Mbps
622.08 MHz or 311.04 MHz
TXCLK_SRC
622.08 MHz
RXDATA[15..0]
622.08 Mbps
RXCLK
622.08 MHz
REFCLK
622.08 MHz
Figure 24 on page 79 shows the 16-bit full-duplex LVDS implementation
of the SFI-4.1 interface.
1
78
For OC-192 configurations, the altlvds_rx megafunction must be
reset at the same time as the core (rxreset_n) for the bit_slip
counter and the core to be reset at the same time,.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Figure 24. Implementation of SFI-4.1 Interface
refclk
stsfrm_top
OC-192
SERDES
tx_pll_locked
stsfrm
Midbus
Interface
mtxdat
mtxslt
mtxffp
mtxfoh
mxtena
mtxefp
mtxeoh
mtxffr
mtxoho
mtxerr
mtxpos
mtxneg
mtxefr
SSTX_DATA
SFI4_TX (altlvds_tx)
stxdat
sfi4_txdata [15:0]
Transmitter
SERDES
sfi4_txclk
Stratix Framer
PLL1
txclk
×1
sfi4_txclk_src
÷4
txclk_en (1)
txreset_n
txclk
lopc (2)
prcclk (2)
prcreset_n (2)
AIRbus
Interface
sel
read
addr
wdata
rdata
irq
dtack
Transmitter
SSTX_PROC (2)
3
SSRX_PROC (2)
Specifications
rxclk
rxreset_n
rxclk_en (1)
srxval
srxfr
los
sef
lof
Midbus
Interface
rxclk
mrxval
mrxena
mrxffp
mrxfoh
mrxefp
mrxeoh
mrxais
rx_pll_locked
data_align
srxdat
SSRX_DATA
PLL2
Phase Shift
÷4
180°
Receiver
SERDES
sfi4_rxclk
sfi4_rxdata [15:0]
SFI4_RX (altlvds_rx)
Receiver
Notes:
(1)
(2)
Depends on the CLKEN parameter.
Depends on the SSPROC parameter. The SSTX_PROC and SSRX_PROC blocks are collectively referred to as
SSPROC.
f
For more information on the SFI-4.1 Interface refer to the Optical
Internetworking Forum, SFI-4 Phase 1 (OC-192 Serdes-Framer Interface) Proposal for a common electrical interface between SONET framer and
serializer/deserializer parts for OC-192 interfaces, OIF-SFI4-01.0, September
2000, available at www.oiforum.com.
f
For more information on implementing the SFI-4.1 Interface refer to
AN 219: Implementing SFI-4 in Stratix Devices.
Altera Corporation
79
SONET/SDH Compiler User Guide
Specifications
Stratix GX Clock & Data Recovery (CDR)
The SONET/SDH Framer can take advantage of dedicated CDR pattern
detection and word alignment provided in Stratix GX devices for OC-12
and OC-48 configurations.
Figure 25 shows an example Stratix GX CDR implementation.
Figure 25. Implementation of Stratix GX CDR
cdr_inclk
tx_pll_areset
tx_pll_locked
stsfrm_top
Midbus
Interface
mtxdat
mtxslt
mtxffp
mtxfoh
mxtena
mtxefp
mtxeoh
mtxffr
mtxoho
mtxerr
mtxpos
mtxneg
mtxefr
OC-192
SERDES
Stratix_GX_TX (altgxb)
stsfrm
SSTX_DATA
Transmitter
PLL
stxdata
Multiplexer
(2-to-1) and
Transmitter FIFO
Parallelto-Serial
cdr_tx_out
txclk
txclk_en (1)
txreset_n
txclk
lopc (2)
prcclk (2)
prcreset_n (2)
AIRbus
Interface
sel
read
addr
wdata
rdata
irq
dtack
Transmitter
SSTX_PROC (2)
SSRX_PROC (2)
rxclk
rxreset_n
rxclk_en (1)
srxval
srxfr
los
sef
lof
Midbus
Interface
rxclk
srxdata
mrxval
mrxena
mrxffp
mrxfoh
mrxefp
mrxeoh
mrxais
Serial-toParallel
Demultiplexer
(1-to-2) and
Receiver FIFO
Pattern
Detector
and Word
Aligner
rx_patterndetect
Clock
Recovery
Unit
cdr_rx_in
rx_a1a2size
Receiver
PLL
rx_enacdet
SSRX_DATA
Stratix_GX_RX (altgxb)
Receiver
Notes:
(1)
(2)
80
Depends on the CLKEN parameter.
Depends on the SSPROC parameter. The SSTX_PROC and SSRX_PROC blocks are collectively referred to as
SSPROC.
Altera Corporation
Specifications
f
SONET/SDH Compiler User Guide
For more information on the CDR, refer to AN 237: Using High-Speed
Transceiver Blocks in Stratix GX Devices.
Midbus Interface
Figure 26 shows a generic block diagram of the Midbus interface. External
logic can be used to multiplex overhead and data to the txdat signal and
demultiplex overhead and data from the rxdat signal, while observing
the rxval/rxena and txval/txena signals, respectively.
1
The direction of data flow on the Midbus interface is from source
to sink.
Figure 26. Generic Midbus Block Diagram
rxdat
Midbus
Interface
Master
(Source)
rxval
Midbus
Interface
Slave
(Sink)
rxena
txena
Midbus
Interface
Master
(Sink)
txval
Midbus
Interface
Slave
(Source)
txdat
Figure 27 on page 82 shows a SONET/SDH specific block diagram of the
Midbus interface.
Altera Corporation
81
3
Specifications
The Midbus interface transfers streams of bytes under the control of the
master-generated signals ena and val. These signals allow the master to
start and stop data flow dynamically, and regulate the data throughput.
The enable signals allow the master to introduce gaps in the payload data
stream to accommodate valid non-payload bytes. The val signal allows
the master to introduce gaps in the data stream to accommodate low data
rate streams and framing information, where the dat signal may contain
invalid information.
SONET/SDH Compiler User Guide
Specifications
Figure 27. SONET/SDH Midbus Block Diagram
mrxdat
mrxval
mrxena
mrxslt
mrxffp
mrxfoh
mrxefp
Midbus
Data
Slave
Sink
Midbus
Overhead
Slave
Sink
mrxeoh
SONET/SDH
Framer
mtxena
mtxslt
mtxdat
mtxoho
mtxerr
mtxffp
mtxfoh
mtxefp
mtxeoh
mtxffr
mtxefr
mtxpos
mtxneg
f
Midbus
Data
Slave
Source
Midbus
Overhead
Slave
Source
Additional information for each signal can be found in Table 33 on
page 94.
Strobes
The SONET/SDH Midbus interface includes additional signals to convey
SONET/SDH frame structure information to a Midbus slave. Figure 27
shows a distinction between a payload slave and an overhead slave. A
data stream payload slave such as an ATM cell or PPP packet processor
requires only the ena and val signals to coordinate dat transactions.
However, a time division multiplexed (TDM) payload slave such as a DS3
or VT mapper would require the efp signal as well to align the data
structure to the SPE/VC boundaries. An overhead slave could provide an
interface to external logic that handles overhead processing not
performed by the core, for instance:
■
■
■
■
■
82
Data communication channel (DCC) (D1-D12)
Orderwire (E1/E2)
APS (K1K2)
VT Super frame boundary or LCAS/Virtual concatenation (H4)
Tandem connection (SONET Z5/SDH N1)
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
The overhead slave would use mrxslt, mrxffp, mrxefp, mrxfoh,
mrxeoh, mtxslt, mtxffp, mtxefp, mtxfoh, and mtxeoh to locate
overhead byte positions on mrxdat and mtxdat, respectively. The
mtxoho and mtxerr signals allow the slave source to force overhead
insertion and overhead error mask insertion, see the pseudo-code in
“SONET/SDH Transmitter (SSTX_DATA) Description” on page 62.
Figure 28 shows the correlation between strobes in the STS-1 frame.
Figure 28. SONET STS-1 Frame
STS-1 Frame
A1 A2
(ffp)
B1 E1
J0
F1
Payload
Z4
D1
D2
D3
start of SPE
Z5
H1
H2
H3
J1
(efp)
B2
K1
K2
B3
D4
D5
D6
C2
D7
D8
D9
Z3
F2
D10 D11 D12
S1
3
Payload
Specifications
G1
Payload
Payload
H4
M0 E2
Fixed overhead (foh)
Embedded overhead (eoh)
Additionally, in applications implementing Midbus loopback or a rate
adaptation first-in first-out (FIFO) buffer, the mtxffr, mtxefr, mtxpos,
and mtxneg signals can be used by the slave source to force the master
sink frame position and pointer movements.
The SONET/SDH master does not provide a txval signal because it is
assumed to be always asserted high.
The SONET/SDH master asserts rxval once rxdat is valid. rxdat is
valid provided the following conditions do not exist:
■
■
■
■
■
■
Altera Corporation
Loss of pointer (LOP)
AIS pointer
AIS-P
Loss of frame (LOF)
Loss of signal (LOS)
AIS-L
83
SONET/SDH Compiler User Guide
Specifications
DAT
The Midbus interface does not support fractional byte data transfer, non
byte-aligned data, or dynamic bus sizing. The Midbus interface supports
only byte-oriented protocols. It is divided into byte lanes, and each one is
eight bits wide. The number of byte lanes, data rate, and clock rate are OC
level specific. See Table 25.
Table 25. Number of Byte Lanes
Application
Clock Rate
(MHz)
PHY Data Rate
(Mbps)
Byte Lanes
OC-1
6.48
51.84
1
OC-3
19.44
155.52
1
OC-12
77.76
622.08
1
OC-48
155.52
2,488.32
2
OC-48
77.76
2,488.32
4
OC-192
155.52
9,953.28
8
By design, the master and slave must be processing the same interleaved
structure. For example, an STS-48c is a contiguous payload stream, as
opposed to an STS-1 × 48 which is 48 interleaved payload streams.
In multiple byte lane implementations of the Midbus interface, the
highest-order byte of mrxdat and mtxdat is received and transmitted
first. The strobes may be defined per byte lane, or for a subset of the byte
lanes, depending on the requirements of the application.
84
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Figure 29 shows a SONET/SDH framer finding frame and pointer lock
(zero offset), and initiating a data transfer.
Figure 29. STS-1 (zero offset) Master Source to Slave Sink (RX/Drop))
(1)
(1)
(2)
(2)
(3)
(3)
(4)
(4)
(5)
(5)
rxclk
rxclk
mrxval
mrxval
...
...
A1
A1
mrxdat
mrxdat
A2
A2
...
...
J0
J0
mrxena
mrxena
...
...
mrxffp
mrxffp
...
...
mrxfoh
mrxfoh
...
...
H1
H1
H2
H2
H3
H3
J1
J1
PL
PL
PL
PL
mrxefp
mrxefp
mrxeoh
mrxeoh
mrxais
mrxais
...
...
Notes:
(6)
Frame is found; LOS and LOF are deasserted.
LOP is still asserted.
LOS, and LOF are still deasserted.
Pointer is valid; LOP is deasserted.
Master asserts mrxena, and drives data onto the mrxdat bus. On the following clock rising edge, a payload slave
observes that mrxval and mrxena are asserted, and captures mrxdat.
This step occurs past the visible portion of the diagram. When overhead replaces payload on mrxdat, mrxena is
deasserted and the appropriate overhead strobe (mrxffp, mrxefp, mrxfoh, mrxeoh) is asserted. A payload
slave observes that mrxena is deasserted, and ignores mrxdat.
Figure 30 shows a typical SONET payload transaction.
Figure 30. STS-1 (522 offset) Master Source to Slave Sink (TX/Add)
(3)
(4)
(1)
(2)
txclk
mtxdat
PL
PL
A1
A2
J0
J1
PL
PL
mtxena
mtxffp
mtxfoh
mtxefp
mtxeoh
Notes:
(1)
(2)
(3)
(4)
Master asserts mtxena. The slave drives payload on mtxdat.
On the following clock rising edge, the master samples payload from mtxdat.
The master stops payload flow by deasserting mtxena. A payload slave observes that mtxena is deasserted and
stalls payload generation.
On the following clock rising edge, the master stops sampling payload from mtxdat.
Altera Corporation
85
3
Specifications
(1)
(2)
(3)
(4)
(5)
SONET/SDH Compiler User Guide
Specifications
An overhead slave would work in a similar fashion, but would use
mtxffp, mtxfoh, mtxefp, and mtxeoh instead of ena for location
strobes.
The SONET/SDH framer samples data from mtxdat on the rising edge
of txclk, following an asserted high mtxena. TOH/POH and fixed stuff
bytes are not sampled unless accompanied by mtxoho or mtxerr, see the
pseudo-code in “SONET/SDH Transmitter (SSTX_DATA) Description”
on page 62.
Figure 31 through Figure 33 on page 87 show additional Midbus signals
in the transmit direction.
Figure 31 shows a fixed frame reset.
Figure 31. Slave Source Driven Fixed Frame Reset STS-1
(1)
(2)
(3)
(4)
txclk
mtxdat
A1
A2
J0
Z3
PL
mtxena
mtxffp
mtxfoh
mtxefp
mtxeoh
mtxffr
mtxefr
mtxpos
mtxneg
Notes:
(1)
(2)
(3)
(4)
86
Fixed frame reset
Strobes for fixed frame pulse
First byte of fixed frame
SPE/VC offset is always set to zero after fixed frame reset.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Figure 32 shows an embedded frame reset.
Figure 32. Slave Source Driven Embedded Frame Reset t
(1)
(2)
(2)
(3) (3)
(3)
(4) (4)
(4)
H1
H2
H3
J1
PL
J1
txclk
mtxdat
H1
H2
H3
J1
PL
PL
...
mtxena
...
mtxffp
...
mtxfoh
...
mtxefp
...
mtxeoh
...
mtxffr
...
mtxefr
...
mtxpos
...
mtxneg
...
PL
PL
PL
Notes:
3
Embedded frame reset requested. Offset is captured as 2 (2 clock advance).
NDF pointer inserted with offset determined by (1).
NDF offset has not been reached.
NDF offset is reached. New SPE/VC starts.
Specifications
(1)
(2)
(3)
(4)
Figure 33 shows a negative stuff.
Figure 33. Slave Source Driven Negative Stuff
(1)
(3)
(2)
txclk
mtxdat
H1
H2
H3
J1
PL
PL
...
mtxena
...
mtxffp
...
mtxfoh
...
mtxefp
...
mtxeoh
...
mtxffr
...
mtxefr
...
mtxpos
...
mtxneg
...
PL
PL
PL
H1
H2
H3/J1
PL
PL
PL
Notes:
(1)
(2)
(3)
Initial offset is zero.
Last opportunity. Must be asserted two clocks cycles before the path.
J1 byte is in H3 negative stuff opportunity byte.
Altera Corporation
87
SONET/SDH Compiler User Guide
Specifications
Timing Information
This section represents the Midbus interface timing information in table
format; these tables show the correlation between the strobes and the data.
In the receive Midbus interface, for a given table row, the strobes occur on
the same clock cycle as data is presented on the data bus. In the transmit
Midbus interface, the strobes are produced by the master one clock cycle
before the master samples the data bus. The tables use the following
abbreviations:
■
■
■
■
PL = Payload
FS = Fixed stuff
UN = Undefined
X = Strobes are asserted as appropriate for TOH, POH, PL, UN, and
FS during this time.
Tables 26 through 29 show the Midbus interface timing information for a
configuration with the following parameters:
■
■
■
OCLEVEL=48
PATH=concatenated
DATW=16
Tables 30 to 31 show the Midbus interface timing information for a
configuration with the following parameters:
■
■
■
OCLEVEL=48
PATH=channelized – STS-1/AU-3
DATW=32
Table 26. Start of Frame Timing Information (Part 1 of 2)
Row
Column
slt[4:0]
dat[15:0]
ffp
foh
efp
eoh
ena
1
1
0
A1A1 (1)
1’b1
1’b1
1’b0
1’b0
1’b0
1
1
1..23
A1A1
1’b0
1’b1
1’b0
1’b0
1’b0
1
2
0
A2A2
1’b0
1’b1
1’b0
1’b0
1’b0
1
2
1..23
A2A2
1’b0
1’b1
1’b0
1’b0
1’b0
1
3
0
J0Z0
1’b0
1’b1
1’b0
1’b0
1’b0
1
3
1..23
Z0Z0
1’b0
1’b1
1’b0
1’b0
1’b0
1
4
0
J1FS (2)
1’b0
1’b0
1’b1
1’b1
1’b0
1
4
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
1
4
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
1
5..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
2..3
1..90
0..23
X
X
X
X
X
X
88
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 26. Start of Frame Timing Information (Part 2 of 2)
Row
Column
slt[4:0]
4
1
0..23
4
2
4
3
4
4
dat[15:0]
ffp
foh
efp
eoh
ena
H1H1
1’b0
1’b1
1’b0
1’b0
1’b0
0..23
H2H2 (3)
1’b0
1’b1
1’b0
1’b0
1’b0
0..23
H3H3=UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
0
G1FS
1’b0
1’b0
1’b0
1’b1
1’b0
4
4
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
4
4
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
4
5..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5..9
1..90
0..23
X
X
X
X
X
X
Notes:
(1)
(2)
(3)
Start of frame
Path 1 (only path) starting with 522 offset.
Normal Pointer
3
Table 27. Negative Stuff Timing Information
Column
slt[4:0]
dat[15:0]
ffp
foh
efp
eoh
ena
1..3
1..90
0..23
X
X
X
X
X
X
4
1
0..23
H1H1
1’b0
1’b1
1’b0
1’b0
1’b0
4
2
0..23
H2H2 (1)
1’b0
1’b1
1’b0
1’b0
1’b0
4
3
0
H3H3=G1FS (2) 1’b0
1’b1
1’b0
1’b1
1’b0
4
3
1..7
H3H3=FSFS
1’b1
1’b0
1’b0
1’b0
4
3
8..23
H3H3=PLPL
1’b0
1’b1
1’b0
1’b0
1’b1
4
4..89
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
4
90
0
F2FS
1’b0
1’b0
1’b0
1’b1
1’b0
4
90
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
4
90
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5
1
0..23
B2B2
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
0
K1UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
0
K2UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
1’b0
Specifications
Row
5
4..90
0..23
X
1’b0
1’b0
X
X
X
6..9
1..90
0..23
X
X
X
X
X
X
Notes:
(1) Negative Stuff Pointer
(2)
foh and eoh are asserted simultaneously
Altera Corporation
89
SONET/SDH Compiler User Guide
Specifications
Table 28. Positive Stuff Timing Information
Row
Column
slt[4:0]
dat[15:0]
ffp
foh
efp
eoh
ena
1..3
1..90
0..23
X
X
X
X
X
X
4
1
0..23
H1H1
1’b0
1’b1
1’b0
1’b0
1’b0
4
2
0..23
H2H2 (1)
1’b0
1’b1
1’b0
1’b0
1’b0
4
3
0..23
H3H3=UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
4
4
0..23
UNUN (2)
1’b0
1’b0
1’b0
1’b0
1’b0
4
5
0
G1FS
1’b0
1’b0
1’b0
1’b1
1’b0
4
5
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
4
5
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
4
6..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5
1
0..23
B2B2
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
0
K1UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
0
K2UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
5
4
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5
5
0
F2FS
1’b0
1’b0
1’b0
1’b1
1’b0
5
5
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
5
5
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5
6..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
6..9
1..90
0..23
X
X
X
X
X
X
Notes:
(1)
(2)
Positive stuff pointer
Positive stuff opportunity
Table 29. NDF Timing Information (Part 1 of 2)
Row
Column
slt[4:0]
dat[15:0]
ffp
foh
efp
eoh
ena
1..3
1..90
0..23
X
X
X
X
X
X
4
1
0..23
H1H1
1’b0
1’b1
1’b0
1’b0
1’b0
4
2
0..23
H2H2 (1)
1’b0
1’b1
1’b0
1’b0
1’b0
4
3
0..23
H3H3=UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
4
4
0
G1FS
1’b0
1’b0
1’b0
1’b1
1’b0
4
4
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
4
4
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
4
5
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
90
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Specifications
SONET/SDH Compiler User Guide
Table 29. NDF Timing Information (Part 2 of 2)
Row
Column
slt[4:0]
dat[15:0]
ffp
J1FS (2)
foh
1’b0
1’b0
efp
1’b1
eoh
ena
4
6
0
1’b1
1’b0
4
6
1..7
FSFS
1’b0
1’b0
4
6
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
4
7..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b1
1’b0
1’b1
5
1
0..23
B2B2
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
0
K1UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
2
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
0
K2UN
1’b0
1’b1
1’b0
1’b0
1’b0
5
3
1..23
UNUN
1’b0
1’b1
1’b0
1’b0
1’b0
5
4..5
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
5
6
0
B3FS
1’b0
1’b0
1’b0
1’b1
1’b0
5
6
1..7
FSFS
1’b0
1’b0
1’b0
1’b0
1’b0
5
6
8..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
7..90
0..23
PLPL
1’b0
1’b0
1’b0
1’b0
1’b1
6..9
1..90
0..23
X
X
X
X
X
X
3
Specifications
5
Notes:
(1)
(2)
NDF to 2 offset
NDF takes effect at offset
Table 30. Start of Frame Timing Information (Part 1 of 2)
Row
1
Column
1
slt[3:0]
0
dat[31:0]
A1A1A1A1
ffp
1’b1
foh
1’b1
efp[3:0]
4’b0000
eoh[3:0]
4’b0000
ena[3:0]
4’b0000
1
1
1..11
A1A1A1A1
1’b0
1’b1
4’b0000
4’b0000
4’b0000
1
2
0
A2A2A2A2
1’b0
1’b1
4’b0000
4’b0000
4’b0000
1
2
1..11
A2A2A2A2
1’b0
1’b1
4’b0000
4’b0000
4’b0000
1
3
0
J0Z0Z0Z0
1’b0
1’b1
4’b0000
4’b0000
4’b0000
1
3
1..11
Z0Z0Z0Z0
1’b0
1’b1
4’b0000
4’b0000
4’b0000
1
4
0..11
J1J1J1J1 (1)
1’b0
1’b0
4’b1111
4’b1111
4’b0000
1
5..32
0..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
1
33
0..11
FSFSFSFS (2)
1’b0
1’b0
4’b0000
4’b0000
4’b0000
1
34..61
0..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
1
62
0..11
FSFSFSFS
1’b0
1’b0
4’b0000
4’b0000
4’b0000
1
63..90
0..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
2..3
1..90
0..11
X
X
X
X
X
X
4
1
0..11
H1H1H1H1 (3)
1’b0
1’b1
4’b0000
4’b0000
4’b0000
Altera Corporation
91
SONET/SDH Compiler User Guide
Specifications
Table 30. Start of Frame Timing Information (Part 2 of 2)
Row
Column
slt[3:0]
dat[31:0]
ffp
foh
1’b0
efp[3:0]
1’b1
4’b0000
eoh[3:0]
4’b0000
ena[3:0]
4
2
0..11
H2H2H2H2
4’b0000
4
3
0..11
H3H3H3H3
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
4
0..11
G1G1G1G1
1’b0
1’b0
4’b0000
4’b1111
4’b0000
4
5..90
0..11
X
1’b0
1’b0
X
X
X
5..9
1..90
0..11
X
1’b0
1’b0
X
X
X
Notes:
(1)
(2)
(3)
All paths start with 522 offset.
STS-1 fixed stuff at column 29 and 58 of 87 column SPE/VC.
Normal pointer
Table 31. Simultaneous Pointer Movements (Part 1 of 2)
Row Column slt[3:0]
dat[31:0]
ffp
foh
efp[3:0]
eoh[3:0]
ena[3:0]
1..3
1..90
0..11
X
X
X
X
X
X
4
1
0..11
H1H1H1H1 (1)
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
2
0..11
H2H2H2H2 (2)
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
3
0
H3H3H3H3= G1UNUNUN (3) 1’b0
1’b1
4’b0000
4’b1000
4’b0000
4
3
1..11
H3H3H3H3
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
4
0
PLG1UNG1
1’b0
1’b0
4’b0000
4’b0101
4’b1000
4
4
1..11
G1G1G1G1
1’b0
1’b0
4’b0000
4’b1111
4’b0000
4
5
0
PLPLG1PL
1’b0
1’b0
4’b0000
4’b0010
4’b1101
4
5
1..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
4
6
0
PLPLPLJ1 (4)
1’b0
1’b0
4’b0001
4’b0001
4’b1110
4
6
1..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
4
7..89
0..11
X
1’b0
1’b0
X
X
X
5
90
0
F2PLPLPL
1’b0
1’b0
4’b0000
4’b1000
4’b0111
5
90
1..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
4
1
0..11
B2B2B2B2
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
2
0
K1UNUNUN
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
2
1..11
UNUNUNUN
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
2
0
K2UNUNUN
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
2
1..11
UNUNUNUN
1’b0
1’b1
4’b0000
4’b0000
4’b0000
4
4
0
PLF2PLPL
1’b0
1’b0
4’b0000
4’b0100
4’b1011
4
4
1..11
F2F2F2F2
1’b0
1’b0
4’b0000
4’b1111
4’b0000
4
5
0
PLPLF2PL
1’b0
1’b0
4’b0000
4’b0010
4’b1101
4
5
1..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
92
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Specifications
SONET/SDH Compiler User Guide
Table 31. Simultaneous Pointer Movements (Part 2 of 2)
Row Column slt[3:0]
dat[31:0]
PLPLPLB3
ffp
1’b0
foh
1’b0
efp[3:0]
4’b0001
eoh[3:0]
4’b0001
ena[3:0]
4
6
0
4’b1110
4
6
1..11
PLPLPLPL
1’b0
1’b0
4’b0000
4’b0000
4’b1111
4
7..90
0..11
X
1’b0
1’b0
X
X
X
5..9
1..90
0..11
X
X
X
X
X
X
Notes:
(1)
(2)
(3)
(4)
Path 1 negative stuff
Path 3 positive stuff
Path 4 NDF to 2 offset
NDF takes effect at offset.
f
For further information on this interface, refer to the Midbus Interface
Functional Specification, available at www.altera.com.
AIRbus interface
f
Altera Corporation
For further information on this interface, refer to the AIRbus Interface
Functional Specification, available at www.altera.com.
93
3
Specifications
The AIRbus interface provides access to internal registers using a simple
synchronous internal bus protocol. This consists of separate read data
(rdata[15:0]) and write data (wdata[15:0]) buses, a data transfer
acknowledge (dtack) signal, a block select (sel) signal, and an interrupt
request (irq) signal. An address (addr[n:0], n is configuration
dependent) bus and read (read) signal indicate the location and type of
access within the block. The rdata buses and dtack signals can be
merged from multiple blocks using a simple OR function. The dtack
signal is sustained until the block sel is removed (four-way
handshaking), meaning the AIRbus interface can cross clock domain
boundaries.
SONET/SDH Compiler User Guide
Signals
Specifications
Tables 32 through 36 list the pins used by the SONET/SDH framer, with
the I/Os shown in Figure 16 on page 51. The active-low signals are
indicated by _n.
f
For information on the altlvds and altgxb megafunction I/Os, shown
in Figure 24 on page 79 and Figure 25 on page 80 respectively, refer to
AN 219: Implementing SFI-4 in Stratix Devices, and AN 237: Using HighSpeed Transceiver Blocks in Stratix GX Devices.
Table 32. Clocks & Resets Signals
Port
Direction
Description
Clocks and Resets
rxclk
Input
Receive clock drives everything on the receive data path (SSRX_DATA).
rxclk_en
Depends on the CLKEN
parameter.
Input
Clock enable. Allows use of higher frequency rxclk by enabling this port
a fraction of the clock cycles.
rxreset_n
Input
Resets all flops on the rxclk domain.
For OC-192 configurations, the altlvds_rx megafunction must be reset at
the same time as the core (rxreset_n) for the bit_slip counter and the
core to be reset at the same time,.
txclk
Input
Transmit clock drives everything on the transmit data path (SSTX_DATA).
txclk_en
Depends on the CLKEN
parameter.
Input
Clock enable. Allows use of higher frequency txclk by enabling this port
a fraction of the clock cycles.
txreset_n
Input
Resets all flops on the txclk domain.
prcclk
Input
Processor clock drives the SSRX_PROC and SSTX_PROC blocks.
prcreset_n
Input
Resets all flops on the prcclk domain.
Table 33. Midbus Signals (Part 1 of 4)
Port
Direction
Description
mrxdat [n:0]
n = (DATW × 8) - 1
Output
This bus carries the received SONET/SDH stream. Transport/section
and path overhead are left intact. Applicable portions of the data stream
may be overwritten with AIS.
mrxslt [n:0]
n depends on the
OCLEVEL and DATW
parameters.
Output
This strobe does not exist for OC-1. It is the time slice counter. It
represents the STS-1 slot number, currently on the Midbus interface,
divided by the number of byte lanes. It's width is appropriate for the
configuration, i.e. OC-12 is 4 bit(0..11), 16bit OC-48 is 5 bit(0..23).
Receive Midbus
94
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 33. Midbus Signals (Part 2 of 4)
Port
Description
mrxval [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters.
Output
This strobe declares the data and other strobes of the receive Midbus
interface are valid. If this port is low, it indicates that the received
SONET/SDH signal is lost, framing is lost, or pointer lock for the
particular path is lost. For multi-byte lane configurations (OC-48 and up)
that support multiple paths, this port is a bus of width equal to the
number of byte lanes. For instance STS-48C has a single bit mrxval,
while 16 bit STS-48 has mrxval[1:0], where mrxval[1] applies to
mrxdat[15:8] and mrxval[0] applies to mrxdat[7:0]. mrxena,
mrxefp, mrxeoh, mrxais are of the same width as mrxval.
mrxena [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the data on mrxdat is payload. It is low for
fixed stuff and overhead.
mrxffp
Output
This strobe declares that the data on mrxdat is the fixed overhead
frame pulse, which indicates the first A1 byte is in the highest-order byte
lane or mrxdat.
mrxfoh
Output
This strobe declares that the data on mrxdat is fixed overhead, which
in SONET/SDH is all the TOH/SOH bytes, including H3 regardless of
current stuff operations.
mrxefp [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the data on mrxdat is the embedded frame
pulse, which is the J1 byte of a particular path.
mrxeoh [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the data on mrxdat is embedded overhead,
which is all the POH bytes.
mrxais [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that a downstream AIS is declared for the PATH
currently on mrxdat. It can be used to propagate AIS to a downstream
DS3 Framer. See the register descriptions for conditions which can be
programmed to assert this port.
mtxdat [n:0]
n = (DATW × 8) - 1
Input
This bus carries the transmit SONET/SDH stream. It is always sampled
the clock cycle following mtxena, and is also sampled any cycle that the
input mtxoho or mtxerr inputs are asserted.
mtxoho [n:0]
n depends on the DATW
parameter.
Input
This input declares to the transmitter that mtxdat is to be sampled for
overhead (or fixed stuff). It is one bit wide for every byte of the data path.
When asserted, mtxdat is used regardless of transmitter RAM buffer
contents or internally generated values(A1,A2,B1,B2,B3,H1,H2). See
the pseudo-code in “SONET/SDH Transmitter (SSTX_DATA)
Description” on page 62.
Transmit Midbus
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Specifications
Direction
SONET/SDH Compiler User Guide
Specifications
Table 33. Midbus Signals (Part 3 of 4)
Port
Direction
Description
mtxerr [n:0]
n depends on the DATW
parameter.
Input
This input declares to the transmitter that mtxdat is to be sampled for
an error mask to be applied to overhead (or fixed stuff). It is one bit wide
for every byte of the data path. For most overhead the result will be
mtxdat XORed with the contents of the transmitter RAM buffer. See the
pseudo-code in “SONET/SDH Transmitter (SSTX_DATA) Description”
on page 62.
mtxpos [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Input
This port is captured at any point in a frame and declares to the
transmitter that a positive stuff should be performed at the next
opportunity. If the 3 frame rule is enabled via AIRbus interface register,
the next opportunity is 3 frames from the last adjustment. If not, the next
opportunity is the next H1H2. It must be asserted 3 clock cycles prior to
when txdat is driven.
mtxneg [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Input
This port is captured at any point in a frame and declares to the
transmitter that a negative stuff should be performed at the next
opportunity. If the 3 frame rule is enabled via AIRbus interface register,
the next opportunity is 3 frames from the last adjustment. If not, the next
opportunity is the next H1H2. It must be asserted 3 clock cycles prior to
when txdat is driven.
mtxefr [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Input
This port is captured at any point in a frame and declares to the
transmitter that a NDF should be performed at the next opportunity. The
offset for the NDF will match the time at which mtxefr was last asserted.
The new H1H2 is inserted at the next H1H2. The SPE/VC position will
be reset at the offset following the new H1H2. It must be asserted 3
clock cycles prior to when txdat is driven.
mtxffr
Input
This allows hardware to force a frame reset. It is equivalent to the
FRAME_RST register bit.
mtxslt [n:0]
n depends on the
OCLEVEL and DATW
parameters.
Output
This strobe does not exist for OC-1. It is the time slice counter. It
represents the STS-1 slot number currently on the Midbus, divided by
the number of byte lanes. It's width is appropriate for the configuration,
i.e. OC-12 is 4 bit(0..11), 16bit OC-48 is 5 bit(0..23).
mtxena [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the SSTX_DATA is sampling payload on the
next clock cycle. It is low preceding fixed stuff and overhead.
mtxffp
Output
This strobe declares that the SSTX_DATA is sampling fixed overhead
frame pulse on the next clock cycle. In SONET/SDH fixed overhead
frame pulse is the first A1 byte.
mtxfoh
Output
This strobe declares that the SSTX_DATA is sampling fixed overhead
on the next clock cycle. In SONET/SDH fixed overhead is all the
TOH/SOH bytes, including H3 regardless of current stuff operations.
96
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 33. Midbus Signals (Part 4 of 4)
Port
Direction
Description
mtxefp [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the SSTX_DATA is sampling embedded
overhead frame pulse on the next clock cycle. In SONET/SDH
embedded overhead frame pulse is the J1 byte of a particular path.
mtxeoh [n:0]
n depends on the
OCLEVEL, DATW, and
PATH parameters
Output
This strobe declares that the SSTX_DATA is sampling embedded
overhead on the next clock cycle. In SONET/SDH embedded overhead
is all the POH bytes.
Table 34. Physical Interface Signals
Port
Direction
Description
srxdata [n:0]
n = (DATW × 8) - 1
Input
This port carries a non-byte aligned SONET/SDH stream. It is the same
width as mrxdat and is on the same clock domain. Only OC-192
configurations include the I/O modules for SFI-4.1. For all other
configurations, the user must implement the required I/Os (flopped IO,
LVDS, serdes, etc.).
srxval
Input
When low, this port indicates that srxdata is invalid, and the
SONET/SDH framer receiver is effectively disabled. This is propagated
to mrxval.
srxfr
Input
This port can be used to force a SEF condition in the framer, effectively
causing the framer to reframe.
stxdata [n:0]
n = (DATW × 8) - 1
Input
This port carries a byte aligned SONET/SDH stream. It is the same
width as mtxdat and is on the same clock domain. Only OC-192
configurations include the I/O modules for SFI-4.1. For all other
configurations, the user must implement the required I/Os (flopped IO,
LVDS, serdes, etc.).
PHY Interface
97
Specifications
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Specifications
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Table 35. AIRbus Interface Signals
Port
Direction
Description
Airbus Interface
sel
Input
This is a block level select that should be asserted until dtack is
received. It is metastable hardened internally.
read
Input
This port is sampled with sel to determine if a read or write operation is
required. Set to 1 for a read and to 0 for a write.
addr [n:0]
n depends on most of the
parameters.
Input
This port is sampled with sel to determine what internal register is to be
accessed.
wdata [15:0]
Input
This port is sampled with sel when read is enabled. The value is
written to the addressed internal register if it is writable.
rdata [15:0]
Output
This port is normally zero to allow read bus ORing. When sel and
read is enabled and a valid address is applied, the contents of the
appropriate internal register is written to this port. In the SONET/SDH
framer core, this can occur on the next cycle after the sel is metastable
hardened, or it may happen several clock cycles later if the particular
register is stored in a RAM that is continuously in use by the core.
dtack
Output
This port is normally zero to allow dtack ORing. It is asserted when a
write operation has been performed, or when rdata contains valid
data. It should be metastable hardened by the AIRbus interface master.
irq
Output
This port is set when an interrupt status bit is set and the corresponding
interrupt enable is asserted. It is cleared when all enabled interrupts are
cleared by AIRbus interface.
Table 36. Miscellaneous Signals
Port
Direction
Description
Input
This input allows SSPROC to automatically insert AIS-P when a loss of
optical carrier occurs upstream.
los
Output
This output mirrors the LOS status register bit. It is asserted when loss
of signal is detected.
lof
Output
This output mirrors the LOF status register bit. It is asserted when loss
of frame is detected.
sef
Output
This output mirrors the SEF status register bit. It is asserted when
severely errored frame is detected.
Miscellaneous Signalling
lopc
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Specifications
Software
Interface
SONET/SDH Compiler User Guide
Table 37 lists the access codes used to describe the type of register bits.
Table 37. Register Bit Description
Code
Description
Read/Write
RO
Read-Only
RW1C
Read/Write 1 to Clear
RW0S
Read/Write 0 to Set
RTC
Read to Clear
RTS
Read to Set
RTCW
Read to Clear/Write
RTSW
Read to Set/Write
RWTC
Read/Write any value to Clear
RWTS
Read/Write any value to Set
RWSC
Read/Write Self-Clearing
RWSS
Read/Write Self-Setting
UR0
Unused bits/Read as 0
UR1
Unused bits/Read as 1
3
1
All of the undefined bits within the software interface registers
should be considered reserved for future use. Their access code
should be considered as being UR0. Reading from them will
return zero, writing to them will have no effect.
1
The default values for the RDIP_CTRL registers need to be set by
a software driver. The reset value is zero
AIRbus Shadow Register
Some AIRbus slaves may have registers that are wider than their rdata
and wdata buses. These oversized registers must be shadowed if atomic
access is required. Atomic access guarantees that the contents of the
register is stable during the required multiple AIRbus reads and writes to
access the entire register.
During a shadow read, the AIRbus master must read the lower address
first, this transfers the contents of the lower address to rdata. At the same
time, the remaining portion of the internal register is transferred to the
shadow register. Therefore, the shadow register maintains a stable value
while the underlying internal register may change.
Altera Corporation
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Specifications
RW
SONET/SDH Compiler User Guide
Specifications
During a shadow write, the AIRbus master writes to the lower addresses
first. The value written is stored in the shadow register. When the AIRbus
master finally writes to the upper address, the contents of the shadow
register and the contents of wdata are transferred to the underlying
internal register, without interruption.
Table 38 shows an example read and write access.
Table 38. AIRbus Shadow Register Access Example
wdata[7:0] rdata[7:0] shadow[23:0] internal[31:0]
Comment
INITIAL
X
X
XXX
XXXX
read 0
X
D
ABC
ABCD
Internal[31:8] is transferred to
shadow[23:0], while internal[7:0] is
transferred to rdata
read 1
X
C
ABC
FFFF
The change from ABCD to FFFF in the
underlying internal register does not affect
the atomic access of the shadow register.
read 2
X
B
ABC
FFFF
read 3
X
A
ABC
FFFF
write 0
4
0
AB4
FFFF
write 1
3
0
A34
FFFF
write 2
2
0
234
FFFF
write 3
1
0
234
1234
Shadow[23:0] is transferred to
internal[23:0] while wdata[7:0] is
transferred to internal[31:24]
Memory Maps
All addresses access 8 or 16-bit registers and are shown as hexadecimal
values. The value is the byte address, thus for 16-bit registers bit 0 is not
used.
Table 39.Memory Map Links
RXT_REG Memory Map
RXT_PRC Memory Map
RXT_OHR (1)
RXP_REG Memory Map
RXP_PRC Memory Map
100
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Specifications
SONET/SDH Compiler User Guide
Table 39.Memory Map Links
RXP_OHR (1)
TXT_REG Memory Map
TXT_PRC Memory Map
TXT_OHR (1)
TXP_REG Memory Map
TXP_PRC Memory Map
TXP_OHR (1)
Note:
(1)
Offsets and overhead memory maps are generated by the IP Toolbench in HTML,
for each configuration.
RXT_REG Memory Map
All addresses are 16-bit accesses and are shown as hex values. Note that
the access addresses for each register increment by units of 2, since the
accesses are 16-bits wide.
Specifications
Table 40. RXT_ REG Memory Map
Address
Register
Description
’h0
RXT_REG_CTRL1
Receiver transport control
’h2
RXT_REG_CTRL2
Receiver AIS control
’h4
RXT_REG_CTRL3
Receiver framer control
’h6
RXT_REG_CTRL4
Receiver framer control
’h8
RXT_REG_CTRL5
Receiver LOS detect threshold control
’hA
RXT_REG_CTRL6
Receiver LOS terminate threshold control
’hC
RXT_REG_CTRL7
Receiver software alignment control
’hE
RXT_REG_STAT
Receiver transport status
’h10
RXT_REG_IS
Receiver transport interrupt status
’h12
RXT_REG_IE
Receiver transport interrupt enable
’h14
RXT_REG_B1_ERR
Receiver transport B1 error count
’h16
RXT_REG_B2_ERR
Receiver transport B2 error count
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Specifications
RXT_REG Register Description
Table 41. RXT_REG_CTRL1 - Receiver transport control - ’h0
Field
Bits
Access
Function
Default
FORCE_SEF
1
RWSC
Writing a 1 to this bit forces the SONET receiver framer to ’h0
declare a severely errored frame (SEF) defect, and forces
the framer out of frame. The framer automatically recovers
frame after a forced SEF. This bit is automatically cleared.
Writing a 0 to this bit has no effect.
DESCRAM_DIS
0
RW
This bit allows software to enable/disable the SONET
receiver's descrambling function. The generating
polynomial is 1+ x6 + x7, and the sequence length is 127.
Writing a 0 enables descrambling.
Writing a 1 disables descrambling.
’h0
Table 42. RXT_REG_CTRL2 - Receiver AIS control - ’h2
Field
Bits
Access
Function
Default
FORCE_AISP
1
RW
This field allows the user to force a downstream path AIS in ’h0
all paths. The RXP_REG.FORCE_AISP reg is for AIS-P
insertion on individual paths.
FORCE_AISL
0
RW
This field allows the user to force a downstream line alarm
indication signal (AIS). AIS-L inserts 8'hFF into all bytes,
except section overhead (SOH/RSOH).
102
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 43. RXT_REG_CTRL3 - Receiver framer control - ’h4
Field
Bits
A1A2_FRAME_THRSH 3:0
Access
RW
Function
This field allows the user to select the number of valid A1
and A2 patterns that must be matched to find frame.
Default
’h1
■
■
When this bit is set to 0, the pattern is F628.
When this bit is set to 1, the pattern is F6F62828.
Table 44. RXT_REG_CTRL4 - Receiver framer control - ’h6
Field
A1A2_SEF_THRSH
Altera Corporation
Bits
3:0
Access
RW
Function
Default
This field allows the user to select the number of invalid A1 ’h1
and A2 patterns that must be found to declare a SEF.
This value is applied to both A1 and A2. The sequence of
invalid patterns can be non-contiguous, except that the first
A2 must follow the last A1. Each byte of the data path is
monitored independently.
Example for OC-192: If this field is set to 50 and at least 50
A1 patterns and 50 A2 patterns contain errors, or if the last
A1 or first A2 contain errors, the frame is declared to be
severely errored.
Note: Once frame is found, four consecutive errored frames
are required before a SEF is declared.
Do not set this register to zero.
103
3
Specifications
For data paths greater than 8-bits wide, only the lower 8 bits
are considered for A1 detection, and only the upper 8 bits
are considered for A2 detection.
The value is applied to both A1 and A2.
Example 1: 8-bit data path with A1A2_FRAME_THRSH
equal 2, framer finds frame on a serial stream containing
(hex)...XXXXXXF6F62828XXXXXX...
Example 2: 32-bit data path with A1A2_FRAME_THRSH
equal 2, framer finds frame on a serial stream containing
(hex)
...XXXXXXXXF6XXXXXXF628XXXXXX28XXXXXXXX...
Do not set this register to zero.
------------------------------------------------------------------------------ --------‘h0
For Stratix GX configurations, two patterns are available:
SONET/SDH Compiler User Guide
Specifications
Table 45. RXT_REG_CTRL5 - Receiver LOS detect threshold control - ’h8
Field
Bits
Access
LOS_SET_THRSH 15:0
RW
Function
Default
This register allows software to specify the number of
’h0
consecutive all-zero words (corresponding to a number of
clock cycles) that must be seen before the SONET receiver
declares a LOS defect.
When this register is set to zero, LOS is not monitored, and
the LOS counter is cleared.
For example:
If clk=6.48, then 2.3 us is 15 cycles, 100 us is 648 cycles
If clk=19.44, then 2.3 us is 45 cycles, 100 us is 1,944 cycles
If clk=77.76, then 2.3 us is 180 cycles, 100 us is 7,776 cycles
If clk=155.52, then 2.3 us is 360 cycles, 100 us is 15,552
cycles (See Table 17 on page 58.)
Table 46. RXT_REG_CTRL6 - Receiver LOS terminate threshold control - ’hA
Field
Bits
Access
LOS_CLR_THRSH 15:0
RW
Function
Default
This register allows software to specify the number of clock ’h0
cycles in the absence of LOS declaration conditions (see
LOS_SET_THRSH) before a detected LOS is cleared.
This register should be set according to the following rule:
The incoming signal level is above the NEs LOS defect
termination threshold (if applicable), and no pulse-free
intervals of length T occur during a time period equal to the
greater of 125 us and 2.5 x T, where 2.3 us <= T <= 100 us.
Example, for OC-3: 2.3 us is 45 cycles, 100 us is 1,944
cycles, and 125 us is 2,493 cycles. If LOS_SET_THRSH is
set to 45, then LOS_CLR_THRSH is set to 2,493. If
LOS_SET_THRSH is set to 1,000, then LOS_CLR_THRSH
is set to 2,500. (See Table 17 on page 58.)
Table 47. RXT_REG_CTRL7 - Receiver software alignment control - ’hC
Field
Bits Access
TOH_CAP_DONE_ROW 3:0
104
RW
Function
Default
This register allows software to specify the row at which the ’h0
TOH_CAP_DONE interrupt occurs. By default, the row is
zero, thus the interrupt occurs after the last Z0 byte.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 48. RXT_REG_STAT - Receiver transport status - ’hE
Field
Bits
Access
Function
Default
LOF
2
RO
This bit is set to 1 when the SONET receiver detects a LOF ’h0
defect. The LOF defect is detected when the SEF timer
reaches 24 (3 ms). It is cleared when the inframe timer
reaches 24 (3 ms).
SEF
1
RO
LOS
0
RO
This bit is set to 1 when the SONET receiver detects a SEF ’h0
defect. The SEF defect is detected when the SONET
receiver does not detect A1A2_SEF_THRSH correct A1/A2
bytes for four consecutive frames.
This bit is set to 1 when the SONET receiver detects a LOS ’h0
defect.
The LOS defect is detected when the SONET receiver
detects LOS_SET_THRSH consecutive all zero words.
The LOS defect is terminated when the SONET receiver
detects the absence of LOS_CLR_THRSH consecutive all
non-zero words.
3
Field
Bits
Access
Function
Default
TOH_CAP_DONE
5
RW1C
This bit is set to 1 after the receiver captures the last TOH ’h0
byte of the row determined by
CTRL7.TOH_CAP_DONE_ROW.
This interrupt can be used by software to synchronize
AIRbus reads of TOH bytes with the received SONET
frame.
Note: the TOH ram is not shadowed, thus a particular byte
of overhead from the previous frame is overwritten with the
overhead from the current frame every 125 us.
B2
4
RW1C
This bit is set to 1 if the SONET receiver detects a B2 error. ’h0
B1
3
RW1C
This bit is set to 1 if the SONET receiver detects a B1 error. ’h0
LOF
2
RW1C
This bit is set to 1 if a change occurs in the LOF bit of the
STAT register.
’h0
SEF
1
RW1C
This bit is set to 1 if a change occurs in the SEF bit of the
STAT register.
’h0
LOS
0
RW1C
This bit is set to 1 if a change occurs in the LOS bit of the
STAT register.
’h0
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Specifications
Table 49. RXT_REG_IS - Receiver transport interrupt status - ’h10
SONET/SDH Compiler User Guide
Specifications
Table 50. RXT_REG_IE - Receiver transport interrupt enable - ’h12
Field
Bits
Access
Function
Default
TOH_CAP_DONE
5
RW
Writing a 1 enables the TOH_CAP_DONE strobe interrupt. ’h0
B2
4
RW
Writing a 1 enables the B2 error interrupt.
’h0
B1
3
RW
Writing a 1 enables the B1 error interrupt.
’h0
LOF
2
RW
Writing a 1 enables the LOF interrupt.
’h0
SEF
1
RW
Writing a 1 enables the SEF interrupt.
’h0
LOS
0
RW
Writing a 1 enables the LOS interrupt.
’h0
Table 51. RXT_REG_B1_ERR - Receiver transport B1 error count - ’h14
Field
FIELD
Bits
Access
3:0
RO
Function
Default
This field holds the sum of B1 bit errors detected in the
previous frame.
’h0
Table 52. RXT_REG_B2_ERR - Receiver transport B2 error count - ’h16
Field
FIELD
Bits
Access
6:0
RO
Function
Default
This field holds the sum of the B2 bit errors detected in the ’h0
previous frame.
RXT_PRC Memory Map
All addresses are 8-bit accesses and are shown as hex values. Note that the
access addresses for each register increment by units of 1, since the
accesses are 8-bits wide.
Table 53. RXT_PRC Memory Map (Part 1 of 3)
Address
Register
Description
'h0
RXT_PRC_CTRL1
Receiver transport control
'h1
RXT_PRC_AUTO_RX_AISP
Receiver transport auto-AIS-P control
'h2
RXT_PRC_STAT
Receiver transport status
'h3
RXT_PRC_IS1
Receiver transport interrupt status
'h4
RXT_PRC_IS2
Receiver transport interrupt status
106
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Specifications
SONET/SDH Compiler User Guide
Table 53. RXT_PRC Memory Map (Part 2 of 3)
Address
Register
Description
RXT_PRC_IE1
Receiver transport interrupt enable
’h6
RXT_PRC_IE2
Receiver transport interrupt enable
’h7
RXT_PRC_K1_ACPT
Receiver K1 accepted Value
’h8
RXT_PRC_K2_ACPT
Receiver K2 accepted Value
’h9
RXT_PRC_S1_ACPT
Receiver S1 accepted Value
’hA
RXT_PRC_RESERVED1
RESERVED
’h10
RXT_PRC_J0_CTRL
Receiver J0 control
’h11
RXT_PRC_J0_STAT1
Receiver trace message storage state
’h12
RXT_PRC_J0_STAT2
Receiver trace internal state
’h13
RXT_PRC_J0_STAT3
Receiver trace status and internal state
’h14
RXT_PRC_REIL_ERR_ACCUM
Receiver REI-L error count
’h18
RXT_PRC_B1_ERR_ACCUM
Receiver B1 error count
’h1C
RXT_PRC_B2_ERR_ACCUM
Receiver B2 error count
’h20
RXT_PRC_RESERVED2
RESERVED
’h80
RXT_PRC_SD_SET_SUB_WIN
Signal degrade set sub-window
’h81
RXT_PRC_SD_SET_BURST_TOL
Signal degrade set burst tolerance
’h83
RXT_PRC_SD_SET_RESERVED
RESERVED
’h85
RXT_PRC_SD_SET_FRM_CTR
Signal degrade set frame count
’h88
RXT_PRC_SD_SET_TIME
Signal degrade set sub-window time
’h8B
RXT_PRC_SD_SET_TOTAL_ERR
Signal degrade set total error sum
’h8E
RXT_PRC_SD_SET_ERR_THRSH
Signal degrade set total error threshold
’h90
RXT_PRC_SD_SET_WIN_STORAGE
Signal degrade set sub-window storage
’hA0
RXT_PRC_SD_CLR_SUB_WIN
Signal degrade clear sub-window
’hA1
RXT_PRC_SD_CLR_BURST_TOL
Signal degrade clear burst tolerance
’hA3
RXT_PRC_SD_CLR_RESERVED
RESERVED
’hA5
RXT_PRC_SD_CLR_FRM_CTR
Signal degrade clear frame count
’hA8
RXT_PRC_SD_CLR_TIME
Signal degrade clear sub-window time
’hAB
RXT_PRC_SD_CLR_TOTAL_ERR
Signal degrade clear total error sum
’hAE
RXT_PRC_SD_CLR_ERR_THRSH
Signal degrade clear total error threshold
’hB0
RXT_PRC_SD_CLR_WIN_STORAGE
Signal degrade clear sub-window storage
’hC0
RXT_PRC_SF_SET_SUB_WIN
Signal fail set sub-window
’hC1
RXT_PRC_SF_SET_BURST_TOL
Signal fail set burst tolerance
’hC3
RXT_PRC_SF_SET_RESERVED
RESERVED
’hC5
RXT_PRC_SF_SET_FRM_CTR
Signal fail set frame count
’hC8
RXT_PRC_SF_SET_TIME
Signal fail set sub-window time
’hCB
RXT_PRC_SF_SET_TOTAL_ERR
Signal fail set total error sum
’hCE
RXT_PRC_SF_SET_ERR_THRSH
Signal fail set total error threshold
Altera Corporation
3
Specifications
’h5
107
SONET/SDH Compiler User Guide
Specifications
Table 53. RXT_PRC Memory Map (Part 2 of 3)
Address
Register
Description
’h5
RXT_PRC_IE1
Receiver transport interrupt enable
’h6
RXT_PRC_IE2
Receiver transport interrupt enable
’h7
RXT_PRC_K1_ACPT
Receiver K1 accepted Value
’h8
RXT_PRC_K2_ACPT
Receiver K2 accepted Value
’h9
RXT_PRC_S1_ACPT
Receiver S1 accepted Value
’hA
RXT_PRC_RESERVED1
RESERVED
’h10
RXT_PRC_J0_CTRL
Receiver J0 control
’h11
RXT_PRC_J0_STAT1
Receiver trace message storage state
’h12
RXT_PRC_J0_STAT2
Receiver trace internal state
’h13
RXT_PRC_J0_STAT3
Receiver trace status and internal state
’h14
RXT_PRC_REIL_ERR_ACCUM
Receiver REI-L error count
’h18
RXT_PRC_B1_ERR_ACCUM
Receiver B1 error count
’h1C
RXT_PRC_B2_ERR_ACCUM
Receiver B2 error count
’h20
RXT_PRC_RESERVED2
RESERVED
’h80
RXT_PRC_SD_SET_SUB_WIN
Signal degrade set sub-window
’h81
RXT_PRC_SD_SET_BURST_TOL
Signal degrade set burst tolerance
’h83
RXT_PRC_SD_SET_RESERVED
RESERVED
’h85
RXT_PRC_SD_SET_FRM_CTR
Signal degrade set frame count
’h88
RXT_PRC_SD_SET_TIME
Signal degrade set sub-window time
’h8B
RXT_PRC_SD_SET_TOTAL_ERR
Signal degrade set total error sum
’h8E
RXT_PRC_SD_SET_ERR_THRSH
Signal degrade set total error threshold
’h90
RXT_PRC_SD_SET_WIN_STORAGE
Signal degrade set sub-window storage
’hA0
RXT_PRC_SD_CLR_SUB_WIN
Signal degrade clear sub-window
’hA1
RXT_PRC_SD_CLR_BURST_TOL
Signal degrade clear burst tolerance
’hA3
RXT_PRC_SD_CLR_RESERVED
RESERVED
’hA5
RXT_PRC_SD_CLR_FRM_CTR
Signal degrade clear frame count
’hA8
RXT_PRC_SD_CLR_TIME
Signal degrade clear sub-window time
’hAB
RXT_PRC_SD_CLR_TOTAL_ERR
Signal degrade clear total error sum
’hAE
RXT_PRC_SD_CLR_ERR_THRSH
Signal degrade clear total error threshold
’hB0
RXT_PRC_SD_CLR_WIN_STORAGE
Signal degrade clear sub-window storage
’hC0
RXT_PRC_SF_SET_SUB_WIN
Signal fail set sub-window
’hC1
RXT_PRC_SF_SET_BURST_TOL
Signal fail set burst tolerance
’hC3
RXT_PRC_SF_SET_RESERVED
RESERVED
’hC5
RXT_PRC_SF_SET_FRM_CTR
Signal fail set frame count
’hC8
RXT_PRC_SF_SET_TIME
Signal fail set sub-window time
’hCB
RXT_PRC_SF_SET_TOTAL_ERR
Signal fail set total error sum
’hCE
RXT_PRC_SF_SET_ERR_THRSH
Signal fail set total error threshold
108
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 53. RXT_PRC Memory Map (Part 3 of 3)
Address
Register
Description
’hD0
RXT_PRC_SF_SET_WIN_STORAGE
Signal fail set sub-window storage
’hE0
RXT_PRC_SF_CLR_SUB_WIN
Signal fail clear sub-window
’hE1
RXT_PRC_SF_CLR_BURST_TOL
Signal fail clear burst tolerance
’hE3
RXT_PRC_SF_CLR_RESERVED
RESERVED
’hE5
RXT_PRC_SF_CLR_FRM_CTR
Signal fail clear frame count
’hE8
RXT_PRC_SF_CLR_TIME
Signal fail clear sub-window time
’hEB
RXT_PRC_SF_CLR_TOTAL_ERR
Signal fail clear total error sum
’hEE
RXT_PRC_SF_CLR_ERR_THRSH
Signal fail clear total error threshold
’hF0
RXT_PRC_SF_CLR_WIN_STORAGE
Signal fail clear sub-window storage
’h100
RXT_PRC_RESERVED3
RESERVED
’h140
RXT_PRC_J0_MSG_EXP
Receiver J0 expected buffer
’h180
RXT_PRC_J0_MSG_ACP
Receiver J0 accepted buffer
’h1C0
RXT_PRC_J0_MSG_RCV
Receiver J0 received buffer
3
Table 54. RXT_PRC_CTRL1 - Receiver transport control - ’h0 (Part 1 of 2)
Field
Bits
Access
Function
Default
SF_EN
5
RW
This bit allows software to enable/disable signal fail (SF)
detection by SSPROC.
’h0
SD_EN
4
RW
This bit allows software to enable/disable signal degrade
(SD) detection by SSPROC.
’h0
REIL_ERR_TYPE
3
RW
This bit allows software to select either bit or frame error
’h0
monitoring for the REI-L (M0/M1) code. If configured for bit
error, SSPROC increments the REIL_ERR_ACCUM
register with the M0/M1 code. If configured for frame error,
SSPROC increments the REIL_ERR_ACCUM register for
each valid non-zero REI-L code. REI-L codes greater than
min(OC*8,255) are not considered valid, and are ignored.
B2_ERR_TYPE
2
RW
This bit allows software to select either bit or frame error
’h0
monitoring for line BIP-8. If configured for bit error, SSPROC
increments the B2_ERR_ACCUM register for each bit of the
B2 code that has an error. If configured for frame error,
SSPROC increments the B2_ERR_ACCUM register for
each frame that contains a B2 error.
Writing a 0 configures SSPROC to count B2 bit errors.
Writing a 1 configures SSPROC to count B2 frame errors.
Altera Corporation
109
Specifications
RXT_PRC Register Description
SONET/SDH Compiler User Guide
Specifications
Table 54. RXT_PRC_CTRL1 - Receiver transport control - ’h0 (Part 2 of 2)
Field
Bits
Access
Function
Default
B1_ERR_TYPE
1
RW
This bit allows software to select either bit or frame error
monitoring for the section BIP-8. If configured for bit error,
SSPROC increments the B1_ERR_ACCUM register for
each bit of the B1 code that has an error. If configured for
frame error, SSPROC increments the B1_ERR_ACCUM
register for each frame that contains a B1 error.
Writing a 0 configures SSPROC to count B1 bit errors.
Writing a 1 configures SSPROC to count B1 frame errors.
’h0
RDIL_AISL_THRSH
0
RW
This bit allows software to select either the SONET or SDH ’h0
mode of operation for RDI-L and AIS-L monitoring. For
SONET, RDI-L and AIS-L codes must persist for 5 frames
before being accepted. For SDH, the threshold is 3 frames.
Writing a 0 configures SSPROC to operate in SONET mode.
Writing a 1 configures SSPROC to operate in SDH mode.
Table 55. RXT_PRC_AUTO_RX_AISP - Receiver transport auto-AIS-P control - ’h1
Field
Bits
Access
Function
Default
SF
7
RW
This bit enables automatic downstream AIS-P insertion
when SSPROC detects a SF alarm.
’h0
SD
6
RW
This bit enables automatic downstream AIS-P insertion
when SSPROC detects a SD alarm.
’h0
J0_INV
5
RW
This bit enables automatic downstream AIS-P insertion
when SSPROC detects a J0 unstable alarm (J0_INV).
’h0
J0_MIS
4
RW
This bit enables automatic downstream AIS-P insertion
when SSPROC detects a J0 mismatch alarm (J0_MIS).
’h0
LOF
3
RW
This bit enables automatic downstream AIS-P insertion
when SSRX_DATA detects a loss of frame (LOF) alarm.
’h0
LOS
2
RW
This bit enables automatic downstream AIS-P insertion
when SSRX_DATA detects a loss of signal (LOS) alarm.
’h0
LOPC
1
RW
This bit enables automatic downstream AIS-P insertion
when the loss of optical carrier (LOPC) input to SSPROC
becomes active.
’h0
AISL
0
RW
This bit enables automatic downstream AIS-P insertion
’h0
when SSPROC detects an AIS-L alarm. AIS-P is inserted by
setting the H1, H2, H3, and all of the SPE/VC bytes to 8’hFF.
110
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 56. RXT_PRC_STAT - Receiver transport status - ’h2
Field
Bits
Access
Function
Default
SF
7
RO
This bit is set to 1 when a SF defect is detected. See the
SF_* registers for descriptions of thresholds.
’h0
SD
6
RO
This bit is set to 1 when a SD defect is detected. See the
SD_* registers for descriptions of thresholds.
’h0
J0_INV
5
RO
This bit is set to 1 when the J0 unstable counter reaches 8. ’h0
The J0 unstable counter is incremented for each message
that differs from the previously received message. This field
is a duplicate of J0_STAT3.TRACE_INV
J0_MIS
4
RO
This bit is set to 1 when the accepted J0 message is different ’h0
from the expected message downloaded by software. This
field is a duplicate of J0_STAT3.TRACE_MISMATCH
S1_INV
3
RO
This bit is set to 1 when the S1 unstable counter reaches 32. ’h0
The S1 unstable counter is incremented for each S1 value
that differs from the previously received S1 value. Only the
least significant 4 bits of the S1 byte are compared.
2
RO
This bit is set to 1 when no three consecutive K1/K2 codes ’h0
of the last 12 successive frames are identical, starting with
the last frame containing a previously consistent code.
RDIL
1
RO
This bit is set to 1 when SSPROC detects RDI-L on the
incoming stream. RDI-L is detected when bits 6, 7, and 8
(the three least significant bits) of the K2 byte contains the
110 pattern in 3 or 5 consecutive frames. See
CTRL1.RDIL_AISL_THRSH.
AISL
0
RO
This bit is set to 1 when SSRX_DATA detects AIS-L on the ’h0
incoming stream. AIS-L is detected when bits 6, 7, and 8(the
three least significant bits) of the K2 byte contain the 111
pattern for 3 or 5 consecutive frames. See
CTRL1.RDIL_AISL_THRSH.
Specifications
APS_INV
3
’h0
Table 57. RXT_PRC_IS1 - Receiver transport interrupt status - ’h3 (Part 1 of 2)
Field
Bits
Access
Function
Default
REIL
6
RW1C
This bit is set if SSPROC detects a non-zero REI-L (M0/M1) ’h0
code.
S1_CONS
5
RW1C
This bit is set if a change occurs in the S1_INV bit of the
STAT register.
Altera Corporation
’h0
111
SONET/SDH Compiler User Guide
Specifications
Table 57. RXT_PRC_IS1 - Receiver transport interrupt status - ’h3 (Part 2 of 2)
Field
Bits
Access
Function
Default
S1_NEW
4
RW1C
This bit is set if SSPROC detects a different consistent S1
value. A consistent S1 value is one that is detected for 8
consecutive frames. Only the least significant 4 bits of the
S1 byte are compared.
’h0
APS_CONS
3
RW1C
This bit is set if a change occurs in the APS_INV bit of the
STAT register.
’h0
RDIL
2
RW1C
This bit is set if a change occurs in the RDI-L bit of the STAT ’h0
register.
AISL
1
RW1C
This bit is set if a change occurs in the AIS-L bit of the STAT ’h0
register.
K1K2_NEW
0
RW1C
This bit is set if SSPROC detects a different consistent K1K2 ’h0
value. A consistent K1K2 value is one that is detected for 3
consecutive frames.
Table 58. RXT_PRC_IS2 - Receiver transport interrupt status - ’h4
Field
Bits
Access
Function
Default
SF
4
RW1C
This bit is set if a change occurs in the SF bit of the STAT
register.
’h0
SD
3
RW1C
This bit is set if a change occurs in the SD bit of the STAT
register.
’h0
J0_CONS
2
RW1C
This bit is set if a change occurs in the J0_INV bit of the
STAT register.
’h0
J0_MIS
1
RW1C
This bit is set if a change occurs in the J0_MIS bit of the
STAT register.
’h0
J0_NEW
0
RW1C
This bit is set if SSPROC detects a different consistent J0 ’h0
message. A consistent J0 message is one that is received 3
or 5 (J0_CTRL.THRSHD) times in succession.
Table 59. RXT_PRC_IE1 - Receiver transport interrupt enable - ’h5 (Part 1 of 2)
Field
Bits
Access
Function
Default
REIL
6
RW
Writing a 1 enables the REI-L interrupt.
’h0
S1_CONS
5
RW
Writing a 1 enables the S1 consistency interrupt.
’h0
S1_NEW
4
RW
Writing a 1 enables the S1 change interrupt.
’h0
APS_CONS
3
RW
Writing a 1 enables the APS consistency interrupt.
’h0
112
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 59. RXT_PRC_IE1 - Receiver transport interrupt enable - ’h5 (Part 2 of 2)
Field
Bits
Access
Function
Default
RDIL
2
RW
Writing a 1 enables the RDI-L interrupt.
’h0
AISL
1
RW
Writing a 1 enables the AIS-L interrupt.
’h0
K1K2_NEW
0
RW
Writing a 1 enables the K1/K2 change interrupt.
’h0
Table 60. RXT_PRC_IE2 - Receiver transport interrupt enable - ’h6
Field
Bits
Access
Function
Default
SF
4
RW
Writing a 1 enables the SF interrupt.
’h0
SD
3
RW
Writing a 1 enables the SD interrupt.
’h0
J0_CONS
2
RW
Writing a 1 enables the J0 consistency interrupt.
’h0
J0_MIS
1
RW
Writing a 1 enables the J0 mismatch interrupt.
’h0
J0_NEW
0
RW
Writing a 1 enables the J0 change interrupt.
’h0
3
Field
FIELD
Bits
7:0
Access
RO
Function
Default
This register provides access to the accepted K1 value. A ’h0
K1 value is accepted if the K1/K2 pair to which it belongs is
received for 3 frames in succession. This register should be
polled by software to determine various APS codes.
Table 62. RXT_PRC_K2_ACPT - Receiver K2 accepted Value - ’h8
Field
FIELD
Altera Corporation
Bits
7:0
Access
RO
Function
Default
This register provides access to the accepted K2 value from ’h0
SSPROC. A K2 value is accepted if the K1/K2 pair to which
it belongs is received for 3 frames in succession. This
register should be polled by software to determine various
APS codes.
113
Specifications
Table 61. RXT_PRC_K1_ACPT - Receiver K1 accepted Value - ’h7
SONET/SDH Compiler User Guide
Specifications
Table 63. RXT_PRC_S1_ACPT - Receiver S1 accepted Value - ’h9
Field
FIELD
Bits
3:0
Access
RO
Function
Default
This register provides access to the accepted S1 value from ’h0
SSPROC. An S1 value is accepted if it is received for 8
frames in succession.
Table 64. RXT_PRC_RESERVED1 - RESERVED - ’hA
Field
RESERVED
Bits
47:0
Access
Function
Default
RW
’h0
Table 65. RXT_PRC_J0_CTRL - Receiver J0 control - ’h10
Field
Bits
Access
Function
Default
RESET
4
RW
This field should be set any time the other fields of this
register are changed. This reset is a self-clearing field.
THRSHD
3
RW
This field determines the J0 message acceptance threshold ’h0
when SSPROC is filtering the J0 message.
0 (SONET) = SSPROC accepts a J0 message after it is
received 3 times in succession.
1 (SDH) = SSPROC accepts a J0 message after it is
received 5 times in succession.
TYPE
2
RW
This field sets the algorithm used by SSPROC to find
message alignment for the J0 byte.
0 = SONET (LF termination)
1 = SDH (1 in most significant bit of first byte)
MSG_LEN
1:0
RW
This field sets the length of the J0 message being received. ’h0
00/01 = message length is 1.
10 = message length is 16.
11 = message length is 64.
114
’h0
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 66. RXT_PRC_J0_STAT1 - Receiver trace message storage state - ’h11
Field
Bits Access
TRACE_BYTE_CNT
7:2
Function
Default
RW
This field is used to determine the byte position in the current ’h0
message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_SWAPPED_LAST 1
RW
This field is used to determine whether J0_MSG_ACP or
J0_MSG_RCV was the last received message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
TRACE_PAGE_SEL
RW
J0_STAT1.TRACE_PAGE_SEL must be read and XORed
with addr[6] when accessing J0_MSG_ACP and
J0_MSG_RCV.
This register should not be written to in normal operation.
’h0
0
3
Field
Bits
Access
Function
Default
TRACE_ACPT_CNT 7:4
RW
This field counts the number of consistent messages
received. When it reaches 3 or 5 (J0_CTRL.THRSH),
TRACE_ACPT is set.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
TRACE_INV_CNT
RW
This field counts the number of inconsistent messages
received. When it reaches 8, TRACE_INV is set.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
3:0
Table 68. RXT_PRC_J0_STAT3 - Receiver trace status and internal state - ’h13 (Part 1 of 2)
Field
TRACE_INCONSISTENT
Altera Corporation
Bits Access
7
RW
Function
This field is set as soon as the last received message is
determined to be different from the current message. It is
cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
Default
’h0
115
Specifications
Table 67. RXT_PRC_J0_STAT2 - Receiver trace internal state - ’h12
SONET/SDH Compiler User Guide
Specifications
Table 68. RXT_PRC_J0_STAT3 - Receiver trace status and internal state - ’h13 (Part 2 of 2)
Field
Bits Access
Function
Default
TRACE_MISMATCH_LAST 6
RW
This field is set as soon as the last received message is
’h0
determined to be different from the expected message. It is
cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_MISMATCH_ACPT 5
RW
This field is set as soon as the accepted message is
’h0
determined to be different from the expected message. It is
cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_NEW
4
RW
This field is set as soon as the current message is
determined to be different from the previously accepted
message. It is cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_ACPT
3
RW
This field is set for one frame after a message is accepted. ’h0
The message is not required to be new.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_CHANGE
2
RW
This field is updated at the end of every received message, ’h0
and indicates that a new message has been accepted.
This register should not be written to in normal operation.
TRACE_INV
1
RW
This field is updated at the end of every received message, ’h0
and indicates that 8 or more inconsistent messages have
been received.
This register should not be written to in normal operation.
TRACE_MISMATCH
0
RW
This field is updated at the end of every received message, ’h0
and indicates that the accepted message is not the same
as the expected message.
This register should not be written to in normal operation.
116
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 69. RXT_PRC_REIL_ERR_ACCUM - Receiver REI-L error count - ’h14
Field
CNT
Bits
31:0
Access
RTCW
Function
This register contains the REI-L error count accumulated
since the last read by software. The counter stops
(saturates) when the count reaches 32’hFFFFFFFF. The
counter counts either bit or frame errors depending on the
value of CTRL1.REIL_ERR_TYPE.
Writing to this register loads the counter with the value
written.
Reading from this register returns the current count, and
resets the counter.
This register is shadowed.
Default
’h0
Table 70. RXT_PRC_B1_ERR_ACCUM - Receiver B1 error count - ’h18
CNT
Altera Corporation
Bits
31:0
Access
RTCW
Function
3
Default
This register contains the B1 error count accumulated since ’h0
the last read by software. The counter stops (saturates)
when the count reaches 32’hFFFFFFFF. The counter
counts either bit or frames errors depending on the value of
CTRL1.B1_ERR_TYPE.
Writing to this register loads the counter with the value
written.
Reading from this register returns the current count, and
resets the counter.
This register is shadowed.
117
Specifications
Field
SONET/SDH Compiler User Guide
Specifications
Table 71. RXT_PRC_B2_ERR_ACCUM - Receiver B2 error count - ’h1C
Field
CNT
Bits
31:0
Access
RTCW
Function
Default
This register contains the B2 error count accumulated since ’h0
the last read by software. The counter stops (saturates)
when the count reaches 32’hFFFFFFFF. The counter
counts either bit or frame errors depending on the value of
CTRL1.B2_ERR_TYPE.
Writing to this register loads the counter with the value
written.
Reading from this register returns the current count, and
resets the counter.
This register is shadowed.
Table 72. RXT_PRC_RESERVED2 - RESERVED - ’h20
Field
Bits
RESERVED
767:0
Access
RW
Function
Reserved
Default
’h0
Table 73. RXT_PRC_SD_SET_SUB_WIN - Signal degrade set sub-window - ’h80
Field
FIELD
Bits
2:0
Access
RW
Function
Default
Indicates which of eight sub-windows is being accumulated. ’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Table 74. RXT_PRC_SD_SET_BURST_TOL - Signal degrade set burst tolerance - ’h81
Field
FIELD
118
Bits
15:0
Access
RW
Function
Default
This register specifies the maximum number of B2 bit errors ’h0
that can be accumulated in a sub-window.
If a sub-window contains more B2 bit errors than the value
contained in this register, the sub-window error count is
capped at the value contained in this register.
This register is shadowed.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 75. RXT_PRC_SD_SET_RESERVED - RESERVED - ’h83
Field
FIELD
Bits
15:0
Access
RW
Function
Reserved
Default
’h0
Table 76. RXT_PRC_SD_SET_FRM_CTR - Signal degrade set frame count - ’h85
Field
FIELD
Bits
23:0
Access
RW
Function
Default
This register indicates how many frames have been
’h0
accumulated in the current sub-window.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
3
Field
FIELD
Bits
23:0
Access
RW
Function
Default
This register sets the sub-window size. The sub-window
’h0
size is specified in units of frames (125us).
There are 8 sub-windows, thus the total time interval being
monitored is 8*SD_SET_TIME*125 us.
This register is shadowed.
Table 78. RXT_PRC_SD_SET_TOTAL_ERR - Signal degrade set total error sum - ’h8B
Field
FIELD
Altera Corporation
Bits
18:0
Access
RW
Function
Default
This register contains the sum of errors across all sub’h0
windows.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
119
Specifications
Table 77. RXT_PRC_SD_SET_TIME - Signal degrade set sub-window time - ’h88
SONET/SDH Compiler User Guide
Specifications
Table 79. RXT_PRC_SD_SET_ERR_THRSH - Signal degrade set total error threshold - ’h8E
Field
FIELD
Bits
15:0
Access
RW
Function
Default
This register sets the total error threshold.
SD is declared if the total error count for all windows
(SD_SET_TOTAL_ERR) exceeds the value contained in
this register.
This register is shadowed.
’h0
Table 80. RXT_PRC_SD_SET_WIN_STORAGE - Signal degrade set sub-window storage - ’h90
Field
FIELD
Bits
127:0
Access
RW
Function
Default
Stores 8 sub-window accumulations. Each sub-window has ’h0
16 bits of accumulation, and saturates at
SD_SET_BURST_TOL.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
Table 81. RXT_PRC_SD_CLR_SUB_WIN - Signal degrade clear sub-window - ’hA0
Field
FIELD
Bits
2:0
Access
RW
Function
Default
Indicates which of 8 sub-windows is being accumulated.
’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Table 82. RXT_PRC_SD_CLR_BURST_TOL - Signal degrade clear burst tolerance - ’hA1
Field
FIELD
120
Bits
15:0
Access
RW
Function
Default
This register specifies the maximum number of B2 bit errors ’h0
that can be accumulated in a sub-window.
If a sub-window contains more B2 bit errors than the value
contained in this register, the sub-window error count is
capped at the value contained in this register.
This register is shadowed.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 83. RXT_PRC_SD_CLR_RESERVED - RESERVED - ’hA3
Field
FIELD
Bits
15:0
Access
RW
Function
Reserved
Default
’h0
Table 84. RXT_PRC_SD_CLR_FRM_CTR - Signal degrade clear frame count - ’hA5
Field
FIELD
Bits
23:0
Access
RW
Function
Default
Indicates how many frames have been accumulated in the ’h0
current sub-window.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
3
Field
FIELD
Bits
23:0
Access
RW
Function
Default
This register sets the sub-window size. The sub-window
’h0
size is specified in units of frames (125us).
There are 8 sub-windows, thus the total time interval being
monitored is 8*SD_CLR_TIME*125 us.
This register is shadowed.
Table 86. RXT_PRC_SD_CLR_TOTAL_ERR - Signal degrade clear total error sum - ’hAB
Field
FIELD
Altera Corporation
Bits
18:0
Access
RW
Function
Default
This register contains the sum of errors across all sub’h0
windows.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
121
Specifications
Table 85. RXT_PRC_SD_CLR_TIME - Signal degrade clear sub-window time - ’hA8
SONET/SDH Compiler User Guide
Specifications
Table 87. RXT_PRC_SD_CLR_ERR_THRSH - Signal degrade clear total error threshold - ’hAE
Field
FIELD
Bits
15:0
Access
RW
Function
Default
This register sets the total error threshold.
’h0
SD is cleared if the total error count for all windows
(SD_CLR_TOTAL_ERR) is lower than the value contained
in this register.
This register is shadowed.
Table 88. RXT_PRC_SD_CLR_WIN_STORAGE - Signal degrade clear sub-window storage - ’hB0
Field
FIELD
Bits
127:0
Access
RW
Function
Default
Stores 8 sub-window accumulations. Each sub-window has ’h0
16 bits of accumulation, and saturates at
SD_CLR_BURST_TOL.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
Table 89. RXT_PRC_SF_SET_SUB_WIN - Signal fail set sub-window - ’hC0
Field
FIELD
Bits
2:0
Access
RW
Function
Default
Indicates which of 8 sub-windows is being accumulated.
’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Table 90. RXT_PRC_SF_SET_BURST_TOL - Signal fail set burst tolerance - ’hC1
Field
FIELD
122
Bits
15:0
Access
RW
Function
Default
This register specifies the maximum number of B2 bit errors ’h0
that can be accumulated in a sub-window.
If a sub-window contains more B2 bit errors than the value
contained in this register, the sub-window error count is
capped at the value contained in this register.
This register is shadowed.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 91. RXT_PRC_SF_SET_RESERVED - RESERVED - ’hC3
Field
FIELD
Bits
15:0
Access
RW
Function
Reserved
Default
’h0
Table 92. RXT_PRC_SF_SET_FRM_CTR - Signal fail set frame count - ’hC5
Field
FIELD
Bits
23:0
Access
RW
Function
Default
Indicates how many frames have been accumulated in the ’h0
current sub-window.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
3
Field
FIELD
Bits
23:0
Access
RW
Function
Default
This register sets the sub-window size. The sub-window
’h0
size is specified in units of frames (125us).
There are 8 sub-windows, thus the total time interval being
monitored is 8*SF_SET_TIME*125 us.
This register is shadowed.
Table 94. RXT_PRC_SF_SET_TOTAL_ERR - Signal fail set total error sum - ’hCB
Field
FIELD
Altera Corporation
Bits
18:0
Access
RW
Function
Default
This register contains the sum of errors across all sub’h0
windows.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
123
Specifications
Table 93. RXT_PRC_SF_SET_TIME - Signal fail set sub-window time - ’hC8
SONET/SDH Compiler User Guide
Specifications
Table 95. RXT_PRC_SF_SET_ERR_THRSH - Signal fail set total error threshold - ’hCE
Field
FIELD
Bits
15:0
Access
RW
Function
Default
This register sets the total error threshold.
SF is declared if the total error count for all windows
(SF_SET_TOTAL_ERR) exceeds the value contained in
this register.
This register is shadowed.
’h0
Table 96. RXT_PRC_SF_SET_WIN_STORAGE - Signal fail set sub-window storage - ’hD0
Field
FIELD
Bits
127:0
Access
RW
Function
Default
Stores 8 sub-window accumulations. Each sub-window has ’h0
16 bits of accumulation, and saturates at
SF_SET_BURST_TOL.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
Table 97. RXT_PRC_SF_CLR_SUB_WIN - Signal fail clear sub-window - ’hE0
Field
FIELD
Bits
2:0
Access
RW
Function
Default
Indicates which of 8 sub-windows is being accumulated.
’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Table 98. RXT_PRC_SF_CLR_BURST_TOL - Signal fail clear burst tolerance - ’hE1
Field
FIELD
124
Bits
15:0
Access
RW
Function
Default
This register specifies the maximum number of B2 bit errors ’h0
that can be accumulated in a sub-window.
If a sub-window contains more B2 bit errors than the value
contained in this register, the sub-window error count is
capped at the value contained in this register.
This register is shadowed.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 99. RXT_PRC_SF_CLR_RESERVED - RESERVED - ’hE3
Field
FIELD
Bits
15:0
Access
RW
Function
Reserved
Default
’h0
Table 100. RXT_PRC_SF_CLR_FRM_CTR - Signal fail clear frame count - ’hE5
Field
FIELD
Bits
23:0
Access
RW
Function
Default
Indicates how many frames have been accumulated in the ’h0
current sub-window.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
3
Field
FIELD
Bits
23:0
Access
RW
Function
Default
This register sets the sub-window size. The sub-window
’h0
size is specified in units of frames (125us).
There are 8 sub-windows, thus the total time interval being
monitored is 8*SF_CLR_TIME*125 us.
This register is shadowed.
Table 102. RXT_PRC_SF_CLR_TOTAL_ERR - Signal fail clear total error sum - ’hEB
Field
FIELD
Altera Corporation
Bits
18:0
Access
RW
Function
Default
This register contains the sum of errors across all sub’h0
windows.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
125
Specifications
Table 101. RXT_PRC_SF_CLR_TIME - Signal fail clear sub-window time - ’hE8
SONET/SDH Compiler User Guide
Specifications
Table 103. RXT_PRC_SF_CLR_ERR_THRSH - Signal fail clear total error threshold - ’hEE
Field
FIELD
Bits
15:0
Access
RW
Function
Default
This register sets the total error threshold.
SF is cleared if the total error count for all windows
(SF_CLR_TOTAL_ERR) is lower than the value contained
in this register.
This register is shadowed.
’h0
Table 104. RXT_PRC_SF_CLR_WIN_STORAGE - Signal fail clear sub-window storage - ’hF0
Field
FIELD
Bits
127:0
Access
RW
Function
Default
Stores 8 sub-window accumulations. Each sub-window has ’h0
16 bits of accumulation, and saturates at
SF_CLR_BURST_TOL.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
This register is not shadowed.
Table 105. RXT_PRC_RESERVED3 - RESERVED - ’h100
Field
Bits
RESERVED
511:0
Access
Function
RW
Default
’h0
Table 106. RXT_PRC_J0_MSG_EXP - Receiver J0 expected buffer - ’h140
Field
FIELD
126
Bits
511:0
Access
RW
Function
Default
This register contains the expected section trace message. ’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 107. RXT_PRC_J0_MSG_ACP - Receiver J0 accepted buffer - ’h180
Field
Bits
FIELD
511:0
Access
RW
Function
Default
This register contains the accepted section trace message. ’h0
J0_STAT1.TRACE_PAGE_SEL must be read and XORed
with bit addr[6] when accessing J0_MSG_ACP. To ensure a
clean read, read TRACE_PAGE_SEL after reading
J0_MSG_ACP. If it has changed while downloading the
J0_MSG_ACP buffer, the ACP and RCV pages are
swapped, and the J0_MSG_ACP buffer should be
downloaded again.
This register should not be written to in normal operation.
Table 108. RXT_PRC_J0_MSG_RCV - Receiver J0 received buffer - ’h1C0
Field
Bits
511:0
RW
Function
Default
This register contains the most recently received section
’h0
trace message.
J0_STAT1.TRACE_PAGE_SEL must be read and XORed
with bit addr[6] when accessing J0_MSG_RCV. This buffer
is updated every frame, and may be swapped with
J0_MSG_ACP if a new message is accepted. Use
TRACE_PAGE_SEL and TRACE_BYTE_CNT to monitor
these conditions.
This register should not be written to in normal operation.
RXP_REG Memory Map
All addresses are 16-bit accesses and are shown as hex values. Note that
the access addresses for each register increment by units of 2, since the
accesses are 16-bits wide.
Table 109. RXP_REG Memory Map (Part 1 of 2)
Address
Register
Description
'h0
RXP_REG_PTR_CTRL
Receiver path control
'h2
RXP_REG_PTR_IS
Receiver path interrupt status
'h4
RXP_REG_PTR_IE
Receiver path interrupt enable
'h6
RXP_REG_PTR_STAT
Receiver path status
'h8
RXP_REG_PATH_CTRL
Receiver path AIS control
Altera Corporation
3
Specifications
FIELD
Access
127
SONET/SDH Compiler User Guide
Specifications
Table 109. RXP_REG Memory Map (Part 2 of 2)
Address
Register
Description
’hA
RXP_REG_PATH_IS
Receiver path interrupt status
’hC
RXP_REG_PATH_IE
Receiver path interrupt enable
’hE
RXP_REG_B3_ERR
Receiver path status
RXP_REG Register Description
Table 110. RXP_REG_PTR_CTRL - Receiver path control - ’h0
Field
Bits
Access
Function
Default
CHECK_SS
1
RW
This bit allows software to enable/disable the requirement ’h0
that the ss bits of H1 be 2’b10, as recommended by the SDH
standard.
Writing a 0 disables this requirement. ss bits are ignored.
Writing a 1 enables this requirement. Pointers with ss bits
not equal to 2’b10 are interpreted as invalid pointers.
CHECK_3FRM
0
RW
This bit allows software to enable/disable the ability to
’h0
ignore a pointer increment or decrement operation detected
within three frames of a previous pointer increment or
decrement. The SONET standard recommends that
increment/decrement pointers be separated by three
frames.
Writing a 0 disables this recommendation. All pointer
increment/decrement operations detected during NDF
normal pointer state are accepted.
Writing a 1 enables this recommendation. All pointer
increment/decrement operations detected within three
frames of a previous pointer increment/decrement are
ignored and interpreted as invalid pointers. If multiple
increment/decrement pointers are received in succession
within three frames of a pointer change operation, they are
all interpreted as invalid pointers.
Table 111. RXP_REG_PTR_IS - Receiver path interrupt status - ’h2 (Part 1 of 2)
Field
AIS
128
Bits
7
Access
RW1C
Function
Default
This bit is set to 1 if the SONET receiver path processor
detects an AIS pointer in the current frame. An AIS pointer
is defined as a pointer with all bits (H1 and H2) set to 1.
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 111. RXP_REG_PTR_IS - Receiver path interrupt status - ’h2 (Part 2 of 2)
Field
Bits
Access
Function
Default
6
RW1C
This bit is set to 1 if the SONET receiver path processor
’h0
detects a new pointer in the current frame. A new pointer is
defined as a legal pointer with NDF disabled, and with a
different offset than the one being used by the SONET
receiver path processor.
INV
5
RW1C
This bit is set to 1 if the SONET receiver path processor
’h0
detects an invalid pointer. An invalid pointer is defined as a
pointer that is not an AIS pointer, not a new pointer, not a
positive stuff pointer, not an negative stuff pointer, and not a
NDF pointer.
DEC
4
RW1C
This bit is set to 1 if the SONET receiver path processor
detects a negative stuff pointer.
’h0
INC
3
RW1C
This bit is set to 1 if the SONET receiver path processor
detects a positive stuff pointer.
’h0
NDF
2
RW1C
This bit is set to 1 if the SONET receiver path processor
detects a NDF pointer.
’h0
STATE_CHANGE
1
RW1C
This bit is set to 1 if the SONET receiver path processor
changes pointer state. Read the PTR_STAT register for
current pointer state.
’h0
OFFSET_CHANGE 0
RW1C
This bit is set to 1 if the SONET receiver path processor
’h0
accepts a new pointer value. Read the PTR_STAT register
for the current pointer offset.
3
Specifications
NEW
Table 112. RXP_REG_PTR_IE - Receiver path interrupt enable - ’h4
Field
Bits
Access
Function
Default
AIS
7
RW
Writing a 1 enables the AIS pointer interrupt.
’h0
NEW
6
RW
Writing a 1 enables the new pointer interrupt.
’h0
INV
5
RW
Writing a 1 enables the invalid pointer interrupt.
’h0
DEC
4
RW
Writing a 1 enables the negative stuff interrupt.
’h0
INC
3
RW
Writing a 1 enables the positive stuff interrupt.
’h0
NDF
2
RW
Writing a 1 enables the NDF interrupt.
’h0
STATE_CHANGE
1
RW
Writing a 1 enables the pointer state change interrupt.
’h0
OFFSET_CHANGE 0
RW
Writing a 1 enables the pointer offset change interrupt.
’h0
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129
SONET/SDH Compiler User Guide
Specifications
Table 113. RXP_REG_PTR_STAT - Receiver path status - ’h6
Field
Bits
Access
Function
Default
AIS
11
RO
This bit is set when the SONET receiver path processor
’h0
detects an AIS-P on the incoming stream. AIS-P is detected
when the path processor’s pointer interpretation finite state
machine (FSM) is in the AIS state.
LOP
10
RO
This bit is set when the SONET receiver path processor
detects a LOP on the incoming stream. LOP is detected
when the path processor's pointer interpretation FSM is in
the LOP state.
CUR_OFFSET
9:0
RO
This field provides access to the pointer offset currently
’h0
accepted by the SONET receiver path processor. The
SONET receiver uses this pointer offset to locate the start of
the SONET payload envelope (SPE) in the incoming frame.
’h0
Table 114. RXP_REG_PATH_CTRL - Receiver path AIS control - ’h8
Field
Bits
Access
Function
Default
FORCE_AISD
1
RW
This field allows the user to force a downstream DS-3 AIS. ’h0
The Midbus signal mrxais is set to 1 for the time slots
associated with the affected path.
FORCE_AISP
0
RW
This field allows the user to force a downstream path AIS. ’h0
The Midbus data is all ones for the H1H2H3, POH, and data
for the affected path.
Table 115. RXP_REG_PATH_IS - Receiver path interrupt status - ’hA
Field
Bits
Access
Function
Default
B3
1
RW1C
This bit is set to 1 if the SONET receiver path processor
detects an B3 BIP error.
J1
0
RW1C
This bit is set to 1 after the J1 POH byte is captured.
’h0
This interrupt can be used by software to synchronize
AIRbus reads of POH bytes on a particular path.
Note: the POH ram is not shadowed, thus a particular byte
of overhead from the previous frame is overwritten with the
overhead from the current frame every 125 µs.
130
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 116. RXP_REG_PATH_IE - Receiver path interrupt enable - ’hC
Field
Bits
Access
Function
Default
B3
1
RW
Writing a 1 enables the B3 BIP error interrupt.
’h0
J1
0
RW
Writing a 1 enables the POH capture done interrupt.
’h0
Table 117. RXP_REG_B3_ERR - Receiver path status - ’hE
Field
Bits
FIELD
Access
3:0
RO
Function
This field holds the sum of B3 bit errors detected in the
previous frame.
Default
’h0
RXP_PRC Memory Map
Table 118. RXP_PRC Memory Map (Part 1 of 2)
Address
Register
Description
'h0
RXP_PRC_CTRL
Receiver path control
'h1
RXP_PRC_AUTO_RX_AISD
Receiver auto AIS downstream control
'h2
RXP_PRC_STAT
Receiver path status
'h3
RXP_PRC_IS1
Receiver path interrupt status
'h4
RXP_PRC_IS2
Receiver path interrupt status
'h5
RXP_PRC_IE1
Receiver path interrupt enable
'h6
RXP_PRC_IE2
Receiver path interrupt enable
'h7
RXP_PRC_RESERVED1
RESERVED
'hC
RXP_PRC_J1_CTRL
Receiver trace control
'hD
RXP_PRC_J1_STAT1
Receiver trace message storage state
'hE
RXP_PRC_J1_STAT2
Receiver trace internal state
'hF
RXP_PRC_J1_STAT3
Receiver trace status and internal state
'h10
RXP_PRC_C2_STAT1
Receiver path label (C2) previous value.
'h11
RXP_PRC_C2_STAT2
Receiver path label (C2) internal state.
'h12
RXP_PRC_C2_STAT3
Receiver path label (C2) accepted value.
'h13
RXP_PRC_C2_CTRL
Receiver Path Label (C2) Expected Value
'h14
RXP_PRC_RDIP_STAT1
Receiver RDI-P accepted and previous values
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131
3
Specifications
All addresses are 8-bit accesses and are shown as hex values. Note that the
access addresses for each register increment by units of 1, since the
accesses are 8-bits wide.
SONET/SDH Compiler User Guide
Specifications
Table 118. RXP_PRC Memory Map (Part 2 of 2)
Address
Register
Description
’h15
RXP_PRC_RDIP_STAT2
Receiver RDI-P internal state.
’h16
RXP_PRC_AUTO_RDIP_CTRL
Receiver RDI-P
’h17
RXP_PRC_RESERVED2
RESERVED
’h18
RXP_PRC_REIP_ERR_ACCUM
Receiver REI-P count
’h1C
RXP_PRC_B3_ERR_ACCUM
Receiver B3 error count
’h20
RXP_PRC_RESERVED3
RESERVED
’h40
RXP_PRC_J1_MSG_EXP
Receiver J1 expected buffer
’h80
RXP_PRC_J1_MSG_ACP
Receiver J1 accepted buffer
’hC0
RXP_PRC_J1_MSG_RCV
Receiver J1 received buffer
RXP_PRC Register Description
Table 119. RXP_PRC_CTRL - Receiver path control - ’h0
Field
Bits
Access
Function
Default
REIP_ERR_TYPE
1
RW
This bit allows software to select either bit or frame error
’h0
monitoring for the REI-P code. The REI-P code is in bits 1
through 4 of the G1 byte. If configured for bit error, SSPROC
increments the REIP_ERR_ACCUM register with the valid
value of the REI-P code. Values greater than 8 are invalid,
and are discarded. If configured for frame error, SSPROC
increments the REIP_ERR_ACCUM register for each valid
non-zero REI-P code. A valid REI-P value is equal to or less
than 8.
Writing a 0 configures SSPROC to count REI-P bit errors.
Writing a 1 configures SSPROC to count REI-P frame
errors.
B3_ERR_TYPE
0
RW
This bit allows software to select either bit or frame error
monitoring for the path BIP-8. If configured for bit error,
SSPROC increments the B3_ERR_ACCUM register for
each B3 code bit that has an error. If configured for frame
error, SSPROC increments the B3_ERR_ACCUM register
for each frame that contains a B3 error.
Writing a 0 configures SSPROC to count B3 bit errors.
Writing a 1 configures SSPROC to count B3 frame errors.
132
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 120. RXP_PRC_AUTO_RX_AISD - Receiver auto AIS downstream control - ’h1
Field
Bits
Access
Function
Default
C2_INV
6
RW
This bit enables automatic downstream (Midbus interface)
AIS insertion when SSPROC detects a C2 unstable alarm
(C2_INV).
’h0
UNEQ
5
RW
This bit enables automatic downstream (Midbus interface)
AIS insertion when SSPROC detects a path unequipped
alarm (UNEQ).
’h0
PLM
4
RW
This bit enables automatic downstream (Midbus interface) ’h0
AIS insertion when SSPROC detects a path label mismatch
alarm (PLM).
J1_INV
3
RW
This bit enables automatic downstream (Midbus interface)
AIS insertion when SSPROC detects a J1 unstable alarm
(J1_INV).
TIMP
2
RW
This bit enables automatic downstream (Midbus interface) ’h0
AIS insertion when SSPROC detects a path trace indicator
mismatch alarm (TIM-P).
’h0
1
RW
This bit enables automatic downstream (Midbus interface)
AIS insertion when SSRX_DATA detects a LOP alarm.
AISP
0
RW
This bit enables automatic downstream (Midbus interface) ’h0
AIS insertion when SSRX_DATA detects an AIS-P alarm.
AIS insertion to the Midbus interface causes the mrxais port
to be set to 1.
Specifications
LOP
3
’h0
Table 121. RXP_PRC_STAT - Receiver path status - ’h2 (Part 1 of 2)
Field
Bits
Access
Function
Default
J1_INV
6
RW
This bit is a duplicate of J1_STAT3.TRACE_INV.
’h0
TIMP
5
RW
This bit is a duplicate of J1_STAT3.TRACE_MISMATCH.
’h0
RDIP
4
RW
This bit is set when RDIP_STAT2.ACPT, the accepted RDI- ’h0
P code, matches a pattern that indicates an RDI-P defect.
For single bit RDI-P (SRDI-P), an RDI-P defect is detected
if the most significant bit of the accepted RDI-P code is a 1.
For enhanced RDI-P (ERDI-P), an RDI-P defect is detected
if the accepted RDI-P code is either 010, 101, or 110.
Altera Corporation
133
SONET/SDH Compiler User Guide
Specifications
Table 121. RXP_PRC_STAT - Receiver path status - ’h2 (Part 2 of 2)
Field
Bits
Access
Function
Default
RDIP_INV
3
RW
This bit is set when the RDI-P unstable counter reaches
’h0
AUTO_RDIP_CTRL.THRSHD. The RDI-P unstable counter
is incremented for each code that differs from the previously
received byte.
This bit is set to 0 when the same RDI-P code is received for
AUTO_RDIP_CTRL.THRSHD consecutive frames. The
RDI-P unstable counter is also cleared.
Regardless of the RDI-P type selected, all 3 bits of the RDIP field are always used to determine the consistency state
of the RDI-P code.
PUNEQ
2
RW
This bit is set when C2_STAT3.ACPT, the accepted path
’h0
label (C2) code, matches a pattern that indicates a PUNEQ
defect.
See the Signal Label (C2) Monitor Section for a definition of
the conditions which result in PUNEQ.
PLMP
1
RW
This bit is set when C2_STAT3.ACPT, the accepted path
’h0
label (C2) code, matches a pattern that indicates a PLM-P
defect.
See the Signal Label (C2) Monitor Section for a definition of
the conditions that result in PLM-P.
C2_INV
0
RW
This bit is set when the C2 unstable counter reaches 5. The ’h0
C2 unstable counter is incremented for each byte that differs
from the previously received byte.
The C2 unstable counter is cleared, and this bit is set to 0
when the same C2 value is received for 5 consecutive
frames.
Table 122. RXP_PRC_IS1 - Receiver path interrupt status - ’h3 (Part 1 of 2)
Field
Bits
Access
Function
Default
RDIP_CONS
7
RW1C
This bit is set if a change occurs in the RDIP_INV bit of the ’h0
STAT register.
RDIP_NEW
6
RW1C
This bit is set if SSPROC accepts a new and different RDI- ’h0
P value. SSPROC accepts an RDI-P value if it detects it for
AUTO_RDIP_CTRL.THRSHD frames in succession.
REIP
5
RW1C
This bit is set if SSPROC detects a non-zero REI-P code.
’h0
PUNEQ
4
RW1C
This bit is set if a change occurs in the PUNEQ bit of the
STAT register.
’h0
134
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 122. RXP_PRC_IS1 - Receiver path interrupt status - ’h3 (Part 2 of 2)
Field
Bits
Access
Function
Default
PLMP
3
RW1C
This bit is set if a change occurs in the PLMP bit of the STAT ’h0
register.
C2_CONS
2
RW1C
This bit is set if a change occurs in the C2_INV bit of the
STAT register.
C2_NEW
1
RW1C
This bit is set if the SSPROC accepts a new and different C2 ’h0
value. SSPROC accepts a C2 value if it detects it for 5
consecutive frames.
IRQ_SET
0
RW1C
This bit is set if any interrupt status bit for this path causes ’h0
an IRQ to be set. This bit's value is |(IS1&IE1) || |(IS2&IE2).
It is used internally to clear the IRQ port. Clear this field if all
other bits in IS1 and IS2 are cleared, otherwise software
should not clear this bit.
’h0
3
Table 123. RXP_PRC_IS2 - Receiver path interrupt status - ’h4
Bits
Access
Function
Default
TIMP
2
RW1C
This bit is set if a change occurs in the TIMP bit of the STAT ’h0
register.
J1_CONS
1
RW1C
This bit is set if a change occurs in the J1_INV bit of the
STAT register.
J1_NEW
0
RW1C
This bit is set if SSPROC accepts a new and different J1
’h0
message. A J1 message is accepted when it is received 3 or
5 (J1_CTRL.THRSHD) times in succession.
’h0
Table 124. RXP_PRC_IE1 - Receiver path interrupt enable - ’h5
Field
Bits
Access
Function
Default
RDIP_CONS
7
RW
Writing a 1 enables the RDI-P consistency interrupt.
’h0
RDIP_NEW
6
RW
Writing a 1 enables the RDI-P change interrupt.
’h0
REIP
5
RW
Writing a 1 enables the REI-P interrupt.
’h0
PUNEQ
4
RW
Writing a 1 enables the UEQ-P interrupt.
’h0
PLMP
3
RW
Writing a 1 enables the PLM interrupt.
’h0
C2_CONS
2
RW
Writing a 1 enables the C2 consistency interrupt.
’h0
C2_NEW
1
RW
Writing a 1 enables the C2 change interrupt.
’h0
RESERVED
0
RW
Reserved.
’h0
Altera Corporation
135
Specifications
Field
SONET/SDH Compiler User Guide
Specifications
Table 125. RXP_PRC_IE2 - Receiver path interrupt enable - ’h6
Field
Bits
Access
Function
Default
TIMP
2
RW
Writing a 1 enables the TIM-P interrupt.
’h0
J1_CONS
1
RW
Writing a 1 enables the J1 consistency interrupt.
’h0
J1_NEW
0
RW
Writing a 1 enables the J1 change interrupt.
’h0
Table 126. RXP_PRC_RESERVED1 - RESERVED - ’h7
Field
RESERVED
Bits
39:0
Access
Function
Default
RW
’h0
Table 127. RXP_PRC_J1_CTRL - Receiver trace control - ’hC
Field
Bits
Access
Function
Default
RESET
4
RW
This field should be set any time the other fields of this
register are changed. This reset is a self-clearing field.
THRSHD
3
RW
This field determines the J1 message acceptance threshold ’h0
when SSPROC is filtering the J1 message.
0 (SONET) = SSPROC accepts a J1 message after it is
received 3 times in succession.
1 (SDH) = SSPROC accepts a J1 message after it is
received 5 times in succession.
TYPE
2
RW
This field sets the algorithm used by SSPROC to find
message alignment for the J1 byte.
0 = SONET (LF termination)
1 = SDH (1 in most significant bit of first byte)
MSG_LEN
1:0
RW
This field sets the length of the J1 message being received. ’h0
00/01 = message length is 1.
10 = message length is 16.
11 = message length is 64.
136
’h0
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 128. RXP_PRC_J1_STAT1 - Receiver trace message storage state - ’hD
Field
Bits Access
TRACE_BYTE_CNT
7:2
Function
Default
RW
This field is used to determine the byte position in the
current message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
TRACE_SWAPPED_LAST 1
RW
This field is used to determine whether J1_MSG_ACP or
J1_MSG_RCV was the last received message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
TRACE_PAGE_SEL
RW
J1_STAT1.TRACE_PAGE_SEL must be read and XORed ’h0
with addr[6] when accessing J1_MSG_ACP and
J1_MSG_RCV.
This register should not be written to in normal operation.
0
3
Field
Bits
Access
Function
Default
TRACE_ACPT_CNT 7:4
RW
This field counts the number of consistent messages
received. When it reaches 3 or 5 (J1_CTRL.THRSH),
TRACE_ACPT is set.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
TRACE_INV_CNT
RW
This field counts the number of inconsistent messages
received. When it reaches 8, TRACE_INV is set.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
3:0
Table 130. RXP_PRC_J1_STAT3 - Receiver trace status and internal state - ’hF (Part 1 of 2)
Field
TRACE_INCONSISTENT
Altera Corporation
Bits Access
7
RW
Function
Default
This field is set as soon as the last received message is ’h0
determined to be different from the current message. It is
cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
137
Specifications
Table 129. RXP_PRC_J1_STAT2 - Receiver trace internal state - ’hE
SONET/SDH Compiler User Guide
Specifications
Table 130. RXP_PRC_J1_STAT3 - Receiver trace status and internal state - ’hF (Part 2 of 2)
Field
Bits Access
Function
Default
TRACE_MISMATCH_LAST 6
RW
This field is set as soon as the last received message is ’h0
determined to be different from the expected message. It
is cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_MISMATCH_ACPT 5
RW
This field is set as soon as the accepted message is
’h0
determined to be different from the expected message. It
is cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_NEW
4
RW
This field is set as soon as the current message is
’h0
determined to be different from the previously accepted
message. It is cleared at the end of the message.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_ACPT
3
RW
This field is set for one frame after a message is accepted. ’h0
The message is not required to be new.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
TRACE_CHANGE
2
RW
This field is updated at the end of every received message, ’h0
and indicates that a new message has been accepted.
This register should not be written to in normal operation.
TRACE_INV
1
RW
This field is updated at the end of every received message, ’h0
and indicates that 8 or more inconsistent messages have
been received.
This register should not be written to in normal operation.
TRACE_MISMATCH
0
RW
This field is updated at the end of every received message, ’h0
and indicates that the accepted message is not the same
as the expected message.
This register should not be written to in normal operation.
Table 131. RXP_PRC_C2_STAT1 - Receiver path label (C2) previous value. - ’h10
Field
PREV
138
Bits
7:0
Access
RW
Function
Default
This register stores the previously received C2 byte.
’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 132. RXP_PRC_C2_STAT2 - Receiver path label (C2) internal state. - ’h11
Field
Bits
Access
Function
Default
C2_INV
6
RW
This field is set when C2_INCONS_CTR_IN reaches 4, and ’h0
is cleared when C2_CONS_CTR reaches 4.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
C2_CONS_CTR
5:3
RW
This field stores the count of consistent C2 bytes received. ’h0
A consistent byte is one that matches the previously
received value.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
C2_INCONS_CTR 2:0
RW
This field stores the count of inconsistent C2 bytes received. ’h0
An inconsistent byte is one that does not match the
previously received value.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
3
Field
ACPT
Bits
7:0
Access
RW
Function
This register stores the accepted C2 byte. An accepted
value is one that has been received consistently for 4
frames.
This register should not be written to in normal operation.
Default
’h0
Table 134. RXP_PRC_C2_CTRL - Receiver Path Label (C2) Expected Value - ’h13
Field
EXP
Altera Corporation
Bits
7:0
Access
RW
Function
Default
This register allows software to specify the expected path
8'hff
label (C2) value. This field is compared with the accepted C2
value in C2_ACPT to monitor for PUNEQ and PLM-P
defects.
139
Specifications
Table 133. RXP_PRC_C2_STAT3 - Receiver path label (C2) accepted value. - ’h12
SONET/SDH Compiler User Guide
Specifications
Table 135. RXP_PRC_RDIP_STAT1 - Receiver RDI-P accepted and previous values - ’h14
Field
Bits
RDIP_CONS_CTR
Access
Function
Default
7:4
RW
This field contains the count of consistent RDI-P codes
’h0
received.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
RDIP_INCONS_CTR 3:0
RW
This field contains the count of inconsistent RDI-P codes
’h0
received.
This register should be considered reserved for verification.
This register should not be written to in normal operation.
Table 136. RXP_PRC_RDIP_STAT2 - Receiver RDI-P internal state. - ’h15
Field
Bits
Access
Function
Default
INV
6
RW
This bit is set when the inconsistent counter reaches the
’h0
threshold. It is cleared when the consistent counter reaches
the threshold.
This register should not be written to in normal operation.
PREV
5:3
RW
This field contains the RDI-P code from the previous frame. ’h0
This register should be considered reserved for verification.
This register should not be written to in normal operation.
ACPT
2:0
RW
This field provides access to the filtered (valid) RDI-P value ’h0
from SSPROC. An RDI-P value is valid if it is received for N
frames in succession, where N is the value of the
RDIP_THRSHD field.
This register should not be written to in normal operation.
Table 137. RXP_PRC_AUTO_RDIP_CTRL - Receiver RDI-P - ’h16 (Part 1 of 2)
Field
RDIP_TYPE
140
Bits
4
Access
RW
Function
Default
This bit allows software to specify the RDI-P type monitored ’h0
by SSPROC.
Writing a 0 sets the RDI-P type to single bit RDI-P. SRDI-P
uses bit 5 of the G1 byte.
Writing a 1 sets the RDI-P type to enhanced RDI-P. ERDI-P
uses bits 5, 6, and 7 of the G1 byte.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 137. RXP_PRC_AUTO_RDIP_CTRL - Receiver RDI-P - ’h16 (Part 2 of 2)
Field
THRSHD
Bits
3:0
Access
RW
Function
Default
This field allows software to specify the number of
’h0
consecutive identical RDI-P codes (bits 5, 6, and 7 of the G1
byte) that must be observed by SSPROC before it is
accepted.
This register is shadowed.
Table 138. RXP_PRC_RESERVED2 - RESERVED - ’h17
Field
RESERVED
Bits
7:0
Access
Function
RW
Default
’h0
3
Table 139. RXP_PRC_REIP_ERR_ACCUM - Receiver REI-P count - ’h18
FIELD
Altera Corporation
Bits
31:0
Access
RTCW
Function
This register contains the REI-P error count accumulated
since the last read by software. The counter stops
(saturates) when the count reaches 32’hFFFFFFFF. The
counter counts either bit or frame errors depending on
CTRL.REIP_ERR_TYPE.
Writing to this register loads the counter with the value
written.
Reading from this register returns the current count, and
resets the counter.
This register is shadowed.
Default
’h0
141
Specifications
Field
SONET/SDH Compiler User Guide
Specifications
Table 140. RXP_PRC_B3_ERR_ACCUM - Receiver B3 error count - ’h1C
Field
FIELD
Bits
31:0
Access
RTCW
Function
Default
This register contains the B3 error count accumulated since ’h0
the last read by software. The counter stops (saturates)
when the count reaches 32’hFFFFFFFF. The counter
counts either bit or frame errors depending on
CTRL.B3_ERR_TYPE.
Writing to this register loads the counter with the value
written.
Reading from this register returns the current count, and
resets the counter.
This register is shadowed.
Table 141. RXP_PRC_RESERVED3 - RESERVED - ’h20
Field
Bits
RESERVED
255:0
Access
Function
Default
RW
’h0
Table 142. RXP_PRC_J1_MSG_EXP - Receiver J1 expected buffer - ’h40
Field
FIELD
Bits
511:0
Access
RW
Function
Default
This register contains the expected path trace message.
’h0
Table 143. RXP_PRC_J1_MSG_ACP - Receiver J1 accepted buffer - ’h80
Field
FIELD
142
Bits
511:0
Access
RW
Function
Default
This register contains the accepted path trace message.
’h0
J1_STAT1.TRACE_PAGE_SEL must be read and XORed
with bit addr[6] when accessing J1_MSG_ACP. To ensure a
clean read, read TRACE_PAGE_SEL after reading
J1_MSG_ACP. If it has changed while downloading the
J1_MSG_ACP buffer, the ACP and RCV pages have been
swapped, and the J1_MSG_ACP buffer should be
downloaded again.
This register should not be written to in normal operation.
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 144. RXP_PRC_J1_MSG_RCV - Receiver J1 received buffer - ’hC0
Field
Bits
FIELD
511:0
Access
RW
Function
Default
This register contains the most recently received path trace ’h0
message.
J1_STAT1.TRACE_PAGE_SEL must be read and XORed
with bit addr[6] when accessing J1_MSG_RCV. This buffer
is updated every frame, and may be swapped with
J1_MSG_ACP if a new message is accepted. Use
TRACE_PAGE_SEL and TRACE_BYTE_CNT to monitor
these conditions.
This register should not be written to in normal operation.
TXT_REG Memory Map
All addresses are 16-bit accesses and are shown as hex values. Note that
the access addresses for each register increment by units of 2, since the
accesses are 16-bits wide.
Specifications
Table 145. TXT_REG Memory Map
Address
Register
Description
'h0
TXT_REG_CTRL1
Transmitter transport control
'h2
TXT_REG_CTRL2
Transmitter software alignment control
'h4
TXT_REG_IS
Transmitter transport interrupt status
'h6
TXT_REG_IE
Transmitter transport interrupt enable
TXT_REG Register Description
Table 146. TXT_REG_CTRL1 - Transmitter transport control - ’h0 (Part 1 of 2)
Field
Bits
Access
Function
Default
FRAME_RST
3
RW
This bit allows software to reset frame in the SONET
transmitter.
Writing a 1 resets the frame counters in the SONET
transmitter. The reset is maintained until this bit is cleared.
’h0
FORCE_LOS
2
RW
This field allows the user to force a downstream LOS (all
zeros).
Writing a 1 forces the SONET transmitter to insert LOS.
’h0
Altera Corporation
3
143
SONET/SDH Compiler User Guide
Specifications
Table 146. TXT_REG_CTRL1 - Transmitter transport control - ’h0 (Part 2 of 2)
Field
Bits
Access
Function
Default
FORCE_AISL
1
RW
This field allows the user to force a downstream line AIS (all ’h0
ones). Changes take affect at frame boundaries.
Writing a 1 forces the SONET transmitter to insert AIS-L at
the beginning of the next transmitted frame.
SCRAM_DIS
0
RW
This bit allows software to enable/disable the SONET
transmitter's scrambling function. The generating
polynomial is1+ x6 + x7, and the sequence length is 127.
Writing a 0 enables scrambling.
Writing a 1 disables scrambling.
’h0
Table 147. TXT_REG_CTRL2 - Transmitter software alignment control - ’h2
Field
Bits Access
TOH_CAP_DONE_ROW 3:0
RW
Function
Default
This register allows software to specify the row at which the ’h0
TOH_CAP_DONE interrupt occurs. By default, the row is
zero, thus the interrupt occurs after the last Z0 byte.
Table 148. TXT_REG_IS - Transmitter transport interrupt status - ’h4
Field
TOH_CAP_DONE
Bits
0
Access
RW1C
Function
Default
This bit is set to 1 after the transmitter inserts the last TOH
byte of the row, determined by the
CTRL2.TOH_CAP_DONE_ROW register.
This interrupt can be used by software to synchronize
AIRbus reads of TOH bytes with the transmitted SONET
frame.
Note: the TOH ram is not shadowed.
’h0
Table 149. TXT_REG_IE - Transmitter transport interrupt enable - ’h6
Field
TOH_CAP_DONE
144
Bits
0
Access
RW
Function
Default
Writing a 1 enables the TOH_CAP_DONE strobe interrupt. ’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
TXT_PRC Memory Map
All addresses are 8-bit accesses and are shown as hex values. Note that the
access addresses for each register increment by units of 1, since the
accesses are 8-bits wide.
Table 150. TXT_PRC Memory Map
Address
Register
Description
’h0
TXT_PRC_J0_CTRL
Transmitter J0 control
’h1
TXT_PRC_AUTO_RDIL_CT
RL
Transmitter RDI-L control
’h2
TXT_PRC_REIL_CTRL
Transmitter control
’h3
TXT_PRC_RESERVED1
RESERVED
’h40
TXT_PRC_J0_MSG_BUF
Transmitter section trace message buffer
TXT_PRC Register Description
3
Field
Bits
Access
Function
Default
BUF_INS
1
RW
This field determines whether SSPROC writes the message ’h0
into the transmitted stream.
Writing a 1 to this bit enables trace insertion. When enabled,
it starts at the first byte of the message.
Writing a 0 to this bit disables trace insertion. For a single
byte trace, use this option and write the desired byte into the
J0 location of the transmitter TOH RAM.
MSG_LEN
0
RW
This field allows software to specify the length of the
message in the transmitter J0 trace buffer memory.
0 = message length is 16.
1 = message length is 64.
’h0
Table 152. TXT_PRC_AUTO_RDIL_CTRL - Transmitter RDI-L control - ’h1 (Part 1 of 2)
Field
AISL
Altera Corporation
Bits
3
Access
RW
Function
Default
This bit enables/disables automatic transmitter RDI-L
’h0
insertion when an AIS-L alarm is detected by SSPROC.
RDI-L is inserted by setting bits 6, 7 and 8 of the K2 byte to
3’b110.
145
Specifications
Table 151. TXT_PRC_J0_CTRL - Transmitter J0 control - ’h0
SONET/SDH Compiler User Guide
Specifications
Table 152. TXT_PRC_AUTO_RDIL_CTRL - Transmitter RDI-L control - ’h1 (Part 2 of 2)
Field
Bits
Access
Function
Default
LOF
2
RW
This bit enables/disables automatic transmitter RDI-L
’h0
insertion when an LOF alarm is detected by SSRX_DATA.
RDI-L is inserted by setting bits 6, 7 and 8 of the K2 byte to
3’b110.
LOS
1
RW
This bit enables/disables automatic transmitter RDI-L
’h0
insertion when an LOS alarm is detected by SSRX_DATA.
RDI-L is inserted by setting bits 6, 7 and 8 of the K2 byte to
3’b110.
FORCE
0
RW
This bit enables a forced RDI-L insertion. RDI-L is inserted ’h0
by setting bits 6, 7 and 8 of the K2 byte to 3’b110.
Writing a 1 to this bit forces RDI-L insertion.
Table 153. TXT_PRC_REIL_CTRL - Transmitter control - ’h2
Field
AUTO_REIL_EN
Bits
0
Access
RW
Function
Default
This bit enables/disables automatic REI-L insertion in the
’h1
transmitted stream when B2 BIP-8 errors are detected in the
receive stream. There is a buffer between the receiver and
transmitter to allow slightly different frame rates. The
received error count is added to the buffer for every received
frame. The transmitter subtracts up to min(OC*8,255) from
the buffer and inserts into the transmitted M0/M1 byte.
Writing a 1 to this bit enables automatic REI-L insertion.
Writing a 0 to this bit disables automatic REI-L insertion.
Table 154. TXT_PRC_RESERVED1 - RESERVED - ’h3
Field
Bits
RESERVED
487:0
Access
Function
RW
Default
’h0
Table 155. TXT_PRC_J0_MSG_BUF - Transmitter section trace message buffer - ’h40
Field
FIELD
146
Bits
511:0
Access
RW
Function
Default
’h0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
TXP_REG Memory Map
All addresses are 16-bit accesses and are shown as hex values. Note that
the access addresses for each register increment by units of 2, since the
accesses are 16 bits wide.
Table 156. TXP_REG Memory Map
Address
Register
Description
’h0
TXP_REG_PTR_CTRL1
Transmitter transport control
’h2
TXP_REG_PTR_CTRL2
Transmitter transport control
’h4
TXP_REG_PTR_CTRL3
Transmitter path pointer offset
’h6
TXP_REG_PATH_IS
Transmitter path interrupt status
’h8
TXP_REG_PATH_IE
Transmitter path interrupt enable
TXP_REG Register Description
3
Table 157. TXP_REG_PTR_CTRL1 - Transmitter transport control - ’h0
Bits
Access
Function
Default
APPLY_SS
1
RW
This bit allows software to enable/disable the requirement ’h0
that the ss bits of H1 be 2’b10, as recommended by the SDH
standard.
Writing a 0 disables this requirement. ss bits are set to
2’b00.
Writing a 1 enables this requirement. ss bits are set to 2’b10.
APPLY_3FRM
0
RW
This bit allows software to enable/disable implementation of ’h0
the SONET standard recommendation that pointer
increment or decrement events should be separated by
three frames.
Writing a 0 disables this recommendation. All pointer
increment/decrement operations requested are accepted.
Writing a 1 enables this recommendation. All pointer
increment/decrement operations requested within three
frames of another pointer change operation are ignored.
Altera Corporation
147
Specifications
Field
SONET/SDH Compiler User Guide
Specifications
Table 158. TXP_REG_PTR_CTRL2 - Transmitter transport control - ’h2
Field
Bits
Access
Function
Default
FORCE_AISP
2
RW
This bit allows software to enable/disable AIS-P insertion in ’h0
the transmit stream. AIS-P is inserted by writing all ones to
the H1, H2, and H3 bytes, and to all bytes of the SPE/VC.
Writing a 1 forces the SONET transmitter to insert AIS-P.
FORCE_NSTUFF
1
RWSC
This bit allows software to force a valid pointer decrement.
Writing a 1 forces an offset decrement at the next valid
opportunity, depending on APPLY_3FRM. It is a selfclearing control bit.
’h0
FORCE_PSTUFF
0
RWSC
This bit allows software to force a valid pointer increment.
Writing a 1 forces an offset increment at the next valid
opportunity, depending on APPLY_3FRM. It is a selfclearing control bit.
’h0
Table 159. TXP_REG_PTR_CTRL3 - Transmitter path pointer offset - ’h4
Field
FORCE_CONT_NDF
Bits
Access
Function
Default
RW
This bit allows software to force the NDF bits to 4'b1001 as ’h0
long as the bit is set. This bit can be used in conjunction with
a change to PTR_OFFSET.
Writing a 1 forces a NDF at each H1 byte until it is written
back to 0.
FORCE_SINGLE_NDF 10
RWSC
This bit allows software to force the NDF bits to 4'b1001 for ’h0
a single frame. This bit can be used in conjunction with a
change to PTR_OFFSET.
Writing a 1 forces a NDF at the next H1 byte. It is a selfclearing control bit.
CUR_OFFSET
RW
This register contains the current pointer offset. PSTUFF
’h0
and NSTUFF events via the AIRbus or Midbus interfaces
are reflected in this register.
It is sampled once per frame at the H1 position, and any
arbitrary changes take effect at the new offset, regardless of
NDF insertion.
It is used internally to insert POH and SPE/VC bytes at the
correct offset, and as such must always be a valid offset. If
it is set to an invalid offset, it automatically resets to zero.
If for test purposes an invalid offset is required, the transmit
TOH RAM can be used to apply an error mask that produces
the required invalid offset.
148
11
9:0
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 160. TXP_REG_PATH_IS - Transmitter path interrupt status - ’h6
Field
Bits
J1
0
Access
RW1C
Function
This bit is set to 1 after the J1 POH byte is transmitted.
This interrupt can be used by software to synchronize
AIRbus reads to POH bytes of a particular path.
Note: the POH ram is not shadowed.
Default
’h0
Table 161. TXP_REG_PATH_IE - Transmitter path interrupt enable - ’h8
Field
Bits
J1
0
Access
RW
Function
Writing a 1 enables the J1 POH done interrupt.
Default
’h0
TXP_PRC Memory Map
Table 162. TXP_PRC Memory Map
Address
Register
Description
'h0
TXP_PRC_J1_CTRL
Transmitter J1 control
'h1
TXP_PRC_AUTO_RDIP_CTRL1
Transmitter RDI-P control
'h2
TXP_PRC_AUTO_RDIP_CTRL2
Transmitter RDI-P control
'h3
TXP_PRC_AUTO_RDIP_CTRL3
Transmitter RDI-P control
'h4
TXP_PRC_AUTO_RDIP_CTRL4
Transmitter RDI-P control
'h5
TXP_PRC_RDIP_CTR
Transmitter RDI-P internal state
'h6
TXP_PRC_RDIP_HOLD
Transmitter RDI-P internal state
'h7
TXP_PRC_RX_STAT
Receiver status storage
'h8
TXP_PRC_REIP_CTRL
Transmitter REI-P control
'h9
TXP_PRC_RESERVED
RESERVED
'h40
TXP_PRC_J1_MSG_BUF
Transmitter path trace message buffer
Altera Corporation
149
3
Specifications
All addresses are 8-bit accesses and are shown as hex values. Note that the
access addresses for each register increment by units of 1, since the
accesses are 8-bits wide.
SONET/SDH Compiler User Guide
Specifications
TXP_PRC Register Description
Table 163. TXP_PRC_J1_CTRL - Transmitter J1 control - ’h0
Field
Bits
Access
Function
Default
MSG_CTR
7:2
RW
This register contains the pointer to the next byte of the trace ’h0
message to be sent.
This field should be considered reserved for verification.
This field should be written to 0 when changing the
MSG_LEN or BUF_INS.
BUF_INS
1
RW
This field determines whether the SSPROC writes the
’h0
message into the transmitted stream.
Writing a 1 to this bit enables trace insertion. When enabled,
it starts at the first byte of the message, if MSG_CTR is
cleared.
Writing a 0 to this bit disables trace insertion. For a singlebyte trace, use this option and write the desired byte into the
J0 location of the transmitter TOH RAM.
MSG_LEN
0
RW
This field allows software to specify the length of the
message in the transmitter J1 trace buffer memory.
0 = message length is 16.
1 = message length is 64.
’h0
Table 164. TXP_PRC_AUTO_RDIP_CTRL1 - Transmitter RDI-P control - ’h1
Field
Bits
Access
Function
Default
LOP_RDIP_CODE
7:5
RW
This field contains the RDI-P code for LOP-P.
3'b101
AUTO_LOP_RDIP
4
RW
This bit enables/disables RDI-P insertion when an LOP-P
alarm is detected by SSRX_DATA, and when LOP-P is
highest priority path alarm. The code inserted is stored in
LOP_RDIP_CODE.
’h0
AISP_RDIP_CODE 3:1
RW
This field contains the RDI-P code for AIS-P.
3'b101
AUTO_AISP_RDIP 0
RW
This bit enables/disables RDI-P insertion when an AIS-P
alarm is detected by SSRX_DATA, and when AIS-P is
highest priority path alarm. The code inserted is stored in
AISP_RDIP_CODE.
’h0
150
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 165. TXP_PRC_AUTO_RDIP_CTRL2 - Transmitter RDI-P control - ’h2
Field
Bits
Access
Function
Default
TIMP_RDIP_CODE
7:5
RW
This field contains the RDI-P code for TIM-P.
3’b110
AUTO_TIMP_RDIP
4
RW
This bit enables/disables RDI-P insertion when a TIM-P
alarm is detected by SSPROC, and when TIM-P is highest
priority path alarm. The code inserted is stored in
TIMP_RDIP_CODE.
’h0
UNEQP_RDIP_CODE 3:1
RW
This field contains the RDI-P code for UNEQ-P.
3'b110
AUTO_UNEQP_RDIP 0
RW
This bit enables/disables RDI-P insertion when an UNEQ-P ’h0
alarm is detected by SSPROC, and when UNEQ-P is
highest priority path alarm. The code inserted is stored in
UNEQP_RDIP_CODE.
3
Table 166. TXP_PRC_AUTO_RDIP_CTRL3 - Transmitter RDI-P control - ’h3
Bits
Access
Function
Default
LCDP_RDIP_CODE 7:5
RW
This field contains the RDI-P code for LCD-P.
AUTO_LCDP_RDIP 4
RW
This bit enables/disables RDI-P insertion when an LCD-P
’h0
alarm is detected on the lcd port, and when LCD-P is highest
priority path alarm. The code inserted is stored in
LCDP_RDIP_CODE.
3'b010
PLMP_RDIP_CODE 3:1
RW
This field contains the RDI-P code for PLM-P.
AUTO_PLMP_RDIP 0
RW
This bit enables/disables RDI-P insertion when a PLM-P
’h0
alarm is detected by SSPROC, and when PLM-P is highest
priority path alarm. The code inserted is stored in
PLMP_RDIP_CODE.
3'b010
Table 167. TXP_PRC_AUTO_RDIP_CTRL4 - Transmitter RDI-P control - ’h4 (Part 1 of 2)
Field
Bits Access
Function
Default
DEFAULT_RDIP_CODE 7:5
RW
This field contains the RDI-P code that is inserted when no ’h0
alarm is active.
RESERVED
4
RW
This bit is unused.
’h0
FORCE_RDIP_CODE
3:1
RW
This field contains the RDI-P code used when
AUTO_FORCE_RDIP is set.
’h0
Altera Corporation
151
Specifications
Field
SONET/SDH Compiler User Guide
Specifications
Table 167. TXP_PRC_AUTO_RDIP_CTRL4 - Transmitter RDI-P control - ’h4 (Part 2 of 2)
Field
Bits Access
AUTO_FORCE_RDIP
0
RW
Function
Default
This bit enables a forced RDI-P insertion. The code inserted ’h0
is stored in FORCE_RDIP_CODE.
Writing a 1 to this bit initiates a 20 frame RDI-P insertion. It
is a self clearing field.
Table 168. TXP_PRC_RDIP_CTR - Transmitter RDI-P internal state - ’h5
Field
FIELD
Bits
4:0
Access
RW
Function
Default
This field contains the 20-frame counter.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
Table 169. TXP_PRC_RDIP_HOLD - Transmitter RDI-P internal state - ’h6
Field
CUR_CODE
Bits
Access
Function
Default
5:3
RW
This field contains the current RDI-P code.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
CUR_CONDITION 2:0
RW
This field contains the current RDI-P condition.
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
Table 170. TXP_PRC_RX_STAT - Receiver status storage - ’h7 (Part 1 of 2)
Field
Bits
Access
Function
Default
RX_LCD
5
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
RX_PLM
4
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
RX_TIMP
3
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
RX_UNEQ
2
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
152
Altera Corporation
Specifications
SONET/SDH Compiler User Guide
Table 170. TXP_PRC_RX_STAT - Receiver status storage - ’h7 (Part 2 of 2)
Field
Bits
Access
Function
Default
RX_LOP
1
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
RX_AISP
0
RW
This field should be considered reserved for verification.
This register should not be written to in normal operation.
’h0
Table 171. TXP_PRC_REIP_CTRL - Transmitter REI-P control - ’h8
Field
Bits Access
Function
Default
RW
This accumulation is added to by RX (0..8), and subtracted ’h0
from by TX (0..8). If RX is slightly faster than TX, this will
act as a buffer so that no B3 errors are lost.
This register should not be written to except to clear the
contents when enabling AUTO_REIP_EN.
AUTO_REIP_EN
RW
This field allows the bits 1 through 4 of the G1 POH byte ’h0
in the transmitted frame to be derived from the receiver B3
BIP-8 error count.
When enabling this feature, clear the buffer by writing 0 to
the AUTO_REIP_ERR_ACCUM field. (i.e. write
8'b10000000 to REIP_CTRL)
0
3
Specifications
AUTO_REIP_ERR_ACCUM 7:1
Table 172. TXP_PRC_RESERVED - RESERVED - ’h9
Field
Bits
RESERVED
439:0
Access
Function
RW
Default
’h0
Table 173. TXP_PRC_J1_MSG_BUF - Transmitter path trace message buffer - ’h40
Field
FIELD
Altera Corporation
Bits
511:0
Access
RW
Function
Default
’h0
153