RapidIO Physical Layer
MegaCore Function User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Core Version:
Document Version:
Document Date:
2.0.0
2.0.0 rev.1
May 2003
Copyright
RapidIO Physical Layer MegaCore Function User Guide
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-MC_RIOPHY-1.2
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
RapidIO Physical Layer MegaCore® function.
Table 1 shows the user guide revision history.
Table 1. User Guide Revision History
Date
May 2003
v2.0.0 rev1
Description
Includes serial RapidIO configuration options, and separate
“Specifications” chapters for Serial and Parallel RapidIO.
Stratix™ GX device family support.
July 2002 v1.0.0p2 Includes corrected screen captures of the IP Toolbench.
July 2002 v1.0.0p1 First public release of this user guide
How to Find
Information
April 2002
Beta release version of this user guide
January 2002
Pre-release version of this user guide
■
■
■
■
Altera Corporation
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About this User Guide
How to Contact
Altera
RapidIO Physical Layer MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For technical support on this product, go to www.altera.com/mysupport.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
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About this User Guide
Typographic
Conventions
RapidIO Physical Layer MegaCore Function User Guide
The RapidIO Physical Layer MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
About this Core ............................................................................................................................................13
Release Information .......................................................................................................................13
Device Family Support ..................................................................................................................13
Introduction ....................................................................................................................................14
New in Version 2.0.0 ......................................................................................................................14
Features ...........................................................................................................................................14
Physical Layer 1× Serial RapidIO Features ........................................................................14
Physical Layer Parallel RapidIO Features ..........................................................................15
Interfaces & Protocols ....................................................................................................................15
RapidIO Interface ...................................................................................................................16
Atlantic Interface ....................................................................................................................16
AIRbus Interface ....................................................................................................................17
Configuration Options ..................................................................................................................17
Performance ....................................................................................................................................19
OpenCore Evaluation ............................................................................................................20
Getting Started ............................................................................................................................................21
Hardware & Software Requirements ..........................................................................................21
Design Flow ....................................................................................................................................21
Download & Install the Core ........................................................................................................21
Downloading the RapidIO Physical Layer MegaCore Function ....................................22
Installing the RapidIO Physical Layer MegaCore Function Files ...................................22
RapidIO Physical Layer MegaCore Function Walkthrough ...................................................23
Create a New Quartus II Project ..........................................................................................24
Launch the IP Toolbench ......................................................................................................25
Configuration Parameters ............................................................................................27
Device Family ......................................................................................................... 27
Baud Rate ................................................................................................................ 28
LVDS Data Rate...................................................................................................... 28
Dynamic Phase Alignment................................................................................... 28
RapidIO Port Width............................................................................................... 28
Atlantic Interface Port Width ............................................................................... 28
RapidIO Port Width Downgrade ........................................................................ 28
Altera Corporation
vii
RapidIO Physical Layer MegaCore Function User Guide
Contents
Buffer Size ............................................................................................................... 29
Receive Buffer Control .......................................................................................... 29
Promotion in Hardware........................................................................................ 29
Step 1: Select Configuration .................................................................................................30
Step 2: Set Up Simulation ......................................................................................................35
Step 3: Generate ......................................................................................................................35
Implementing the System .....................................................................................................36
Instantiating a Design File in AHDL ...........................................................................38
Simulate the Design .......................................................................................................................38
Using the Verilog HDL Demonstration Testbench ...........................................................38
Serial RapidIO Demonstration Testbench Description ............................................38
Parallel RapidIO Demonstration Testbench Description .........................................41
Using the Visual IP Software ................................................................................................45
Synthesize, Compile & Place & Route ........................................................................................45
Using Third-Party EDA Tools for Synthesis ......................................................................45
Using the Quartus II Development Tool for Compilation & Place-and-Route ............45
Set Up Licensing .............................................................................................................................46
Append the License to Your license.dat File ......................................................................47
Specify the Core’s License File in the Quartus II Software ..............................................47
Perform Post-Route Simulation ...................................................................................................48
Serial RapidIO Specifications ................................................................................................................49
Functional Description ..................................................................................................................49
Layer 1 .....................................................................................................................................49
Layer 2 .....................................................................................................................................49
Layer 3 .....................................................................................................................................50
Clock Domains ...............................................................................................................51
RapidIO Physical Sub-Layer Descriptions .................................................................................53
Layer 1 .....................................................................................................................................53
Receiver ...................................................................................................................................54
Clock & Data ...................................................................................................................54
Receiver Transceiver ......................................................................................................55
Demultiplexer & Buffer .................................................................................................55
Lane Synchronization State Machine ..........................................................................55
Packet/Symbol Delineation & Idle Character Extraction ........................................55
CRC Check ......................................................................................................................56
Atlantic Interface/Packet Data Packing .....................................................................56
S0 & S1 Symbol Interface ..............................................................................................56
Transmitter ..............................................................................................................................56
Clock and Data ...............................................................................................................56
Transmitter Transceiver ................................................................................................56
Multiplexer & Buffer .....................................................................................................57
Initialization State Machine ..........................................................................................57
Packet/Symbol Assembling & Idle Character Insertion ..........................................57
Idle Sequence Generation .............................................................................................57
CRC Generation & Insertion ........................................................................................58
viii
Altera Corporation
Contents
RapidIO Physical Layer MegaCore Function User Guide
Atlantic Interface/Packet Data Packing .....................................................................58
S0 & S1 Symbol Interface ..............................................................................................58
Layer 2 .............................................................................................................................................58
Receiver ...................................................................................................................................59
Clock and Data ...............................................................................................................59
Symbol FIFO Buffer .......................................................................................................59
Symbol Control ..............................................................................................................60
Packet Control ................................................................................................................60
Error Recovery Control .................................................................................................60
Transmitter ..............................................................................................................................60
Clock and Data ...............................................................................................................60
Symbol FIFO Buffer .......................................................................................................61
Symbol Control ..............................................................................................................61
Packet Control ................................................................................................................61
Error Recovery Control .................................................................................................61
Layer 3 .............................................................................................................................................61
Receiver ...................................................................................................................................62
Clock & Data ...................................................................................................................62
Scheduler .........................................................................................................................62
Free Queue ......................................................................................................................63
Transmit Queue ..............................................................................................................63
Receiver Buffers ..............................................................................................................63
Transmitter ..............................................................................................................................63
Clock & Data ...................................................................................................................64
Manager ...........................................................................................................................64
Scheduler .........................................................................................................................64
Retransmit Queue ..........................................................................................................65
Free Queue ......................................................................................................................65
Priority Queues ..............................................................................................................65
Promotion Control (optional) .......................................................................................65
Transmitter Buffers ........................................................................................................66
Signals ..............................................................................................................................................66
Software Interface ..........................................................................................................................68
Registers ..................................................................................................................................68
Master Register Description .........................................................................................69
Parallel RapidIO Specifications ............................................................................................................75
Functional Description ..................................................................................................................75
Layer 1 .....................................................................................................................................75
Layer 2 .....................................................................................................................................75
Layer 3 .....................................................................................................................................75
Clock Domains .......................................................................................................................77
Dynamic Phase Alignment ...........................................................................................................78
Features ...................................................................................................................................79
Functional Description ..........................................................................................................79
ALTLVDS_Receiver Megafunction .............................................................................80
Altera Corporation
ix
RapidIO Physical Layer MegaCore Function User Guide
Contents
Byte Aligner ....................................................................................................................80
RapidIO Training Pattern ..................................................................................... 81
8:4 Deserializer ...............................................................................................................81
RapidIO Physical Sub-Layer Descriptions .................................................................................82
Layer 1 .....................................................................................................................................82
Receiver ...................................................................................................................................83
Clock & Data ...................................................................................................................83
High-Speed Interface & Deserializer ..........................................................................83
Time Division Multiplexing ................................................................................. 86
I/O Port Training ...........................................................................................................86
Packet/Symbol Delineation .........................................................................................87
Parity Check ....................................................................................................................87
Idle Symbol Extraction ..................................................................................................88
CRC Check ......................................................................................................................88
Transmitter ..............................................................................................................................88
Clock and Data ...............................................................................................................88
High-Speed Interface and Serializer ...........................................................................88
I/O Port Training ...........................................................................................................91
Packet/Control Symbol Assembling ..........................................................................91
Parity Generation ...........................................................................................................92
Idle Symbol Insertion ....................................................................................................92
CRC Generation .............................................................................................................92
Layer 2 .............................................................................................................................................92
Receiver ...................................................................................................................................93
Clock and Data ...............................................................................................................93
Symbol FIFO Buffer .......................................................................................................93
Symbol Control ..............................................................................................................94
Packet Control ................................................................................................................94
Error Recovery Control .................................................................................................94
Transmitter ..............................................................................................................................94
Clock and Data ...............................................................................................................94
Symbol FIFO Buffer .......................................................................................................95
Symbol Control ..............................................................................................................95
Packet Control ................................................................................................................95
Error Recovery Control .................................................................................................95
Layer 3 .............................................................................................................................................96
Clock & Data ...................................................................................................................96
Scheduler .........................................................................................................................96
Free Queue ......................................................................................................................97
Transmit Queue ..............................................................................................................97
Receiver Buffers ..............................................................................................................97
256 to 128 Atlantic Adapter ..........................................................................................97
Transmitter ..............................................................................................................................98
Clock & Data ...................................................................................................................98
Manager ...........................................................................................................................98
Scheduler .........................................................................................................................99
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Altera Corporation
Contents
RapidIO Physical Layer MegaCore Function User Guide
Retransmit Queue ..........................................................................................................99
Free Queue ......................................................................................................................99
Priority Queues ..............................................................................................................99
Promotion Control (optional) .....................................................................................100
Transmitter Buffers ......................................................................................................100
Signals ............................................................................................................................................100
Software Interface ........................................................................................................................103
Registers ................................................................................................................................105
Transmitter Register Description ..............................................................................105
Receiver Register Description ....................................................................................106
Master Register Description .......................................................................................106
Appendix–Pin Constraints & Board Design .....................................................................................111
Pin Constraints .............................................................................................................................111
Board Design Configuration ......................................................................................................111
Appendix–Static Alignment & AC Timing .......................................................................................113
Static Alignment ...........................................................................................................................113
Altera Solutions ....................................................................................................................114
AC Timing Analysis ....................................................................................................................114
APEX II Timing ....................................................................................................................115
Stratix Timing .......................................................................................................................117
Altera Corporation
xi
About this Core
1
Table 4 provides information about this release of the RapidIO Physical
Layer MegaCore function.
Table 4. RapidIO Physical Layer Release Information
Item
Description
Version
Device Family
Support
2.0.0
Release Date
May 2003
Ordering Code
IP-RIOPHY
Product ID
0095
Vendor ID
6AF8
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
Table 5 shows the level of support offered by the RapidIO Physical Layer
MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
Altera Corporation
Support
Stratix GX
Preliminary
Stratix
Full
APEX™ II
Full
Other device families
No support
13
About this Core
Release
Information
RapidIO Physical Layer MegaCore Function User Guide
About this Core
Introduction
The RapidIO™ interconnect—an open standard developed by the RapidIO
Trade Association—is a high-performance packet-switched interconnect
technology designed to pass data and control information between
microprocessors, digital signal processors (DSPs), communications and
network processors, system memories, and peripheral devices. Its small
silicon footprint makes it ideal for complex programmable logic devices
(CPLDs).
New in Version
2.0.0
■
Features
This section lists the serial and parallel RapidIO features, including any
updates required by revision 1.2 of the RapidIOTM Interconnect Specification.
■
1× serial RapidIO support from 500 megabits per second (Mbps) to
3.125 gigabits per second (Gbps)
Stratix GX device family support:
–
Including integrated dynamic phase alignment (DPA) hardware
module
–
8-bit parallel LVDS performance up to 1 Gbps
–
Optimizations for improved fMAX
Physical Layer 1× Serial RapidIO Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
14
Clock and data recovery (CDR)
8B/10B encoding and decoding
Point-to-point, serial, packet-based interconnect
One lane (1×) serial differential signaling at nominal baud rates from
500 Mbps to 3.125 Gbps (decoded data rates from 400 Mbps to
2.5 Gbps)
Common interface for serial or parallel RapidIO to upper layers
(Logical and Transport)
Packet buffering (optional), flow control, error detection, packet
assembly and delineation
–
New encoding scheme for five-bit buf_status
–
Configurable buffers up to 32 Kbytes
24-bit control symbols with ability to carry two functions with 5-bit
CRC error protection
Capability of holding up to 31 unacknowledged packets with 5-bit
ackID (8 Kbyte or larger transmit buffer required)
Maximum 276 bytes packet length with one CRC (≤ 80 bytes) or two
CRCs (> 80 bytes)
User-defined order of message retrieval
Four packet transmission priorities
Port initialization
Bit synchronization and code-group boundary alignment
Pseudo-random idle sequence generation
Flow control
–
Receiver-controlled flow control
Error detection and recovery
Altera Corporation
About this Core
RapidIO Physical Layer MegaCore Function User Guide
1
About this Core
■
■
■
–
Idle sequence error
–
Control symbol error
–
Packet error
Time-out waiting for an acknowledgement control symbol
32-bit Atlantic interface
Fixed start of packet (SOP) alignment
Physical Layer Parallel RapidIO Features
■
■
■
■
■
■
■
■
■
Point-to-point, parallel, packet-based interconnect
Parallel True-LVDS™ high-speed interface ports
–
8 bits at up to 1 Gbps port data rate (500-MHz double data rate
(DDR) clock) for a throughput rate of up to 8 Gbps in each
direction
–
16 bits at up to 750 Mbps (375-MHz DDR clock) for a throughput
rate of up to 12 Gbps in each direction
Common interface for serial or parallel RapidIO to upper layers
(Logical and Transport)
Packet buffering (optional), flow control, error detection, packet
assembly and delineation
–
New encoding scheme for four-bit buf_status
–
Configurable buffers up to 16 Kbytes
Input/output port training for byte alignment
–
Unsolicited training is treated as a corrupt symbol
–
Both input and output port training state machines with one
added state transition
Fixed start of packet (SOP) alignment
User-defined order of message retrieval
Supports port width downgrade (from 16 to 8 bits)
Configurable Atlantic width for 32, 64, or 128 bits
The RapidIO Physical Layer MegaCore function is compliant with all
applicable standards, including:
■
■
■
f
Interfaces &
Protocols
Altera Corporation
RapidIO Trade Association, RapidIO™ Interconnect Specification,
Revision 1.2, June 2002.
–
Part IV: Physical Layer 8/16 LP-LVDS Specification
–
Part VI: Physical Layer 1×/4× LP Serial Specification.
Altera Corporation, Atlantic Interface Specification.
Altera Corporation, AIRbus Interface Specification.
More detailed information on the RapidIO interface is available from the
RapidIO Trade Association’s web site at www.rapidio.org.
Three interfaces support the RapidIO core: the RapidIO interface, the
Atlantic interface, and the access to internal registers (AIRbus) interface.
15
RapidIO Physical Layer MegaCore Function User Guide
About this Core
RapidIO Interface
RapidIO is a packet-switched interconnect protocol defined by the
RapidIO Trade Association. The protocol is divided into a three-layer
hierarchy: physical layer, transport layer, and logical layer.
The RapidIO Physical Layer MegaCore function implements only the
physical layer, which is further divided into three sub-layers: Layer 1,
Layer 2, and Layer 3.
Table 6 shows the different layers and sub-layers, as well as their
respective functions.
Table 6. RapidIO Layers
RapidIO Layer
OSI Layer
Description
Logical
Transport and End point operation protocols
upper layers
Transport
Network layer Point to point packet delivery addressing
scheme
Physical Layer 3 Physical and Buffering
Layer 2 Data link layer Flow control
Layer 1
f
Electrical (True-LVDS) interface, CDR,
differential AC coupling, error detection,
packet assembling and delineation
More detailed information on the RapidIO interface is available from the
RapidIO Trade Association’s web site at www.rapidio.org.
Atlantic Interface
The Atlantic interface, an Altera proprietary protocol, is the user interface.
It also connects the different sub-layers of the RapidIO core. For parallel
configurations, the width of this interface can be configured for 32, 64, or
128 bits. For 1× serial configurations the Atlantic interface is always
32 bits.
The Atlantic interface is a full-duplex synchronous protocol. The transmit
Atlantic interface supports 32-, 64-, or 128-bit packet data transfers from
the Layer 3 to the Layer 1 sub-layers. It works as a slave-source interface.
The receive Atlantic interface supports 32-, 64-, or 256-bit packet data
transfers from the Layer 1 to the Layer 3 sub-layers. It works as a slavesink interface.
16
Altera Corporation
About this Core
RapidIO Physical Layer MegaCore Function User Guide
The Layer 2 monitors packet data flow between the Layer 1 and the
Layer 3 to provide flow control and generate the appropriate control
symbols.
AIRbus Interface
The AIRbus interface, in Layer 2, provides access to internal registers
using a simple synchronous internal processor bus protocol. This consists
of separate read data (rdata[31:0]) and write data (wdata[31:0])
buses, a data transfer acknowledge (dtack) signal, and a block-select
(sel) signal. An address (addr[16:2]) bus and read (read) signal
indicate the location and type of access within the block. The rdata buses
and dtack signals can be merged from multiple blocks using a simple OR
function. The dtack signal is sustained until the sel signal is removed
(four-way handshaking), meaning the AIRbus can cross clock domain
boundaries. All registers are 32-bits wide.
1
f
Configuration
Options
Although the AIRbus interface specification lists a clock
(clk) and an interrupt request (irq) as part of its signals,
the RapidIO core does not have an AIRbus-specific clock, or
an irq signal.
More detailed information on the Atlantic and AIRbus interfaces is
available from the Altera web site at www.altera.com.
The RapidIO Physical Layer MegaCore function is highly configurable.
Each configuration is defined by its parameters, and generated via the IP
Toolbench.
The IP Toolbench is a toolbar from which you can quickly and easily view
documentation, specify core parameters, set up third-party tools, and
generate all files necessary for integrating the parameterized core into
your design. You can launch the IP Toolbench from within the
Quartus® II software.
f
For detailed instructions on generating a custom RapidIO core, refer to the
“Getting Started” chapter.
Tables 7 and 8 show the configuration options available to generate a
serial or a parallel mode RapidIO core, respectively. Some of the available
configuration parameters are interdependent; for example, the port width
downgrade parameter applies only to the 16-bit RapidIO port width.
Altera Corporation
17
1
About this Core
If the Layer 3 sub-layer is implemented (BUFRSIZE > 0), the Layer 3 to
user interface can be configured for 32, 64, or 128 bits. If the Layer 3 is not
implemented (BUFRSIZE = 0), the Layer 2 to user interface can be
configured for 32, 64, or 256 bits.
RapidIO Physical Layer MegaCore Function User Guide
1
About this Core
Tables 7 and 8 do not capture all of the parameter
interdependencies. Altera recommends that you run the
IP Toolbench to select your parameters..
Table 7. Serial RapidIO Configuration Options
Options
Parameters
Choices
Device family
DEVICE
Stratix GX
Baud rate
RATE
500 Mbps to 3.125 Gbps
Buffer size
BUFRSIZE
0, 16 or 32 Kbytes
Receive buffer control (1)
RXBFCTL
Yes/ No
Promotion in hardware (2)
PROMO
Yes/ No
Notes from Table 7:
(1)
(2)
If Yes is chosen, the user has control; if No is chosen, the block operates on a FIFO
basis.
The promotion in hardware parameter is not available in this release (v2.0.0).
Table 8. Parallel RapidIO Configuration Options
Options
Parameters
Choices
Device Family
DEVICE
APEX II, Stratix, or
Stratix GX
Dynamic phase alignment
DPA
Yes/ No
LVDS data rate (1)
SPEED
350 Mbps to 1 Gbps
RapidIO port width
PORT
8 or 16 bits
Atlantic interface port width (2)
ADAT
32, 64, or 128 bits
RapidIO port width downgrade (3) DGRADE
Yes/ No
Buffer size
BUFRSIZE
0, 4, 8, or 16 Kbytes
Receive buffer control (4)
RXBFCTL
Yes/ No
Promotion in hardware (5)
PROMO
Yes/ No
Notes from Table 8:
(1)
(2)
(3)
(4)
(5)
f
18
Stratix GX and DPA are required for performance above 840 Mbps.
Not all combinations of options are available because of clock frequency and pin
constraints on FPGAs.
Choosing No can significantly reduce the number of LEs. Only applicable for the 16bit RapidIO port width.
If Yes is chosen, the user has control; if No is chosen, the block operates on a FIFO
basis.
The promotion in hardware parameter is not available in this release (v2.0.0).
Refer to the “Parallel RapidIO Specifications” chapter of this user guide
for further details regarding these parameters.
Altera Corporation
About this Core
RapidIO Physical Layer MegaCore Function User Guide
Performance
Table 9. RapidIO Utilization & Performance (Part 1 of 2)
Parameters
Stratix
LEs
Stratix GX
Memory
M512
M4K M-RAM
fMAX
(MHz)
LEs
Memory
M512
M4K M-RAM
fMAX
(MHz)
Serial
–
–
–
–
6,295
5
161
0
115
PORT=8,
8,887
SPEED=840/1000(1),
ADAT=64,
BUFRSIZE=16,
RXBFCTL=Yes
2
77
0
125
9,425
2
77
0
131
PORT=8,
6,486
SPEED=840/1000(1),
ADAT=64,
BUFRSIZE=0
2
0
0
137
6,956
2
0
0
127
PORT=8, SPEED=500,
ADAT=32,
BUFRSIZE=16,
RXBFCTL=Yes
5,774
2
80
o
131
6,252
2
80
0
132
PORT=8, SPEED=500,
ADAT=32,
BUFRSIZE=0
3,883
2
0
0
128
4,388
2
0
0
139
PORT=16,
DGRADE=Yes,
SPEED=750,
ADAT=128,
BUFRSIZE=16,
RXBFCTL=Yes
18,995
4
80
0
113
19,975
4
80
0
127
PORT=16,
DGRADE=Yes,
SPEED=750,
ADAT=128,
BUFRSIZE=0
16,118
4
80
0
125
16,961
4
8
0
126
RATE=3.125,
BFRSIZE=32,
RXBFCTL=Yes
–
Parallel
Altera Corporation
19
1
About this Core
Table 9 lists the resources and performance of some RapidIO
MegaCore function configurations. These results were obtained using the
Quartus® II software version 2.2, for Stratix EP1S40-C5 and Stratix GX
EP1SGX40-C5 devices.
RapidIO Physical Layer MegaCore Function User Guide
About this Core
Table 9. RapidIO Utilization & Performance (Part 2 of 2)
Parameters
Stratix
LEs
Stratix GX
Memory
M512
M4K M-RAM
fMAX
(MHz)
LEs
Memory
M512
M4K M-RAM
fMAX
(MHz)
PORT=16,
DGRADE=No,
SPEED=750,
ADAT=128,
BUFRSIZE=16,
RXBFCTL=Yes
17,888
4
80
0
123
19,281
4
80
0
128
PORT=16,
DGRADE=No,
SPEED=750,
ADAT=128,
BUFRSIZE=0
17,983
4
8
0
124
16,197
4
8
0
120
Notes from Table 9:
(1)
840 applies to Stratix devices; 1000 applies to Stratix GX devices.
OpenCore Evaluation
The OpenCore® feature lets you test-drive Altera MegaCore functions for
free using the Quartus II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
20
Altera Corporation
Getting Started
Hardware &
Software
Requirements
The instructions in this section require the following hardware and
software:
■
■
Design Flow
Download &
Install the Core
Altera Corporation
The RapidIO Physical Layer MegaCore function design flow involves the
following steps:
1.
Obtain and install the RapidIO MegaCore function.
2.
Create a custom configuration of the RapidIO MegaCore function
using the IP Toolbench.
3.
Implement the rest of your system using VHDL, Verilog HDL, or
schematic entry.
4.
Use the IP Toolbench-generated simulation models to confirm your
custom core’s operation.
5.
Use the RapidIO encrypted netlists to perform static timing analysis
of your customized core in the Quartus II software.
6.
Compile your design and perform place-and-route.
7.
License the RapidIO MegaCore function.
8.
Perform post-route simulation (optional).
9.
Configure or program Altera devices with the design.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC or workstation. The
following instructions describe this process.
21
2
Getting Started
■
A PC running the Windows 98/NT/2000/XP operating system; or a
SUN workstation running the Solaris operating system
Quartus II development tool, version 2.2 service pack 1 (SP2) or
higher
Model Technology™ ModelSim®-Altera simulation software, version
5.6a or higher; or Innoveda Visual IP RTL simulation software,
version 4.3 or higher
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Downloading the RapidIO Physical Layer MegaCore Function
You can download MegaCore functions from Altera’s web site at
www.altera.com. Follow the instructions below to obtain the RapidIO
MegaCore function via the Internet. If you do not have Internet access,
you can obtain the RapidIO MegaCore function from your local Altera
representative.
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Type RapidIO in the Keyword Search box.
3.
Click Go.
4.
Click the link for the Altera RapidIO MegaCore function in the
search results table. The product description web page displays.
5.
Click the Download Free Evaluation OpenCore graphic on the top
right of the product description web page.
6.
Follow the online instructions to download the core and save it.
Installing the RapidIO Physical Layer MegaCore Function Files
For Windows, perform the following steps:
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The RapidIO MegaCore function Installation dialog box
appears. Follow the on-line instructions to finish installation.
1
You may be prompted to remove older versions of the
RapidIO MegaCore function that exist on your system.
For Solaris systems, perform the following steps:
22
1.
Download the core, see “Downloading the RapidIO Physical Layer
MegaCore Function” on page 22.
2.
Decompress/untar the package, using the following commands:
gunzip xxx.tar.gz; tar xvf xxx.tar
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
3.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically <path>/riophyv2.0.0/lib) as a user library in the Quartus II software to access the
core in the MegaWizard® Plug-In Manager. Search for “User
Libraries” in Quartus II Help for instructions on how to add these
libraries.
Figure 1 shows the directory structure for the RapidIO MegaCore
function.
2
Figure 1. RapidIO MegaCore Function Directory Structure
Getting Started
<path>/riophy-v2.0.0
The default path is c:/MegaCore
doc
Contains the core documentation.
lib
Contains the core files.
RapidIO
Physical Layer
MegaCore
Function
Walkthrough
Altera Corporation
This walkthrough explains how to create a RapidIO MegaCore function
using the Altera IP Toolbench within the Quartus II software. As you go
through the IP Toolbench, each page is described in detail. When you are
finished generating a RapidIO core, you can incorporate it into your
overall project.
You can use Altera’s OpenCore evaluation feature to compile and
simulate the MegaCore functions, and to complete static timing analysis,
allowing you to evaluate the POS-PHY Level 4 MegaCore function before
deciding to purchase a license. However, you must purchase a license
before you can generate programming files or EDIF, VHDL, or
Verilog HDL gate-level netlist files for port place-and-route timing
simulation in third-party EDA tools.
23
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
This walkthrough consists of the following steps:
■
■
■
■
■
“Create a New Quartus II Project” on page 24
“Launch the IP Toolbench” on page 25
“Step 1: Select Configuration” on page 30
“Step 2: Set Up Simulation” on page 35
“Step 3: Generate” on page 35
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You must also specify the RapidIO MegaCore function user library. To
create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
1
Stratix GX configurations require version 2.2 SPI or higher.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
1
Steps 7 to 10 only apply to Solaris systems.
7.
Click User Library Pathnames.
8.
Type <path>\riophy-v.2.0.0\lib\ into the Library name box,
where <path> is the directory in which you installed the RapidIO
MegaCore function. The default installation directory is
c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
24
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the IP Toolbench
To launch the IP Toolbench from within the Quartus II software, perform
the following steps:
Choose MegaWizard Plug-In Manager (Tools menu).
2.
Select Create a new custom megafunction variation (default).
3.
Click Next.
4.
Expand the Interfaces folder under Installed Plug-Ins by clicking
the + next to the name.
5.
Expand the RapidIO folder under Interfaces.
6.
Click riophy v-2.0.0.
7.
Choose the output file type for your design; the IP Toolbench
supports VHDL, and Verilog HDL. This walkthrough uses
Verilog HDL, however, you can use either language.
1
8.
For Altera hardware description language (AHDL)
instructions, refer to “Instantiating a Design File in AHDL”
on page 38.
Type the name of the output file. Figure 2 on page 26 shows the page
after you have made these settings.
1
Altera Corporation
2
Getting Started
1.
The screen captures shown in this user guide are representative
examples of the IP Toolbench. The wizard windows displayed in
your project may differ from these examples.
25
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Figure 2. MegaWizard Plug-In Manager
9.
26
Click Next. The IP Toolbench for RapidIO MegaCore function
launches. See Figure 3 on page 27.
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Figure 3. IP Toolbench
2
Getting Started
You are now ready to configure your RapidIO core.
Configuration Parameters
This subsection describe the optional parameters available to configure a
RapidIO Physical Layer MegaCore function.
Device Family
The RapidIO MegaCore function is targeted for APEX II, Stratix, or
Stratix GX devices.
The Stratix GX device family with its clock and data recovery
input/outputs is the only family that meets the serial RapidIO
specifications. However, its faster port speeds (up to 1 Gbps), and its
dynamic phase alignment features also make it ideal for the parallel
RapidIO core.
The APEX II and Stratix device families with their True-LVDS buffers
meet the high data rate and low power consumption requirements of the
RapidIO standard by using a low-voltage differential signal capable of
travelling at rates up to 1 Gbps. Also, the APEX II and Stratix devices offer
a high-speed serial interface (HSSI) combined with
serialization/deserialization (SERDES) capability and frequency
multiplication all in one circuit.
Altera Corporation
27
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Baud Rate
The baud rate is the external device’s serial data rate.
The serial RapidIO specification specifies baud rates of 500 Mbps to
3.125 Gbps. Table 14 on page 53 shows the relationship between baud
rates and internal clock rates.
LVDS Data Rate
The LVDS data rate parameter offers True-LVDS data rates of up to
1 Gbps for 8-bit port widths, and up to 750 Mbps for 16-bit port widths.
Data is clocked on both rising and falling edges, for throughput rates of
up to 8 and 12 Gbps in each direction, respectively.
The throughput rate depends on the LVDS data rate and PORT
parameters. See Table 30 on page 78 for further details.
Dynamic Phase Alignment
RapidIO specifications require DPA at 750 Mbps and above.
RapidIO Port Width
The RapidIO core supports both the 8- and 16-bit parallel True-LVDS
ports specified by the RapidIO standard.
Atlantic Interface Port Width
The Atlantic interface packet data path can be configured for 32, 64, or 128
bits. See “Atlantic Interface” on page 16 for further details.
1
For serial RapidIO, the Atlantic port width is 32 bits.
RapidIO Port Width Downgrade
The RapidIO specification allows for an 8-bit device to be connected to a
16-bit device. The system uses the training pattern to determine the width
of the connected devices. If the training pattern is found only on the upper
half of the 16-bit device, the system assumes that it is connected to an 8-bit
device and downgrades its output port to operate as an 8-bit device,
treating its lower half as a duplicate of the upper half.
The RapidIO port width downgrade parameter gives the user the option
to implement this feature if required, or save logic elements (LEs) by
omitting it.
28
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Buffer Size
The buffer size parameter allows users to select their required buffer size.
■
■
Serial: 0, 16, or 32 Kbytes
Parallel: 0, 4, 8, or 16 Kbytes
Buffer size 0 means that the Layer 3 sublayer is omitted, thus no buffer
management is provided by the RapidIO core. Users must implement
their own buffer management.
If the Layer 3 sublayer is omitted (Buffer size 0), the Atlantic
interface is a master-source and master-sink interface. If the
Layer 3 sublayer is included, the Atlantic interface is a slavesource and slave-sink interface.
Receive Buffer Control
If the receive buffer control parameter is chosen (Yes), the user decides
which packet to retrieve by selecting the appropriate address. If this
parameter is not chosen (No), the receiver buffer operates on a FIFO basis.
Promotion in Hardware
Choosing Yes for the PROMO parameter enables the priority of response
packets to be elevated when a deadlock situation occurs. If No is chosen,
the system waits until the priority queue is cleared before normal
operation can continue.
Promotion is done in hardware by implementing a promotion control
block within the Layer 3 transmitter, see “Promotion Control (optional)”
on page 100 for more details.
1
Altera Corporation
The promotion in hardware parameter is not available in
this release (v2.0.0).
29
2
Getting Started
1
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Step 1: Select Configuration
Since the RapidIO core is highly configurable, a vast number of
configurations are possible. To reduce package sizes and download time,
this version of the IP Toolbench offers two possible methods of obtaining
the configuration(s) best suited to your design.
■
■
Select an installed configuration
–
Installed configurations are pre-packaged and installed with the
IP Toolbench
Request a custom configuration
–
Custom configurations are available by entering a MySupport
request (several days may be required to process a request)
This section describes how to select an installed configuration, or
customize one to suit your design. To select a configuration, perform the
following steps:
1.
Click the Step 1: Select Configuration button in the IP Toolbench.
2.
A window opens showing installed configurations. From the left
window pane, select the configuration that best meets your
requirements. A brief list of this configuration’s parameters appears
in the right pane. See Figure 4.
Figure 4. Installed Configurations
30
3.
Click the View/Configure button.
4.
A parameterization window opens. See Figure 5 on page 31.
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Figure 5. Parameters
2
Getting Started
Altera Corporation
5.
Choose your required mode. This walkthrough uses the serial mode.
6.
Verify that all parameters meet your requirements. Modify all
parameters as required. See Figure 6 on page 32.
31
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Figure 6. Serial Parameters
32
7.
When you are satisfied with your selection, click Finish.
8.
If you have selected an installed configuration (see Figure 4 on
page 30)—and have not modified any parameters, you may proceed
to “Step 2: Set Up Simulation” on page 35.
9.
If you customized your own configuration, the next page that opens
is a Custom Configuration Request dialog box showing a list (text
format) of the parameters you chose for your customized
configuration. See Figure 7 on page 33. Select and copy all of this
text.
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Figure 7. Custom Configuration Request
2
Getting Started
10. Click Ok.
11. Point your web browser to Altera’s technical on-line support system,
mySupport, at:www.altera.com/mysupport/
1
If this is your first time using this system, you must register
to obtain a login and password.
12. Log on, and click Create a Service Request.
13. Click Product Related Request.
14. Enter your project information, complete all fields as appropriate.
See Figure 8 on page 34.
15. Select Intellectual Property in the Category list.
16. Select Communications from the Megafunction Category list.
17. Select RapidIO Physical Layer from the Megafunction Product list.
Altera Corporation
33
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
18. Paste the configuration parameters text—generated with the IP
Toolbench—into the Description field.
Figure 8. MySupport Product Related Request
19. Click Submit Product Related Request.
1
Altera e-mails your custom configuration to the address you
provided for your mySupport account. Requests take up to three
business days to process.
20. Click the × in the top corner of IP Toolbench to close the application,
or continue selecting configurations. Do not click Step 3: Generate.
34
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Step 2: Set Up Simulation
Now that you have chosen your RapidIO configuration(s), you are ready
to set up the simulation outputs for your system.
1.
Click the Step 2: Set Up Simulation button in the IP Toolbench. (See
Figure 3 on page 27.)
2.
Turn on Generate Simulation Model. See Figure 9.
3.
Select the simulator of your choice.
2
Getting Started
Figure 9. Set Up Simulation
4.
Click Finish.
Step 3: Generate
Now that you have set up the outputs for your system, you are ready to
generate your system.
1.
Click Step 3: Generate in the IP Toolbench to begin generation. (See
Figure 3 on page 27.) The IP Toolbench performs the actions you
specified, and generates any resulting output files. See Figure 10 on
page 36.
1
Altera Corporation
If you generate files without parameterizing the core, the IP
Toolbench creates a default core.
35
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Figure 10. Generate
2.
Click Exit IP Toolbench when you are finished.
Implementing the System
Once you have generated your custom RapidIO core, you are ready to
implement it. You can use the files generated by the IP Toolbench, and use
the Quartus II software or other electronic design automation (EDA) tools
to create your design. Figure 11 on page 37 shows an example directory
structure.
1
36
<configuration> is a unique code (aot###_<configuration>
#_riophy) assigned to the specific configuration requested
through the IP Toolbench.
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Figure 11. RapidIO MegaCore Function Quartus II Directory Structure
<working directory>
Directory name selected by user in project wizard
db
Quartus II software-generated directory.
<output file name>.v (or .vhd)
<output file name>.bsf
<output file name>.cmp
<output file name>.inc
<output file name>.log
IP Toolbench-generated files.
aot####_<configuration>_riophy_tx_gxb.v (or .vhd)
aot####_<configuration>_riophy_rx_gxb.v (or .vhd)
aot####_<configuration>_riophy_txpll.v (or .vhd)
aot####_<configuration>_riophy_rxpll.v (or .vhd)
Clear-text wrappers for serial configurations (1)
aot####_<configuration>_riophy.e.vqm
Encrypted vqm Verilog HDL netlist for Quartus II development tool
<output file name>.esf
Entitiy settings file for Quartus II development tool
2
Getting Started
<output file name>_sim
Contains the simulation models.
riophy-v2.0.0
Configuration based on parameter choices.
sim_lib
aot####_<configuration>_riophy
test
Contains the scripts to run the simulation models
& demonstration testbench
run_modelsim_verilog
run_modelsim_vhdl
run_modelsim_visual_ip
tb.v
riophy_tx_gxb.v (or .vhd)
riophy_rx_gxb.v (or .vhd)
riophy_txpll.v (or .vhd)
riophy_rxpll.v (or .vhd)
riophy.v (or .vhd)
demo_hookup.iv
demo_util.iv
hutil.iv
<simulator db> (2)
Simulator database
Notes:
(1)
(2)
Altera Corporation
Parallel configurations would have three wrapper files, with the following suffixes:
_altlvds_tx.v (or .vhd), _altlvds_rx.v (or .vhd), and _altpll_rx.v (or .vhd).
<simulator db> must be the same as the simulator chosen during parameterization.
37
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
Instantiating a Design File in AHDL
To instantiate a lower-level Verilog HDL design file in an AHDL file,
perform the following steps:
Simulate the
Design
1.
When the Verilog design file is open in Quartus II, create an AHDL
include file by choosing Create AHDL Include Files for Entities in
Current File (Tools menu).
2.
Add an Include statement to your AHDL file. The Include statement
allows you to import text from the AHDL include file into the
current file.
3.
Instantiate the Verilog design in the AHDL file as described in the
“Instance Declaration” section of the Quartus II Help.
4.
In the logic section of the AHDL design, connect the ports of the
instance to the rest of your design.
Altera provides models you can use for functional verification of the
RapidIO interface within your design. A Verilog HDL demonstration
testbench, including scripts to run it, is also provided. This demonstration
testbench, used with the ModelSim-Altera simulator, demonstrates how
to instantiate a model in a design. To find the simulation models for your
selected configuration, refer to Figure 11 on page 37.
Using the Verilog HDL Demonstration Testbench
The demonstration testbenches include some simple stimulus to control
the user interfaces of the RapidIO interface. Each RapidIO interface
configuration includes scripts to compile and run the demonstration
testbenches using a variety of simulators and models.
Serial RapidIO Demonstration Testbench Description
The demonstration testbench provided with the serial RapidIO core tests
the following functions:
■
■
■
■
38
Port initialization process
Transmission, reception, and acknowledgment of packets with 8 to
256 bytes of data payload
Writing to and reading from the Atlantic slave interfaces
Reading from the software interface registers
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
The testbench consists of two RapidIO cores interconnected through their
high-speed serial interfaces. (Each core’s td output is connected to the
other core’s rd input.) The tb module provides clocking and reset control
along with tasks to write to and read from the core’s Atlantic interfaces,
and a task to read from the command and status register (CSR) set.
Figure 12. Serial RapidIO Demonstration Testbench
Atlantic
Interface
Note (1)
78.125 MHz
78.125 MHz
RapidIO
Clock
Clock
1x LP-Serial Links
(3.125 Gbps)
RapidIO A
td
rd
rd
td
2
Getting Started
A_Send_Packet
Atlantic
Interface
B_Receive_Packet
RapidIO B
A_Receive_Packet
B_Send_Packet
AIRbus
Interface
AIRbus
Interface
A_Read_Register
B_Read_Register
tb module
Note:
(1)
The external blocks, shown in white, are Verilog HDL tasks.
The testbench starts with the cores in a reset state. A 78.125 MHz reference
clock is provided to all clock inputs. After coming out of reset, the cores
start the port initialization process to detect the presence of a partner and
establish bit synchronization and code group boundary alignment.Once
the cores have asserted their port_initialized output signals, the
testbench checks that the port initialization process completed
successfully by reading the Error and Status CSR to confirm the expected
values of the PORT_OK and PORT_UNINIT register bits.
Packets with 8 to 256 bytes of data payload are then transmitted from one
core to the other. The receiving core sends the proper acknowledgment
symbols and the received packets are checked in the expected sequence
for data integrity.
Altera Corporation
39
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
The format of the transmitted packets is described in Table 10.
Table 10. Serial Packets Format
Packet Byte
Format
First Header word {AckID[4:0],Reserved[2:0],
prio[2:0],tt[1:0],ftype[2:0]}
DestinationID
{DestinationID[31:0]}
Payload bytes
8 to 256 bytes
Description
AckID is set to zero and is replaced by the transmitting
core. The prio field is used by the receiver to select the
output queue. The tt and ftype fields are for use by the
transport and logical layers and are ignored by the
physical layer cores.
These fields are for use by the Transport and Logical
layers and are transferred unchanged by the physical
SourceID
{SourceID[31:0]}
Last Header word {Transaction[3:0],Size[3:0],TID[7:0]} layer cores.
The payload bytes in the packet are set to an
incrementing sequence starting at 0.
The received packets’ format is similar, but CRCs and padding (when
required) are appended to the packet and a intermediate CRC is inserted
in the packets after the first 80 bytes, when the packet’s size exceeds 80
byte.
Table 11 lists the tasks used to write packets to a core for transmission,
read and check a received packet, and read the value from a register and
compare it to an expected value.
Table 11. Serial Tasks
Function
Write Packet to an
Atlantic slave sink.
Prototype
task send_packet;
input [1:0] prio;
input [1:0] tt;
input [3:0] ftype;
input [8:0] payload_sizes;
Read and check a
task receive_packet;
packet from an
input [1:0] prio;
Atlantic slave source.
input [1:0] tt;
input [3:0] ftype;
input [8:0] payload_size;
Read from Register
40
task read_register;
input [16:0]address;
input [31:0]expected;
Comments
The payload_size should be an even number between 8
and 256 inclusive.
The actual name of the task is prepended with A_ or B_
depending on which core it should act.
prio – packet priority
tt – transport type
ftype – packet format type
payload size – size of the packet payload
The read value is compared to the expected value, any
difference is flagged as an error. “don’t care” values can be
specified by putting “x”s in the corresponding bit position.
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
All of the packets are sent in sequence with no breaks between them. After
all packets have been sent, the idle symbols are transmitted until the end
of the simulation.
The testbench concludes by checking that all of the packets have been
received. If no error is detected and all packets are received, the testbench
issues a “TESTBENCH PASSED” message stating that the simulation was
successful.
Scripts to run the testbench in ModelSim under UNIX are provided in the
test directory. To run the testbench, simply choose the model language
and type one of the following:
■ ./run_modelsim_verilog
■ ./run_modelsim_vhdl
■ ./run_modelsim_visual_ip
1
In all cases, the testbench itself is in Verilog HDL, therefore a
license to run mixed language simulations is required to run the
testbench with the VHDL model.
Parallel RapidIO Demonstration Testbench Description
The testbench provided with the parallel RapidIO core tests the following
functions:
■
■
■
■
Port Initialization and training
Transmission, reception, and acknowledgment of packets with 8 to
256 bytes of data payload
Writing to and reading from the Atlantic slave interfaces
Reading from the software interface registers
The testbench consists of two RapidIO cores interconnected through their
parallel RapidIO interfaces. (Each core’s tclk, td, and tframe outputs
are connected to the other core’s rclk, rd, and rframe inputs,
respectively.) The tb modules provide clocking and reset control along
with tasks to write to and read from the core’s Atlantic interfaces, and
tasks to read from the command and status register (CSR) set.
Altera Corporation
41
2
Getting Started
If an error is detected, a “TESTBENCH FAILED” message is issued to
indicate that the testbench has failed. A “TESTBENCH INCOMPLETE”
message is issued if the expected number of checks is not made. For
example, if not all packets are received before the testbench is terminated.
The variable tb.exp_chk_cnt determines the number of checks done to
insure completeness of the testbench.
RapidIO Physical Layer MegaCore Function User Guide
Figure 13. Parallel RapidIO Demonstration Testbench
Atlantic
Interface
A_Send_Packet
A_Receive_Packet
Reference
Clock
Getting Started
Note (1)
Reference
RapidIO
Clock
8/16 LP-LVDS Links
(3.125 Gbps)
tclk
tframe
8 or 16
td
8 or 16
RapidIO A
rd
rframe
rclk
rclk
rframe
rd
RapidIO B
td
tframe
tclk
AIRbus
Interface
Atlantic
Interface
B_Receive_Packet
B_Send_Packet
AIRbus
Interface
A_Read_Register
B_Read_Register
tb module
Note:
(1)
The external blocks, shown in white, are Verilog HDL tasks.
The testbench starts with the cores in a reset state. A reference clock is
provided to all clock inputs. After coming out of reset, the cores start the
link initialization process to detect the presence of a partner and establish
sampling window and 32-bit boundary alignment. Once the cores have
asserted the train_done output signals, the testbench checks that the port
initialization process completed successfully by reading the Error and
Status CSR to confirm the expected values of the PORT_OK and
PORT_UNINIT register bits.
Packets with 8 to 256 bytes of data payload are then transmitted from one
core to the other. The receiving core sends the proper acknowledgment
symbols and the received packets are checked in the expected sequence
for data integrity.
42
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
The format of the transmitted packets is described in Table 12.
Table 12. Parallel Packets Format
Packet Byte
Format
Description
DestinationID
{DestinationID[31:0]}
These fields are for use by the Transport and Logical
layers and are transferred unchanged by the physical
SourceID
{SourceID[31:0]}
Last Header word {Transaction[3:0],Size[3:0],TID[7:0]} layer cores. They are set to easily recognizable
patterns for testing purposes.
Payload bytes
8 to 256 bytes
The payload bytes in the packet are set to an
incrementing sequence starting at 0.
The received packets’ format is similar, but CRCs and padding (when
required) are appended to the packet and an intermediate CRC is inserted
into the packets after the first 80 bytes, when the packet’s size exceeds 80
bytes.
Table 11 lists the tasks used to write packets to a core for transmission,
read and check a received packet, and read the value from a register and
compare it to an expected value.
Table 13. Parallel Tasks
Function
Write Packet to an
Atlantic slave sink.
Prototype
task send_packet;
input [1:0] prio;
input [1:0] tt;
input [3:0] ftype;
input [8:0] payload_sizes;
Read and check a
task receive_packet;
packet from an
input [1:0] prio;
Atlantic slave source.
input [1:0] tt;
input [3:0] ftype;
input [8:0] payload_size;
Read from Register
Altera Corporation
task read_register;
input [16:0]address;
input [31:0]expected;
Comments
The payload_size should be an even number between 8
and 256 inclusive.
The actual name of the task is prepended with A_ or B_
depending on which core it should act.
prio – packet priority
tt – transport type
ftype – packet format type
payload size – size of the packet payload
The read value is compared to the expected value, any
difference is flagged as an error. “don’t care” values can be
specified by putting “x”s in the corresponding bit position.
43
2
Getting Started
First Header word {S, AckID[2:0], Reserved1, S_BAR, AckID is set to zero and is replaced by the transmitting
Reserved2[2:0], prio[2:0], tt[1:0],
core. S is set to zero and S_BAR is set to one. The prio
ftype[2:0]}
field is used by the receiver to select the output queue.
The tt and ftype fields are for use by the transport and
logical layers and are ignored by the physical layer
cores. The Reserved, prio, tt, and ftype fields are set
to zero in the demonstration testbench.
RapidIO Physical Layer MegaCore Function User Guide
Getting Started
All of the packets are sent in sequence with no breaks between them. After
all packets have been sent, the idle symbols are transmitted until the end
of the simulation.
The testbench concludes by checking that all of the packets have been
received. If no error is detected and all packets are received, the testbench
issues a “TESTBENCH PASSED” message stating that the simulation was
successful.
If an error is detected, a “TESTBENCH FAILED” message is issued to
indicate that the testbench has failed. A “TESTBENCH INCOMPLETE”
message is issued if the expected number of checks is not made. For
example, if not all packets are received before the testbench is terminated.
The variable tb.exp_chk_cnt determines the number of checks done to
insure completeness of the testbench.
To get a value change dump file called dump.vcd for all viewable signals,
simply un-comment the line “//‘define MAKEDUMP” in the tb.v file.
Bash shell scripts to run the testbench in ModelSim under UNIX are
provided in the test directory. To run the testbench, simply go to the test
directory, select a model language and type one of the following:
■ ./run_modelsim_verilog
■ ./run_modelsim_vhdl
■ ./run_modelsim_visual_ip
1
In all cases, the testbench itself is in Verilog HDL, therefore a
license to run mixed language simulations is required to run the
testbench with the VHDL model.
In addition to the specified model, the scripts make use of a few clear text
source files:
■
■
tb.v is the top level testbench file
riophy.v (or .vhd) is a wrapper that instantiates the encrypted
RapidIO model along with the required megafunctions
■ hutil.iv defines a few general purpose testing utilities
■ demo_hookup.iv connects the two instantiations of the cores
together and generates the required clock and reset signals
■ demo_util.iv defines the tasks to read and write on the AIRbus or
Atlantic interfaces.
The 220model, altera_mf and altgxb simulation libraries are also provided
because they are required for simulation.
44
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
Using the Visual IP Software
The Visual IP software facilitates the use of Visual IP simulation models
with third-party simulation tools. To view a simulation model, you must
have the Visual IP software installed on your system. To download the
software, or for instructions on how to use the software, refer to the Altera
web site at www.altera.com, and search for Visual IP. For examples of
how to use the provided Visual IP model, refer to the sample scripts
included with the demo testbench.
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar Logic™,
Mentor Graphics®, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
1.
Create your custom design instantiating a RapidIO.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the RapidIO core instantiation as a black box by
either setting attributes or ignoring the instantiation.
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Placeand-Route
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
1.
Altera Corporation
Specify the input settings for the project.
a.
Choose EDA Tool Settings (Assignments menu).
b.
Select Synplify in the Design entry/synthesis tool list.
c.
Click Settings.
d.
In the EDA Tool Input Settings dialog box, select Synplify from
the Design Entry/Synthesis Tool list.
45
2
Getting Started
Synthesize,
Compile &
Place & Route
RapidIO Physical Layer MegaCore Function User Guide
2.
Specify the netlist optimizations for the project in Settings >
Compiler Settings > Netlist Optimizations (Assignments menu).
a.
Click the Perform WYSIWYG primitive resynthesis check box.
b.
Click the Perform gate-level register retiming checkbooks.
c.
Click the Automatically duplicate logic elements check box.
d.
Click the Perform logic element level LUT resynthesis check
box.
1
f
Set Up
Licensing
Getting Started
Steps c) and d) are not applicable for APEX II devices.
3.
Add your third-party EDA tool-generated netlist file to your project.
4.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
5.
Add the pre-synthesized and encrypted .e.vqm file from your
project directory, created by the MegaWizard Plug-In Manager.
6.
If required, constrain your design.
7.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design.
Refer to the Quartus II Help for further instructions on performing
compilation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FPGA device. You can use Altera’s
OpenCore evaluation software to compile and simulate the RapidIO
MegaCore function in the Quartus II software, allowing you to evaluate it
before purchasing a license. However, you must obtain a license from
Altera before you can generate programming files or EDIF, VHDL, or
Verilog HDL gate-level netlist files for simulation in third-party EDA
tools.
After you purchase a license for the RapidIO core, you can request a
license file from the Altera web site at www.altera.com/licensing and
install it on your PC. When you request a license file, Altera e-mails you a
license.dat file. If you do not have Internet access, contact your local
Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
46
Altera Corporation
Getting Started
RapidIO Physical Layer MegaCore Function User Guide
1
Before you set up licensing for the RIOPHY, you must already
have the Quartus II software installed on your PC or
workstation, with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC or
workstation:
2
Quartus II
MAX+PLUS® II
LeonardoSpectrumTM
Synplify
ModelSim
2.
Open the RapidIO core license file in a text editor. The file should
contain one FEATURE line, spanning two lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the RapidIO core license file and paste
it into a new line in the Quartus II license file.
1
5.
Getting Started
■
■
■
■
■
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Altera Corporation
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Run the Quartus II software.
47
RapidIO Physical Layer MegaCore Function User Guide
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Perform PostRoute
Simulation
48
Getting Started
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
After you have licensed the RapidIO core, you can generate EDIF, VHDL,
Verilog HDL, and Standard Delay Output (.sdo) files from the Quartus II
software and use them with your existing EDA tools to perform functional
modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, refer to the
“Using the Quartus II Development Tool for Compilation & Placeand-Route”section. The Quartus II software generates output and
programming files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
Altera Corporation
Serial RapidIO
Specifications
Functional
Description
This section describes the serial RapidIO core, which is divided into three
sub-layers. Layer 1 is the first layer of the three layer partition of the 1×
serial physical layer. It provides a full-duplex interface with serial
differential ports to a serial RapidIO device or core. Layer 1 uses many
features provided by the Stratix GX high-speed transceiver.
Layer 1
■
■
3
Serial
Specifications
■
Port initialization
Receiver
–
One lane high-speed (up to 3.125 Gbps) data deserialization
–
Clock and data recovery
–
Lane synchronization
–
8B/10B decoding
–
Packet/control symbol delineation
–
CRC checking on packets
–
Control symbol CRC-5 checking
–
Error detection
–
Idle character extraction
–
32-bit master-source Atlantic interfaces
Transmitter
–
One lane high-speed (up to 3.125 Gbps) data serialization
–
8B/10B encoding
–
Packet/control symbol assembly
–
CRC generation on packets
–
Control symbol CRC-5 generation
–
Pseudo-random idle sequence generation
–
32-bit master-sink Atlantic interfaces
Layer 2
■
■
■
■
■
Altera Corporation
Processor access
–
Symbol queue, status
Flow control (window tracking)
–
Time-out on acknowledgements
Order of retransmission maintenance, and acknowledgements
AckID assignment
Error management
49
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Layer 3
■
■
■
Atlantic interface with clock decoupling
Transmitter
–
Four queues with priority ordering, free queue, and
retransmission queue
–
Optional block for hardware priority promotion
–
Minimum 51 full-size (276 bytes) message buffers
Receiver
–
Notification to user when message received
–
User controls retrieve order
–
Minimum 51 full-size (276 bytes) message buffers
Figure 14 on page 51 shows a high-level block diagram of the serial
RapidIO core.
50
Altera Corporation
Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 14. Serial RapidIO Block Diagram
Atlantic Interface
Atlantic
Interface
Transmit
Buffer
Transmit
Receive
Buffer
Buffer
Control
Control
arxclk
arxreset_n
arxena
arxdav
arxdat[31:0]
arxval
arxsop
arxeop
arxmty[1:0]
arxerr
atxclk
atxreset_n
atxena
atxdav
atxdat[31:0]
atxsop
atxeop
atxmty[1:0]
atxerr
rxbena
rxbadr[m:0] (1)
rxbtag[7:0]
rxfena
rxfack
rxfadr[m:0] (1)
Atlantic Interface
Receive
Buffer
Atlantic
Interface
Layer 3
sel
addr[16:2]
Registers
3
Layer 2
Flow Control
Serial
Specifications
read
AIRbus
Interface wdata[31:0]
rdata[31:0]
dtack
Layer 1
txclk
tx_reset_n
rxclk
rx_reset_n
input_enable
output_enable
port_initialized
rxpll_locked
td
rd
Low Level Interface
RapidIO Interface
RapidIO Interface
Note:
(1)
Depends on buffer size: m is equal to [8] for 32 K buffers, or [7] for 16 K buffers.
Clock Domains
The serial RapidIO core comprises six clock domains: two Stratix GX
transceiver clocks, two internal global clocks, and two interface clocks, as
illustrated in Figure 15 on page 52.
Altera Corporation
51
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Figure 15. Clock Domains
(3) rxclk
rxgxbclk (1)
Receiver
PLL
/2
arxclk (5)
rd
PLL
Multiplexer/
FIFO Buffer
Layer 2
Layer 3
Layer 2
Layer 3
arxdat
Layer 1
(4) txclk
txgxbclk (2)
Transmitter
PLL
x2
atxclk (6)
td
PLL
Multiplexer/
FIFO Buffer
atxdat
Layer 1
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
52
rxgxbclk: Receiver transceiver clock
txgxblck: Transmitter transceiver clock
rxclk: Receiver internal global clock; rxclk will not operate until receive PLL is locked
txclk: Transmitter internal global clock
arxclk: Atlantic interface clock—greater than, or equal to rxclk
atxclk: Atlantic interface clock—greater than, or equal to txclk
Altera Corporation
Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
The serial RapidIO specification specifies baud rates of 1.25, 2.5, and 3.125
Gbps. Table 14 shows the relationship between baud rates and internal
clock rates.
Table 14. Baud Rates and Internal Clock Rates
f
Altera Corporation
Transceiver Clock (MHz)
(txgxbclk/rxgxbclk)
Internal Clock (MHz)
(txclk/rxclk)
3.125
156.25
78.13
2.5
125.00
62.50
1.25
62.50
31.25
For more information on using high-speed transceiver blocks, refer to AN
237: Using High-Speed Transceiver Blocks in Stratix GX Devices.
This section describes the serial RapidIO sub-layers, and their respective
block functions.
3
Layer 1
The layer 1 sub-layer is designed to be a full-duplex interface with serial
differential ports to a serial RapidIO device or core. This section gives a
block-by-block description of the layer 1 functions. Figure 16 on page 54
shows a detailed block diagram of the layer 1.
53
Serial
Specifications
RapidIO
Physical SubLayer
Descriptions
Baud Rates
(Gbps)
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Figure 16. Layer 1 Data Flow Block Diagram
From Symbol
FIFO Buffer
13
S0 Symbol
Interface
13
32
6
13
Atlantic Interface/
S1 Symbol
Interface Packet Data Packing
13
32
6
S0 Symbol
Interface
32
6
To Packet
FIFO Buffer
To Symbol
FIFO Buffer
From Packet
FIFO Buffer
S1 Symbol
Interface
Atlantic Interface/
Packet Data Packing
32
6
CRC
Generation/
Insertion
CRC Check
Idle Sequence
Generation
32
32
Packet/Symbol Delineation
Idle Character Extraction
Packet/Symbol Assembling
Idle Character Insertion
32
Lane Synchronization
State Machine
Initialization
State Machine
32
TX
txclk
rxclk
Multiplexer & Buffer
32
Demultiplexer & Buffer
16
RX
16
txgxbclk
rxgxbclk
Transmitter Transceiver
Receiver Transceiver
Serial RapidIO Interface
Serial RapidIO Interface
Receiver
The layer 1 receiver sub-layer receives and passes packets to the layer 3,
and passes control symbols to the layer 2 over a slave-sink Atlantic
interface.
Clock & Data
The layer 1 receiver requires two clock domains: a Stratix GX
Megafunction clock (rxgxbclk), and an internal global clock (rxclk).
54
Altera Corporation
Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Receiver Transceiver
The receiver transceiver is an embedded Megafunction within the
Stratix GX FPGA. Serial data from differential input pins is fed into the
clock and recovery unit (CRU) to detect clock and data. Recovered data is
deserialized into 10-bit code groups and sent to the pattern detector and
word aligner block to detect word boundaries. Properly aligned 10-bit
code groups are then 8B/10B decoded into 8-bit characters and converted
to 16-bit data via the 8-to-16 demultiplexer. Figure 17 shows the structure
and the data flow of the receiver transceiver.
Figure 17. Receiver Transceiver Structure
16
Input
Data
8 to 16
Demultiplexer
8
8B/10B
Decoder
10
Pattern Detector/
Word Aligner
10
Serial to Parallel
Clock & Data
Recovery
Differential Pins
Serial Input
Data
Serial
Specifications
Demultiplexer & Buffer
Input data packets are demultiplexed in the same order as they are
received on the input pins.
Lane Synchronization State Machine
The lane synchronization state machine monitors the lane
synchronization status. If the signal lane_sync is asserted, then the lane
is synchronized and the valid data is presented at the input path.
Packet/Symbol Delineation & Idle Character Extraction
The packet/symbol delineation and idle character extraction block
delineates the input data into two data streams. One goes into the packet
FIFO buffer, and the other goes into the symbol FIFO buffer.
This block also extracts idle characters from the data stream. It detects
stomp symbol and packet size error, and asserts the corresponding error
signals to layer 2. This block checks the 5-bit CRC at the end of the 24-bit
symbol that covers the first 19 bits. The polynomial X5+ X4+ X2+ 1 is used.
If the CRC is incorrect, the error signal sym_err is asserted.
Altera Corporation
3
55
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
CRC Check
The CCITT polynomial X16 + X12 + X5 + 1 is used for CRC checking. This
block checks 16-bit CRCs that cover all packet header bits, except the first
six bits and all data payload. The size of the packet determines how many
CRCs are required.
For packets of 80 bytes or fewer—header and payload data excluded—a
single CRC is used and appended at the end.
For packets longer than 80 bytes, two CRCs are used. The first CRC is
appended after the first 80 bytes; the second CRC is a continuation of the
calculation of the first CRC and is appended at the end of the packet.
This block also flags CRC errors, and packet size errors.
Atlantic Interface/Packet Data Packing
This block sends 32-bit data to the upper layer via a 32-bit master-source
Atlantic interface. It generates all required handshake signals for the
interface.
S0 & S1 Symbol Interface
These blocks receive 13-bit stype0 control symbols and 6-bit stype1
control symbols, respectively. These blocks send control symbols to the
upper layer via a simple dual-port FIFO interface.
Transmitter
The layer 1 transmitter sub-layer assembles packets and control symbols,
received over a slave-source Atlantic interface, into one message and
passes it to the serial RapidIO interface.
Clock and Data
The layer 1 transmitter uses two clocks: a Stratix GX Megafunction clock
(txgxbclk), and an internal global clock (txclk).
Transmitter Transceiver
The transmitter transceiver is an embedded Megafunction within the
Stratix GX FPGA. The 16-bit parallel output data is internally multiplexed
to 8-bit data and 8B/10B encoded. The 10-bit encoded data is then
serialized and sent to differential output pins. Figure 18 on page 57 shows
the transmitter transceiver structure and data flow direction.
56
Altera Corporation
Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 18. Transmitter Transceiver Structure
16
Output
Data
8
16 to 8
Multiplexer
8B/10B
Encoder
10
Parallel to Serial
Differential Pins
Serial Output
Data
Multiplexer & Buffer
Input data packets are multiplexed in the same order as they are received
on the output pins.
Initialization State Machine
The serial port must be initialized before it can receive valid data. This
state machine works closely with the lane synchronization state machine
to monitor the lane_sync signal. When the lane_sync signal is
asserted, the state machine enters the 1×_MODE state. The
port_initialized signal is also asserted.
3
Packet/Symbol Assembling & Idle Character Insertion
Idle Sequence Generation
When there is no data to transmit, layer 1 automatically inserts idle
characters to transmit. The serial RapidIO specifies three idle characters:
K (K28.5), R (K29.7, and A (K27.7), and they are inserted based on a
pseudo-random generator of the 7th order polynomial X7+ X6+ X+ 1. The
following requirements must also be met:
■
■
Altera Corporation
The first character of an idle sequence generated by a port operating
in 1× model must be a K character. The first character must be
transmitted immediately following the last character of a packet or
delimited control symbol.
At least once every 5,000 characters transmitted, an idle sequence
containing the /K/R/R/R sequence must be transmitted. This is also
known as the compensation sequence.
57
Serial
Specifications
The packet/symbol assembling and idle character insertion block
assembles packet data and control symbol into a proper output format,
with corresponding delimiting symbols and special characters. It
generates 5 bit CRCs to cover the 19-bit symbol and appends the CRC at
the end of the symbol. The polynomial X5+ X4+ X2+ 1 is used. It inserts an
idle sequence if both the packet FIFO and symbol FIFO buffers are empty.
If a packet termination symbol is encountered, it inserts idle characters
until ERR or EOP is set high. During port initialization, it continues to send
idle characters until the port is initialized.
RapidIO Physical Layer MegaCore Function User Guide
■
■
Serial RapidIO Specifications
When not transmitting the compensation sequence, all characters
following the character of an idle sequence must be a pseudorandomly selected of A, K, and R based on a pseudo-random
sequence generator of 7th order or greater, and subject to the
minimum and maximum A character spacing requirements.
The number of non-A characters between A characters in the idle
sequence must be no less than 16 and no more than 32. The number
must be pseudo-randomly selected, uniformly distributed across the
range, and based on a pseudo-random sequence generator of 7th
order or greater.
CRC Generation & Insertion
The CCITT polynomial X16 + X12 + X5 + 1 is used for CRC generation. This
block generates a CRC that covers all packet header bits, except the first
six bits and all data payload. The size of the packet determines how many
CRCs are required.
For packets of 80 bytes or fewer—header and payload data excluded—a
single CRC is used and appended at the end.
For packets longer than 80 bytes, two CRCs are used. The first CRC is
appended after the first 80 bytes; the second CRC is a continuation of the
calculation of the first CRC and is appended at the end of the packet.
Atlantic Interface/Packet Data Packing
The transmitter receives packet data from upper layers via a 32-bit mastersink Atlantic interface. It generates all required handshake signals for the
interface.
S0 & S1 Symbol Interface
The transmitter receives control symbols from upper layers via 13-bit and
6-bit FIFO interfaces. The 13-bit interface is for stype0 control symbols,
and the 6-bit interface is for stype1 control symbols. It also decodes packet
termination symbols: stomp, restart from retry, and link request.
Layer 2
58
The layer 2 sub-layer provides flow control for the serial RapidIO physical
layer. This section gives a block-by-block description of the layer 2.
Figure 19 on page 59 shows a detailed block diagram of the layer 2.
Altera Corporation
Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 19. Layer 2 Data Flow Block Diagram
Layer 3
Buffer Control
Atlantic Interface
Packet
Control
Packet
Control
Error Recovery
Control
13
Layer 3
Buffer Control
6
Atlantic Interface
Error Recovery
Control
13
32
(Packet
Data)
6
Symbol Control
13
Symbol FIFO
Buffer
(Packet
Data) 32
6
13
Symbol FIFO
Buffer
6
13
Symbol FIFO
Buffer
TX
RX
13
6
Symbol FIFO
Buffer
6
3
Serial
Specifications
Receiver
The layer 2 receiver sub-layer is responsible for processing incoming
control symbols. It also monitors incoming packet ackIDs to maintain
proper flow.
Clock and Data
The layer 2 receiver comprises one clock domain: an internal global clock
(rxclk).
Symbol FIFO Buffer
Incoming 13-bit stype0 control symbols and 6-bit stype1 control symbols
are stored in their respective symbol FIFO buffers by the layer 1. These
symbols are retrieved by the layer 2 for further processing.
The AIRbus interface allows the processor to insert or extract symbols
from the FIFO buffers. The receiver FIFO buffers connect to the layer 1 via
a simple dual-port FIFO interface.
Altera Corporation
59
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Symbol Control
On the receive side, the layer 2 keeps track of the sequence of ackIDs and
tells the layer 3 which packets have been acknowledged, and which
packets to drop.
Packet Control
The packet control block uses a sliding window protocol to handle
incoming and outgoing packets. Each incoming and outgoing packet has
an attached 5-bit ackID in the header field. The value of ackID is zero at
reset. It increments after each packet is sent out, and rolls over to zero after
it has reached 31. All packets can only be accepted by the receiver in the
sequential order specified by the ackID. If a packet is lost at the receiver,
a packet retry request with the lost ackID is sent to the sender. The sender
then retransmits all packets starting from the lost ackID.
Error Recovery Control
A packet or control symbol corrupted by an incorrect CRC, or by a
CRC-5 error, must be recovered. During the error recovery process, two
interdependent state machines are required to operate the input and
output ports, respectively.
When an incoming packet is corrupted, the receiver sends a packet not
accepted symbol to the sender. The sender then retransmits all packets
starting from the retried ackID of the corrupted packet.
When an incoming control symbol is corrupted, the receiver sends a
packet not accepted control symbol to inform the sender of the
internal status, and the expected ackID. The sender then proceeds to
retransmit the control symbol.
Transmitter
The layer 2 transmitter sub-layer is responsible for creating and
transmitting outgoing control symbols. It also monitors outgoing packet
ackIDs to maintain proper flow.
Clock and Data
The layer 2 transmitter comprises one clock domain: an internal global
clock (txclk).
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Serial RapidIO Specifications
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Symbol FIFO Buffer
The layer 2 provides these symbol FIFO buffers to store outgoing 13-bit
stype0 control symbols and 6-bit stype1 control symbols. These symbols
are retrieved by the layer 1, and sent out via the serial RapidIO interface.
The AIRbus interface allows the processor to insert or extract symbols
from the FIFO buffers. The transmitter FIFO buffers connect to the layer 1
via a simple dual-port FIFO interface.
Symbol Control
On the transmit side, the layer 2 keeps track of the sequence of ackIDs
and tells the layer 3 which packet to send with what ackID. The layer 2
also tells the layer 3 which packet has been acknowledged, and thus can
be discarded in the buffers.
Packet Control
Error Recovery Control
An uncorrupted protocol violating control symbol, or a control symbol
corrupted by an incorrect CRC, or by a CRC-5 error must to be recovered.
During the error recovery process, two interdependent state machines are
required to operate the input and output ports, respectively.
For error recovery, transmitted packets are held by the output port for
possible retransmission in case an error is detected by the receiving
device. The packets are held until the sending device receives a packetaccepted control symbol for that packet. If a packet is retransmitted, the
time-out counter is reset for that retransmitted packet.
Layer 3
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The layer 3 sub-layer provides buffers, and buffer management for packet
data. This section gives a block-by-block description of the layer 3
functions.
61
3
Serial
Specifications
The packet control block uses a sliding window mechanism to handle
incoming and outgoing packets. This block also sets the time-out counters
for each outgoing packet. When time-out occurs to an outgoing packet, the
packet control block treats it as an unexpected acknowledge control
symbol, and starts the packet retry process.
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Receiver
The layer 3 receiver sub-layer accepts packet data from the layer 1 sublayer, and stores it in its buffers for the user. Figure 20 shows a detailed
block diagram of the receiver layer 3.
Figure 20. Layer 3 Receiver Data Flow Block Diagram
Control Message
to/from Upper Layer
Transmit
Queue
Scheduler
Atlantic Interface
32 (Packet
Data)
Address D
Receiver
Buffers
Free
Queue
Address E
32 (Packet
Data)
Control Message
from Layer 2
Atlantic Interface
Clock & Data
The layer 3 receiver sub-layer comprises two clock domains: an internal
global clock (rxclk), and an Atlantic interface slave clock (arxclk). The
Atlantic interface provides clock decoupling.
Scheduler
On the user interface side, the scheduler block retrieves packet data from
the receiver buffer on a FIFO basis.
This block also offers the user the option to retrieve data out of order. With
this option, the scheduler notifies the user of the received tagged packet.
This allows the user to determine which packet to retrieve next by sending
a control message with a specific address to the scheduler.
On the internal side, this block receives control messages from the layer 2
and determines which packets to drop.
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Free Queue
The free queue stores all available buffer addresses. It consists of 512
entries of 9 bits per entry. For a 16-Kbyte buffer, there are 256 entries of 8bit addresses in the free queue that correspond to 64 blocks in the buffer.
If the control message received by the scheduler indicates the packet
should be dropped (canceled), the scheduler deletes the packet, and its
address is added to the free queue block.
Transmit Queue
The transmit queue stores the address of the received packet. It consists of
256 entries of 12 bits per entry. For a 16Kbyte buffer, each entry comprises
a SOP, EOP, and SKIP bit, and an 8-bit address, which together form a
label list. The address of a new packet is inserted at the bottom of the
queue, and a stored packet is usually retrieved from the top of the queue.
Receiver Buffers
Packets are stored in the receiver buffers in the addresses indicated by the
transmit queue. The buffer is partitioned into 64 byte blocks. The buffer
size can be configured to 16 or 32 Kilobytes.
f
Refer to Table 9 on page 19 for examples of memory usage depending on
on buffer size.
Transmitter
The layer 3 transmitter sub-layer accepts packet data from the user logic,
via the Atlantic interface, and stores it into its buffers for the layer 1 sublayer. Figure 21 on page 64 shows a detailed block diagram of the
transmitter layer 3.
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63
3
Serial
Specifications
If the receive buffer control parameter is chosen, the user selects
which packet is to be retrieved next, and its address is taken from
whatever location it occupies in the queue. The address is returned to the
free queue if the corresponding packet is retrieved by the upper layer, or
if the packet is cancelled by the scheduler.
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Figure 21. Layer 3 Transmitter Data Flow Block Diagram
Atlantic Interface
(Packet
Data) 32
Promotion Control
Free
Queue
Address E
Priority
Queue
0
Transmitter
Buffers
Address D
Priority
Queue
1
Priority
Queue
2
Priority
Queue
3
Scheduler
Retransmit
Queue
Manager
(Packet
Data) 32
Control Message
from Layer 2
Atlantic Interface
Clock & Data
The layer 3 transmitter sub-layer requires two clock domains: an internal
global clock (txclk), and an Atlantic interface slave clock (atxclk). The
Atlantic interface provides clock decoupling.
Manager
The manager block receives control commands from the layer 2, and
manages the data flow accordingly. It assigns an ackID to the next packet
to be transmitted. It retransmits a packet when it is timed-out, or when an
acknowledge control symbol with an unexpected ackID has been
received, and stops the current transmission. The manager block drops
the packets that have been acknowledged.
Scheduler
The scheduler determines the order of packets to be transmitted according
to the 2-bit priority from the packet header, 11 (‘h3) is the highest priority,
and 00 (‘h0) is the lowest. This block also sets the timer (time-stamp) on
packets.
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RapidIO Physical Layer MegaCore Function User Guide
If the manager block receives a retransmit command, the scheduler stops
the current transmission and uses the corresponding address from the
retransmit queue to retrieve data from the transmitter buffer.
Retransmit Queue
The retransmit queue stores the address of transmitted, but not
acknowledged packets. It consists of 32 entries of 12 bits per entry, and is
configured to 256 entries of 16 bits per entry.
A transmitted packet is to be retransmitted if it has timed-out, or if and
acknowledge control symbol with an unexpected ackID has been
received. If an acknowledge control symbol with an expected ackID is
received, the corresponding address pointer is cleared and returned to the
free queue.
Free Queue
If the control message received by the scheduler indicates for the packet
to be dropped (canceled), the scheduler deletes the packet, and its address
is added to the free queue block.
Priority Queues
There are four priority queues, and each one consists of 64 entries of 12
bits per entry that form a label list. These queues store the addresses of the
incoming packets. The address is fetched from the free queue. Each packet
header contains two-bits that indicate the packet priority. Data is stored in
one of the four queues depending on the packet priority setting.
Promotion Control (optional)
The promotion control block is optional, and is used to promote the
priority of a response packet in case a deadlock situation occurs. This
block stores the time-stamp of each low-priority response packet stored in
the buffer. When the time-stamp set by the scheduler expires (times-out),
two courses of action are possible: the packet is canceled, or its priority is
elevated. For example, when an untransmitted packet times-out, the
promotion control block promotes the address of that packet to the next
higher-level priority queue.
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3
Serial
Specifications
The free queue stores all available buffer addresses. It consists of 512
entries of 8 bits per entry. For a 16-Kbyte buffer, there are 256 entries of 8bit addresses in the free queue that correspond to 64 blocks in the buffer.
RapidIO Physical Layer MegaCore Function User Guide
1
Serial RapidIO Specifications
The promotion control parameter is not available in this
release (v2.0.0).
Transmitter Buffers
The transmitter buffer is partitioned into 64 byte blocks, for a total data
storage space of 16 Kbytes. The buffer can be expanded by 16 Kbytes.
Packet are taken from the transmitter buffers according to priority, in
descending order.
Signals
Tables 15 through 16 list the I/O signals used in the serial layer 1. The
active-low signals are indicated by _n.
Table 15. Serial RapidIO Interface Layer 1 Signals
Signal
rd
rd_n
Direction
Description
Input
Receive data—the receive data is a unidirectional packet data input
bus. It is connected to the td bus of the transmitting device.
Input
Receive data complement.
td
Output
Transmit data—the transmit data is a unidirectional point-to-point
bus designed to transmit the packet information. The td bus of one
device is connected to the rd bus of the receiving device.
td_n
Output
Transmit data complement.
Table 16. Serial Layer 1 Global Signals
Signal
Direction
Description
rxclk
Output
Receive reference clock
txclk
Input
Transmit reference clock
rxreset_n
Input
Receive active-low reset
tx_reset_n
Input
Transmit active-low reset
input_enable
Input
Enables the inputs
output_enable
Input
Enables the outputs
port_initialized
Output
Port is initialized
rxpll_locked
Output
Receive PLL is locked
Table 17 lists the I/O signals used in the layer 2.
Table 17. Serial Layer 2 AIRbus Interface Signals (Part 1 of 2)
Signal
sel
66
Direction
Input
Note (1)
Description
AIRbus interface selects
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Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 17. Serial Layer 2 AIRbus Interface Signals (Part 2 of 2)
Signal
Note (1)
Direction
Description
addr[16:2]
Input
AIRbus address bus
read
Input
AIRbus read
wdata[31:0]
Input
AIRbus write data bus
rdata[31:0]
Output
AIRbus read data bus
dtack
Output
AIRbus interface data acknowledge
Note from Table 17:
(1)
Although the AIRbus interface specification lists a clock (clk) and an interrupt request (irq) as part of its signals,
the RapidIO core does not have an AIRbus-specific clock, or an irq signal.
Tables 18 through 20 list the I/O signals used in the layer 3. The active-low
signals are indicated by _n
Table 18. Serial Layer 3 Atlantic Receive Interface Signals
Signal
Direction
3
Description
Serial
Specifications
arxclk
Input
Receive clock
arxreset_n
Input
Receive active-low reset
arxena
Input
Receive enable
arxdav
Output
Receive data available
arxdat[31:0]
Output
Receive data bus
arxsop
Output
Receive start of packet
arxeop
Output
Receive end of packet
arxmty[1:0]
Output
Number of invalid bytes on the receive data bus
arxerr
Output
Receive data error
Note:
(1)
Depends on buffer size: m is equal to [8] for 32 K buffers, or [7] for 16 K buffers..
Table 19. Serial Layer 3 Receive Buffer Control Signals
Signal
Direction
Description
rxbena
Output
Buffer notification enable
rxbadr[m:0] (1)
Output
Buffer notification address
rxbtag[7:0]
Output
Buffer notification tag
rxfena
Input
rxfack
Output
rxfadr[m:0] (1)
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Input
Buffer fetch enable
Buffer fetch acknowledge
Buffer fetch address
67
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Note:
(1)
Depends on buffer size: m is equal to [8] for 32 K buffers, or [7] for 16 K buffers.
Table 20. Serial Layer 3 Atlantic Transmit Interface Signals
Signal
Direction
Description
atxclk
Input
Transmit clock
atxreset_n
Input
Transmit active-low reset
atxena
Input
Transmit enable
atxval
Output
Transmit data valid
atxdav
Output
Transmit data available
atxdat[31:0]
Input
Transmit data bus
atxsop
Input
Transmit start of packet
atxeop
Input
Transmit end of packet
atxmty[1:0]
Input
Number of invalid bytes on the transmit data bus
atxerr
Input
Transmit data error
Software
Interface
All addresses access 32-bit registers and are shown as hexadecimal values.
The access addresses for each register increment by units of 4. Table 21
shows the memory map for the serial RapidIO core.
Table 21. Master Memory Map
Address
Name
Description
’h0
PHEAD0
’h4
PHEAD1
Port Maintenance Block Header 0
Port Maintenance Block Header 1
’h20
PLTCTRL
Port Link Time-out Control CSR
’h24
PRTCTRL
Port Response Time-out Control CSR
’h3C
PGCTRL
Port General Control CSR
’h58
ERRSTAT
Port 0 Error and Status CSR
’h5C
PCTRL0
Port 0 Control CSR
Registers
Table 22 lists the access codes used to describe the type of register bits.
Table 22. Registers (Part 1 of 2)
Code
RW
68
Description
Read/write
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Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 22. Registers (Part 2 of 2)
Code
Description
RO
Read-only
RW1C
Read/write 1 to clear
RW0S
Read/write 0 to set
RTC
Read to clear
RTS
Read to set
RTCW
Read to clear/write
RTSW
Read to set/write
RWTC
Read/write any value to clear
RWTS
Read/write any value to set
RWSC
Read/write self-clearing
RWSS
Read/write self-setting
UR0
Unused bits/read as 0
UR1
Unused bits/read as 1
3
Tables 23 to 29 describe the registers for the master functions of the serial
RapidIO core. The offset values are as defined by the RapidIO standard
Table 23. PHEAD0 - Port Maintenance Block Header 0 - ’h0
Field
Bits
Access
Function
Default
EF_PTR
31:16
RO
Hard wired pointer to the next block in the data
structure, if one exists.
0
EF_ID
15:0
RO
Hard wired extended features ID
0
Table 24. PHEAD1 - Port Maintenance Block Header 1 - ’h4
Field
RSRV
Bits
Access
31:0
UR0
Function
Reserved
Default
0
Table 25. PLTCTRL - Port Link Time-Out Control CSR - ’h20
Field
Bits
Access
Function
Default
VALUE
31:8
RW
Time-out interval value
’hffffff
RSRV
7:0
UR0
Reserved
0
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Serial
Specifications
Master Register Description
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Table 26. PRTCTRL - Port Response Time-Out Control CSR - ’h24
Field
Bits
Access
Function
Default
VALUE
31:8
RW
Time-out internal value
’hffffff
RSRV
7:0
UR0
Reserved
0
Table 27. PGCTRL - Port General Control CSR - ’h3C
Field
Bits
Access
HOST
31
RW
A host device is a device that is responsible for
0
system exploration, initialization, and maintenance.
Agent or slave devices are typically initialized by
host devices.
’b0 - agent or slave device
’b1 - host device
ENA
30
RW
The master enable bit controls whether or not a
0
device is allowed to issue requests into the system.
If the master enable is not set, the device may only
respond to requests.
’b0 - processing element cannot issue requests
’b1 - processing element can issue requests
DISCOVERED
29
RW
This device has been located by the processing
0
element responsible for system configuration.
’b0 - The device has not been previously discovered
’b1 - The device has been discovered by another
processing element.
28:0
UR0
Reserved
RSRV
Function
Default
0
Table 28. ERRSTAT - Port 0 Error and Status CSR - ’h58 (Part 1 of 2)
Field
Bits
Access
31:21
UR0
OUT_RTY_ENC
20
RW1C
Output port has encountered a retry condition. This 0
bit is set when bit 18 is set.
OUT_RETRIED
19
RO
Output port has received a packet-retry control
0
symbol and cannot make forward progress. This bit
is set when bit 18 is set. This bit is cleared when a
packet-accepted or a packet-not-accepted control
symbol is received.
OUT_RTY_STOP
18
RO
Output port has received a packet-retry control
symbol and is in the output retry-stopped state.
RSRV
70
Function
Default
Reserved
0
0
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Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 28. ERRSTAT - Port 0 Error and Status CSR - ’h58 (Part 2 of 2)
Field
Bits
Access
OUT_ERR_ENC
17
RW1C
OUT_ERR_STOP
16
RO
Output port is in the output error-stopped state.
0
RSRV1
Function
Default
Output port has encountered (and possibly
0
recovered from) a transmission error. This bit is set
when bit 16 is set.
15:11
UR0
Reserved
0
IN_RTY_STOP
10
RO
Input port is in the input retry-stopped state.
0
IN_ERR_ENC
9
RW1C
Input port has encountered (and possibly recovered 0
from) a transmission error. This bit is set when bit 8
is set.
8
RO
Input port is in the input error-stopped state.
0
7:5
UR0
Reserved
0
PWRITE_PEND
4
RW1C
RSRV3
3
UR0
PORT_ERR
2
RW1C
PORT_OK
1
RO
Input and output ports are initialized and the port is 0
exchanging error-free control symbols with the
adjacent device.
PORT_UNINIT
0
RO
Input and output ports are not initialized. This bit and ’b1
bit 1 are mutually exclusive.
IN_ERR_STOP
RSRV2
Port has encountered a condition which requires it to 0
initiate a maintenance port-write operation. This bit
is only valid if the device is capable of issuing a
maintenance port-write transaction.
0
Input or output port has encountered an error from
which hardware was unable to recover.
0
3
Serial
Specifications
Reserved
Table 29. PCTRL0 - Port 0 Control CSR - ’h5C (Part 1 of 3)
Field
Bits
Access
PORT_WIDTH
28:27
UR0
Hardware width of the port:
’b00 - Single-lane port
’b01 - Four-lane port
’b10 - ’b11 - Reserved
PWIDTH_OVRIDE
26:24
RW
Soft port configuration to override the hardware size: 0
’b000 - No override
’b001 - Reserved
’b010 - Force single lane, lane 0
’b011 - Force single lane, lane 2
’b100 - ’b111 - Reserved
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Function
Default
0
71
RapidIO Physical Layer MegaCore Function User Guide
Serial RapidIO Specifications
Table 29. PCTRL0 - Port 0 Control CSR - ’h5C (Part 2 of 3)
Field
Bits
Access
PORT_DIS
23
RW
Port disable:
0
’b0 - port receivers/drivers are enabled.
’b1 - port receivers/drivers are disabled and are
unable to receive/transmit to any packets or control
symbols.
OUT_PENA
22
RW
Output port transmit enable:
’b0 - port is stopped and not enabled to issue any
packets except to route or respond to I/O logical
MAINTENANCE packets, depending upon the
functionality of the processing element. Control
symbols are not affected and are sent normally.
’b1 - port is enabled to issue any packets.
IN_PENA
21
RW
Input port receive enable:
0
’b0 - port is stopped and only enabled to respond I/O
logical MAINTENANCE packets, depending upon
the functionality of the processing element. Other
packets generate packet-not-accepted control
symbols to force an error condition to be signaled by
the sending device. Control symbols are not
affected and are received and handled normally.
’b1 - port is enabled to respond to any packet.
ERR_CHK_DIS
20
RW
This bit disables all RapidIO transmission error
0
checking
’b0 - Error checking and recovery is enabled.
’b1 - Error checking and recovery is disabled.
Device behavior when error checking and recovery
is disabled and an error condition occurs is
undefined.
MULTICAST
19
RW
Send incoming Multicast-event control to this port
(multiple port devices only)
0
18:1
UR0
Reserved
0
0
UR1
This indicates the port-type, parallel or serial.
’b0 - Parallel port
’b1 - Serial port
0
28:27
UR0
Hardware width of the port:
’b00 - Single-lane port
’b01 - Four-lane port
’b10 - ’b11 - Reserved
0
RSRV2
PORT_TYPE
PORT_WIDTH
72
Function
Default
0
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Serial RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 29. PCTRL0 - Port 0 Control CSR - ’h5C (Part 3 of 3)
Field
Bits
Access
PWIDTH_OVRIDE
26:24
RW
Function
Default
Soft port configuration to override the hardware size: 0
’b000 - No override
’b001 - Reserved
’b010 - Force single lane, lane 0
’b011 - Force single lane, lane 2
’b100 - ’b111 - Reserved
3
Serial
Specifications
Altera Corporation
73
Parallel RapidIO
Specifications
Functional
Description
This section describes the parallel RapidIO core, which is subdivided into
three sub-layers. The following is a list of features for the three sub-layers.
Layer 1
■
■
■
■
8- or 16-bit parallel True-LVDS high-speed interface
I/O port training function to set up byte alignment
Receiver
–
Packet/control symbol delineation
–
Parity checking on control symbols
–
Cyclic redundancy code (CRC) checking on packets
–
Idle symbol extraction
Transmitter
–
Packet/control symbol assembly
–
Parity generation on control symbols
–
CRC generation on packets
–
Idle symbol insertion
3
Serial
Specifications
Layer 2
■
■
4
Parallel
Specifications
■
■
■
Processor access
–
Symbol queue, status
Flow control (window tracking)
–
Time-out on acknowledgements
Order of retransmission maintenance, and acknowledgements
AckID assignment
Error management
Layer 3
■
■
■
Altera Corporation
Atlantic interface with clock decoupling
Transmitter
–
Four queues with priority ordering, free queue, and
retransmission queue
–
Optional block for hardware priority promotion
–
Minimum 12 full-size (276 bytes) message buffers
Receiver
–
Notification to user when message received
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RapidIO Physical Layer MegaCore Function User Guide
–
–
Parallel RapidIO Specifications
User controls retrieve order
Minimum 12 full-size (276 bytes) message buffers
Figure 22 shows a high-level block diagram of the parallel RapidIO core.
Figure 22. Parallel RapidIO Block Diagram
Atlantic
Interface
rxbena
rxbadr[5:0]
rxbtag[7:0]
rxfena
rxfack
rxfadr[5:0]
arxclk
arxreset_n
arxena
arxdav
arxdat[127/63/31:0]
arxval
arxsop
arxeop
arxmty[3/2:0]
arxerr
Atlantic Interface
atxclk
atxreset_n
atxena
atxdav
atxdat[127/63/31:0]
atxsop
atxeop
atxmty[3/2:0]
atxerr
Atlantic Interface
Transmit
Transmit
Buffer
Receive
Buffer
Buffer
Control
Control
Receive
Buffer
Atlantic
Interface
Layer 3
sel
addr[16:2]
read
AIRbus
Interface wdata[31:0]
Registers
Layer 2
Flow Control
rdata[31:0]
dtack
Layer 1
txclk
tx_reset_n
rxclk (1)
rx_reset_n
input_enable
output_enable
train_done
rd[15:8]
rd[15:8]_n
rframe
rframe_n
rd[7:0]_n
rclk_n
rd[7:0]
rclk
td[15:8]
RapidIO Interface
td[15:8]_n
tframe
tframe_n
td[7:0]
td[7:0]_n
tclk
tclk_n
Low Level Interface
RapidIO Interface
Note:
(1)
76
Available in Stratix devices only.
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Clock Domains
The RapidIO core comprises six clock domains: four interface clocks, and
two global clocks, as illustrated in Figure 23.
Figure 23. Clock Domains
Note (1)
(4) rxclk
Receiver
(2) rclk
PLL
2/J
arxclk (6)
1
rd
to
rframe
J
Layer 1
Layer 2
Layer 3
arxdat
3
LVDS Macro
Serial
Specifications
(5) txclk
Transmitter
PLL
J/2
atxclk (7)
J
td
to
Layer 1
Layer 2
Layer 3
4
atxdat
1
Parallel
Specifications
tframe
(3) tclk
LVDS Macro
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
The J setting controls the width of the data bus driven into the transmitter or out of the receiver. J is the
deserialization factor, and can be equal to 4 or 8.
rclk: RapidIO interface clock
tclk: RapidIO interface clock
rxclk: Receiver internal global clock; rxclk will not operate until receive PLL is locked
txclk: Transmitter global clock—reference for tclk generation
arxclk: Atlantic interface clock—greater than, or equal to rxclk
atxclk: Atlantic interface clock—greater than, or equal to txclk
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RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Table 30 shows the minimum external and internal clock required by the
RapidIO specification.
Table 30. External and Internal Clock Rates
LVDS Data
Rates
Double Data
Rate (DDR)
Clock
RapidIO
Port Width
Internal Rate (rxclk & txclk)
500 Mbps
250 MHz
8 bits
16 bits
125 MHz
–
62.5 MHz
–
–
62.5 MHz
4 Gbps
8 Gbps
750 Mbps
375 MHz
8 bits
16 bits
–
–
93.75 MHz
–
–
93.75 MHz
6 Gbps
12 Gbps
1 Gbps
500 MHz
8 bits
–
125 MHz
–
8 Gbps
32-Bit Width
64-Bit Width 128-Bit Width
Throughput
Bit Rate
f
For more information on using high-speed I/O, refer to AN166: Using
High-Speed I/O Standards in APEX II devices, and AN202: Using High-Speed
Differential I/O Interfaces in Stratix Devices.
f
For more information on using high-speed transceiver blocks, refer to AN
237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Dynamic Phase
Alignment
Dynamic phase alignment (DPA) is used for source-synchronous interface
protocols that operate at increasingly higher data rates (e.g., 1 Gbps). The
goal of DPA is to allow devices to actively respond to changes in the
operational board skew. Devices equipped with DPA continuously check
the incoming data and adjust the phase of the clock to align with it. Several
industry standards responsible for defining chip-to-chip interfaces,
including RapidIO, have recognized the value of DPA, and have included
or recommended it in their specifications.
Every Stratix GX receiver channel features an embedded DPA block
(located in I/O banks 1 and 2). A complete, FPGA-integrated hard-silicon
DPA solution offers several benefits to system designers. It is
implemented for each data channel, such that each channel receives its
own phase-adjusted clock. This individual alignment for each channel
minimizes the chance for errors introduced by mismatches in signal
propagation paths. Also, it does not require a training mode; rather, it
continuously realigns the clock to the data during device operation. The
training patters specified by standards such as RapidIO are supported,
but no training pattern is required when using DPA with other interfaces.
The RapidIO core also features an integrated DPA block on its receiving
path, between the high-speed serial bus and the parallel bus. The RapidIO
DPA block functions include: data deserialization and clock division,
dynamic phase alignment, and byte alignment.
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
The RapidIO DPA block makes use of the DPA capability of Stratix GX
devices, supporting data rates of up to 1 Gbps. The DPA block can be
configured to support 9 or 17 hi-speed channels, and internal data widths
in excess of 32, 64, or 128 bits.
Features
■
■
■
■
■
■
Dynamic clock-data synchronization (phase alignment) to
compensate the clock-channel and channel-channel skew
Dynamic byte alignment using training patterns
Supports the RapidIO protocol
Corrects the data skew difference of up to +/- 0.75 bits (1.5 bits)
Supports SERDES factor of 8 and 4
Supports data rates from 350 Mbps to 1 Gbps
1
Stratix GX and DPA are required for performance beyond
840 Mbps
Functional Description
3
The block consists of the following sub-blocks: an ALTLVDS receiver
Megafunction (with the DPA feature enabled), a byte aligner, and an 8:4
deserializer (needed to achieve deserialization factor of 4). It also consists
of two status signals: locked and lvds_locked (one bit per channel),
and one control signal: force_unlock.
Altera Corporation
79
4
Parallel
Specifications
The rxdpa_locked and lvds_ch_locked (bit AND of lvds_locked)
status signals are accessible to the user. The force_unlock control
signal is not accessible to the user. See Figure 24 on page 80.
Serial
Specifications
The DPA block takes in the serial hi-speed phase/channel/byte
misaligned serial data, and outputs the phase/channel/byte aligned
parallel data and clock.
RapidIO Physical Layer MegaCore Function User Guide
Figure 24. DPA Block Diagram
Parallel RapidIO Specifications
Note (1)
RapidIO MegaCore Function
clk_out
clk_in
x2
PLL
clk x 2
Atlantic
Interface
reset
Serial
Data
data_in
ALTLVDS
Receiver
Megafunction
(with DPA)
8+1/16+1
data_out
128+/64+
align
Byte
Aligner
8:4
Deserializer
(2)
aligned_
data_out
128+/64+
aligned_
data : 2
128+/64+/32+
locked
force_unlock
lvds_locked
8+1/16+1
8+1/16+1
RapidIO
PHY 1
PHY 2
PHY 3
Bit
AND
rxdpa_
locked
rxlvds_
ch_locked
DPA
Notes:
(1)
(2)
The width of the data path for the data_out, aligned_data_out, and aligned_data:2 signals depends on
the SERDES factor.
Exists only for a deserialization factor of 4.
ALTLVDS_Receiver Megafunction
The ALTLVDS receiver Megafunction performs the phase equalization
(data and clock), the deserialization and the bit slipping (per channel) if
requested by the byte aligner sub-block, via the align signal (one bit for
each channel). The ALTLVDS_Receiver Megafunction is generated by the
MegaWizard Plug-in Manager in the Quartus II software.
Byte Aligner
The byte aligner sub-block aligns the parallel data (channel by channel). It
pulses the align signal until all channels are aligned (based on the
training patterns). For every align pulse, the ALTLVDS_Receiver
Megafunction sub-block shifts the data on the corresponding channel by
one bit to the left. The byte aligner retimes the parallel data.
Alignment is done once at start-up, and whenever requested by the
RapidIO processor by asserting the force_unlock signal (based on the
RapidIO protocol link-response symbol time-out).
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
1
If lock cannot be achieved after the state machine has
received many force_unlock signals, it is a good
indication that the LVDS is not locked on some or all
channels, that the lvds_locked signal was deasserted
during training, or that the lvds_locked signal is asserted
but the channel-to-channel skew is greater than the
maximum supported skew.
The byte aligner works in parallel, with one state machine per channel.
The byte aligner state machines begin the alignment process once the
ALTLVDS_Receiver Megafunction asserts the lvds_locked signal
(high). During the alignment process, the byte aligner does not monitor
the lvds_locked signal, and should it become deasserted (low) during
alignment, the output data may be misaligned. Therefore it is
recommended that the master RapidIO core monitor the lvds_locked
signal if alignment cannot be achieved, or if it detects too many DIP errors,
indicating a misalignment.
3
RapidIO Training Pattern
For example, for 16+1 channels and a serialization factor of 8, the parallel
data looks as shown in Table 31.
4
Table 31. Training Pattern Example
Framing
[7:0]
Ch16
Ch15
Ch14
Ch13
Ch12
Ch11
...
Ch0
0
‘hF0 (1)
‘hF0
‘hF0
‘hF0
‘hF0
‘hF0
...
‘hF0
1
‘hF0 (1)
‘hF0
‘hF0
‘hF0
‘hF0
‘hF0
...
‘hF0
...
...
...
...
...
...
...
...
...
Parallel
Specifications
Cycle
Data
(Channel 15 ... 0, bit [7:0])
Note from Table 31:
(1)
Could also be ‘h0F (see the RapidIO™
Interconnect Specification).
8:4 Deserializer
The 8:4 deserializer sub-block is only required to support a deserialization
factor of 4. It consists of a PLL and 4-bit demultiplexers, one for each
channel.
Altera Corporation
Serial
Specifications
The RapidIO training pattern consists of four 1s and four 0s (on all
channels) repeating 256 times (the framing channel could also be inverted:
four 0s and four 1s). The number of channels is 8+1 or 16+1 (data and
framing), depending on the serialization factor.
81
RapidIO Physical Layer MegaCore Function User Guide
f
RapidIO
Physical SubLayer
Descriptions
Parallel RapidIO Specifications
For more information on using dynamic phase alignment, refer to AN236:
Using Source-Synchronous Signaling with DPA in Stratix GX Devices.
This section describes the parallel RapidIO sub-layers, and their
respective block functions.
Layer 1
The layer 1 sub-layer is designed to be a full-duplex interface with 8- or
16-bit unidirectional True-LVDS ports. This section gives a block-by-block
description of the layer 1 functions. Figure 25 shows a detailed block
diagram of the layer 1.
Figure 25. Layer 1 Data Flow Block Diagram
Atlantic Interface
Master Sink
Atlantic Interface
Master Source
16 (Control Symbol)
16(Control Symbol)
(Packet data)
32, 64, or 128
Idle Symbol
Insertion
Idle Symbol
Extraction
CRC
Generation
16
CRC Check
16
Parity Generation
Parity Check
32, 128, or 256
32
32, 64, or 128
32
32, 128, or 256
(Packet Data)
Packet/Symbol
Assembling
Packet/Symbol
Delineation
32, 64, or 128
32, 64, or 128
I/O Port Training
32, 64, or 128
32, 64, or 128
High-Speed Interface
& Serializer
16 or 8
RapidIO Interface
82
High-Speed Interface
& Deserializer
16 or 8
TX
RX
RapidIO Interface
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Receiver
The layer 1 receiver sub-layer receives and passes packets to the layer 3,
and passes control symbols to the layer 2 over a slave-sink Atlantic
interface.
Clock & Data
The layer 1 receiver requires two clock domains: a RapidIO interface clock
(rclk), and an internal global clock (rxclk).
The 8- or 16-bit data is received from the RapidIO interface on True-LVDS
pins (ports). The data associated with the clock is double data rate (DDR).
High-Speed Interface & Deserializer
Using the high-speed serial interface (HSSI) features of the APEX II and
Stratix devices, the 8- or 16-bit bus is deserialized to a 32-, 64-, or 128-bit
bus. The deserialization factor can be 4 or 8.
Figure 26 on page 84 shows the layer 1 input port configuration: 16 TrueLVDS pin data, 128-bit internal data path, rclk/4 internal clock.
3
Serial
Specifications
The system receives the serial data and clock on its input True-LVDS pins.
Data words arrive on the rd bus at 2 × rclk (DDR). A high-frequency
clock, generated by a phase-lock loop (PPL), shifts the serial data through
the receiver’s SERDES module. The deserialized data (rd line) is driven
out in parallel with a low-frequency clock—the receiver’s global clock
(rxclk)—which drives the internal logic elements (LEs).
4
Parallel
Specifications
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83
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Figure 26. Layer 1 16-/128-Bit Input Port Configuration
8
rd0
SERDES
.
.
.
8
rd7
128
SERDES
rxdata_locked
8
rd10
SERDES
.
.
.
Byte
&
Channel
Aligner
8
rxframe_locked
8
rd17
SERDES
frm_locked
start_train
8
rframe
SERDES
PLL
x W/J (1)
rclk
Note:
(1)
W = 2; J = 8
Figure 27 shows the layer 1 input port configuration: 8 True-LVDS pin
data, 64-bit internal data path, rclk/4 internal clock.
Figure 27. Layer 1 8-/64-Bit Input Port Configuration
8
rd0
SERDES
64
rxdata_locked
.
.
.
8
rd7
SERDES
rframe
SERDES
8
rclk
8
Byte
&
Channel
Aligner
rxframe_locked
frm_locked
start_train
PLL
x W/J (1)
Note:
(1)
84
W = 2; J = 8
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 28 shows the layer 1 input port configuration: 16 True-LVDS pin
data, 64-bit internal data path, rclk/2 internal clock.
Figure 28. Layer 1 16-/64-Bit Input Port Configuration
4
rd0
SERDES
.
.
.
rd7
4
rxdata_locked
4
rd10
64
SERDES
SERDES
.
.
.
Nibble
&
Channel
Aligner
4
rxframe_locked
4
rd17
SERDES
frm_locked
4
rclk
3
start_train
Serial
Specifications
rframe
SERDES
PLL
x W/J (1)
Note:
(1)
W = 2; J = 4
Altera Corporation
85
4
Parallel
Specifications
Figure 29 on page 86 shows the layer 1 input port configuration: 8 TrueLVDS pin data, 128-bit internal data path, rclk/8 internal clock.
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Figure 29. Layer 1 8-/128-Bit Input Port Configuration
16
rd0
128
SERDES
rxdata_locked
.
.
.
16
rd7
SERDES
rframe
SERDES
16
rclk
16
Two-Byte
&
Channel
Aligner
rxframe_locked
frm_locked
start_train
PLL
x W/J (1)
Note:
(1)
W = 2; J = 16
Time Division Multiplexing
Input data packets are multiplexed in the same order as they are received
on the input pins. The APEX II and Stratix deserializer block outputs data
pin-by-pin and the first bit received is the most significant bit (MSB).
I/O Port Training
The RapidIO interface is source synchronous, and requires link
initialization to ensure that the input port receives the packets and control
symbols properly. Link initialization is required in the following
circumstances:
■
■
■
System power-up
Normal operation: system reset or error recovery (by request)
Connecting to another processing element
To ensure proper reception, the receiver performs two procedures, which
can be done in parallel, to initialize the input ports.
Sampling window alignment: During initialization, a predefined
training pattern is applied to the input port to set it up for reliable data
sampling. The training pattern is a special bit pattern that differs from the
control symbols and packets, it is easily recognized by the input port logic
when initialization is required, but ignored when not required.
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
The training pattern includes the following characteristics:
■
■
■
■
■
32 bits of binary 1 followed by 32 bits of binary 0 (8-bit port)
64 bits of binary 1 followed by 64 bits of binary 0 (16-bit port)
A frame signal switches at the same time as the data bits
The frame signal does not have to transition high to low or low to
high in phase with the data bits
The same pattern is sent from the output port for 256 times followed
by an idle symbol for each send-training request.
1
A training pattern cannot be embedded within, or
terminate, a packet.
32-bit boundary alignment: In order to ensure that the input port is
aligned to the 32-bit boundary of the connected output port, all control
symbols are delineated on this 32-bit boundary, thus allowing for an
aligned and steady stream of frame signals.
I/O port training (initialization) requires two state machines: input and
output port training state machines.
A port can only transition from its unitialized state to its OK
state when both state machines are in their OK states.
The layer 1 uses the I/O training pattern to perform byte alignment, under
the control of the layer 2.
Packet/Symbol Delineation
4
This block also detects start of packet (SOP), end of packet (EOP) control
symbol, and s bit errors.
Parity Check
The s bit is protected by an odd parity bit. The aligned control symbol is
protected by a 16-bit inverted value. This block checks the inverted value
and the s bit to ensure data integrity.
87
Parallel
Specifications
The packet/symbol delineation block delineates the input data on a 32-bit
boundary when the port is in its OK state, and the data is valid. It takes the
input data stream and divides it into two streams: control symbols which
go to the parity check block, and packet data which goes to the CRC check
block.
Altera Corporation
Serial
Specifications
1
3
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Idle Symbol Extraction
The idle symbol extraction block extracts and discards all control symbols
with an undefined stype field, and sets a symbol valid signal if the
appropriate control symbol is not an idle control symbol, and the s bit and
the control symbol parity are correct.
CRC Check
The CCITT polynomial X16 + X12 + X5 + 1 is used for CRC checking. The
size of the packet determines how many CRCs are required.
For packets of 80 bytes or fewer—header and payload data included—a
single CRC is used and appended at the end.
For packets longer than 80 bytes, two CRCs are used. The first CRC is
appended after the first 80 bytes; the second CRC is appended at the end
of the packet.
This block also flags CRC errors, and packet size errors.
Transmitter
The layer 1 transmitter sub-layer assembles packets and control symbols,
received over a slave-source Atlantic interface, into one message and
passes it to the parallel RapidIO interface.
Clock and Data
The layer 1 transmitter uses two clocks: a global clock (txclk), and a
RapidIO interface clock (tclk).
The tclk signal is a data output of the True-LVDS pins. It is generated by
the deserialization of txclk.
The data is transmitted on True-LVDS pins. The data associated with the
clock is DDR.
High-Speed Interface and Serializer
Using the HSSI features of the APEX II and Stratix devices, the 32-, 64-, or
128-bit bus is serialized to an 8- or 16-bit bus. Data words are sent on the
td data bus at 2 × tclk rate. A SERDES module serializes the word inputs
into output high-speed td/tframe lines.
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 30 shows the layer 1 output port configuration: 16 True-LVDS pin
data, 128-bit internal data path, internal clock, and a core clock.
Figure 30. Layer 1 16-/128-bit Output Port Configuration
td0
Note (1)
8
SERDES
.
.
.
td7
8
128
SERDES
data
8
td10
SERDES
.
.
.
td17
tclk
Demultiplexer
8
SERDES
3
8
send_train
SERDES
8
SERDES
Serial
Specifications
tframe
frame
8
10101010
core clk
Note:
(1)
4
The deserialization factor is 8.
Altera Corporation
89
Parallel
Specifications
Figure 31 on page 90 shows the layer 1 output port configuration: 8 TrueLVDS pin data, 64-bit internal data path, internal clock, and a core clock.
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Figure 31. Layer 1 8-/64-bit Output Port Configuration
td0
Note (1)
8
64
SERDES
data
.
.
.
td7
8
frame
8
SERDES
Demultiplexer
tframe
tclk
8
send_train
SERDES
8
SERDES
10101010
core clk
Note:
(1)
The deserialization factor is 8.
Figure 32 shows the layer 1 output port configuration: 8 True-LVDS pin
data, 128-bit internal data path, internal clock, and a core clock.
Figure 32. Layer 1 8-/128-bit Output Port Configuration
td0
16
128
SERDES
data
.
.
.
td7
Note (1)
16
frame
16
SERDES
Demultiplexer
tframe
tclk
16
send_train
SERDES
16
SERDES
1010101010101010
core clk
Note:
(1)
90
The deserialization factor is 16.
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 33 shows the layer 1 output port configuration: 16 True-LVDS pin
data, 64-bit internal data path, internal clock, and a core clock.
Figure 33. Layer 1 16-/64-bit Output Port Configuration
td0
Note (1)
4
SERDES
.
.
.
td7
4
64
SERDES
data
4
td10
SERDES
.
.
.
td17
tclk
Demultiplexer
4
SERDES
3
4
send_train
SERDES
4
SERDES
Serial
Specifications
tframe
frame
4
1010
core clk
Note:
(1)
4
The deserialization factor is 4.
The output port sends out a training pattern on power-up, or when a link
request/send-training control symbol is received.
The layer 1 generates the training pattern under the control of the layer 2.
See “I/O Port Training” on page 86, for more details.
Packet/Control Symbol Assembling
The packet/control symbol assembling block assembles the control
symbol and packet data streams into the required output format, with
corresponding framing signal.
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Parallel
Specifications
I/O Port Training
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Parity Generation
16-bit control symbols are followed by a bit-wise inversion of themselves
for alignment on a 32-bit boundary, but this inversion also serves for
parity error checking. This block generates the 16-bit inverted value.
Idle Symbol Insertion
The symbol insertion block inserts an idle symbol if a throttle request is
received to add a wait state to the output packet, or if no data (packet or
control symbol) is available for transfer.
CRC Generation
The CRC generation block generates a CRC over the entire packet header
and data payload, except for the first six bits of the first packet, which are
covered by protocol and parity.
For packets of 80 bytes or fewer—header and payload data included—a
single CRC is used and appended at the end.
For packets longer than 80 bytes, two CRCs are generated. The first CRC
is appended after the first 80 bytes; the second CRC is appended at the end
of the packet. The second CRC is a continuation of the calculation of the
first CRC.
Layer 2
92
The layer 2 sub-layer provides flow control for the parallel RapidIO
physical layer. This section gives a block-by-block description of the layer
2. Figure 34 on page 93 shows a detailed block diagram of the layer 2.
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Figure 34. Layer 2 Data Flow Block Diagram
Layer 3
Buffer Control
Layer 3
Buffer Control
Atlantic Interface
Packet
Control
Packet
Control
Error Recovery
Control
Atlantic Interface
Error Recovery
Control
32, 64,
or 256
(Packet
Data)
16
16
Symbol Control
16
16
Symbol FIFO
Buffer
(Packet
Data)
32, 64,
or 128
16
Symbol FIFO
Buffer
16
TX
3
Layer 1
Atlantic Interface
Serial
Specifications
Layer 1
Atlantic Interface
RX
Receiver
The layer 2 receiver sub-layer is responsible for processing incoming
control symbols. It also monitors incoming packet ackIDs to maintain
proper flow.
4
The layer 2 receiver comprises one clock domain: an internal global clock
(rxclk).
Symbol FIFO Buffer
Incoming symbols are stored in the receiver’s symbol FIFO buffer by the
layer 1. These symbols are retrieved by the layer 2 for further processing.
The AIRbus interface allows the processor to insert or extract symbols
from the FIFO buffer. The receiver FIFO buffer connects to the layer 1 via
an Atlantic slave interface.
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93
Parallel
Specifications
Clock and Data
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Symbol Control
On the receive side, the layer 2 keeps track of the sequence of ackIDs and
tells the layer 3 which packets have been acknowledged, and which
packets to drop.
Packet Control
The packet control block uses a sliding window protocol to handle
incoming and outgoing packets. Each incoming and outgoing packet has
an attached 3-bit ackID in the header field. The value of ackID is zero at
reset. It increments after each packet is sent out, and rolls over to zero after
it has reached seven. All packets can only be accepted by the receiver in
the sequential order specified by the ackID. If a packet is lost at the
receiver, a packet retry request with the lost ackID is sent to the sender.
The sender then retransmits all packets starting from the lost ackID.
Error Recovery Control
A packet or control symbol corrupted by an incorrect CRC, or by a parity
error, must be recovered. During the error recovery process, two
interdependent state machines are required to operate the input and
output ports, respectively.
When an incoming packet is corrupted, the receiver sends a packet not
accepted acknowledgment to the sender. The sender then retransmits all
packets starting from the retried ackID of the corrupted packet.
When an incoming control symbol is corrupted, the receiver sends a
packet not accepted control symbol to inform the sender of the internal
status, and the expected ackID. The sender then proceeds to retransmit
the control symbol.
Transmitter
The layer 2 transmitter sub-layer is responsible for creating and
transmitting outgoing control symbols. It also monitors outgoing packet
ackIDs to maintain proper flow.
Clock and Data
The layer 2 transmitter comprises one clock domain: an internal global
clock (txclk).
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Symbol FIFO Buffer
The layer 2 provides this symbol FIFO buffer to store outgoing symbols.
These symbols are retrieved by the layer 1, and sent out via the output
port.
The AIRbus interface allows the processor to insert or extract symbols
from the FIFO buffer. The transmitter FIFO buffer connects to the layer 1
via an Atlantic slave interface.
Symbol Control
On the transmit side, the layer 2 keeps track of the sequence of ackIDs
and tells the layer 3 which packet to send with what ackID. The layer 2
also tells the layer 3 which packet has been acknowledged, and thus can
be discarded in the buffer.
Packet Control
Error Recovery Control
For error recovery, transmitted packets are held by the output port for
possible retransmission in case an error is detected by the receiving
device. The packets are held until the sending device receives a packetaccepted control symbol for that packet. If a packet is retransmitted, the
time-out counter is reset for that retransmitted packet.
Altera Corporation
95
4
Parallel
Specifications
An uncorrupted protocol violating control symbol, or a control symbol
corrupted by an incorrect CRC, or by a parity error must to be recovered.
During the error recovery process, two interdependent state machines are
required to operate the input and output ports, respectively.
3
Serial
Specifications
The packet control block uses a sliding window mechanism to handle
incoming and outgoing packets. This block also sets the time-out counters
for each outgoing packet. When time-out occurs to an outgoing packet, the
packet control block treats it as an unexpected acknowledge control
symbol, and starts the packet retry process.
RapidIO Physical Layer MegaCore Function User Guide
Layer 3
Parallel RapidIO Specifications
The layer 3 sub-layer provides buffers, and buffer management for packet
data. This section gives a block-by-block description of the layer 3
functions.
Receiver
The layer 3 receiver sub-layer accepts packet data from the layer 1 sublayer, and stores it in its buffers for the user. Figure 35 shows a detailed
block diagram of the receiver layer 3.
Figure 35. Layer 3 Receiver Data Flow Block Diagram
Control Message
to/from Upper Layer
Atlantic Interface
32, 64, (Packet
or 128 Data)
256 to 128
Atlantic Adapter
Transmit
Queue
Scheduler
Address D
Receiver
Buffers
Free
Queue
Address E
32, 64, (Packet
or 256 Data)
Control Message
from Layer 2
Atlantic Interface
Clock & Data
The layer 3 receiver sub-layer comprises two clock domains: an internal
global clock (rxclk), and an Atlantic interface slave clock (arxclk). The
Atlantic interface provides clock decoupling.
Scheduler
On the user interface side, the scheduler block retrieves packet data from
the receiver buffer on a FIFO basis.
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
This block also offers the user the option to retrieve data out of order. With
this option, the scheduler notifies the user of the received tagged packet.
This allows the user to determine which packet to retrieve next by sending
a control message with a specific address to the scheduler.
On the internal side, this block receives control messages from the layer 2
and determines which packets to drop.
Free Queue
The free queue stores all available buffer addresses. It consists of 512
entries of 8 bits per entry. For a 4-Kbyte buffer, there are 64 entries of 6-bit
addresses in the free queue that correspond to 64 blocks in the buffer.
If the control message received by the scheduler indicates the packet
should be dropped (canceled), the scheduler deletes the packet, and its
address is added to the free queue block.
Transmit Queue
Receiver Buffers
Packets are stored in the receiver buffers in the addresses indicated by the
transmit queue. The buffer is partitioned into 64 blocks of 64 bytes each.
The buffer size can be configured to 4, 8, or 16 Kilobytes.
f
Refer to Table 9 on page 19 for examples of memory usage depending on
on buffer size.
256 to 128 Atlantic Adapter
The 256 to 128 Atlantic adapter block is optional, and is used to convert a
256-bit Atlantic slave-source into a 128-bit Atlantic slave-source interface.
This block is only required if the layer 3 sub-layer is implemented.
Altera Corporation
97
4
Parallel
Specifications
If the receive buffer control parameter is chosen, the user selects which
packet is to be retrieved next, and its address is taken from whatever
location it occupies in the queue. The address is returned to the free queue
if the corresponding packet is retrieved by the upper layer, or if the packet
is cancelled by the scheduler.
3
Serial
Specifications
The transmit queue stores the address of the received packet. It consists of
256 entries of 9 bits per entry. For a 4 Kbyte buffer, each entry comprises
a SOP, EOP, and SKIP bit, and a 6-bit address, which together form a label
list. The address of a new packet is inserted at the bottom of the queue,
and a stored packet is usually retrieved from the top of the queue.
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Transmitter
The layer 3 transmitter sub-layer accepts packet data from the user logic,
via the Atlantic interface, and stores it into its buffers for the layer 1 sublayer. Figure 36 shows a detailed block diagram of the transmitter layer 3.
Figure 36. Layer 3 Transmitter Data Flow Block Diagram
Atlantic Interface
(Packet
Data)
32, 64,
or 128
Promotion Control
Free
Queue
Address E
Priority
Queue
0
Transmitter
Priority
Queue
1
Priority
Queue
2
Priority
Queue
3
Buffers
Address D
Scheduler
Retransmit
Queue
(Packet
Data)
32, 64,
or 128
Manager
Control Message
from Layer 2
Atlantic Interface
Clock & Data
The layer 3 transmitter sub-layer requires two clock domains: an internal
global clock (txclk), and an Atlantic interface slave clock (atxclk). The
Atlantic interface provides clock decoupling.
Manager
The manager block receives control commands from the layer 2, and
manages the data flow accordingly. It assigns an ackID to the next packet
to be transmitted. It retransmits a packet when it is timed-out, or when an
acknowledge control symbol with an unexpected ackID has been
received, and stops the current transmission. The manager block drops
the packets that have been acknowledged.
98
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Scheduler
The scheduler determines the order of packets to be transmitted according
to the 2-bit priority from the packet header, 11 (‘h3) is the highest priority,
and 00 (‘h0) is the lowest. This block also sets the timer (time-stamp) on
packets.
If the manager block receives a retransmit command, the scheduler stops
the current transmission and uses the corresponding address from the
retransmit queue to retrieve data from the transmitter buffer.
Retransmit Queue
The retransmit queue stores the address of transmitted, but not
acknowledged packets. It consists of 8 entries of 9 bits per entry and is
configured to 256 entries of 16 bits per entry.
Free Queue
The free queue stores all available buffer addresses. It consists of 512
entries of 8 bits per entry. For a 4-Kbyte buffer, there are 64 entries of 6-bit
addresses in the free queue that correspond to 64 blocks in the buffer.
Priority Queues
There are four priority queues, and each one consists of 64 entries of 9 bits
per entry that form a label list. These queues store the addresses of the
incoming packets. The address is fetched from the free queue. Each packet
header contains two-bits that indicate the packet priority. Data is stored in
one of the four queues depending on the packet priority setting.
Altera Corporation
99
4
Parallel
Specifications
If the control message received by the scheduler indicates for the packet
to be dropped (canceled), the scheduler deletes the packet, and its address
is added to the free queue block.
3
Serial
Specifications
A transmitted packet is to be retransmitted if it has timed-out, or if and
acknowledge control symbol with an unexpected ackID has been
received. If an acknowledge control symbol with an expected ackID is
received, the corresponding address pointer is cleared and returned to the
free queue.
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Promotion Control (optional)
The promotion control block is optional, and is used to promote the
priority of a response packet in case a deadlock situation occurs. This
block stores the time-stamp of each low-priority response packet stored in
the buffer. When the time-stamp set by the scheduler expires (times-out),
two courses of action are possible: the packet is canceled, or its priority is
elevated. For example, when an untransmitted packet times-out, the
promotion control block promotes the address of that packet to the next
higher-level priority queue.
1
The promotion control parameter is not available in this
release (v2.0.0).
Transmitter Buffers
The transmitter buffer is partitioned into 64 blocks of 64 bytes each, for a
total data storage space of 4 Kbytes. The buffer can be expanded by 4
Kbytes. Packet are taken from the transmitter buffers according to
priority, in descending order.
Signals
Tables 32 through 34 list the I/O signals used in the parallel layer 1. The
active-low signals are indicated by _n.
Table 32. Parallel Layer 1 Receive Signals
Signal
Direction
Description
rclk
Input
Receive clock—free-running input clock for the 8-bit port and the
most significant half of the 16-bit port. rclk connects to tclk of the
transmitting device.
rclk_n
Input
Receive clock complement—this signal is the differential pair of the
rclk signal. rclk connects to tclk of the transmitting device.
rd[7:0]
Input
Receive data—the receive data is a unidirectional packet data input
bus. It is connected to the td bus of the transmitting device.
rd[7:0]_n
Input
Receive data complement—this vector is the differential pair of the
rd vector.
rframe
Input
Receive frame—this control signal indicates a special packet
framing event on the rd pins. rframe is sampled with respect to
rclk.
rframe_n
Input
Receive frame complement—this signal is the differential pair of the
rframe signal.
rd[15:8]
Input
Receive data—least significant half of the 16-bit port. These signals
are not used when connected to an 8-bit device.
rd[15:8]_n
Input
Receive data complement—this vector is the differential pair of the
rd[8-15] vector.
100
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 33. Parallel Layer 1 Transmit Signals
Signal
Direction
Description
Output
Transmit clock—free-running clock for the 8-bit port and the most
significant half of the 16-bit port. tclk connects to rclk of the
receiving device.
tclk_n
Output
Transmit clock complement—this signal is the differential pair of the
tclk signal.
td[7:0]
Output
Transmit data—the transmit data is a unidirectional point-to-point
bus designed to transmit the packet information along with the
associated tclk and tframe. The td bus of one device is
connected to the rd bus of the receiving device. td[0-7] is always
asserted with a fixed relationship to tclk, as defined in the AC
section.
td[7:0]_n
Output
Transmit data complement—this vector is the differential pair of
td[0-7].
tframe
Output
Transmit framing signal—when issued as active, this signal
indicates a packet control event. tframe is connected to rframe of
the receiving device. tframe is always asserted with a fixed
relationship to tclk, as defined in the AC section.
tframe_n
Output
Transmit frame complement—this signal is the differential pair of the
tframe signal.
td[15:8]
Output
Transmit data—least significant half of the 16-bit port. These signals
are not used when connected to an 8-bit device. td[8-15] is
always asserted with a fixed relationship to tclk, as defined in the
AC timing section.
td[15:8]_n
Output
Transmit data complement—this vector is the differential pair of
td[8-15].
4
Parallel
Specifications
Table 34. Parallel Layer 1 Global Signals
Signal
Direction
Description
rxclk
Output
txclk
Input
Transmit reference clock
rxreset_n
Input
Receive active-low reset
tx_reset_n
Input
Transmit active-low reset
input_enable
Input
Enables the inputs.
Input
Enables the outputs.
output_enable
train_done
Altera Corporation
Output
3
Serial
Specifications
tclk
Receive reference clock (Available for Stratix devices only.)
Indicates that port training has been completed.
101
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Table 35 shows the DPA signals used by the receiver.
1
Only applicable when using the DPA circuitry of a
Stratix GX device.
Table 35. DPA Status Signals (Receiver Only)
Signal
rxdpa_locked
Direction
Output
Description
The DPA byte aligner is locked so all channels are aligned.
rxlvds_ch_locked Output
All channels are locked to the DPA mode. This signal is the bit AND of the
Stratix GX altlvds_rx rx_dpa_locked [number of channels1..0] signal.
Table 36 lists the I/O signals used in the parallel layer 2.
Table 36. Parallel Layer 2 AIRbus Interface Signals
Signal
Note (1)
Direction
Description
sel
Input
AIRbus interface selects
addr[16:2]
Input
AIRbus address bus
read
Input
AIRbus read
wdata[31:0]
Input
AIRbus write data bus
rdata[31:0]
Output
AIRbus read data bus
dtack
Output
AIRbus interface data acknowledge
Note from Table 36:
(1)
Although the AIRbus interface specification lists a clock (clk) and an interrupt request (irq) as part of its signals,
the RapidIO core does not have an AIRbus-specific clock, or an irq signal.
Tables 37 through 39 list the I/O signals used in the parallel layer 3. The
active-low signals are indicated by _n.
Table 37. Parallel Layer 3 Atlantic Receive Interface Signals (Part 1 of 2)
Signal
Direction
Description
arxclk
Input
Receive clock
arxreset_n
Input
Receive active-low reset
arxena
Input
Receive enable
arxdav
Output
Receive data available
arxdat
[127/63/31:0]
Output
Receive data bus
arxval
Output
Receive data valid
102
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Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 37. Parallel Layer 3 Atlantic Receive Interface Signals (Part 2 of 2)
Signal
Direction
Description
arxsop
Output
Receive start of packet
arxeop
Output
Receive end of packet
arxmty[3/2:0]
Output
Number of invalid bytes on the receive data bus
arxerr
Output
Receive data error
Table 38. Parallel Layer 3 Receive Buffer Control Signals
Signal
Direction
Description
rxbena
Output
Buffer notification enable
rxbadr[5:0]
Output
Buffer notification address
rxbtag[7:0]
Output
Buffer notification tag
rxfena
Input
rxfack
Output
rxfadr[5:0]
Input
Buffer fetch enable
Buffer fetch acknowledge
3
Buffer fetch address
Serial
Specifications
Table 39. Parallel Layer 3 Atlantic Transmit Interface Signals
Signal
Direction
Description
atxclk
Input
Transmit clock
atxreset_n
Input
Transmit active-low reset
atxena
Input
Transmit enable
atxdav
Output
4
Transmit data available
Input
Transmit data bus
atxsop
Input
Transmit start of packet
atxeop
Input
Transmit end of packet
atxmty[3/2:0]
Input
Number of invalid bytes on the transmit data bus
atxerr
Input
Transmit data error
Software
Interface
Parallel
Specifications
atxdat
[127/63/31:0]
All addresses access 32-bit registers and are shown as hexadecimal values.
The access addresses for each register increment by units of 4. Table 40 to
Table 42 show the memory maps for the parallel RapidIO core.
Table 40. Transmitter Memory Map (Part 1 of 2)
Address
’h10000
Altera Corporation
Name
TXCTRL
Description
Transmitter Control
103
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Table 40. Transmitter Memory Map (Part 2 of 2)
Address
Name
Description
’h10004
TXSTAT
Transmitter Status
’h10008
TXSYM
Transmitter Symbol
Table 41. Receiver Memory Map
Address
Name
Description
’h10020
RXCTRL
Receiver Control
’h10024
RXSTAT
Receiver Status
’h10028
RXSYM
Receiver Symbol
Table 42. Master Memory Map
Address
104
Name
Description
’h100
PHEAD0
Port Maintenance Block Header 0
’h104
PHEAD1
Port Maintenance Block Header 1
’h120
PLTCTRL
Port Link Time-out Control CSR
’h124
PRTCTRL
Port Response Time-out Control CSR
’h13C
PGCTRL
Port General Control CSR
’h158
ERRSTAT
Port 0 Error and Status CSR
’h15C
PCTRL0
Port 0 Control CSR
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Registers
Table 43 lists the access codes used to describe the type of register bits.
Table 43. Registers
Code
Description
RW
RO
Read/write
RW1C
Read/write 1 to clear
RW0S
Read/write 0 to set
RTC
Read to clear
RTS
Read to set
RTCW
Read to clear/write
RTSW
Read to set/write
RWTC
Read/write any value to clear
RWTS
Read/write any value to set
RWSC
Read/write self-clearing
RWSS
Read/write self-setting
UR0
Unused bits/read as 0
UR1
Unused bits/read as 1
Read-only
3
Serial
Specifications
Transmitter Register Description
Tables 44 to 46 describe the registers for the transmitter section of the
RapidIO core. The offset values are as defined by the RapidIO standard.
Field
SYM_INS
Bits
Access
0
RW
Function
When a transition from 0 to 1 occurs, inserts one
symbol into the symbol queue. After insertion, this
bit is cleared.
Default
0
Table 45. TXSTAT - ’h10004
Field
RSRV
Altera Corporation
Bits
Access
31:0
UR0
Function
Reserved
Default
0
105
Parallel
Specifications
Table 44. TXCTRL - ’h10000
4
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Table 46. TXSYM - ’h10008
Field
SYMBOL
Bits
Access
15:0
RW
Function
Default
16-bit symbol to be inserted into the symbol queue. 0
Receiver Register Description
Tables 47 to 49 describe the registers for the receiver section of the
RapidIO core. The offset values are as defined by the RapidIO standard.
Table 47. RXCTRL - ’h10020
Field
SYM_EXT
Bits
Access
0
RW
Function
Default
Symbol extraction control.
0
Table 48. RXSTAT - ’h10024
Field
RSRV
Bits
Access
31:0
UR0
Function
Default
Reserved
0
Table 49. RXSYM - ’h10028
Field
SYMBOL
Bits
Access
15:0
RO
Function
Default
Extracted symbol. The AIRbus interface does not
assert the dtack signal until symbol is received.
0
Master Register Description
Tables 50 to 56 describe the registers for the master functions of the
RapidIO core. The offset values are as defined by the RapidIO standard.
Table 50. PHEAD0 - Port Maintenance Block Header 0 - ’h100
Field
Bits
Access
EF_PTR
31:16
RO
Hard wired pointer to the next block in the data
structure, if one exists.
0
EF_ID
15:0
RO
Hard wired extended features ID
0
106
Function
Default
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 51. PHEAD1 - Port Maintenance Block Header 1 - ’h104
Field
RSRV
Bits
Access
31:0
UR0
Function
Reserved
Default
0
Table 52. PLTCTRL - Port Link Time-out Control CSR - ’h120
Field
Bits
Access
Function
Default
VALUE
31:8
RW
Time-out interval value
’hffffff
RSRV
7:0
UR0
Reserved
0
Table 53. PRTCTRL - Port Response Time-out Control CSR - ’h124
Field
Bits
Access
Function
Default
VALUE
31:8
RW
Time-out internal value
’hffffff
RSRV
7:0
UR0
Reserved
0
3
Field
HOST
Bits
Access
31
RW
Function
Default
A host device is a device that is responsible for
0
system exploration, initialization, and maintenance.
Agent or slave devices are typically initialized by
host devices.
’b0 - agent or slave device
’b1 - host device
30
RW
The master enable bit controls whether or not a
0
device is allowed to issue requests into the system.
If the master enable is not set, the device may only
respond to requests.
’b0 - processing element cannot issue requests
’b1 - processing element can issue requests
DISCOVER
29
RW
This device has been located by the processing
0
element responsible for system configuration.
’b0 - The device has not been previously discovered
’b1 - The device has been discovered by another
processing element.
28:0
UR0
Reserved
RSRV
Altera Corporation
4
Parallel
Specifications
ENA
Serial
Specifications
Table 54. PGCTRL - Port General Control CSR - ’h13C
0
107
RapidIO Physical Layer MegaCore Function User Guide
Parallel RapidIO Specifications
Table 55. ERRSTAT - Port 0 Error and Status CSR - ’h158
Field
Bits
Access
31:21
UR0
OUT_BLOCK_ENC
20
RW1C
OUT_BLOCK
19
RO
Output port is blocked (receiving continuous retries) 0
and cannot make forward progress.
OUT_RTY_STOP
18
RO
Output port has been stopped due to a retry and is
trying to recover.
0
OUT_ERR_ENC
17
RW1C
Output port has encountered (and possibly
recovered from) a transmission error.
0
OUT_ERR_STOP
16
RO
Output port has been stopped due to a transmission 0
error and is trying to recover.
15:11
UR0
Reserved
0
Input port has been stopped due to a retry.
0
RSRV
RSRV1
Function
Default
Reserved
0
Output port has encountered a blocked condition.
0
IN_RTY_STOP
10
RO
IN_ERR_ENC
9
RW1C
IN_ERR_STOP
8
RO
Input port has been stopped due to a transmission
error.
0
RSRV2
Input port has encountered (and possibly recovered 0
from) a transmission error.
7:4
UR0
Reserved
0
PORT_PRES
3
RO
The port is receiving the free-running clock on the
input port.
0
PORT_ERR
2
RW1C
Input or output port has encountered an
unrecoverable error and has shut down (turned off
both port enables).
0
PORT_OK
1
RO
Input and output ports are initialized and can
communicate with the adjacent device.
0
PORT_UNINIT
0
RO
Input and output ports are not initialized and are in
training mode.
’b1
Table 56. PCTRL0 - Port 0 Control CSR - ’h15C (Part 1 of 2)
Field
Bits
Access
OUT_PWIDTH
31
RO
Opening width of the port:
’b0 - 8-bit port.
’b1 - 16-bit port.
0
OUT_PENA
30
RW
Output port transmit enable:
’b0 - port is stopped and not enabled to issue any
packets, except to respond to I/O logical
maintenance packets.
’b1 - port is enabled to issue any packets.
0
108
Function
Default
Altera Corporation
Parallel RapidIO Specifications
RapidIO Physical Layer MegaCore Function User Guide
Table 56. PCTRL0 - Port 0 Control CSR - ’h15C (Part 2 of 2)
Field
Access
OUT_PDRIV_DIS
29
RW
Output port driver disable:
0
’b0 - output port drivers are turned on, and drive the
pins normally.
’b1 - output port drivers are turned off, and do not
drive the pins. This is useful for power management.
RSRV
28
UR0
Reserved
0
IN_PWIDTH
27
RO
Operating width of the port:
’b0 - 8-bit port
’b1 - 16-bit port
0
IN_PENA
26
RW
Input port receive enable:
0
’b0 - port is stopped and only enabled to respond to
I/O logical maintenance requests. Other requests
return packet-not-accepted control symbols to force
an error condition to be signaled by the sending
device.
’b1 - port is enabled to respond to any packet.
IN_PRECV_DIS
25
RW
Input port receiver enable:
0
’b0 - input port receivers are enabled.
’b1 - input port receivers are disabled and are unable
to receive any packets or control symbols.
RSRV1
24
UR0
Reserved
ERR_CHK_DIS
23
RW
This bit disables all RapidIO transmission error
0
checking
’b0 - Error checking and recovery is enabled.
’b1 - Error checking and recovery is disabled. Device
behavior is undefined when error checking and
recovery are disabled and an error condition occurs.
RSRV2
Altera Corporation
Default
3
0
22
RW
Send incoming TOD-synchronization control
symbols to this port (multiple port devices only).
0
21:0
UR0
Reserved
0
4
Parallel
Specifications
TOD_PART
Function
Serial
Specifications
Bits
109
Appendix–Pin Constraints
& Board Design
Pin Constraints
The pinouts for the APEX II, Stratix, and Stratix GX device families
include dedicated True-LVDS clock input pins located on either the
RXCLK_IN1n/p bank, or the RXCLK_IN2n/p bank. All pins for the
receiver must be kept on the same bank. These True-LVDS banks require
a clean, filtered power supply.
Board Design
Configuration
For detailed board layout guidelines, refer to the High-Speed Board Layout
Guidelines Application Note, AN224, available at www.altera.com.
For detailed board layout guidelines in Stratix devices, refer to the Using
High-Speed Differential I/O Interfaces in Stratix Devices Application Note,
AN202, available at www.altera.com.
For detailed board layout guidelines—including the decoupling scheme
for the high-speed PLLs—in APEX II devices, refer to the Using High-Speed
I/O Standards in APEX II Devices Application Note, AN166, available at
www.altera.com.
1
AN202 and AN166 both specify pin limitations on either side of
the True-LVDS banks, refer to the High-Speed Interface Pin
Location sections of these application notes for further details.
A parallel combination of 0.1, 0.01, and 0.001µF capacitors should be used
to decouple the high-speed PLL power and ground planes.
For the output clock (tdclk), the user should not use the True-LVDS
output clock pins, but should use an appropriate True-LVDS data pair
instead. Clock pins can be treated as data pins, because the SERDES is
preloaded with a binary 1010 pattern that guarantees an appropriate skew
between the clock and data.
5
1
Appendix
Altera Corporation
As for True-LVDS traces running at 1 Gbps, the standard board layout
guidelines for laying out high-speed True-LVDS traces should apply.
Special attention should be given to status channel lines to
ensure setup and hold time requirements are met. Trace lengths
should match.
111
Appendix–Static
Alignment & AC Timing
Static
Alignment
The RapidIO Parallel Physical Layer MegaCore function, in a Stratix or
APEX II device, implements static alignment. The reference material for
this appendix was obtained from the RapidIO Trade Association’s
Enhancements to the RapidIO AC Specification, Item 01-05-001.13.
The timing margin for a statically-aligned system is calculated by
subtracting all of the delays from the overall period of the clock. These
delays include:
■
■
■
Transmitter clock-to-data skews
Receiver sampling windows
Jitter components
3
Serial
Specifications
The remaining time is allocated to the connection between parts. All of the
differential delays between traces—caused by factors such as board
routing, transmission line effects, and connector skews—consume this
margin of time. Static alignment is appropriate for areas where such
factors can be well controlled. For example, the connection between
adjacent devices is generally short, and can be controlled— at layout
time—to within a few millimeters.
Figure 37 shows an example of static alignment.
Figure 37. Static Alignment Timing Diagram
Clock
Data 1
5
Data 2
Altera Corporation
Appendix
Inferred
Sample Clock
Receiver Sampling
Window
113
RapidIO Physical Layer MegaCore Function User Guide
Appendix–Static Alignment & AC Timing
Altera Solutions
The APEX II and Stratix device families have built-in high-speed interface
macros. Using DDR clocking, these macros allow the devices to receive
data at rates exceeding 800 Mbps. Built-in logic within the macros is used
to present this data to the core logic—at lower frequencies—for
subsequent protocol processing. Both device families have a staticallyaligned receiver element. A reference sampling clock is used to recover
the data. This sampling clock is selected at design time, and cannot be
changed when the device is operating. It is possible, however, to
compensate for fixed interconnection skews by sampling different
receivers on skewed phases of the original receiver reference.
AC Timing
Analysis
In the static alignment mode, all data obeys a common set of timing
parameters (e.g. set up and hold times with respect to a sampling clock).
This section describes the timing analysis for various configurations and
components. These timing components are referenced to Figure 38. This
figure shows the timing path as related to the paths followed by the clock
and data signals through the user’s system. Figure 39 on page 115
references the timing values to the clock and data edges.
Figure 38. Timing Analysis Model
Buffer Distortion
(Duty Cycle)
Channel Distortion
Data Dependent Jitter
(Deterministic)
Board Effects
Data Sampling Window
Serializer
for
Serializer
Data
Channel
Buffer Distortion
(Duty Cycle)
Channel-to-Channel
Skew Relative to Clock
Serializer
for
Source
Synchronous
Clock
PLL
Random (Intrinsic)
Jitter
Jitter Attenuation/Pass-Through
plus Intrinsic Jitter
Fast
PLL
Reference Point A
Reference Point B
Clock Source
Jitter
Clock
Source
114
Altera Corporation
Appendix–Static Alignment & AC Timing
RapidIO Physical Layer MegaCore Function User Guide
Figure 39. Timing Diagram
Clock Placement
Internal Clock
Synchronization
Transmitter
Output Data
TCCS
TCCS/2
Receiver
Input Data
SW
APEX II Timing
Tables 57 through 59 analyze the component contributions and derive the
overall timing budget for system contributions between points A and B in
Figure 38 on page 114.
Table 57. APEX II Transmitter to “Specification” Receiver at 500 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
2000 ps
Reference
500 MHz
Transmitter
Clock to data skew
700 ps
Transmit channel-to-channel
skew (TCCS), ref AN166,
Table 12
Clock duty cycle distortion
40 ps
2% of period, ref AN120 Table
6, tDUTY
Data duty cycle distortion
40 ps
2% of period, ref AN120 Table
6, tDUTY
Data jitter (Intrinsic)
36 ps
Internal characterization
5
816 ps
Subtotal
Receiver
460 ps
0.23UI, ref spec 01-05001.13, Table 3-6
Clock duty cycle distortion
120 ps
6% of period, ref spec 01-05001.13, Table 3-6
Altera Corporation
115
Appendix
Time to valid data
RapidIO Physical Layer MegaCore Function User Guide
Appendix–Static Alignment & AC Timing
Table 57. APEX II Transmitter to “Specification” Receiver at 500 Mbps (Part 2 of 2)
Parameter
Total Budget
Data static skew
300 ps
0.15UI, ref spec 01-05001.13, Table 3-6
880 ps
Subtotal
System margin
Reference
0.15UI, ref spec 01-05001.13, Table 3-6
304 ps
Table 58. “Specification” Transmitter to APEX II Receiver at 500 Mbps
Parameter
Total Budget
Clock period
2000 ps
Reference
500 MHz
Transmitter
Time to valid data
370 ps
0.185UI, ref spec 01-05001.13, Table 2-1
Clock duty cycle distortion
80 ps
4% of period, ref spec 01-05001.13, Table 2-1
Data duty cycle distortion
80 ps
4% of period, ref spec 01-05001.13, Table 2-1
Clock to data skew
180 ps
0.09UI, ref spec 01-05001.13, Table 2-1
710 ps
Subtotal
Receiver
Sampling Error
440 ps
SW, ref AN166
Input jitter
40 ps
2% of period, ref AN120 Table
6, Input jitter
480 ps
Subtotal
System margin
810 ps
Table 59. APEX II Transmitter to APEX II Receiver at 500 Mbps(Part 1 of 2)
Parameter
Total Budget
Clock period
2000 ps
Reference
500 MHz
Transmitter
Clock to data skew
116
700 ps
Transmit channel-to-channel
skew (TCCS), ref AN166,
Table 12
Altera Corporation
Appendix–Static Alignment & AC Timing
RapidIO Physical Layer MegaCore Function User Guide
Table 59. APEX II Transmitter to APEX II Receiver at 500 Mbps(Part 2 of 2)
Parameter
Total Budget
Reference
Clock duty cycle distortion
40 ps
2% of period, ref AN120 Table
6, tDUTY
Data duty cycle distortion
40 ps
2% of period, ref AN120 Table
6, tDUTY
Data jitter (Intrinsic)
36 ps
Internal characterization
816 ps
Subtotal
Receiver
Sampling Error
440 ps
SW, ref AN166
Input jitter
40 ps
2% of period, ref AN120 Table
6, Input jitter
480 ps
Subtotal
System margin
704 ps
Stratix Timing
Tables 60 through 62 analyze the component contributions and derive the
overall timing budget for system contributions between points A and B in
Figure 38 on page 114.
Table 60. Stratix Transmitter to "Specification" Receiver at 750 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
1333 ps
Reference
750MHz
Transmitter
200 ps
Ref 1, Table 5-7. Transmit
channel-to-channel skew
(TCCS)
Clock duty cycle distortion
67 ps
Ref 1, Table 5-7. tDUTY 47.552.5%
Data duty cycle distortion
67 ps
Ref 1, Table 5-7. tDUTY 47.552.5%
Data jitter (Intrinsic)
160 ps
Ref 1, Table 5-7. Output jitter
494 ps
Subtotal
Receiver
Time to valid data
373 ps
Ref 2, Table 8-2. X2=0.28UI
Clock duty cycle distortion
80 ps
Ref 2, Table 8-2. DC 47-53%
Altera Corporation
117
5
Appendix
Clock to data skew
RapidIO Physical Layer MegaCore Function User Guide
Appendix–Static Alignment & AC Timing
Table 60. Stratix Transmitter to "Specification" Receiver at 750 Mbps (Part 2 of 2)
Parameter
Total Budget
Data static skew
267 ps
Reference
Ref 2, Table 8-2. tSKEW 0.2UI
720 ps
Subtotal
System margin
119 ps
Table 61. “Specification” Transmitter to Stratix Receiver at 750 Mbps
Parameter
Total Budget
Clock period
1333 ps
Reference
750MHz
Transmitter
Time to valid data
267 ps
Ref 2, Table 8-4. X2=0.2UI
Clock duty cycle distortion
53 ps
Ref 2, Table 8-4. DC 48-52%
Data duty cycle distortion
53 ps
Ref 2, Table 8-4. DC 48-52%
Clock to data skew
133 ps
Ref 2, Table 8-4. tSKEW 0.1UI
506 ps
Subtotal
Receiver
Sampling Error
440 ps
Input jitter
250 ps
Ref 1, Table 5-7. SW
Ref 1, Table 5-7.
690 ps
Subtotal
System margin
137 ps
Table 62. Stratix Transmitter to Stratix Receiver at 750 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
1333 ps
Reference
750MHz
Transmitter
Clock to data skew
200 ps
Ref 1, Table 5-7. Transmit
channel-to-channel skew
(TCCS)
Clock duty cycle distortion
67 ps
Ref 1, Table 5-7. tDUTY 47.552.5%
Data duty cycle distortion
67 ps
Ref 1, Table 5-7. tDUTY 47.552.5%
Data jitter (Intrinsic)
160 ps
Subtotal
118
Ref 1, Table 5-7. Output jitter
494 ps
Altera Corporation
Appendix–Static Alignment & AC Timing
RapidIO Physical Layer MegaCore Function User Guide
Table 62. Stratix Transmitter to Stratix Receiver at 750 Mbps (Part 2 of 2)
Parameter
Total Budget
Reference
Receiver
Sampling Error
440 ps
Ref 1, Table 5-7. SW
Input jitter
250 ps
Ref 1, Table 5-7.
Subtotal
System margin
690 ps
149 ps
References from Tables 60 through 62:
(1)
(2)
Stratix Device Handbook, Volume 2, Chapter 5: Using High-Speed Differential I/O Interface in Stratix Devices.
RapidIO Interconnect Specification, Part IV, Chapter 8: AC Specifications.
f
For further timing information on the RapidIO interface, refer to the
RapidIO Trade Association, RapidIO™ Interconnect Specification, Revision
1.2, June 2002.
■
■
Parallel—Part IV: Physical Layer 8/16 LP-LVDS Specification
Serial—Part VI: Physical Layer 1×/4× LP Serial Specification
5
Appendix
Altera Corporation
119