POS-PHY Level 4
MegaCore Function User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Core Version:
Document Version:
Document Date:
2.0.0
2.0.0 rev1
May 2003
Copyright
POS-PHY Level 4 MegaCore Function User Guide
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-IPPOSPHY4-2.0
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
POS-PHY Level 4 MegaCore® function.
Table 1 shows the user guide revision history.
Table 1. User Guide Revision History
Date
How to Read
this User Guide
Description
May 2003
v2.0.0 rev1
New format, including a “Choosing an Architecture” chapter
and four “Specifications” chapters, one for each buffer mode.
Support for Stratix™ GX and Cyclone™ device families.
August 2002
v1.0.0p4
Fourth revision. Added two parameters for bursts. Support for
Stratix device family.
April 2002
v1.0.0p3
Third revision. Changed version numbering scheme. Added
detailed block diagrams, and new parameters. Added
Appendix containing timing information.
October 2001
v1.02
Second revision. Added description and figures for multi-PHY
support.
August 2001
v1.01
First revision. Made corrections to I/O signals in Tables 5, 6,
and 7.
August 2001
v1.00
Initial release.
The format for the POS-PHY Level 4 MegaCore Function User Guide
v2.0.0 rev1 is quite different from other Altera user guides. It is comprised
of the following chapters:
■
■
■
■
■
About this Core
Choosing an Architecture
Getting Started
Specifications
Appendices
The “About this Core” chapter gives an overview of the core, including
new features and parameters.
Altera Corporation
iii
About this User Guide
POS-PHY Level 4 MegaCore Function User Guide
The “Choosing an Architecture” chapter describes the parameters
according to the flow in the IP Toolbench, and provides a brief
comparison of each one’s benefits and disadvantages.
1
The IP Toolbench is a toolbar from which you can quickly
and easily view documentation, specify core parameters, set
up third-party tools, and generate all files necessary for
integrating the parameterized core into your design. You
can launch the IP Toolbench from within the Quartus® II
software.
1
Altera strongly recommends that you read this chapter
before attempting to configure or use a POS-PHY Level 4
core.
The “Getting Started” chapter describes how to obtain the core, install it,
and configure it using the IP Toolbench.
1
Altera recommends that you read this section prior to using
IP Toolbench because the POS-PHY Level 4 core uses a
different IP Toolbench flow and method of generation than
other Altera MegaCore functions.
The “Specifications” chapters describe the core’s function, FIFO buffer,
signals, etc. This user guide includes four different “Specifications”
chapters—a dedicated chapter for each buffer mode.
1
Because each “Specifications” chapter contains replicated
information, with the exception of the buffer mode
description, you need only read the chapter that applies to
the buffer mode you selected in IP Toolbench. Refer to the
“Choosing an Architecture” chapter for further information.
The first “Appendix” provides links and information concerning pin
constraints and board layout guidelines. The second “Appendix”
describes static and dynamic alignment, including the dynamic phase
alignment macro used in the core and Stratix GX devices.
How to Find
Information
■
■
■
■
iv
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click the binoculars toolbar icon to open the Find dialog
box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
Altera Corporation
About this User Guide
How to Contact
Altera
POS-PHY Level 4 MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For technical support on this product, go to www.altera.com/mysupport.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
You can also contact your local Altera sales office or sales representative.
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v
About this User Guide
Typographic
Conventions
POS-PHY Level 4 MegaCore Function User Guide
The POS-PHY Level 4 MegaCore Function User Guide uses the typographic
conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
vi
Altera Corporation
Contents
PAbout this User Guide ............................................................................................................................ iii
How to Read this User Guide ...................................................................................................... iii
How to Find Information .............................................................................................................. iv
How to Contact Altera ....................................................................................................................v
Typographic Conventions ............................................................................................................ vi
About this Core ............................................................................................................................................13
Release Information .......................................................................................................................13
Device Family Support ..................................................................................................................13
Introduction ....................................................................................................................................14
New in Version 2.0.0 ......................................................................................................................14
Features ...........................................................................................................................................14
Interfaces & Protocols ....................................................................................................................15
SPI-4.2 Interface ......................................................................................................................15
Control Words ................................................................................................................16
Atlantic Interface ....................................................................................................................17
Configuration Options ..................................................................................................................17
Typical Applications ......................................................................................................................18
OpenCore Evaluation ....................................................................................................................19
Choosing an Architecture ........................................................................................................................21
Overview .........................................................................................................................................21
Configuring a POS-PHY Level 4 Core ........................................................................................21
Device Family .........................................................................................................................21
Dynamic Phase Alignment ...................................................................................................22
LVDS Data Rate ......................................................................................................................22
Data Path Width .....................................................................................................................23
Data Flow Direction ...............................................................................................................24
Number of Ports .....................................................................................................................24
Buffer Mode ............................................................................................................................24
Individual FIFO Buffer(s) .............................................................................................25
Shared FIFO Buffer with Embedded Addressing .....................................................29
Virtual FIFO Segments with Buffer Management ....................................................32
FIFO Buffer Size per Port ......................................................................................................34
Almost Empty & Almost Full ..............................................................................................34
MaxBurst1 & MaxBurst2 .......................................................................................................36
Atlantic Data Width ...............................................................................................................36
FIFO Buffer Threshold Low & FIFO Buffer Threshold High ..........................................37
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vii
POS-PHY Level 4 MegaCore Function User Guide
Contents
Transmit Bandwidth Optimization .....................................................................................38
Burst Mode & Burst Size .......................................................................................................40
Multiple Continues ................................................................................................................41
Maximum Training Sequence Interval ...............................................................................43
Training Pattern Repetitions ................................................................................................44
Status Channel Clock Edge ...................................................................................................44
Calendar Multiplier ...............................................................................................................44
Getting Started ............................................................................................................................................47
Hardware & Software Requirements ..........................................................................................47
Design Flow ....................................................................................................................................47
Download & Install the Core ........................................................................................................48
Downloading the POS-PHY Level 4 MegaCore Function ...............................................48
Installing the POS-PHY Level 4 MegaCore Function Files ..............................................48
POS-PHY Level 4 MegaCore Function Walkthrough ..............................................................49
Create a New Quartus II Project ..........................................................................................50
Launch the IP Toolbench ......................................................................................................51
Step 1: Select Configuration .................................................................................................54
Step 2: Set Up Simulation ......................................................................................................61
Step 3: Generate ......................................................................................................................62
Implementing the System .....................................................................................................63
Instantiating a Design File in AHDL ...........................................................................64
Simulate the Design .......................................................................................................................65
Using the Verilog HDL Demonstration Testbench ...........................................................65
Receiver Testbench Description ...................................................................................65
Transmitter Testbench Description .............................................................................68
Using the Visual IP Software ................................................................................................71
Synthesize, Compile & Place & Route ........................................................................................71
Using Third-Party EDA Tools for Synthesis ......................................................................71
Using the Quartus II Development Tool for Compilation & Place-and-Route ............72
Set Up Licensing .............................................................................................................................73
Append the License to Your license.dat File ......................................................................73
Specify the Core’s License File in the Quartus II Software ..............................................74
Perform Post-Route Simulation ...................................................................................................74
Specifications – Single-PHY ..................................................................................................................77
Overview .........................................................................................................................................77
Functional Description ..................................................................................................................77
Receiver ...................................................................................................................................77
Transmitter ..............................................................................................................................77
Receiver ...........................................................................................................................................77
Clock & Data ...........................................................................................................................78
High-Speed Interface & Deserializer ..........................................................................79
Control Word Processing & DIP-4 ..............................................................................80
SOP Alignment & Atlantic Conversion ......................................................................81
FIFO Buffer Status & Management .............................................................................81
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Altera Corporation
Contents
POS-PHY Level 4 MegaCore Function User Guide
FIFO Buffer .............................................................................................................................82
Atlantic FIFO Error Checker ........................................................................................83
Missing SOP............................................................................................................ 83
Missing EOP ........................................................................................................... 84
Atlantic FIFO Buffer ......................................................................................................85
Crossing Clock Domains....................................................................................... 85
Converter Block ..............................................................................................................85
Signals ..............................................................................................................................................85
Transmitter ......................................................................................................................................88
Clock & Data ...........................................................................................................................88
High-Speed Interface & Serializer ...............................................................................89
Control Word Insertion & DIP-4 .................................................................................90
Scheduler .........................................................................................................................91
Training Pattern Insertion ............................................................................................91
FIFO Buffer Status & Management .............................................................................92
FIFO Buffer .............................................................................................................................92
Atlantic FIFO Buffer ......................................................................................................93
Signals ..............................................................................................................................................93
Specifications – Multi-PHY with Individual FIFO Buffer per Port .............................................97
Overview .........................................................................................................................................97
Functional Description ..................................................................................................................97
Receiver ...................................................................................................................................97
Transmitter ..............................................................................................................................97
Receiver ...........................................................................................................................................97
Clock & Data ...........................................................................................................................99
High-Speed Interface & Deserializer ........................................................................100
Control Word Processing & DIP-4 ............................................................................101
SOP Alignment & Atlantic Conversion ....................................................................101
FIFO Buffer Status & Management ...........................................................................102
FIFO Buffer ...........................................................................................................................102
Atlantic FIFO Error Checker ......................................................................................103
Missing SOP.......................................................................................................... 104
Missing EOP ......................................................................................................... 104
Atlantic FIFO Buffer ....................................................................................................105
Crossing Clock Domains..................................................................................... 105
Converter Block ............................................................................................................106
Signals ............................................................................................................................................106
Transmitter ....................................................................................................................................109
Clock & Data .........................................................................................................................111
High-Speed Interface & Serializer .............................................................................111
Control Word Insertion & DIP-4 ...............................................................................113
Scheduler .......................................................................................................................113
Training Pattern Insertion ..........................................................................................113
FIFO Buffer Status & Management ...........................................................................114
FIFO Buffer ...........................................................................................................................114
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POS-PHY Level 4 MegaCore Function User Guide
Contents
Atlantic FIFO Buffer ....................................................................................................115
Converter Block ............................................................................................................115
Signals ............................................................................................................................................115
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing ................119
Overview .......................................................................................................................................119
Functional Description ................................................................................................................119
Receiver .................................................................................................................................120
Transmitter ............................................................................................................................120
Receiver .........................................................................................................................................120
Clock & Data .........................................................................................................................121
High-Speed Interface & Deserializer ........................................................................122
Control Word Processing & DIP-4 ............................................................................123
SOP Alignment & Atlantic Conversion ....................................................................123
FIFO Buffer Status & Management ...........................................................................124
FIFO Buffer ...........................................................................................................................124
Atlantic FIFO Error Checker ......................................................................................125
Missing SOP.......................................................................................................... 126
Missing EOP ......................................................................................................... 127
Atlantic FIFO Buffer ....................................................................................................127
Converter Block ............................................................................................................128
Signals ............................................................................................................................................128
Transmitter ....................................................................................................................................130
Clock & Data .........................................................................................................................131
High-Speed Interface & Serializer .............................................................................132
Control Word Insertion & DIP-4 ...............................................................................133
Scheduler .......................................................................................................................134
Training Pattern Insertion ..........................................................................................135
FIFO Buffer Status & Management ...........................................................................135
FIFO Buffer ...........................................................................................................................136
Atlantic FIFO Buffer ....................................................................................................137
Converter Block ............................................................................................................137
Signals ............................................................................................................................................137
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management .141
Overview .......................................................................................................................................141
Functional Description ................................................................................................................141
Receiver .................................................................................................................................141
Transmitter ............................................................................................................................141
Receiver .........................................................................................................................................141
Clock & Data .........................................................................................................................142
High-Speed Interface & Deserializer ........................................................................143
Control Word Processing & DIP-4 ............................................................................144
SOP Alignment & Atlantic Conversion ....................................................................145
FIFO Buffer Status & Management ...........................................................................145
Buffer Manager .............................................................................................................................146
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Altera Corporation
Contents
POS-PHY Level 4 MegaCore Function User Guide
Features .................................................................................................................................146
Functional Description ........................................................................................................146
Start/End of Packet Error Checking .........................................................................147
Memory Structure ........................................................................................................148
Write ...................................................................................................................... 149
Read ....................................................................................................................... 150
Next Available Address FIFO Buffer ........................................................................151
Status ..............................................................................................................................151
Dual Clock Domain Status .................................................................................151
Polled Status Outputs.......................................................................................... 151
Underflow ............................................................................................................. 152
Initialization ..................................................................................................................152
Atlantic Interface ..................................................................................................................152
Signals ............................................................................................................................................159
Transmitter ....................................................................................................................................162
Clock & Data .........................................................................................................................163
High-Speed Interface & Serializer .............................................................................163
Control Word Insertion & DIP-4 ...............................................................................164
Scheduler .......................................................................................................................165
Training Pattern Insertion ..........................................................................................165
FIFO Buffer Status & Management ...........................................................................166
Buffer Manager .............................................................................................................................166
Features .................................................................................................................................166
Functional Description ........................................................................................................167
Start/End of Packet Error Checking .........................................................................168
Memory Structure ........................................................................................................169
Write ...................................................................................................................... 169
Read ....................................................................................................................... 170
Next Available Address FIFO Buffer ........................................................................171
Status ..............................................................................................................................171
Dual Clock Domain Status ................................................................................. 171
Polled Status Outputs.......................................................................................... 172
Overflow ............................................................................................................... 172
Initialization ..................................................................................................................172
Atlantic Interface ..................................................................................................................173
Signals ............................................................................................................................................180
Appendix–Pin Constraints & Board Design .....................................................................................183
Pin Constraints .............................................................................................................................183
Board Design Configuration ......................................................................................................183
Appendix–Static & Dynamic Phase Alignment ..............................................................................185
Static vs Dynamic Alignment .....................................................................................................185
Static Alignment ...................................................................................................................185
Dynamic Alignment ............................................................................................................186
Altera Solutions ............................................................................................................................187
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POS-PHY Level 4 MegaCore Function User Guide
Contents
Static Alignment ...................................................................................................................187
Dynamic Phase Alignment (DPA) .....................................................................................188
Features .................................................................................................................................188
Functional Description ........................................................................................................189
ALTLVDS_Receiver Megafunction ...........................................................................189
Byte Aligner ..................................................................................................................190
POS-PHY Level 4 Training Pattern ................................................................... 191
8:4 Deserializer .............................................................................................................191
Signals ....................................................................................................................................192
AC Timing Analysis ....................................................................................................................192
APEX II Timing ....................................................................................................................194
Stratix Timing .......................................................................................................................196
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Altera Corporation
About this Core
1
Table 4 provides information about this release of the POS-PHY Level 4
MegaCore function.
Table 4. POS-PHY Level 4 MegaCore Function Release Information
Item
Description
Version
Device Family
Support
2.0.0
Release Date
May 2003
Ordering Code
IP-POSPHY4
Product ID
0088
Vendor ID
6AF7
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus II software.
Table 5 shows the level of support offered by the POS-PHY Level 4
MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
Cyclone
Full (32-bit data path width configurations only)
Stratix GX
Preliminary
Stratix
Full
™
Altera Corporation
Support
APEX II
Full (128-bit data path width configurations only)
Other device families
No support
13
About this Core
Release
Information
POS-PHY Level 4 MegaCore Function User Guide
Introduction
About this Core
The packet over SONET/SDH physical layer (POS-PHY) Level 4 interface,
first developed by the SATURN® Development Group, was later adopted
by the Optical Internetworking Forum (OIF) as the System Packet
Interface Level 4—Phase 2 (SPI-4.2). Therefore, POS-PHY Level 4 and SPI4.2 are synonymous.
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for
high-speed cell and packet transfers between physical (PHY) and linklayer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS
solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY
connection in multi-gigabit applications, including: ATM and packet over
SONET/SDH (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel
Gbit Ethernet.
New in Version
2.0.0
■
■
■
■
■
Features
■
■
■
■
■
■
■
■
■
14
Stratix GX device family support
–
Including integrated dynamic phase alignment (DPA) hardware
module, and performance up to 1 gigabit per second (Gbps)
32- or 64-bit internal data path width for significantly reduced LE
consumption
Multi-PHY burst mode support
Small packet support always enabled
Cyclone device family support (32-bit data path width configurations
only)
Supports up to 1 Gbps on each LVDS channel with integrated DPA
Operates in single-PHY (SPHY), or multi-PHY (MPHY) mode with
up to 256 ports
Configurable data path width—affecting the core size and speed—for
various performance requirements and applications:
–
128 bits—full size
–
64 bits—half size
–
32 bits—quarter rate
Fixed start of packet (SOP) alignment to the most significant byte lane
eases subsequent packet processing
Configurable for receive or transmit directions
First-in first-out (FIFO) buffer status management and indications
Configurable FIFO buffer modes
–
SPHY with an individual FIFO buffer
–
MPHY with an individual FIFO buffer per port
–
MPHY with a shared FIFO buffer and embedded addressing
–
MPHY with virtual FIFO segments per port and buffer
management
Configurable Atlantic slave interface data width of 32, 64, 128, or 256
bits for simple connection to other Atlantic interface compatible cores
Configurable support for 64- or 128-byte contiguous burst mode for
optimized use with network processors
Altera Corporation
About this Core
POS-PHY Level 4 MegaCore Function User Guide
■
1
About this Core
Interfaces &
Protocols
Compliant with all applicable standards, including:
–
Optical Internetworking Forum (OIF), System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and
Link Layer Devices, OIF-SPI4-02.0, January 2001.
–
PMC-Sierra Inc., POS-PHYTM Level 4 A Saturn Packet and Cell
Interface Specification for OC-192 SONET/SDH and 10 GB/s
Ethernet Applications, Issue 5 (Draft): June 2000.
–
Altera Corporation, AtlanticTM Interface Specification.
Two interfaces support the POS-PHY Level 4 core: the SPI-4.2 interface
and the Atlantic interface. While multiple Atlantic interfaces can be used,
the SPI-4.2 interface can only support a single transmitter and/or a single
receiver.
SPI-4.2 Interface
The SPI-4.2 interface is an external interface protocol developed by the
Optical Internetworking Forum (OIF). The POS-PHY Level 4 core uses
this protocol to pass data and control words in both the transmitter (slave
source) and receiver (master sink) directions. It features a high-speed data
portion and a FIFO buffer status portion. The high-speed portion
comprises a 16-bit data bus, a 1-bit control line, and a double data rate
(DDR) clock. The FIFO buffer status portion comprises a 2-bit status
channel and a clock. The interface can be a PHY-link, link-link, link-PHY,
or PHY-PHY connection.
1
For the purpose of this document, the POS-PHY Level 4 core is
implemented as a link-layer device.
Figure 1 shows an SPI-4.2 PHY-link configuration.
Figure 1. SPI-4.2 Top Level View
tdclk
tctl
Transmitter
Source
Link Layer
tdat[15:0]
tsclk
Receiver
Sink
PHY Layer
tstat[1:0]
rdclk
rctl
Receiver
Sink
Link Layer
rdat[15:0]
rsclk
Transmitter
Source
PHY Layer
rstat[1:0]
Altera Corporation
15
POS-PHY Level 4 MegaCore Function User Guide
About this Core
Control Words
In compliance with the SPI-4.2 specification, the receiver and transmitter
do not receive/send successive SOP signals less than eight cycles apart. If
the packet size is small (twelve bytes or less), the transmitter pads the
packet with IDLE control words. Table 6 shows a five-byte packet as an
example.
Table 6. Five-Byte Packet Padded with IDLE Control Words
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word 8
Word N
SOP
B1 B2
B3 B4
B5 NULL
EOP
IDLE
IDLE
IDLE
SOP
...
Table 7 shows the contents of control words, as specified by the SPI-4.2
specification.
Table 7. Control Word Contents
Bit Position
Label
Description
15
Type
Control word type
When 0: IDLE or training control word
When 1: Payload control word (payload transfer immediately follows the control
word)
14:13
EOPS
End of packet (EOP) status
When 00: Not an EOP
When 01: EOP abort (application specific error condition)
When 10: EOP normal condition (2 bytes valid)
When 11: EOP normal condition (1 byte valid)
12
SOP
Start of packet (SOP)
Set to 1 if the payload transfer immediately following the control word
corresponds to the start of a packet. Set to 0 otherwise.
Set to 0 for all training and IDLE control words.
11:4
ADDR
8-bit port address of the payload data that follows the control word.
Set to all 0s for IDLE control words
Set to all 1s for training control words
3:0
DIP-4
4-bit DIP odd parity computed over the current control word and preceding data
words (if any) following the last control word.
f
16
For further information on this interface, refer to the System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer
Devices, available at www.oiforum.com.
Altera Corporation
About this Core
POS-PHY Level 4 MegaCore Function User Guide
Atlantic Interface
1
The Atlantic interface provides a connection between the FIFO buffer and
neighboring logic. The width of the output bus (to FIFO buffer) is always
as wide as, or wider than, the width of the input bus (Atlantic interface).
The FIFO buffer is used for crossing the clock domain from the Atlantic
interface to the POS-PHY Level 4 reference clock.
f
Configuration
Options
For further information on this interface, refer to the Atlantic Interface
Functional Specification, available at www.altera.com.
Table 8 lists the options available to generate all configurations of the
POS-PHY Level 4 MegaCore function.
Table 8. Configuration Options (Part 1 of 2)
Options
Parameters
Choices
Device family
DEVICE
Stratix GX, Stratix, APEX II, or Cyclone (1)
Dynamic phase alignment
DPA
v (2)
LVDS data rate
LVDSDR
up to 1000 Mbps
Data path width
DPATHW
32, 64, or 128 bits
Data flow direction
DFLOW
RX or TX
Number of ports
NPORTS
1 - 256 (3)
Buffer mode
BUFMODE
Individual FIFO Buffer per Port, Shared FIFO
Buffer with Embedded Addressing, or Virtual FIFO
Segments with Buffer Management (4)
FIFO buffer size per port
FSIZE
512 to 32,768 bytes
Almost empty
AE
0<AE<AF bytes
Almost full
AF
AE<AF<FSIZE bytes
MaxBurst1
MB1
8 - 127 (16-byte units)
MaxBurst2
MB2
8 - 127 (16-byte units)
Atlantic data width
ATLDW
32, 64, 128, or 256 bits
FIFO threshold low
FTL
0<FTL<FSIZE bytes
FIFO threshold high
FTH
0<FTH<FSIZE bytes
Transmit bandwidth optimization
TXBOPT
v (5) (6)
Burst mode
BRSTMODE
v (5) (7)
Burst size
BRSTSIZE
64 or 128 bytes
Altera Corporation
17
About this Core
The Atlantic interface is a full-duplex synchronous protocol supporting
both packets and cells. The POS-PHY Level 4 core is an Atlantic interface
slave using a configurable data path of 32, 64, 128, or 256 bits to transfer
packets on the user side.
POS-PHY Level 4 MegaCore Function User Guide
About this Core
Table 8. Configuration Options (Part 2 of 2)
Options
Parameters
Multiple continues
Choices
v (6) (8)
MCONT
Maximum training sequence interval (MaxT) MAXT
8 - 32,767 (16-byte cycles) (5)
Training pattern repetitions (ALPHA )
ALPHA
0 - 255 (5)
Status channel clock edge
STATEDGE
Positive or Negative
Calendar multiplier
CALM
1 - 255
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Only available for certain 32-bit configurations.
Available for Stratix GX devices only.
If one port is chosen, the core operates in SPHY mode; if 2 to 256 ports are chosen, the core operates in MPHY mode.
The buffer manager mode is not available for 32 and 64-bit configurations, and is limited to a maximum of 16 ports
in 128-bit configurations.
Only applicable for transmitter configurations.
Not available for 32 and 64-bit buffer manager mode configurations. Enabled by default for all other 32-bit
configurations.
Not available in the buffer manager mode, or for 32-bit configurations.
Only applicable for receiver configurations.
f
Typical
Applications
See “Configuring a POS-PHY Level 4 Core” on page 21, for a full
description of these parameters, and their inter-dependencies
In compliance with the SPI-4.2 interface specification, the POS-PHY Level
4 core allows users to implement both transmit and receive link- and PHYside support.
Figure 2 shows a full-duplex POS-PHY Level 4 core configured for the
link layer, in an Altera FPGA device.
Figure 2. POS-PHY Level 4 Core as Link Layer Configuration
SPI-4.2 Interface
OC-192
POS Framer
or
10 GbitE MAC
Atlantic Interface
POS-PHY Level 4
Receiver
POS-PHY Level 4
Transmitter
User Packet
Processing
Switch
Interface
Switch
Fabric
FPGA
18
Altera Corporation
About this Core
POS-PHY Level 4 MegaCore Function User Guide
Figure 3 shows a full-duplex POS-PHY Level 4 core configured for the
PHY layer, in an Altera FPGA device.
1
About this Core
Figure 3. POS-PHY Level 4 Core as PHY Layer Configuration
Atlantic Interface
OC-192 or
10 GbitE
POS-PHY Level 4
Transmitter
Framer or MAC
Logic
FPGA
OpenCore
Evaluation
Altera Corporation
SPI-4.2 Interface
POS-PHY Level 4
Receiver
Packet
Classifier
The OpenCore® feature lets you test-drive Altera MegaCore functions for
free using the Quartus II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
19
Choosing an Architecture
Overview
This chapter is intended to help FPGA design engineers and system
designers choose the appropriate POS-PHY Level 4 core configuration for
their application.
1
Configuring a
POS-PHY
Level 4 Core
This guide assumes you have a basic knowledge of the SPI-4.2
protocol, and of the system in which the POS-PHY Level 4 core
will be used.
To properly configure the POS-PHY Level 4 core, you must determine
your design’s constraints and performance requirements.
This section describes the parameters available to configure a POS-PHY
Level 4 MegaCore function, as well as the benefits of different options. The
parameters are ordered as they appear in the IP Toolbench.
1
Not all parameters are supported by, or are relevant for, every
configuration. Altera recommends that you run the IP Toolbench
to select your parameters, after you have reviewed this chapter
of the user guide.
Device Family
The POS-PHY Level 4 MegaCore function can be targeted to Stratix GX,
Stratix, APEX II, and Cyclone devices.
The Stratix GX device family with its faster LVDS rates (up to 1 Gbps), and
its embedded dynamic phase alignment circuitry makes it ideal for
standard SPI-4.2 applications (i.e., 622 Mbps and above).
Altera Corporation
21
2
Choosing an
Architecture
Care must be taken when selecting a configuration, to ensure
compatibility with other SPI-4.2 devices, and to meet system
requirements. As with any design, there are certain trade-offs between
features, size, performance and target device.
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
The Stratix and APEX II devices offer a high-speed serial interface (HSSI)
combined with serialization/deserialization (SERDES) capability and
frequency multiplication all in one circuit. These families are applicable to
systems with matched trace lengths connecting the devices directly
without skew inducing components, such as connectors, in the SPI-4.2
path.
The Cyclone device family offers a low-cost alternative for non-standard
quarter-rate (32-bit) applications running at speeds of up to 250 Mbps.
Dynamic Phase Alignment
As high-speed interfaces with source-synchronous clocking schemes
approach 700 Mbps and beyond, the margin for clock-to-channel and
channel-to-channel skew contracts significantly. To stay within the
permitted skew, designers must use precise printed circuit board (PCB)
design techniques because the slightest mismatch in trace lengths or the
use of connectors could result in erroneous data transfer. Additionally,
skew inducing effects such as process, voltage, and temperature
variations compound the problem, making static phase alignment
techniques ineffective.
The SPI-4.2 protocol specifies a training sequence which can be used by
receivers to correct skew up to +/- 1 bit period. This function is commonly
referred to as dynamic phase alignment (DPA). Recommended for data
rates exceeding 622 Mbps, and considered essential for high-quality
signaling at 800 Mbps, or across connectors at 700 Mbps. DPA is only
available in Stratix GX devices.
LVDS Data Rate
Typical SPI-4.2 applications require performance in the range of 10 to
16 Gbps—or 622 Mbps to 1 Gbps on each LVDS channel. The speed at
which your design runs the interface ultimately determines the type of
architecture you require. The speed also impacts the device family and
speed grade requirement.
The LVDS data rate parameter offers LVDS data rates of up to 1 Gbps for
Stratix GX devices, up to 840 Mbps for Stratix and APEX II devices, and
up to 250 Mbps for Cyclone devices.
For a receiver, this parameter specifies the data rate into the FPGA, on
each LVDS pair. For a transmitter, this parameter specifies the data rate
out of the FPGA, on each LVDS pair.
22
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
This parameter eliminates the need to run the ALTLVDS configuration
wizard. The POS-PHY Level 4 core’s IP Toolbench precompiles all of this
information in a file. Only the data rate field is unknown because it is
design specific. Once you input all of your required parameters, including
the LVDS data rate, IP Toolbench can generate your configuration, and
create the associated ALTLVDS file.
For example, to configure a transmitter with a data rate of 700 Mbps on
the tdat line, enter 700 in the LVDS Data Rate field of IP Toolbench.
2
Data Path Width
■
Full size — 128 bits running at a frequency of 1/8 the LVDS data rate
■
Half size — 64 bits running at 1/4 the LVDS data rate
■
Quarter rate — 32 bits running at 1/2 the LVDS data rate (for nonstandard applications—maximum 250 Mbps)
1
The core clock target fMAX depends on the LVDS data rate and
data path width parameters.
For example, configurations with a data path width of 64 bits running at
700 Mbps use approximately 50 – 60% of the logic elements (LEs) of a
similarly parameterized 128-bit configuration. The trade-off, however, is
that the 64-bit configuration requires an internal fMAX of 175 MHz, while
the 128-bit configuration requires only 87.5 MHz, and that the 64-bit
configuration does not support the higher data rates required by some
applications. See Tables 10 through 13 on pages 27, 28, 31, and 33,
respectively, for approximate LE usage of the major POS-PHY Level 4
core configurations. The SPI-4.2 interface can be used for OC-48
applications running the input and outputs (I/Os) at a quarter of the
normal SPI-4.2 data rates. The quarter-rate option (data path width = 32
bits) is intended for applications that run the SPI-4.2 interface at nonstandard low rates (approximately 250 Mbps per LVDS channel). Where
applicable, this configuration parameter yields a minimum LE
consumption.
Altera Corporation
23
Choosing an
Architecture
Internally, the POS-PHY Level 4 core deserializes each LVDS channel in
order to operate at internal frequencies supported by the Stratix GX,
Stratix, APEX II, and Cyclone device families. The data path width
parameter affects two important aspects of the core: size and performance.
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Data Flow Direction
Typical designs may include one or more receivers and/or one or more
transmitters per FPGA. The POS-PHY Level 4 core functions either as a
transmitter (TX) or as a receiver (RX). The transmitter is always
configured as the source, where data flows from the Atlantic interface to
the SPI-4.2 interface. The receiver is always configured as the sink, where
data flows from the SPI-4.2 interface to the Atlantic interface.
Since the receiver and transmitter configurations are separate building
blocks in a design, with no dependency on each other, parameters are
selected independently.
1
In order for the core to act as a full-duplex, bidirectional
transceiver, you need to instantiate one of each
configuration.
Number of Ports
The SPI-4.2 protocol supports from 1 to 256 individual port addresses.
When interfacing to a 10-channel Gbit Ethernet MAC device, for example,
the number of ports would be 10.
The number of ports parameter determines the number of port addresses
supported by the POS-PHY Level 4 core, up to 256 individual ports to be
connected to an Atlantic interface.
By selecting the number of ports, the user determines the mode of
operation: single-PHY—1 port, or multi-PHY—2 to 256 ports.
In SPHY configurations, address polling or decoding is not required. A
single user-selectable size FIFO buffer is connected to the Atlantic
interface(s).
In MPHY configurations, the SPI-4.2 interface performs priority
scheduling, with priorities assigned based on FIFO buffer status. A hardcoded address is held for each port.
1
The POS-PHY Level 4 core does not currently support
asymmetrical ports. For example, two OC-48 ports and eight
OC-12 ports are not currently supported.
Buffer Mode
The type of FIFO buffer used is an important architectural consideration.
The POS-PHY Level 4 core is available in four buffer modes.
24
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
■
■
■
■
SPHY with an individual FIFO buffer
MPHY with an individual FIFO buffer per port
MPHY with a shared FIFO buffer and embedded addressing
MPHY with virtual FIFO segments per port and buffer management
1
The buffer management mode is not available for 32- and
64-bit configurations.
Table 9 shows the different buffer modes that are available for all data
path width configurations
2
Table 9. Buffer Modes
SPHY
MPHY
Individual FIFO
Buffer
Individual FIFO
Buffer per Port
Shared FIFO Buffer & Virtual FIFO Buffer Segments
Embedded Addressing
& Buffer Management
128 bits
Available
Available
Available
Available
64 bits
Available
Available
Available
Not available
32 bits
Available
Available
Available
Not available
Individual FIFO Buffer(s)
The individual FIFO buffer(s) parameter configures the POS-PHY Level 4
core to use a single Atlantic FIFO buffer for each port. Therefore, there are
as many Atlantic FIFO buffers of the same depth and width—each with a
unique Atlantic interface on the user end—as the number of ports chosen.
This buffer implementation is used in all SPHY (number of ports = 1)
configurations.
Figure 4 shows example receive and transmit single-PHY configurations.
Figure 4. Single-PHY Configurations
SPI-4.2 Interfaces
Altera Corporation
Atlantic Interfaces
Atlantic Interfaces
POS-PHY Level 4
Receiver
Individual
FIFO Buffer
POS-PHY Level 4
Transmitter
Individual
FIFO Buffer
25
Choosing an
Architecture
Data Path
Width
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
For MPHY configurations, the maximum number of ports supported by
the individual FIFO buffers mode is limited to:
■
■
■
f
4 ports for full-size (128 bits) configurations
10 ports for half-size (64 bits) configurations
10 ports for quarter-rate (32 bits) configurations.
See Table 14 on page 34.
Figure 5 shows example receive and transmit four-port multi-PHY with
four individual FIFO buffers configurations.
Figure 5. Multi-PHY with Four Individual FIFO Buffers Configurations
Atlantic Interfaces
Atlantic Interfaces
Individual
FIFO Buffer
SPI-4.2 Interface
Individual
FIFO Buffer
POS-PHY Level 4
Receiver
Individual
FIFO Buffer
Individual
FIFO Buffer
Individual
FIFO Buffer
SPI-4.2 Interface
Individual
FIFO Buffer
POS-PHY Level 4
Transmitter
Individual
FIFO Buffer
Individual
FIFO Buffer
26
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
The advantage of the individual buffer mode is that each Atlantic
interface can be accessed in parallel and independently, thus avoiding
head-of-line blocking.
Head-of-line blocking occurs when the port for a data burst at the head of
the buffer queue is not free (i.e., it is satisfied or as reached FTH). This data
burst blocks the queue and does not allow the bursts behind it to proceed
even if their respective ports are free (i.e., are hungry or starving, or have
reached FTL).
Since the number of individual FIFO buffers increases the LE utilization
directly, this buffer mode is not well suited for applications with a large
number of ports. See Table 10 for an estimate of LE consumption for a
selection of SPHY configurations. See Table 11 on page 28 for an estimate
of LE consumption for a selection of MPHY configurations.
Table 10 lists the resources and internal core speeds of a selection of SPHY
implementations. For receiver implementations, the multiple continue
parameter is enabled; the burst mode parameter is not enabled. For
transmitter implementations, the transmit bandwidth optimization and
burst mode parameters are not enabled. These results were obtained
using the Quartus II software, version 2.2 SP2, for Stratix GX devices. For
128- and 32-bit configurations, the device used is an EP1SGX25DF1020C6; for 64-bit configurations, the device used is an EP1SGX25DF1020-C5.
Table 10. Single-PHY Performance (Part 1 of 2)(Part 1 of 2)
Parameters
Stratix GX (DPA Enabled)
LEs
Memory
fMAX
(MHz)
M512
M4K
M-RAM
976
0
10
0
193
64-bit data path, 4,096- byte
FIFO buffer
3,673
0
13
0
184
128-bit data path, 4,096-byte
FIFO buffer
9,044
0
8
0
117
Receiver
32-bit data path, 4,096-byte FIFO
buffer
Altera Corporation
27
2
Choosing an
Architecture
For POS-PHY Level 4 core transmitters, scheduling logic decodes the
incoming status channel and decides which FIFO buffer (port) to serve.
For POS-PHY Level 4 core receivers, the Atlantic-side user logic may read
from each FIFO buffer in parallel. The relative fill level (starving, hungry,
satisfied) for each port is reflected in the SPI-4.2 interface FIFO buffer
status channel transmitted by the POS-PHY Level 4 core receiver.
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Table 10. Single-PHY Performance (Part 2 of 2)(Part 2 of 2)
Parameters
Stratix GX (DPA Enabled)
LEs
Memory
M512
M4K
M-RAM
fMAX
(MHz)
Transmitter
f
32-bit data path, 4,096-byte FIFO
buffer
1,483
0
8
0
150
64-bit data path, 4,096-byte FIFO
buffer
2,912
0
16
0
204
128-bit data path, 4,096-byte
FIFO buffer
3,241
0
8
0
142
For detailed description, refer to the “Specifications – Single-PHY”
chapter.
Table 11 lists the resources and internal core speeds of a selection of
MPHY implementations. For receiver implementations, the multiple
continue parameter is enabled; the burst mode parameter is not enabled.
For transmitter implementations, the transmit bandwidth optimization
and burst mode parameters are not enabled. These results were obtained
using the Quartus II software version 2.2 SP2, for Stratix GX devices. For
128- and 32-bit configurations, the device used is an EP1SGX25DF1020C6; for 64-bit configurations, the device used is an EP1SGX25DF1020-C5.
Table 11. Multi-PHY with Individual FIFO Buffers Performance (Part 1 of
2)(Part 1 of 2)
Parameters
Stratix GX
LEs
Memory
M512
M4K
M-RAM
fMAX
(MHz)
Receiver
28
32-bit data path, 4-port, 4,096
bytes per port FIFO buffer
2,689
0
40
0
198
64-bit data path, 4-port, 4,096
bytes per port FIFO buffer
6,027
0
38
0
178
128-bit data path, 4-port, 4,096
bytes per port FIFO buffer
17,650
0
45
0
112
32-bit data path, 10-port, 2,048
bytes per port FIFO buffer
5,433
10
40
0
197
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Table 11. Multi-PHY with Individual FIFO Buffers Performance (Part 2 of
2)(Part 2 of 2)
Parameters
Stratix GX
LEs
64-bit data path, 10-port, 2,048
bytes per port FIFO buffer
9,428
Memory
M512
M4K
M-RAM
0
86
0
fMAX
(MHz)
177
2
Transmitter
4,377
0
32
0
110
64-bit data path, 4-port, 4,096
bytes per port FIFO buffer
6,391
0
64
0
168
128-bit data path, 4-port, 4,096
bytes per port FIFO buffer
8,564
0
32
0
122
32-bit data path, 10-port, 2,048
bytes per port FIFO buffer
9,062
0
40
0
99
64-bit data path, 10-port, 2,048
bytes per port FIFO buffer
12,898
0
60
0
167
For detailed description, refer to the “Specifications – Multi-PHY with
Individual FIFO Buffer per Port” chapter.
Shared FIFO Buffer with Embedded Addressing
The shared FIFO buffer with embedded addressing mode can be used in
MPHY applications. In this mode, multiple ports share a single Atlantic
FIFO buffer, with a single Atlantic interface, and an 8-bit address field that
supports up to 256 ports. While this buffer mode yields the least LE
consumption and highest performance (fMAX), it can lead to head of line
blocking.
For POS-PHY Level 4 core receivers, this means that the Atlantic-side
logic cannot selectively pick a port to access. Instead, data bursts from all
ports are stored collectively into one physical buffer, and the ordering of
the data bursts is maintained in the order in which they were received on
the SPI-4.2 bus. The FIFO buffer status channel generated by the POS-PHY
Level 4 receiver reflects the relative fill level of the physical FIFO buffer,
for all ports as opposed to a per-port basis.
Figure 6 on page 30 shows an example multi-PHY receiver sharing a FIFO
buffer with embedded addressing.
Altera Corporation
29
Choosing an
Architecture
f
32-bit data path, 4-port, 4,096
bytes per port FIFO buffer
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Figure 6. MPHY Receiver with Shared FIFO Buffer & Embedded Addressing
SPI-4.2 Interface
Atlantic Interface
Atlantic Interface
POS-PHY Level 4
Receiver
FIFO Buffer
Address
Data
Address
For POS-PHY Level 4 core transmitters, the order in which data bursts are
transmitted on the SPI-4.2 bus is ultimately dictated by the Atlantic-side
logic. When using this mode, user-defined logic is required to schedule
the ports to be transmitted. The data burst sent is the next data burst in the
FIFO buffer regardless of its port. In order to prevent overflows on the
receiving end, the POS-PHY Level 4 transmitter decodes the incoming
FIFO buffer status channel, and makes its transmission decision based on
the worst-case port. For example, if one port out of ten is satisfied, the
transmitter does not transmit because the FIFO buffer may contain data
bursts for that port. Thus, the FIFO status of one port can block
transmission to other ports in the system.
Figure 7 shows an example MPHY transmitter sharing a FIFO buffer with
embedded addressing.
Figure 7. MPHY Transmitter with Shared FIFO Buffer & Embedded Addressing
SPI-4.2 Interface
Atlantic Interface
POS-PHY Level 4
Transmitter
30
FIFO Buffer
Address
Atlantic Interface
Data
Address
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Table 12 on page 31 lists the resources and internal core speeds for a
selection of MPHY with a shared FIFO buffer with embedded addressing
implementations. For receiver implementations, the multiple continue
parameter is enabled; the burst mode parameter is not enabled. For
transmitter implementations, the transmit bandwidth optimization and
burst mode parameters are not enabled. These results were obtained
using the Quartus II software version 2.2 SP2, for Stratix GX devices. For
128- and 32-bit configurations, the device used is an EP1SGX25DF1020C6; for 64-bit configurations, the device used is an EP1SGX25DF1020-C5.
2
Parameters
Stratix GX
LEs
Memory
M512
M4K
M-RAM
fMAX
(MHz)
Receiver
32-bit data path, 4-port, 4,096
bytes per port FIFO buffer
1,172
0
10
0
199
64-bit data path, 4-port, 4,096
bytes per port FIFO buffer
3,948
0
14
0
182
128-bit data path, 4-port, 4,096
bytes per port FIFO buffer
12,084
0
19
0
113
32-bit data path, 10-port, 2,048
bytes per port FIFO buffer
1,461
0
5
0
199
64-bit data path, 10-port, 2,048
bytes per port FIFO buffer
4,151
4
14
0
185
128-bit data path, 10-port, 2,048
bytes per port FIFO buffer
12,688
1
19
0
121
32-bit data path, 4-port, 4,096
bytes per port FIFO buffer
1,588
0
8
0
124
64-bit data path, 4-port, 4,096
bytes per port FIFO buffer
3,118
0
16
0
185
128-bit data path, 4-port, 4,096
bytes per port FIFO buffer
3,659
0
8
0
116
32-bit data path, 10-port, 2,048
bytes per port FIFO buffer
1,529
1
4
0
124
64-bit data path, 10-port, 2,048
bytes per port FIFO buffer
3,027
0
16
0
167
128-bit data path, 10-port, 2,048
bytes per port FIFO buffer
3,551
0
8
0
115
Transmitter
Altera Corporation
31
Choosing an
Architecture
Table 12. Multi-PHY with a Shared FIFO Buffer and Embedded Addressing
Performance
POS-PHY Level 4 MegaCore Function User Guide
f
Choosing an Architecture
For detailed description, refer to the “Specifications – Multi-PHY with
Shared FIFO Buffer & Embedded Addressing” chapter.
Virtual FIFO Segments with Buffer Management
The virtual FIFO segment with buffer management mode can be used for
MPHY applications. In this mode, a single buffer is logically segmented to
provide a separate virtual FIFO buffer per port. This configuration
requires multiple ports to share a single Atlantic interface, and leads to
fewer instances of head of line blocking. This configuration yields a fixed
increase to the LE consumption regardless of the number of ports, making
it well suited for applications with a higher number of ports where head
of line blocking must be reduced. Currently, up to 16 ports are supported
for full-size (128-bit) configurations.
Figure 8 shows example receive and transmit multi-PHY virtual FIFO
segments with buffer management configurations.
Figure 8. MPHY Virtual FIFO Segments with Buffer Management Configurations
SPI-4.2 Interfaces
Atlantic Interfaces
POS-PHY Level 4
Receiver
POS-PHY Level 4
Transmitter
1
32
Atlantic Interfaces
FIFO Buffers
Data
Address
Management
Address
FIFO Buffers
Data
Address
Management
Address
The virtual FIFO segments with buffer management mode is
not available for half-size (64-bit) configurations, and
quarter-rate (32-bit) configurations.
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Table 13 lists the resources and internal core speeds for a selection of
MPHY virtual FIFO segments with buffer management implementations.
For receiver implementations, the multiple continue parameter is enabled;
the burst mode parameter is not enabled. For transmitter
implementations, the transmit bandwidth optimization and burst mode
parameters are not enabled. These results were obtained using the
Quartus II software version 2.2 SP2, for Stratix GX devices. For 128-bit
configurations, the device used is an EP1SGX40DF1020-C6; for 64-bit
configurations, the device used is an EP1SGX25DF1020-C5; for 32-bit
configurations, the device used is an EP1SGX25DF1020-C6.
Parameters
Choosing an
Architecture
Table 13. Multi-PHY Virtual FIFO Segments with Buffer Management
Performance
Stratix GX
LEs
Memory
M512
M4K
M-RAM
fMAX
(MHz)
Receiver (128-Bit Data Path)
4-port, 4,096 byte FIFO
buffer
19,184
15
159
0
107
10-port, 2,048 byte FIFO
buffer
19,674
15
270
0
104
16-port, 1,024 byte FIFO
buffer
19,763
15
159
0
102
Transmitter (128-Bit Data Path)
f
Altera Corporation
4-port, 4,096 byte FIFO
buffer
7,827
15
138
0
110
10-port, 2,048 byte FIFO
buffer
9,042
15
270
0
104
16-port, 1,024 byte FIFO
buffer
9,256
15
138
0
111
2
For detailed description, refer to the “Specifications – Multi-PHY with
Virtual FIFO Buffer Segments & Buffer Management” chapter.
33
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Table 14 summarizes the performance limitations of the different
configurations in the device families supported.
Table 14. Performance and Device Support
Data Path
Width
Device
Family
128 bits
APEX II
SPHY
MPHY
Individual FIFO
Buffer
Individual FIFO
Buffer per Port
Shared FIFO Buffer
& Embedded
Addressing
Virtual FIFO Buffer
Segments & Buffer
Management
840 Mbps
840 Mbps
840 Mbps
840 Mbps
up to 16 ports
Stratix GX
1 Gbps with DPA
1 Gbps with DPA
up to 4 ports
1 Gbps with DPA
1 Gbps with DPA
up to 16 ports
Stratix &
Stratix GX
700 Mbps
700 Mbps
up to 10 ports
700 Mbps
Not Available
Stratix
250 Mbps
250 Mbps
up to 10 ports
250 Mbps
Not Available
Stratix
64 bits
32 bits
Cyclone
FIFO Buffer Size per Port
The FIFO buffer (for each port) is of variable size, and is used to pass data
between clock domains. The POS-PHY Level 4 core supports a FIFO
buffer size per port of:
■ 512 bytes
■ 1,024 bytes
■ 2,048 bytes
■ 4,096 bytes
■ 8,192 bytes
■ 16,384 bytes
■ 32,768 bytes
1
Total buffer size is device dependent.
Almost Empty & Almost Full
1
The almost empty (AE) and almost full (AF) parameters are
inputs to the core which may be hardwired or controlled via
external logic. These parameter settings do not affect the
POS-PHY Level 4 core netlist, and changing these settings
will have little to no effect on speed or area.
The AE and AF watermarks are used to segregate the receiver FIFO buffer
into three parts:
34
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
■
Starving—Occurs when the number of elements in the FIFO buffer is
under the AE watermark, and presumably close to a FIFO buffer
underflow condition
■
Hungry—Occurs when the number of elements in the FIFO buffer is
between the AE watermark and the AF watermark
■
Satisfied—Occurs when the number of elements in the FIFO buffer is
over the AF watermark, and presumably close to a FIFO buffer
overflow condition
Figure 9 on page 35 illustrates the relationship between the almost empty
(AE) and almost full (AF) watermarks and the MaxBurst1 and MaxBurst2
values.
Figure 9. FIFO Buffer Watermarks
AE
(Empty)
Starving
Lmax + ε
AF
Hungry
(Full)
Satisfied
Lmax + MaxBurst2+ ε
Lmax + MaxBurst1+ ε
Notes:
(1)
(2)
Lmax corresponds to the worst-case response time, from the delay in receiving a
status update over the FIFO status channel, until observing the reaction to that
update on the corresponding data path.
ε corresponds to the difference between the granted credit and the
actual data transfer length. This difference arises from various
protocol overheads.
(3)
The MaxBurst1 and MaxBurst2 values used to determine the AE and AF
watermarks on the receiver FIFO are configured in the adjacent device’s
transmitter. Determining the optimal MaxBurst1 and MaxBurst2 values is
application-specific, and requires an analysis of the data flows, beyond the scope of
this user guide.
The starving, hungry, and satisfied conditions are reported on the rstat
line, which operates at ¼ of the rdclk frequency. The rstat line also
performs framing operations, in compliance with the SPI-4.2 specification.
Altera Corporation
35
2
Choosing an
Architecture
The SPI-4.2 specification defines 2-bit values for starving, hungry, and
satisfied. These 2-bit values are calculated based on the available space in
the FIFO buffer, and on the user-defined parameters for almost empty and
almost full for each FIFO buffer.
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
For example, when the available space is less than almost empty, the FIFO
buffer is given the 2-bit value 2’b00 for its time slot on the stat line. The
possible 2-bit values are shown in Table 15.
Table 15. FIFO Buffer Status Format
MSB
LSB
Description
1
1
Reserved for framing
1
0
SATISFIED – FIFO buffer is almost full. When the buffer is satisfied, only transfers using
any remaining previously granted 16-byte blocks may be sent to the corresponding port
until the next status update. No additional transfers are permitted as long as the buffer
indicates that it is satisfied.
0
1
HUNGRY – When the buffer is hungry, transfers for up to MaxBurst2 16-byte blocks or
the remainder of what was previously granted (whichever is greater) may be sent to the
corresponding port until the next status update.
0
0
STARVING – FIFO buffer is almost empty. When the buffer is starving, transfers for up
to MaxBurst1 16-byte blocks may be sent to the corresponding port until the next status
update.
MaxBurst1 & MaxBurst2
1
The MaxBurst1 (MB1) and MaxBurst2 (MB2) parameters are
inputs to the core which may be hardwired or controlled via
external logic. These parameter settings do not affect the
POS-PHY Level 4 core netlist, and changing these settings
will have little to no effect on speed or area.
The MaxBurst1 parameter allows the user to select the number of 16-byte
blocks— 8 to 127—that can be transmitted when the adjacent device’s
FIFO buffer is starving.
The MaxBurst2 parameter allows the user to select the number of 16-byte
blocks—8 to 127—that can be transmitted when the adjacent device’s
FIFO buffer is hungry.
1
Each MaxBurst integer is eight clock cycles on the 16-bit
high-speed interface (tdat).
1
MB2 must be less than or equal to (≤) MB1.
Atlantic Data Width
This parameter sets the Atlantic interface data width. Four choices are
available: 32, 64, 128, or 256 bits.
36
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
FIFO Buffer Threshold Low & FIFO Buffer Threshold High
1
The FIFO buffer threshold low and high parameters are
inputs to the core which may be hardwired or controlled via
external logic. These parameter settings do not affect the
POS-PHY Level 4 core netlist, and changing these settings
will have little to no effect on speed or area.FTL must be
greater than zero.
1
FTL must be greater than zero.
Figure 10 illustrates the FIFO buffer fill level indicated by the FIFO
threshold low (FTL) and FIFO threshold high (FTH) watermarks. The
arxdav/atxdav signals provide flow control information to the user
logic.
The arxdav signal indicates when there is data available to be read from
the FIFO buffer. For example, FTL=1 indicates that one element is
available to be read from the FIFO buffer.
The atxdav signal indicates when there is room available to write new
data into the FIFO buffer. For example, FTH=8 indicates that eight
elements are currently available to be written data into the FIFO buffer,
without overflow.
Figure 10. FIFO Buffer Thresholds
(Empty)
FTL
Altera Corporation
(Full)
FTH
37
2
Choosing an
Architecture
The FIFO buffer threshold low (FTL) watermark for receiver
configurations controls when the arxdav signal is asserted and
deasserted for the read side of the FIFO buffer. The FIFO buffer threshold
high (FTH) watermark for transmitter configurations controls when the
atxdav signal is asserted and deasserted for the write side of the FIFO
buffer.
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Transmit Bandwidth Optimization
To achieve maximum bandwidth utilization, the transmitter should send
packets back-to-back on the SPI-4.2 data bus.
Enabling the transmit bandwidth optimization parameter results in the
transmission of packets with minimal IDLE insertion, or in some cases no
IDLE insertion (SOP and EOP markers share a common control word).
Enabling the transmit bandwidth optimization parameter increases the
effective bandwidth rate on the SPI-4.2 data bus, but significantly
increases the LE consumption.
Disabling the transmit bandwidth optimization parameter allows IDLEs
to be inserted between EOP control words and the next SOP or payload
control word. The maximum number of IDLEs is a function of packet size,
but is a maximum of six for full-size (128 bit) configurations, and two for
half-size (64 bit) configurations. Although not using transmit bandwidth
optimization lowers the effective bandwidth rate on the SPI-4.2 data bus,
it greatly reduces the LE consumption.
1
This parameter is not applicable for receiver configurations.
The additional logic is not required to avoid IDLE insertion
for 32-bit data path width transmitter configurations (i.e.,
selecting this option in IP Toolbench will not affect the
netlist).
Table 16 shows the availability of the transmit bandwidth optimization
parameter for all buffer mode and data path width configurations.
Table 16. Transmit Bandwidth Optimization
Data Path
Width
SPHY
MPHY
Individual FIFO
Buffer
Individual FIFO
Buffer per Port
Shared FIFO Buffer & Virtual FIFO Buffer Segments &
Embedded Addressing
Buffer Management
128 bits
Available
Not Available
Available
Available
64 bits
Available
Available
Available
Not Available
32 bits
Available by
Default
Available by Default
Available by Default
Not Available
Disabling the transmit bandwidth optimization parameter reduces the LE
consumption by approximately:
■
■
38
3,600 LEs for 128-bit configurations
1,400 LEs for 64-bit configurations
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Whether or not the transmit bandwidth optimization parameter is
selected has no effect on fixed packet sizes of 16N - 2 bytes (128-bit
configurations), or of 8N -2 bytes (64-bit configurations).
Figure 11 and Figure 12 on page 40 show throughput results for the
transmit bandwidth optimization parameter for 128-and 64-bit
configurations.
Figure 11. Packet Throughput
2
POS-PHY Level 4 at 700 Mbps LVDS
Choosing an
Architecture
350
Packet Throughput (Mpps)
300
250
200
TXBOPT
no TXBOPT 128 bit
no TXBOPT 64 bit
150
100
50
0
0
16
32
48
64
80
96
112
128
144
160
Packet Size (Bytes)
Altera Corporation
39
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Figure 12. Bit Throughput
POS-PHY Level 4 at 700 Mbps LVDS
10500
10000
Bit Throughput (Mbps)
9500
9000
8500
TXBOPT
no TXBOPT 128 bit
8000
no TXBOPT 64 bit
7500
7000
6500
6000
0
16
32
48
64
80
96
112
128
144
160
Packet Size (Bytes)
Burst Mode & Burst Size
The burst mode parameter is provided to ensure optimal operation with
devices with element-based FIFO buffers (e.g., network processors).
Enabling the burst mode parameter configures the POS-PHY Level 4
transmitter to always send a minimum of burst size bytes, without
interruption, between payload control words and the next non-EOP
control word. A burst size can be set to be either 64 or 128 bytes.
The FIFO buffer turns into a store and forward engine. It buffers enough
data to ensure a fixed burst of data, or burst of an entire packet.
f
Refer to the POS-PHY Level 4 MegaCore Optimization for the Intel® IXP2800
Network Processor white paper for a detailed description of the benefits of
this feature when interfacing to the Intel® IXP2800 network processor.
1
40
The burst mode parameter is not applicable for receiver
configurations.
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Table 17 shows the availability of the transmit bandwidth optimization
parameter for all buffer mode and data path width configurations.
Table 17. Burst Mode
Data Path
Width
SPHY
MPHY
Individual FIFO
Buffer
Individual FIFO
Buffers per Port
Shared FIFO Buffer &
Embedded Addressing
Virtual FIFO Buffer Segments
& Buffer Management
128 bits
Available
Not Available
Available
Not Available
64 bits
Available
Not Available
Available
Not Available
32 bits
Not Available
Not Available
Not Available
Not Available
2
Choosing an
Architecture
Enabling the burst mode parameter increases the LE consumption by
approximately:
■
■
700 LEs for 128-bit configurations
400 LEs for 64-bit configurations
Multiple Continues
For ease of implementation, the SPI-4.2 standard specifies that start-ofpacket control words may not occur less than eight cycles apart. However,
there are no specific restrictions for other control words. Accordingly, it is
possible to encounter multiple continue control words in less than eight
cycles. A continue is a payload control word that is not immediately
followed by a payload transfer corresponding to a start-of-packet (i.e., Bit
15 = 1, indicating payload transfer immediately follows the control word;
Bit 12 = 0, indicating the payload transfer does not correspond to a startof-packet).
1
Non-standard SPI-4.2 devices: The specific implementation
of the SPI-4.2 protocol on the neighbouring device might
deviate from the standard specifications. Therefore, it is
recommended that you understand the specific capabilities
of the neighbouring device’s transmitter, and know whether
that device supports IDLE insertion after EOP control
words, to avoid multiple continue traffic. Disabling this
feature reduces LE consumption and increases fMAX.
In worst-case scenarios for standard SPI-4.2 implementations, the receiver
may be required to process the remaining bytes of several packets,
destined for various ports, occurring less than eight cycles apart. Figure 13
shows an example where the multiple continue parameter is enabled.
Figure 14 shows an example where the multiple continue parameter is not
enabled, nor required, because the data is already pre-formatted.
Altera Corporation
41
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Figure 13. Multiple Continue Example
Port 1 EOP
SOP
Port 2 EOP
EOP
Scheduler
16-Byte Burst CCW
SOP
Port 4 EOP
SOP
SCW
EOP
SOP
Port 3 EOP
SCW
SOP
CCW
SCW
EOP
ICW
CCW
ICW
EOP
SOP
SPI-4.2
SOP
SCW
CCW
128
Bits
ICW
SOP
ICW
Multiple
Continues
SOP = start of packet
EOP = end of packet
CCW = continue control word
ICW = idle control word
SCW = start-of-packet control word
Figure 14. Non-Multiple Continue Example
Port 1 EOP
Port 2 EOP
Port 3 EOP
Port 4 EOP
SOP
SOP
SOP
SOP
Scheduler
16-Byte Burst
ICW
CCW
CCW
CCW
ICW
ICW
ICW
ICW
CCW
SOP
ICW
ICW
ICW
ICW
ICW
ICW
ICW
ICW
ICW
ICW
ICW
ICW
SCW
SCW
SPI-4.2
SOP
SCW
SOP
SCW
SOP
ICW
ICW
ICW
ICW
ICW
ECW
ECW
ECW
ECW
ICW
EOP
EOP
EOP
EOP
ICW
128
Bits
SOP = start of packet
EOP = end of packet
CCW = continue control word
ICW = idle control word
SCW = start-of-packet control word
ECW = end-of-packet control word
In order to properly process this stream without dropping payload, the
multiple continue parameter must be enabled. When enabled, this
parameter allows the insertion of internal buffers to properly manage the
streams. A FIFO status and management block and a scheduler ensure
that the tail end of the packets are sent to the proper FIFO buffers.
If the multiple continue parameter is not enabled when interfacing to a
standard SPI-4.2 transmitter, and the data stream shown in Figure 13
occurred, the first two payload words would be sent to the correct FIFO
buffer, but the last two payload words would be dropped.
42
1
This parameter is not applicable to transmitter
configurations.
1
For quarter-rate (32-bit) receiver configurations, the
multiple continue parameter is always enabled.
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Table 18 shows the availability of the multiple continue parameter for all
buffer mode and data path width receiver configurations.
Table 18. Multiple Continues
Data Path
Width
SPHY
MPHY
Individual FIFO
Buffer per Port
128 bits
Available
Available
Available
Available
64 bits
Available
Available
Available
Not Available
Available by default
Not Available
32 bits
Available by default Available by default
Shared FIFO Buffer & Virtual FIFO Buffer Segments
Embedded Addressing
& Buffer Management
2
Disabling the multiple continue parameter reduces the LE consumption
by approximately:
■
■
2,500 LEs for 128-bit configurations
0 LEs for 64-bit configurations
Enabling the multiple continue parameter increases the memory
consumption by approximately:
■
■
■
4 Kbytes for 128-bit configurations
2 Kbytes for 64-bit configurations
Not applicable for 32-bit configurations
Maximum Training Sequence Interval
1
The maximum training sequence interval (MaxT) parameter
is an input to the core which may be hardwired or controlled
via external logic. This parameter setting does not affect the
POS-PHY Level 4 core netlist, and changing this setting will
have little to no effect on speed or area.
The MaxT parameter allows the user to select the interval at which the
training sequence occurs—8 to 32,767—in units of 16-byte cycles. The
training sequence is inserted after a payload burst, or during the
transmission of IDLEs. Once a training sequence is sent, the next training
sequence is not sent any earlier than MaxT 16-byte cycles. For example,
MaxT=8 corresponds to 64 SPI-4.2 clock cycles on the high-speed interface
(i.e., 8 × 16 bytes = 8 × 8 × (2 bytes) = 64 × (16-bits) = 64 SPI-4.2 clock
cycles).
1
Altera Corporation
This parameter is not applicable to receiver configurations.
43
Choosing an
Architecture
Individual FIFO
Buffer
POS-PHY Level 4 MegaCore Function User Guide
Choosing an Architecture
Training Pattern Repetitions
1
The training pattern repetitions (ALPHA) parameter is an
input to the core which may be hardwired or controlled via
external logic. This parameter setting does not affect the
POS-PHY Level 4 core netlist, and changing this setting will
have little to no effect on speed or area.
The training sequence includes one IDLE word, plus ALPHA(α) × 20
training words. ALPHA is a user selectable option (0 to 255).
1
If ALPHA is zero, the transmitter does not send a training
pattern.
The twenty words are separated into ten consecutive tdat words of
16’h0FFF with tctl of 1’b1, followed by ten consecutive tdat words of
16’hF000 with tctl of 1’b0. You should expect some IDLEs before, and
after, the training sequence.
1
This parameter is not applicable to receiver configurations.
Status Channel Clock Edge
Determines on which clock edge—positive (rising) or negative (falling)—
the 2-bit status channel is transmitted (receiver data flow), or sampled
(transmitter data flow) in reference to its associated clock.
1
The status channel should either be delayed, or utilize the
negative edge to ensure proper sampling of the status
information.
Calendar Multiplier
1
The calendar multiplier parameter is an input to the core
which may be hardwired or controlled via external logic.
This parameter setting does not affect the POS-PHY Level 4
core netlist, and changing this setting will have little to no
effect on speed or area.
The FIFO buffer stat line inserts DIP-2 calculations and framing bits at
the required time, in accordance with the state machine shown in
Figure 15 on page 45. The user determines the amount of time by choosing
a value from 1 - 255. These user-selectable calendar fields are used, in the
state machine, to manage the FIFO buffer status channels.
44
Altera Corporation
Choosing an Architecture
POS-PHY Level 4 MegaCore Function User Guide
Figure 15. FIFO Buffer Status State Diagram
Calendar
2’b11
SYNC
cal[0]
Enable
DIP-2
.
cal[1]
.
.
cal[2]
.
DISABLE
....
.
….
.….
cal[cl]
Iteration #2
2
Iteration
#Calendar_M
2’b11
cl = Calendar Length
The rstat and tstat lines report the status of the FIFO buffer in a
round-robin format. Figure 16 on page 45 is a timing diagram showing the
time and location of the DIP-2 insertion, as well as the round-robin status
updates.
Figure 16. FIFO Buffer Channel Status Timing Diagram
tsclk/rsclk
...
Round-Robin Period
rstat[1]/tstat[1]
rstat[0]/tstat[0]
Altera Corporation
MSB(1)
LSB(1)
MSB(2)
...
MSB(N)
DIP(1)
MSB(1)
MSB(2)
LSB(2)
...
LSB(N)
DIP(0)
LSB(1)
LSB(2)
45
Choosing an
Architecture
.
….
.
Disable
Iteration #1
Getting Started
Hardware &
Software
Requirements
The instructions in this section require the following hardware and
software:
Design Flow
The POS-PHY Level 4 MegaCore function design flow involves the
following steps:
A PC running the Windows 98/NT/2000/XP operating system; or a
SUN workstation running the Solaris operating system
■ Quartus II development tool, version 2.2 service pack 1 (SP1) or
higher
■ Model TechnologyTM ModelSim®-Altera simulation software, version
5.6a or higher; or Innoveda Visual IP RTL simulation software,
version 4.3 or higher
1
Access to the Internet is required to configure the POS-PHY
Level 4 MegaCore function.
3
Getting Started
Altera Corporation
■
1.
Obtain and install the POS-PHY Level 4 MegaCore function.
2.
Create a custom configuration of the POS-PHY Level 4 MegaCore
function using the IP Toolbench.
3.
Implement the rest of your system using VHDL, Verilog HDL, or
schematic entry.
4.
Use the IP Toolbench-generated simulation models to confirm your
custom core’s operation.
5.
Use the POS-PHY Level 4 encrypted netlists to perform static timing
analysis of your customized core in the Quartus II software.
6.
Compile your design and perform place-and-route.
7.
License the POS-PHY Level 4 MegaCore function.
8.
Perform post-route simulation (optional).
9.
Configure or program Altera devices with the design.
47
POS-PHY Level 4 MegaCore Function User Guide
Download &
Install the Core
Getting Started
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC or workstation. The
following instructions describe this process.
Downloading the POS-PHY Level 4 MegaCore Function
You can download MegaCore functions from Altera’s web site at
www.altera.com. Follow the instructions below to obtain the POS-PHY
Level 4 MegaCore function via the Internet.
1
Web access is required to configure the POS-PHY Level 4
core.
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Type PL4 in the Keyword Search box.
3.
Click Go.
4.
Click the link for the Altera POS-PHY Level 4 MegaCore function in
the search results table. The product description web page displays.
5.
Click the Download Free Evaluation OpenCore graphic on the top
right of the product description web page.
6.
Follow the online instructions to download the core and save it.
Installing the POS-PHY Level 4 MegaCore Function Files
For Windows, perform the following steps:
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The POS-PHY Level 4 MegaCore function Installation
dialog box appears. Follow the on-line instructions to finish
installation.
For Solaris systems, perform the following steps:
1.
48
Download the core, see “Downloading the POS-PHY Level 4
MegaCore Function” on page 48.
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
2.
Decompress/untar the package, using the following commands:
gunzip xxx.tar.gz; tar xvf xxx.tar
3.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically <path>/posphy4v2.0.0/lib) as a user library in the Quartus II software to access the
core in the MegaWizard® Plug-In Manager. Search for “User
Libraries” in Quartus II Help for instructions on how to add these
libraries.
Figure 29 shows the directory structure for the POS-PHY Level 4
MegaCore function.
Figure 17. POS-PHY Level 4 MegaCore Function Directory Structure
<path>/posphy4-v2.0.0
The default path is c:/MegaCore
doc
Contains the core documentation.
3
POS-PHY
Level 4
MegaCore
Function
Walkthrough
This walkthrough explains how to create a POS-PHY Level 4 MegaCore
function using the Altera IP Toolbench within the Quartus II software. As
you go through the IP Toolbench, each page is described in detail. When
you are finished generating a POS-PHY Level 4 core, you can incorporate
it into your overall project.
You can use Altera’s OpenCore evaluation feature to compile and
simulate the MegaCore functions, and to complete static timing analysis,
allowing you to evaluate the POS-PHY Level 4 MegaCore function before
deciding to purchase a license. However, you must purchase a license
before you can generate programming files or EDIF, VHDL, or
Verilog HDL gate-level netlist files for port place-and-route timing
simulation in third-party EDA tools.
This walkthrough consists of the following steps:
■
■
■
■
■
Altera Corporation
“Create a New Quartus II Project” on page 50
“Launch the IP Toolbench” on page 51
“Step 1: Select Configuration” on page 54
“Step 2: Set Up Simulation” on page 61
“Step 3: Generate” on page 62
49
Getting Started
lib
Contains the core design files.
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You must also specify the POS-PHY Level 4 MegaCore function user
library. To create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
1
Steps 7 to 10 only apply to Solaris systems.
7.
Click User Library Pathnames.
8.
Type <path>\posphy4-v.2.0.0\lib\ into the Library name box,
where <path> is the directory in which you installed the POS-PHY
Level 4 MegaCore function. The default installation directory is
c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
50
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Launch the IP Toolbench
To launch the IP Toolbench from within the Quartus II software, perform
the following steps:
1.
Choose MegaWizard Plug-In Manager (Tools menu).
2.
Select Create a new custom megafunction variation (default).
3.
Click Next.
4.
Expand the Communications folder under Installed Plug-Ins by
clicking the + next to the name.
5.
Expand the POS-PHY folder under Communications.
6.
Click POS-PHY Level 4 MegaCore function v2.0.0.
7.
Choose the output file type for your design; the IP Toolbench
supports VHDL, and Verilog HDL. This walkthrough uses
Verilog HDL, however, you can use either language.
8.
Type the name of the output file. Figure 18 on page 52 shows the
page after you have made these settings.
1
Altera Corporation
For AHDL instructions, refer to “Instantiating a Design File
in AHDL” on page 64.
The screen captures shown in this user guide are representative
examples of the IP Toolbench. The wizard windows displayed in
your project may differ from these examples.
51
Getting Started
1
3
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Figure 18. MegaWizard Plug-In Manager
9.
52
Click Next. The IP Toolbench for POS-PHY Level 4 MegaCore
function launches. See Figure 19 on page 53.
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 19. IP Toolbench
3
1
Before you proceed, it is highly recommended that you review
the “Choosing an Architecture” chapter of this user guide.
Since the POS-PHY Level 4 core is highly configurable, a vast number of
configurations are possible. To reduce package sizes and download time,
this version of the IP Toolbench offers three possible methods of obtaining
the configuration(s) best suited to your design.
■
■
■
f
Altera Corporation
Select an installed configuration (indicated by a green marker)
–
Installed configurations are pre-packaged and installed with the
IP Toolbench
Download a configuration (indicated by a yellow marker)
–
Configurations available for download are stored on a web
repository accessible via the Internet
A slight download time may be required
Request a custom configuration
–
Custom configurations are available by entering a MySupport
request
Several days may be required to process a request
See the legend in Figure 20 on page 54.
53
Getting Started
You are now ready to configure your POS-PHY Level 4 core.
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Step 1: Select Configuration
To select a configuration, perform the following steps:
1.
Click the Step 1: Select Configuration button in the IP Toolbench.
2.
A window opens showing a directory structure. From the left
window pane, select the configuration that best meets your
requirements. A brief list of this configuration’s parameters appears
in the right pane. Only parameters that affect the netlist are
displayed. See Figure 20 for an example.
Figure 20. Directory Structure & Configuration Parameters
54
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
1
1.
Once you have selected a configuration, click the View/Configure
button.
2.
A parameterization window opens (this may take several seconds).
Verify that all parameters, including the parameters identified by an
asterisk, meet your requirements. Modify all parameters as required.
The asterisked parameters do not affect the netlist and can be
modified via the wrapper. See Figure 21 on page 56 through
Figure 24 on page 59 for example parameters.
1
If you could not find your exact configuration(s) in the directory
structure, select a configuration that closely resembles your
desired configuration and modify its parameters.
55
3
Getting Started
Altera Corporation
Upon start-up, IP Toolbench attempts to connect to the
Internet. If it cannot connect, an error message appears. This
message states that your network settings may not be
configured correctly for the MegaWizard Plug-In. If you see
this message, click the Network Settings button (see
Figure 20 on page 54) and verify or add the required
information. Consult your network administrator for help.
For the new network settings to take effect, you must close
and restart the IP Toolbench.
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Figure 21. General Parameters.
56
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 22. Buffer Parameters.
3
Getting Started
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57
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Figure 23. Optimizations Parameters.
58
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 24. Status & Training Parameters.
3
When you are satisfied with your selection, click Finish.
4.
If you have selected an installed configuration—indicated by a green
marker or a configuration available for download—indicated by a
yellow marker (see Figure 20 on page 54)—and have not modified
any non-asterisked parameters, you may proceed to “Step 2: Set Up
Simulation” on page 61.
5.
If you customized your own configuration, the next page to open is a
Custom Configuration Request dialog box showing a list (text
format) of the parameters you chose for your customized
configuration. See Figure 25 on page 60. Select and copy all of this
text.
1
Altera Corporation
Getting Started
3.
If the Custom Configuration Request dialog box does not
appear, you may be have unknowingly chosen either a presynthesized configuration available for download. In this
case, proceed to “Step 2: Set Up Simulation” on page 61.
59
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
Figure 25. Custom Configuration Request
6.
Click Ok.
7.
Point your web browser to Altera’s technical on-line support system,
mySupport, at:www.altera.com/mysupport/
1
If this is your first time using this system, you must register
to obtain a login and password.
8.
Log on, and click Create a Service Request.
9.
Click Product Related Request.
10. Enter your project information, complete all fields as appropriate.
See Figure 26 on page 61.
11. Select Intellectual Property in the Category list.
12. Select Communications from the Megafunction Category list.
13. Select POS-PHY L4 from the Megafunction Product list.
14. Paste the configuration parameters text—generated with the IP
Toolbench—into the Description field.
60
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 26. MySupport Product Related Request
3
Getting Started
15. Click Submit Product Related Request.
1
Altera e-mails your custom configuration to the address you
provided for your mySupport account. Requests take up to three
business days to process.
16. Click the × in the top corner of IP Toolbench to close the application,
or continue selecting configurations. Do not click Step 3: Generate.
Step 2: Set Up Simulation
Now that you have chosen your POS-PHY Level 4 configuration(s), you
are ready to set up the simulation outputs for your system.
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61
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
1.
Click the Step 2: Set Up Simulation button in the IP Toolbench. (See
Figure 19 on page 53.)
2.
Turn on Generate Simulation Model. See Figure 27.
3.
Select the simulator of your choice.
Figure 27. Set Up Simulation
4.
Click Finish.
Step 3: Generate
Now that you have set up the outputs for your system, you are ready to
generate your system.
1.
Click Step 3: Generate in the IP Toolbench to begin generation. (See
Figure 19 on page 53.) The IP Toolbench performs the actions you
specified, and generates any resulting output files. (See Figure 28 on
page 63.)
1
62
If you have selected a configuration from the web
repository, a download progress indicator should appear in
the IP Toolbench report window (see Figure 28 on page 63).
Download times may vary depending on your internet
connection and the size of the configuration. The average
size of a POS-PHY Level 4 configuration is 7 megabytes.
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Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 28. Generate
3
Getting Started
2.
Click Exit IP Toolbench when you are finished.
Implementing the System
Once you have generated your custom POS-PHY Level 4 core, you are
ready to implement it. You can use the files generated by the IP
Toolbench, and use the Quartus II software or other EDA tools to create
your design.Figure 29 on page 64 shows an example project directory
structure.
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63
POS-PHY Level 4 MegaCore Function User Guide
1
Getting Started
<configuration> is a unique code (aot###_<configuration>
#_posphy4) assigned to the specific configuration requested
through the IP Toolbench.
Figure 29. POS-PHY Level 4 MegaCore Directory Structure
<working directory>
Directory name selected by user in project wizard
db
Quartus II software-generated directory.
<output file name>.v (or .vhd)
<output file name>.bsf
<output file name>.cmp
<output file name>.inc
<output file name>_inst.v (or inst. vhd)
<output file name>.log
IP Toolbench-generated files.
posphy4_<configuration>_mw_wrapper.v (or .vhd)
Clear-text wrapper
aot####_<configuration>_posphy4.e.vqm
Encrypted vqm Verilog HDL netlist for Quartus II development tool
aot####_<configuration>_posphy4.esf
Entity settings file for Quartus II development tool
<output file name>_sim
Contains the simulation models.
posphy4-v2.0.0
Configuration based on parameter choices.
sim_lib
aot####_<configuration>_posphy4
test
Contains the scripts to run the simulation models
& demo testbench
run_modelsim_verilog
run_modelsim_vhdl
run_modelsim_visual_ip
tb.v
<simulator db> (1)
Simulator database
Note:
(1)
<simulator db> must be the same as the simulator chosen during parameterization.
Instantiating a Design File in AHDL
To instantiate a lower-level Verilog HDL design file in an AHDL file,
perform the following steps:
64
Altera Corporation
Getting Started
Simulate the
Design
POS-PHY Level 4 MegaCore Function User Guide
1.
When the Verilog design file is open in Quartus II, create an AHDL
include file by choosing Create AHDL Include Files for Entities in
Current File (Tools menu).
2.
Add an Include statement to your AHDL file. The Include statement
allows you to import text from the AHDL include file into the
current file.
3.
Instantiate the Verilog design in the AHDL file as described in the
“Instance Declaration” section of the Quartus II Help.
4.
In the logic section of the AHDL design, connect the ports of the
instance to the rest of your design.
Altera provides models you can use for functional verification of the POSPHY Level 4 core within your design. A Verilog HDL demonstration
testbench, including scripts to run it, is also provided. This demonstration
testbench, used with the ModelSim-Altera simulator tool, demonstrates
how to instantiate a model in a design. To find the simulation models for
your selected configuration, refer to Figure 29 on page 64.
The demonstration testbench stimulates the inputs and outputs of the user
interfaces of the POS-PHY Level 4 core, demonstrating basic sanity. Each
POS-PHY Level 4 configuration includes scripts to compile and run the
demonstration testbench using a variety of simulators and models.
Receiver Testbench Description
The testbench provided with the receive configurations of the POS-PHY
Level 4 core tests the following functions:
■
■
■
■
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Synchronization of the core with the SPI-4.2 training pattern
Data integrity from the SPI-4.2 interface through the user’s core to the
Atlantic back-end interface
The ability to send data to multiple ports
Verifies that the core can create back pressure on the SPI-4.2 interface.
(This test can be turned on and off)
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Getting Started
Using the Verilog HDL Demonstration Testbench
3
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
The testbench consists of three basic modules: packet_gen, user’s POSPHY Level 4 receiver configuration, and sapmon. It also consists of
multiple support modules for pin monitoring, clock generation, and reset
generation. See Figure 30. The packet_gen module generates SPI-4.2
packets. These packets are received by the user’s receiver configuration
which processes the packets and converts them to Atlantic interface
format. Finally the sapmon module, one for each port, receives the data
from the Atlantic interface and verifies the correctness of the data.
Figure 30. POS-PHY Level 4 Receiver Configuration Testbench
SPI-4.2
Interface
Device Under Test
Atlantic
Interface
packet_gen
POS-PHY Level 4
Packet Generation
POS-PHY
Level 4
Receiver
Configuration
sapmon
Atlantic Interface
Data Analyser
(one per port)
reset
clk_gen
pin_mon
The packet_gen module begins by sending the idle pattern (16'h000f) and
then the training pattern (16'h0fff,16'hf000) until the POS-PHY Level 4
receiver configuration is synchronized to the data source.
The packet_gen module then begins sending packets of random lengths.
To allow for automated packet checking, a special packet format is used.
Table 19 shows the format of each packet.
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Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Table 19. Packet Format
Packet Byte
Format
Description
Header byte
{0,0,len[5:1],ext}
Contains information about the packet. len represents the length of the
packet if the length can be encoded in six bits. If the length is beyond
32 bits, ext is set to indicate that the next byte in the packet contains
the length information.
Extra length byte
{size[16:0]}
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes). (Optional)
Number byte
{N[7:0] ^
port_num}
Packet number (packet number begins at ’h01 and is incremented by
one for each packet) XORed with the port number
Payload bytes
{N++^ port_num}
The following bytes in the packet are incremented by one and XORed
with the port number
There are three pattern generation functions, capable of generating idles,
training patterns, and data packets. Table 20 shows the format of each
function.
Command
Format
Description
Training pattern
packet_gen.tp
(width, number)
width is the number of clock cycles the training pattern takes; number
is the number of training pattern sequences
Idle
packet_gen.idles
(number)
number is the number of sequential idles
Data packet
packet_gen.pkt2
(port_number, err,
size, num)
port_number is the target port for the packet. err is set to zero; size is
the packet size in bytes (2-216 bytes); num is the packet sequence
number
All of the packets are sent in sequence with no breaks between them.
However, idles can be inserted by adding the idle command in the
testbench data generation section. After all packets have been sent, the
idle pattern is repeated until the end of the simulation.
The testbench concludes by checking that all of the packets have been
received. In addition, it checks that the Atlantic packet receivers (sapmon
modules, one for each port) have not detected any errors in the received
packets. If no errors have been detected, and all packets have been
received, the testbench issues a message stating that the simulation was
successful.
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67
Getting Started
Table 20. Function Format
3
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
If errors have been detected, a message states that the testbench has failed.
If not all packets have been detected, a message states that the testbench is
incomplete. The variable tb.exp_chk_cnt determines the number of checks
done to insure completeness of the testbench. For each port tested, one
completeness check is done. In addition, a final check is done for the
conclusion of the testbench.
Optionally, the testbench can create back pressure on the SPI-4.2 interface.
When the back pressure variable is defined, back pressure is generated on
port 0. This is accomplished by first turning off the sapmon receiver for
port 0. As the receive FIFO buffer begins to fill, it goes from the hungry
state to the satisfied state. When the FIFO buffer is satisfied, the status on
the SPI-4.2 interface notifies the packet_gen module that it should stop
sending data. There is a break in packet generation during which idles are
sent. After the status returns to the hungry state, the packet generation
resumes.
Transmitter Testbench Description
The testbench provided with the transmit configurations of the POS-PHY
Level 4 core tests the following functions:
■
■
■
■
Synchronization of the core with a training pattern
Data integrity from the Atlantic back-end interface through the user’s
configuration to the SPI-4.2 interface
The ability to send data from multiple ports to the SPI-4.2 interface.
Verifies that the core can create back pressure on the SPI-4.2 interface.
(This test can be turned on and off)
The testbench consists of three basic modules: sapgen_p3, user transmitter
configuration, and packet_mon. It also consists of multiple support
modules for pin monitoring, clock generation, SPI-4.2 state machine
tracking and reset generation. See Figure 31 on page 69. The sapgen_p3
module is made by calling one sapgen module per port. Each sapgen
generates Atlantic interface packets for a single port. These packets are
received by the user’s transmitter configuration which processes the
packets and converts them to SPI-4.2 bus format. Finally the packet_mon
module receives the data from the SPI-4.2 interface and verifies the
correctness of the data.
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Getting Started
POS-PHY Level 4 MegaCore Function User Guide
Figure 31. POS-PHY Level 4 Transmitter Configuration Testbench
SPI-4.2
Atlantic
Interface
Device Under Test
Interface
packet_mon
POS-PHY Level 4
Packet Analyzer
POS-PHY
Level 4
Transmitter
Configuration
sapgen
Atlantic Interface
Data Generator
(one per port)
reset
clk_gen
pin_mon
3
During the main test the sapgen module sends data to each port. Table 21
summarizes the two pattern commands.
Table 21. Training Pattern Commands
Command
Pause
Data Packet
Format
Description
sapgen.portN.
pause;
sapgen.portN.
pkt(length,packet
number,error);
This command pauses a given port. No data is sent to a paused port.
N is the port number to pause.
Altera Corporation
N is the port to which the data packet will be sent. length is the
number in bytes of the data pattern. packet number is a user supplied
number which identifies the packet. error generates an error on the
Atlantic interface.
The error value can be:
0: no error
1: assert Atlantic error, set header error bit
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Getting Started
Framing is asserted from the packet_mon module on the status channel
going to the POS-PHY Level 4 transmitter configuration which asserts the
training pattern (16’h0fff,16’hf000) until the packet_mon module is
synchronized with the SPI-4.2 interface of the packet_mon module. Once
the synchronization is complete the sapgen module can begin sending
data.
POS-PHY Level 4 MegaCore Function User Guide
Getting Started
When an error is asserted on the Atlantic interface with a valid EOP, and
an end of packet abort message is sent to the SPI-4.2 interface. This is not
counted as an error in the data and will not cause the testbench to fail.
The packet tasks for each port are called in parallel via a fork/join
statement. Arbitration is handled in the sapgen_p3 module and varies for
each buffer mode.
■
■
■
For individual FIFO buffer per port configurations, the packets can be
written in parallel.
For virtual FIFO buffer segments with buffer management
configurations, the arbitration logic picks the hungriest port and
allows that port to write.
For shared FIFO buffer with embedded addressing configurations,
the arbiter selects each port in a round-robin manner, switching to the
next port at a fixed interval.
The packets have random lengths and follow the format in Table 22.
Table 22. Packet Format
Packet Byte
Format
Description
Header byte
{0,0,len[5:1],ext}
Contains info about the packet. len is the length of the packet if the
length can be encoded in six bits. If the length is beyond 32 bits, ext
is set to indicate that the next byte in the packet contains the length
information.
Extra length byte
{size[16:0]}
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes) (Optional)
Number byte
{N[7:0] ^ port_num}
Packet number (packet number begins at ’h01 and is incremented by
one for each packet) XORed with the port number.
Payload bytes
{N++^ port_num}
The following bytes in the packet are incremented by one and XORed
with the port number.
The testbench concludes by checking that all of the packets have been
received. In addition, it checks that the POS-PHY Level 4 packet receiver
(packet_mon module) has not detected any errors in the received packets.
If no error has been detected, and all packets have been received, the
testbench issues a message stating that the simulation was successful.
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Getting Started
POS-PHY Level 4 MegaCore Function User Guide
If an error has been detected, a message states that the testbench has
failed. If not all packets have been detected, a message states that the
testbench is incomplete. The variable tb.exp_chk_cnt determines the
number of checks done to insure completeness of the testbench. For each
port tested, one completeness check is done. In addition, a preliminary
check is done to make sure synchronization is complete, and a final check
is done for the conclusion of the testbench.
Optionally, the testbench can create back pressure on the SPI-4.2 interface.
When the back pressure variable is defined, back pressure is generated on
port 0. This is accomplished by first turning off the packet_mon receiver
for port 0. As the receive FIFO buffer begins to fill, it goes from the hungry
state to the satisfied state. When the FIFO buffer is satisfied, the status on
the SPI-4.2 interface notifies the sapgen module that it should stop
sending data. There is a break in packet generation during which idles are
sent. After the status returns to the hungry state, the packet generation
resumes.
Using the Visual IP Software
Synthesize,
Compile &
Place & Route
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar LogicTM, Mentor
Graphics®, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
Altera Corporation
1.
Create your custom design instantiating a POS-PHY Level 4 core.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the POS-PHY Level 4 core instantiation as a black
box by either setting attributes or ignoring the instantiation.
71
3
Getting Started
The Visual IP software facilitates the use of Visual IP simulation models
with third-party simulation tools. To view a simulation model, you must
have the Visual IP software installed on your system. To download the
software, or for instructions on how to use the software, refer to the Altera
web site at www.altera.com, and search for Visual IP. For examples of
how to use the provided Visual IP model, refer to the sample scripts
included with the demonstration testbench.
POS-PHY Level 4 MegaCore Function User Guide
3.
Getting Started
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Placeand-Route
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
1.
2.
Specify the input settings for the project.
a.
Choose EDA Tool Settings (Assignments menu).
b.
Select Synplify in the Design entry/synthesis tool list.
c.
Click Settings.
d.
In the EDA Tool Input Settings dialog box, select Synplify from
the Design Entry/Synthesis Tool list.
Specify the netlist optimizations for the project in Settings >
Compiler Settings > Netlist Optimizations (Assignments menu).
a.
Click the Perform WYSIWYG primitive resynthesis check box.
b.
Click the Perform gate-level register retiming checkbooks.
c.
Click the Automatically duplicate logic elements check box.
d.
Click the Perform logic element level LUT resynthesis check
box.
1
72
Steps c) and d) are not applicable for APEX II devices.
3.
Add your third-party EDA tool-generated netlist file to your project.
4.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
5.
Add the pre-synthesized and encrypted .e.vqm file from your
project directory, created by the MegaWizard Plug-In Manager.
6.
If required, constrain your design.
7.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design.
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Getting Started
f
Set Up
Licensing
POS-PHY Level 4 MegaCore Function User Guide
Refer to the Quartus II Help for further instructions on performing
compilation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FPGA device. You can use Altera’s
OpenCore evaluation software to compile and simulate the POS-PHY
Level 4 MegaCore function using the encrypted RTL models with your
simulator software, and to complete static timing analysis in the Quartus
II software. Thus allowing you to evaluate the core before purchasing a
license. However, you must obtain a license from Altera before you can
generate programming files or EDIF, VHDL, or Verilog HDL gate-level
netlist files for post place-and-route timing simulation in third-party EDA
tools.
After you purchase a license for the POS-PHY Level 4 MegaCore, you can
request a license file from the Altera web site at
www.altera.com/licensing and install it on your PC or workstation.
When you request a license file, Altera e-mails you a license.dat file.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
Before you set up licensing for the POS-PHY Level 4 MegaCore,
you must already have the Quartus II software installed on your
PC or workstation, with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
Altera Corporation
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrumTM
Synplify
ModelSim
2.
Open the POS-PHY Level 4 MegaCore license file in a text editor.
The file should contain one FEATURE line, spanning two lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the POS-PHY Level 4 MegaCore
license file and paste it into a new line in the Quartus II license file.
73
Getting Started
1
3
POS-PHY Level 4 MegaCore Function User Guide
1
5.
Getting Started
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Perform PostRoute
Simulation
74
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
After you have licensed the POS-PHY Level 4 core, you can generate
EDIF, VHDL, Verilog HDL, and Standard Delay Output (.sdo) files from
the Quartus II software and use them with your existing EDA tools to
perform functional modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
Altera Corporation
Getting Started
POS-PHY Level 4 MegaCore Function User Guide
3.
Compile your design with the Quartus II software, refer to “Using
the Quartus II Development Tool for Compilation & Place-andRoute” on page 72. The Quartus II software generates output and
programming files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
3
Getting Started
Altera Corporation
75
Specifications – Single-PHY
Overview
This chapter describes single-PHY configurations, which use the
individual FIFO buffer mode. This mode configures the POS-PHY Level 4
core to use a single Atlantic FIFO buffer. These configurations are
available in three versions (full size, half size, and quarter rate).
Functional
Description
The POS-PHY Level 4 core functions either as a transmitter source where
data flows from the Atlantic interface to the SPI-4 interface, or as a receiver
sink where data flows from the SPI-4 interface to the Atlantic interface.
1
The transmitter is always configured as the source, the receiver
is always configured as the sink. In order for the core to act as a
full-duplex, bidirectional transceiver, you need to instantiate one
of each configuration.
The following sections list the features for the receiver and transmitter,
assuming a full-featured configuration.
Receiver
Accepts packets (or cells) from the SPI-4.2 interface
Control word processing
Diagonal interleaved parity (DIP-4) parity error detection
Fixed SOP alignment to the most significant byte lane
FIFO buffer status management
4
Single-PHY
■
■
■
■
■
Transmitter
■
■
■
■
■
Receiver
Altera Corporation
Inserts training sequence
Sends data packets (or cells) on the SPI-4.2 interface
Inserts control words
Generates DIP-4 parity
FIFO buffer status management
This section gives a block-by-block description of how the SPHY POSPHY Level 4 core functions as a receiver. Figure 32 on page 78 shows the
blocks and signals that comprise the SPHY receiver.
77
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
Figure 32. Receiver Block Diagram
(3)
Receiver
DPA
Signals
(1)
rrefclk
rxreset_n
dpa_locked
dpa_error
dpa_lvds_locked
dpa_force_unlock
rdclk
rctl
rdat[15:0]
SPI-4.2
Interface
rsclk
a0_arxclk
a0_arxreset_n
a0_arxena
SERDES
(2)
a0_arxdav
POS-PHY
Level 4
Block
ALT
DDRIO
Atlantic
FIFO
Buffer
a0_arxdat[ATLDW-1:0] (4)
a0_arxval
Atlantic
Interface
a0_arxsop
a0_arxeop
rstat[1:0]
a0_arxmty[ATLMTY-1:0] (5)
rsfrm
dip4_err
msop_err
meop_err
Core
sop8_err
Status
Signals mp_erradr[7:0] (6)
paddr_err
rxfifo_oflw0
a0_arxerr
Receiver
Status
Processor
rxfifo_uflw0
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
The DPA signals are only valid if the dynamic phase alignment parameter is enabled.
Serializer/deserializer block.
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
The mp_erradr signal is always set to zero.
Clock & Data
The receiver requires two global clock domains: one for the Atlantic
interface side, and one for the SPI-4.2 interface side.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is deserialized to either:
■
■
■
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
For rates above 311 Mbps, the Stratix GX (including an embedded DPA
macro), Stratix and APEX II devices contain a dedicated full custom
SERDES (ALTLVDS function) implemented in hard silicon (True-LVDS™
I/Os). For rates below 250 Mbps, Flexible-LVDS™ I/O pins are used.
1
78
A fast PLL is required for the ALTLVDS SERDES.
Altera Corporation
Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Figure 33 shows the data flow within the receiver.
Figure 33. Receiver Data Flow
SPI-4.2 Interface
Atlantic Interface
(Master Source)
High-Speed
Interface (1)
& Deserializer
Control Word
Processing
& DIP-4
SOP
Alignment
& Atlantic
Conversion
FIFO Buffer
Status & Management
To
FIFO Buffer
From
FIFO Buffer
Note:
(1)
The high-speed interface is only present for full- and half-size configurations.
High-Speed Interface & Deserializer
For full- and half-size configurations, an ALTLVDS function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/8 and
1/4 the rdat data rate depending on application.
Figure 34 on page 80 shows the receiver input port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an internal clock.
The rxpll_outclock (rrefclk) is the main clock that drives the
internal logic elements for the receiver.
1
Altera Corporation
The ALTLVDS macro does not require a reset.
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4
Single-PHY
Data words arrive on the rdat bus at 2×rdclk rate. Payload data words
contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form the
second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least
significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB
of the second byte.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
Figure 34. Receiver Input Port Configuration
Deserializer
rdat0
SERDES
.
.
.
rdat7
SERDES
rdat8
SERDES
.
.
.
TDM
8, 4 (2)
txctl
rdat15
SERDES
rctl
SERDES
rdclk
128, 64 (2)
txdat
PLL
x W/J (1)
rxpll_outclock
Notes:
(1)
(2)
W = 2; J = 8 (full size), J=4 (half size)
Depends on selected data path width.
For quarter-rate configurations, the ALTDDRIO function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/2 the
rdat data rate depending on application.
Control Word Processing & DIP-4
This block analyses the input data stream, and checks the output of the
running DIP-4 calculation.
The data word on the bus can be either a control word or payload. If the
word currently on the bus is a control word, this block verifies that its
DIP-4 nibble is equal to the DIP-4 calculated over the previous payload
packet by checking the output of the running DIP-4 calculation. If the
running DIP-4 calculation (calculated over the previous payload packet)
does not match the DIP-4 nibble contained in the control word, dip4_err
is asserted. A DIP-4 error on an EOP control word causes the packet to be
marked with an error (the a0_arxerr signal on the Atlantic interface is
asserted at EOP).
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
This block also checks for SOP violations, where SOPs occur less than eight
cycles apart. A violation drives the sop8_err signal high. This signal
remains high for one rrefclk clock cycle, and is self-clearing.
If the number of bytes in a packet is odd, the last byte in the data word
[7:0] is set to all 0s. If the number of bytes in a packet is odd, but the last
byte [7:0] is not set to 0, the packet is marked with an error (the
a0_arxerr signal on the Atlantic interface is asserted at EOP).
The training pattern is treated as IDLEs and discarded. The training
pattern has no internal function because the data entering the main core is
already byte aligned. The same applies for reserved control words and
extended addressing.
If the destination address is invalid (i.e., larger than the calendar
multiplier parameter), the paddr_err line is asserted.
f
For further information on the DIP-4, refer to the System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer
Devices, available at www.oiforum.com.
SOP Alignment & Atlantic Conversion
This block locates the SOP in the current data words and aligns the data to
ensure that valid data is contiguous (no IDLEs) before sending it to the
FIFO buffer. This procedure involves three steps:
1.
The control words are shifted to one end of the data bus, and data is
packed together at the other end. The control words are now
considered null data.
The null data is removed by overlaying new valid data into the null
data locations in a compaction buffer.
3.
The SOP is now aligned to the most significant byte with contiguous
valid data in the data word. When either an entire word is filled or
an EOP is received, the word is transferred to the buffer.
For 128- or 64-bit data paths the data word is expanded times two, so the
compaction buffer never overflows.
FIFO Buffer Status & Management
This block manages the rstat line. FIFO buffer usage statistics are taken
from the FIFO buffer and processed using the user-defined AE and AF
parameters. This block also inserts the DIP-2 running calculation.
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81
Single-PHY
2.
4
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
When the rsfrm signal is asserted, the status channel contains only the
framing pattern. When the rsfrm signal is deasserted, the status channel
is enabled.
1
This is a method to manually request training from the
adjacent device.
FIFO Buffer
The individual FIFO buffer mode uses a single Atlantic FIFO buffer.
■
■
■
■
■
■
Single receive slave-sink Atlantic interface on the user end
Configurable FIFO buffer size
Support for crossing clock domains
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
–
Optional packet-based data available (dav) signal assertion
Atlantic interface error checking
–
Missing or spurious SOP/EOP detection and correction
Atlantic interface data width conversion
Figure 35 shows the data flow within the receiver’s FIFO buffer.
Figure 35. Receiver FIFO Buffer Data Flow
Atlantic Interface
(Slave Sink)
From
Main Core
Clock Domain
Border
Atlantic
Error
Checker
Atlantic
FIFO
Buffer
Atlantic Interface
(Slave Source)
Converter
Block
To User Logic
To FIFO Buffer Status & Management
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Atlantic FIFO Error Checker
This block performs error checking, and recovery on data and control
signals before they are written to the Atlantic FIFO buffer. It checks for
missing SOP and EOP markers, at each port. If these markers are found to
be missing, their respective msop_err and meop_err signals are driven
high. These signals remain high for one rrefclk clock cycle, and are selfclearing. These error conditions do not correlate directly—in terms of
latency—to the data coming out of the FIFO buffer.
Missing SOP
If incoming data contains one or more EOPs without corresponding SOPs
(see Figure 36), the block deasserts the enable after the last EOP (see
Figure 37). This deassertion indicates that the current data between the
SOP to EOP transition is a valid packet, and that everything following the
EOP is discarded until the next SOP is received. None of the packets are
marked as errored, so it is up to the user logic to determine which cells or
packets have been dropped.
Figure 36. Missing SOP Input Timing Diagram
clk
ena
Missing SOP
sop
eop
4
err
Single-PHY
Figure 37. Missing SOP Output Timing Diagram
clk
ena
sop
eop
err
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POS-PHY Level 4 MegaCore Function User Guide
1
Specifications – Single-PHY
Certain conditions within the internal core logic may cause
part of the missing SOP to merge with the previous good
packet. If such a merger occurs, no more than 64 bytes are
added.
Missing EOP
Figure 38 shows that if one or more extra SOPs are received before an EOP
is received, the SOP signal going to the FIFO buffer is negated and the data
is concatenated with the previous packet. Figure 39 shows that the ERR
signal is asserted to indicate a corrupt packet.
Figure 38. Missing EOP Input Timing Diagram
Packet A
Packet B
clk
ena
sop
eop
err
1
Internal core logic may not allow for perfect packet
concatenation. Therefore, the resulting corrupt packet size is
equal to: packet A+ packet B ± 32 bytes.
Figure 39. Missing EOP Output Timing Diagram
clk
ena
sop
eop
err
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Atlantic FIFO Buffer
The FIFO buffer is used for clock decoupling between the a0_arxclk and
the rrefclk clock signals. A dedicated FIFO buffer is instantiated, and is
user configurable. The read and write sides of the FIFO buffer operate on
different clock domains. The FIFO buffer is a dual Atlantic interface slave.
Crossing Clock Domains
To cross from the receiver core clock rate to the user-specific clock rate, a
FIFO buffer is placed between the clocks to perform statistical averaging
of smaller packets.
Converter Block
This block reduces the FIFO buffer width by a factor of two. The function
of this block depends on the Atlantic interface data width chosen as a
parameter (256, 128, 64, or 32 bits).
Signals
Tables 23 through 27 list the I/O signals used in the receiver core. The
active low signals are indicated by _n.
Table 23. SPI-4.2 Receive Interface
Signal
Direction
Description
4
LVDS Input
(clock pin)
SPI-4.2 differential receive clock. Ideally a 50% duty cycle.
rctl
LVDS Input
(data pin)
SPI-4.2 differential receive control. When high, the word on rdat is a control
word. When low, the word on rdat is a payload word. rctl runs at 2 × rdclk
MHz.
rdat[15:0] LVDS Input
(data pin)
SPI-4.2 differential receive data bus. Bus carries packets/cells or in-band
control words. rdat runs at 2 × rdclk MHz.
LVTTL Output
(data pin)
SPI-4.2 receive status clock. This signal does not use a global clock out pin, it
uses a regular LVTTL data pin.
rstat[1:0] LVTTL Output
(data pin)
SPI-4.2 receive status channel. Used to indicate the upstream device’s FIFO
buffers.
rsclk
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Single-PHY
rdclk
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
Table 24. Atlantic Receive Interface (Slave Source)
Signal
Direction
Description
a0_arxclk
Input
Clock
a0_arxreset_n
Input
Active low reset to all internal logic, synchronous to the
a0_arxclk domain.
a0_arxdav
Output
FIFO buffer has at least FTL words to read.
a0_arxena
Input
Enable
a0_arxdat[ATLDW-1:0](1)
Output
Data bus
a0_arxval
Output
Data valid
a0_arxsop
Output
Start of packet
a0_arxeop
Output
End of packet
a0_arxmty[ATLMTY-1:0](2) Output
Output
a0_arxerr
Number of invalid octets on the data bus
Data error
Notes from Table 24:
(1)
(2)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Table 25. Internal Receiver Core Configuration Signals Note (1)
Signal
Direction
Description
rxAE[n-1:0](2)
Input
Almost empty—starving to hungry threshold
rxAF[n-1:0](2)
Input
Almost full—hungry to satisfied threshold
rxCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and framing occurs.
rxFTL[n-1:0](2) Input
FIFO buffer threshold low watermark
Notes from Table 25:
(1)
(2)
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
For 128-bit configurations, n is equal to log2(FIFO buffer size per port/(data path width × 2). For 64- and 32-bit
configurations, n is equal to log2(FIFO buffer size per port/data path width).
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Table 26. Core Receive Status Signals
Signal
Direction
Description
dip4_err
Output
The DIP-4 calculated over the rdat line does not match the DIP-4 value in the
control line. Single system clock (rrefclk) tick wide pulse.
msop_err
Output
Missing SOP
meop_err
Output
Missing EOP
sop8_err
Output
SOP violation. Two SOPs occurred less than eight tdat cycles apart.
mp_erradr[7:0]
Output
Address qualifier for meop_err and msop_err flags. This signal is set to zero.
paddr_err
Output
Port address error. Attempting to write to an non-existent port.
rsfrm
Input
When asserted, the rsfrm signal forces the receiver status channel into
framing mode. This can be used to indicate that the receiver requires retraining.
rxfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
rxfifo_uflw0
Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Synchronous to the Atlantic interface clock.
Table 27. Global Receive Signals
Signal
Direction
Description
rrefclk
Output
Derived from rdclk, depends on data path width.
rxreset_n
Input
Active low reset to all internal logic, synchronized to the rrefclk domain
4
1
Single-PHY
Table 28 shows the DPA signals used by the receiver.
Only applicable when using the DPA circuitry of a
Stratix GX device.
Table 28. DPA Status Signals (Receiver Only)
Signal
dpa_error
Direction
Output
dpa_force_unlock Input
Description
Error flag to indicate that the DPA circuitry could not find byte alignment
Forces the DPA circuitry and PLL to unlock and retrain
dpa_locked
Output
When this signal is high, it indicates that the DPA aligner has aligned to
the training pattern
dpa_lvds_locked
Output
When this signal is high, it indicates that the DPA PLL has locked
Altera Corporation
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POS-PHY Level 4 MegaCore Function User Guide
Transmitter
Specifications – Single-PHY
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a transmitter. Figure 40 on page 88 shows the
blocks and signals that comprise the transmitter.
Figure 40. Transmitter Block Diagram
(1)
Transmitter
dip2_err
Core
Status tstat_sync
Signals txfifo_uflw0
a0_atxclk
a0_atxreset_n
a0_atxena
trefclk
a0_atxdav
txreset_n
POS-PHY
Level 4
Block
Atlantic
FIFO
Buffer
tdclk
tctl
SPI-4.2
Interface
a0_atxdat[ATLDW-1:0] (2)
Atlantic
Interface
a0_atxsop
a0_atxeop
SERDES
a0_atxmty[ATLMTY-1:0] (3)
tdat[15:0]
a0_atxerr
txfifo_oflw0
tsclk
ALT
DDRIO
tstat[1:0]
Notes:
(1)
(2)
(3)
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Clock & Data
The transmitter requires three clock domains: one for the Atlantic
interface side, one for the SPI-4.2 interface side, and one for the status
clock domain.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is serialized to either:
■
■
■
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
Figure 41 on page 89 shows the data flow within the transmitter.
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Figure 41. Transmitter Data Flow
SPI-4.2 Interface
Atlantic Interface
(Master Sink)
High-Speed
Interface (1)
& Serializer
Control Word
Insertion
& DIP-4
Scheduler
&
Training
Pattern
Insertion
From
FIFO Buffer
FIFO Buffer
Status & Management
Note:
(1)
The high-speed interface is only present for full- and half-size configurations.
High-Speed Interface & Serializer
Data words are sent on the tdat data bus at 2×tdclk rate. Payload data
words contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form
the second byte. Bit 15 is the MSB, and bit 8 is the LSB of the first byte. Bit
7 is the MSB, and bit 0 is the LSB of the second byte.
For full- and half-size configurations, an ALTLVDS function is used to
serialize the words into input high-speed tdat/tctl lines.
4
For the output clock (tdclk), the user should not use the LVDS output
clock pins, but should use an appropriate LVDS data pair instead. The
tdclk pin can be treated as a data pin, because the SERDES is preloaded
with a binary 1010 pattern that guarantees an appropriate skew between
the clock and data.
1
Altera Corporation
The ALTLVDS macro does not require a reset.
89
Single-PHY
Figure 42 on page 90 shows the transmitter output port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an output clock.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
Figure 42. Transmitter Output Port Configuration
Serializer
tdat0
SERDES
.
.
.
tdat7
128, 64 (1)
rxdat
SERDES
8, 4 (2)
rxctl
tdat8
SERDES
.
.
.
Demultiplexer
tdat15
SERDES
tctl
SERDES
tdclk
trefclk
SERDES
PLL
Notes:
(1)
(2)
Depends on selected data path width.
The deserialisation factor is 8 for full-size, or 4 for half-size configurations.
For quarter-rate configurations, an ALTDDRIO function is used to
serialize the words into input high-speed tdat/tctl lines.
Control Word Insertion & DIP-4
This block inserts control words into the data path, and performs DIP-4
insertion.
An EOP abort condition can be generated on the SPI-4.2 interface by
asserting a0_atxerr with a valid a0_atxeop on the Atlantic interface.
This condition is the only one for which the EOP abort bit can be set in the
control word.
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Scheduler
The scheduler block receives decoded status channel information. It uses
this information to determine whether the FIFO buffer is starving, hungry,
or satisfied. The port becomes active if that channel status is starving or
hungry, and the FIFO buffer indicates that it contains some data.
No address polling or decoding is required, but the starving and hungry
conditions are still monitored. When a selected FIFO buffer is starving or
hungry, the scheduler continuously reads out of the FIFO buffer. It does
not stop reading until the status channel reports that the FIFO buffer is
ready for satisfied mode. An internal counter counts up to MB1 or MB2,
(depending on the FIFO buffer mode as determined by the scheduler), and
inserts a continue control word before proceeding to read MB1 or MB2
chunks of data from the FIFO buffer. If a training pattern is scheduled, the
current packet completes to the continue insertion mark (MB1/MB2) before
the training pattern is inserted. If the scheduler runs dry, the scheduler
prompts the insertion of IDLEs.
Training Pattern Insertion
This block inserts the training pattern at a scheduled interval defined by
the maximum training sequence interval parameter. If the training pattern
is asserted on the status channel, the core continuously sends training
patterns. The training pattern is sent out ALPHA (α) times.
1
If α = 0, the training pattern is not sent at MaxT, but still responds
to the framing pattern. The tstat_sync signal is observed as
low in this state.
1
Altera Corporation
This feature is used to support dynamic alignment on adjacent
receivers.
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4
Single-PHY
The training sequence includes one IDLE control word, plus α×20 words.
The twenty words are separated into ten consecutive tdat words of
16’h0FFF with tctl of 1’b1, followed by ten consecutive tdat words of
16’hF000 with tctl of 1’b0. The user should expect some IDLEs before
and after the training sequence.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
FIFO Buffer Status & Management
This block monitors the tstat line (status channel) for DIP-2 or loss of
frame (LOF) errors. If a DIP-2 error occurs, the dip2_err signal is
asserted. The scheduler table is cleared when a DIP-2 error occurs. The
current transfer is not interrupted because the transfer is based on
MB1/MB2. If the status channel has not recovered by the time MB1/MB2 is
transmitted, it transmits IDLEs until a valid frame of status is received,
and the scheduler table is refreshed. The block forwards the extracted
status information (when requested) to the scheduler block. The DIP-2
error is cleared at the next tstat framing sequence.
When a DIP-2 error occurs, all the queues in the scheduler are cleared, and
the system recovers on its own (the current transfer continues to
completion).
FIFO Buffer
The individual FIFO buffer mode uses a single Atlantic FIFO buffer.
■
■
■
■
■
Single transmit slave-source Atlantic interface on the user end
Configurable FIFO buffer size
Support for crossing clock domains
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
–
Optional packet-based data available (dav) signal assertion
Atlantic interface data width conversion
Figure 43 on page 93 shows the data flow within the transmitter’s FIFO
buffer.
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Figure 43. Transmitter FIFO Buffer Data Flow
Atlantic Interface
(Master Sink)
To
Main Core
Atlantic Interface
(Slave Sink)
Atlantic
FIFO Buffer
Converter
Block
From User
Atlantic FIFO Buffer
The FIFO buffer is used for clock decoupling between the atxclk and the
trefclk clock signals. A dedicated FIFO buffer is instantiated, and is
user configurable. The read and write sides of the FIFO buffer operate on
different clock domains. The FIFO buffer is a dual Atlantic interface slave.
Converter Block
This block expands the data path to the FIFO buffer width by a factor of
two. The function of this block depends on the Atlantic interface data
width chosen as a parameter.
Signals
Tables 29 through 33 list the I/O signals used in the transmitter core. The
active low signals are indicated by _n.
Single-PHY
Table 29. SPI-4.2 Transmit Interface(Part 1 of 2)
Signal
Direction
Description
tdclk
LVDS Output
(data pin)
SPI-4.2 differential transmit clock. Ideally a 50% duty cycle. This signal uses
the data pin to produce the output clock to match the skew with tdat[15:0].
tctl
LVDS Output
(data pin)
SPI-4.2 differential transmit control. When high, the word on tdat is a control
word. When low, the word on tdat is a payload word. tctl runs at 2 × tdclk
MHz.
tdat[15:0] LVDS Output
(data pin)
tsclk
LVTTL Input
(clock pin)
Altera Corporation
4
SPI-4.2 differential transmit data bus. Bus carries packets/cells or in-band
control words. tdat runs at 2 × tdclk MHz.
SPI-4.2 transmit status clock.
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POS-PHY Level 4 MegaCore Function User Guide
Specifications – Single-PHY
Table 29. SPI-4.2 Transmit Interface(Part 2 of 2)
Signal
Direction
tstat[1:0] LVTTL Input
(data pin)
Description
SPI-4.2 transmit status channel. Used to indicate the downstream device’s
FIFO buffers.
Table 30. Atlantic Transmit Interface
Signal
Direction
Description
a0_atxclk
Input
Clock
a0_atxreset_n
Input
Active low reset to all internal logic, synchronous to the atxclk
domain
a0_atxdav
Output
FIFO buffer has at least FTH words to be written.
a0_atxena
Input
Enable
a0_atxdat[ATLDW-1:0](1)
Input
Data bus
a0_atxsop
Input
Start of packet
a0_atxeop
Input
End of packet
a0_atxmty[ATLMTY-1:0](2) Input
Input
a0_atxerr
Number of invalid octets on the data bus
Data error
Notes from Table 30:
(1)
(2)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Table 31. Core Transmit Status Signals
Signal
Direction
Description
dip2_err
Output
The DIP-2 calculated for the FIFO buffer stat line does not match the DIP-2
provided. Single FIFO buffer stat (trefclk) clock tick wide pulse.
tstat_sync
Output
Indicates that the status channel is synchronized with proper framing. Asserted
low for improper configuration of status channel.
txfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
Synchronous to the Atlantic interface clock.
txfifo_uflw0
Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
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Specifications – Single-PHY
POS-PHY Level 4 MegaCore Function User Guide
Table 32. Global Transmit Signals
Signal
Direction
Description
trefclk
Input
Reference for tdclk.
txreset_n
Input
Active low reset to all internal logic. Must be synchronous to trefclk.
Table 33. Internal Transmitter Core Configuration Signals Note (1)
Signal
Direction
Description
txALPHA[7:0]
Input
Number of training pattern sequence repetitions
txCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and framing occurs.
txAE[n-1:0](2)
Input
Almost empty—starving to hungry threshold for each PHY port
txAF[n-1:0](2)
Input
Almost full—hungry to satisfied threshold for each PHY port
txFTH[n-1:0](2) Input
FIFO buffer threshold high watermark
txFTL[n-1:0](2) Input
FIFO buffer threshold low watermark
txMAXT[15:0]
Input
Training sequence interval
txMB1[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
starving.
txMB2[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
hungry.
4
Notes from Table 33:
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
n is equal to the FIFO buffer size per port/(data path width × 2).
Altera Corporation
95
Single-PHY
(1)
(2)
Specifications – Multi-PHY with
Individual FIFO Buffer per Port
Overview
This chapter describes multi-PHY configurations using the individual
FIFO buffer per port mode. This mode configures the POS-PHY Level 4
core to use a single Atlantic FIFO buffer for each port. These
configurations are available in three versions (full size, half size, and
quarter rate).
Functional
Description
The POS-PHY Level 4 core functions either as a transmitter source where
data flows from the Atlantic interface to the SPI-4 interface, or as a receiver
sink where data flows from the SPI-4 interface to the Atlantic interface.
1
The transmitter is always configured as the source, the receiver
is always configured as the sink. In order for the core to act as a
full-duplex, bidirectional transceiver, you need to instantiate one
of each configuration.
The following sections list the features for the receiver and transmitter,
assuming a full-featured configuration.
Receiver
Accepts packets (or cells) from the SPI-4.2 interface
Control word processing
Diagonal interleaved parity (DIP-4) parity error detection
Fixed SOP alignment to the most significant byte lane
FIFO buffer status management
4
Transmitter
■
■
■
■
■
Receiver
Altera Corporation
Inserts training sequence
Sends data packets (or cells) on the SPI-4.2 interface
Inserts control words
Generates DIP-4 parity
FIFO buffer status management
This section gives a block-by-block description of how the MPHY POSPHY Level 4 core functions as a receiver. Figure 44 on page 98 shows an
example MPHY receiver with four ports and FIFO buffers, including the
blocks and signals that comprise this configuration.
97
Specifications-MPHY
Individual Buffers
■
■
■
■
■
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Figure 44. Receiver Block Diagram
(3)
Receiver
a0_arxclk
a0_arxreset_n
a0_arxena
a0_arxdav
Atlantic
FIFO
Buffer
a0_arxdat[ATLDW-1:0] (4)
a0_arxval
Atlantic
Interface
a0_arxsop
a0_arxeop
a0_arxmty[ATLMTY-1:0] (5)
rrefclk
a0_arxerr
rxreset_n
dpa_locked
dpa_error
dpa_lvds_locked
dpa_force_unlock
DPA
Signals
(1)
rdclk
rxfifo_uflw0
a1_arxclk
a1_arxreset_n
SERDES
(2)
a1_arxena
a1_arxdav
rctl
Atlantic
FIFO
Buffer
rdat[15:0]
SPI-4.2
Interface
rsclk
a1_arxdat[ATLDW-1:0] (4)
a1_arxval
ALT
DDRIO
a1_arxsop
a1_arxeop
a1_arxmty[ATLMTY-1:0] (5)
rstat[1:0]
rsfrm
dip4_err
msop_err
meop_err
a1_arxerr
POS-PHY
Level 4
Block
rxfifo_uflw1
a2_arxclk
a2_arxreset_n
sop8_err
Core
Status mp_erradr[7:0]
Signals
paddr_err
...
rxfifo_oflw0
Atlantic
Interface
a2_arxena
a2_arxdav
Atlantic
FIFO
Buffer
a2_arxdat[ATLDW-1:0] (4)
a2_arxval
Atlantic
Interface
a2_arxsop
rxfifo_oflwn
a2_arxeop
a2_arxmty[ATLMTY-1:0] (5)
(4)
a2_arxerr
...
rxfifo_uflw2
(6)
an_arxclk
an_arxreset_n
an_arxena
an_arxdav
Atlantic
FIFO
Buffer
an_arxadr[7:0]
an_arxdat[ATLDW-1:0] (4)
Atlantic
Interface
an_arxval
an_arxsop
an_arxeop
an_arxmty[ATLMTY-1:0] (5)
(6)
an_arxerr
rxfifo_uflwn
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
98
The DPA signals are only valid if the dynamic phase alignment parameter is enabled.
Serializer/deserializer block.
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
n is equal to the number of ports.
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Clock & Data
The receiver requires a maximum of 1 + n clock domains: n for the Atlantic
interface side (where n is the number of ports), and one for the SPI-4.2
interface side. A separate clock can be used for each port’s Atlantic
interface, or can be combined to a single clock domain.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is deserialized to either:
■
■
■
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
For rates above 311 Mbps, the Stratix GX (including an embedded DPA
macro), Stratix and APEX II devices contain a dedicated full custom
SERDES (ALTLVDS function) implemented in hard silicon (True-LVDS™
I/Os). For rates below 250 Mbps, Flexible-LVDS™ I/O pins are used.
1
A fast PLL is required for the ALTLVDS SERDES.
Figure 45 shows the data flow within the receiver.
Figure 45. Receiver Data Flow
SPI-4.2 Interface
Atlantic Interface
(Master Source)
4
FIFO Buffer
Status & Management
SOP
Alignment
& Atlantic
Conversion
To
FIFO Buffer
From
FIFO Buffer
Note:
(1)
Altera Corporation
The high-speed interface is only present for full- and half-size configurations.
99
Specifications-MPHY
Control Word
Processing
& DIP-4
Individual Buffers
High-Speed
Interface (1)
& Deserializer
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
High-Speed Interface & Deserializer
Data words arrive on the rdat bus at 2×rdclk rate. Payload data words
contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form the
second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least
significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB
of the second byte.
For full- and half-size configurations, an ALTLVDS function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/8 and
1/4 the rdat data rate depending on application.
Figure 46 on page 100 shows the receiver input port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an internal clock.
The rxpll_outclock (rrefclk) is the main clock that drives the
internal logic elements for the receiver.
1
The ALTLVDS macro does not require a reset.
Figure 46. Receiver Input Port Configuration
Deserializer
rdat0
SERDES
.
.
.
rdat7
SERDES
rdat8
SERDES
.
.
.
TDM
8, 4 (2)
txctl
rdat15
SERDES
rctl
SERDES
rdclk
128, 64 (2)
txdat
PLL
x W/J (1)
rxpll_outclock
Notes:
(1)
(2)
100
W = 2; J = 8 (full size), J=4 (half size)
Depends on selected data path width.
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
For quarter-rate configurations, the ALTDDRIO function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/2 the
rdat data rate depending on application.
Control Word Processing & DIP-4
This block analyses the input data stream, and checks the output of the
running DIP-4 calculation.
The data word on the bus can be either a control word or payload. If the
word currently on the bus is a control word, this block verifies that its
DIP-4 nibble is equal to the DIP-4 calculated over the previous payload
packet by checking the output of the running DIP-4 calculation. If the
running DIP-4 calculation (calculated over the previous payload packet)
does not match the DIP-4 nibble contained in the control word, dip4_err
is asserted. A DIP-4 error on an EOP control word causes the packet to be
marked with an error (the an_arxerr signal on the Atlantic interface is
asserted at EOP).
This block also checks for SOP violations, where SOPs occur less than eight
cycles apart. A violation drives the sop8_err signal high. This signal
remains high for one rrefclk clock cycle, and is self-clearing.
If the number of bytes in a packet is odd, the last byte in the data word
[7:0] is set to all 0s. If the number of bytes in a packet is odd, but the last
byte [7:0] is not set to 0, the packet is marked with an error (the
an_arxerr signal on the Atlantic interface is asserted at EOP).
f
For further information on the DIP-4, refer to the System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer
Devices, available at www.oiforum.com.
SOP Alignment & Atlantic Conversion
This block locates the SOP in the current data words and aligns the data to
ensure that valid data is contiguous (no IDLEs) before sending it to the
FIFO buffer. This procedure involves three steps:
Altera Corporation
101
Specifications-MPHY
If the destination address is invalid (i.e., larger than the calendar
multiplier parameter), the paddr_err line is asserted.
4
Individual Buffers
The training pattern is treated as IDLEs and discarded. The training
pattern has no internal function because the data entering the main core is
already byte aligned. The same applies for reserved control words and
extended addressing.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
1.
The control words are shifted to one end of the data bus, and data is
packed together at the other end. The control words are now
considered null data.
2.
The null data is removed by overlaying new valid data into the null
data locations in a compaction buffer.
3.
The SOP is now aligned to the most significant byte with contiguous
valid data in the data word. When either an entire word is filled or
an EOP is received, the word is transferred to the buffer.
For 128- or 64-bit data paths the data word is expanded times two, so the
compaction buffer never overflows.
FIFO Buffer Status & Management
This block manages the rstat line. FIFO buffer usage statistics are taken
from each FIFO buffer and processed using the user-defined AE and AF
parameters. This block also inserts the DIP-2 running calculation.
When the rsfrm signal is asserted, the status channel contains only the
framing pattern. When the rsfrm signal is deasserted, the status channel
is enabled.
1
This is a method to manually request training from the
adjacent device.
FIFO Buffer
The individual FIFO buffer per port mode configures the POS-PHY
Level 4 core to use a single Atlantic FIFO buffer for each port.
■
■
■
■
■
102
Single receive slave-sink Atlantic interface per buffer on the user end
Configurable FIFO buffer size, all buffers are configured to the same
depth and width
Supports a maximum of:
–
Four ports for full-size (128-bit) configurations
–
Ten ports for half-size (64-bit) configurations
–
Ten ports for quarter-rate (32-bit) configurations
Support for crossing clock domains
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
■
■
POS-PHY Level 4 MegaCore Function
–
Optional packet-based data available (dav) signal assertion
Atlantic interface error checking
–
Missing or spurious SOP/EOP detection and correction
Atlantic interface data width conversion
The advantage of the individual FIFO buffer per port mode is that each
Atlantic interface can be accessed in parallel and independently, thus
avoiding head of line blocking. For POS-PHY Level 4 receivers, the
Atlantic-side user logic may read from each FIFO buffer in parallel. The
relative fill level (starving, hungry, satisfied) for each port is reflected in
the SPI-4.2 interface FIFO buffer status channel transmitted by the POSPHY Level 4 core receiver.
1
Since the number of ports increases the LE utilization
directly, this buffer mode is not well suited for applications
with a large number of ports.
Figure 47 shows the data flow within the receiver’s FIFO buffer.
Figure 47. Receiver FIFO Buffer Data Flow
Atlantic Interface
(Slave Sink)
From
Main Core
Clock Domain
Border
Atlantic
Error
Checker
Atlantic
FIFO
Buffer
Atlantic Interface
(Slave Source)
Converter
Block
To User Logic
4
Atlantic FIFO Error Checker
This block performs error checking, and recovery on data and control
signals before they are written to the Atlantic FIFO buffer. It checks for
missing SOP and EOP markers, at each port. If these markers are found to
be missing, their respective msop_err and meop_err signals are driven
high. These signals remain high for one rrefclk clock cycle, and are selfclearing. These error conditions do not correlate directly—in terms of
latency—to the data coming out of the FIFO buffer.
Altera Corporation
103
Specifications-MPHY
Individual Buffers
To FIFO Buffer Status & Management
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Missing SOP
If incoming data contains one or more EOPs without corresponding SOPs
(see Figure 48), the block deasserts the enable after the last EOP (see
Figure 49). This deassertion indicates that the current data between the
SOP to EOP transition is a valid packet, and that everything following the
EOP is discarded until the next SOP is received. None of the packets are
marked as errored, so it is up to the user logic to determine which cells or
packets have been dropped.
Figure 48. Missing SOP Input Timing Diagram
clk
Missing SOP
ena
sop
eop
err
Figure 49. Missing SOP Output Timing Diagram
clk
ena
sop
eop
err
1
Certain conditions within the internal core logic may cause
part of the missing SOP to merge with the previous good
packet. If such a merger occurs, no more than 64 bytes are
added.
Missing EOP
Figure 50 on page 105 shows that if one or more extra SOPs are received
before an EOP is received, the SOP signal going to the FIFO buffer is
negated and the data is concatenated with the previous packet. Figure 51
on page 105 shows that the ERR signal is asserted to indicate a corrupt
packet.
104
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Figure 50. Missing EOP Input Timing Diagram
Packet A
Packet B
clk
ena
sop
eop
err
1
Internal core logic may not allow for perfect packet
concatenation. Therefore, the resulting corrupt packet size is
equal to: packet A+ packet B ± 32 bytes.
Figure 51. Missing EOP Output Timing Diagram
clk
ena
sop
eop
err
4
Crossing Clock Domains
To cross from the receiver core clock rate to the user-specific clock rate, a
FIFO buffer is placed between the clocks to perform statistical averaging
of smaller packets.
Altera Corporation
105
Specifications-MPHY
FIFO buffers are used for clock decoupling between the a0_arxclk and
the rrefclk clock signals. A dedicated FIFO buffer is instantiated for
each port in the core, and is user configurable. The read and write sides of
the FIFO buffer operate on different clock domains. The FIFO buffers are
dual Atlantic interface slaves.
Individual Buffers
Atlantic FIFO Buffer
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Converter Block
This block reduces the FIFO buffer width by a factor of two. The function
of this block depends on the Atlantic interface data width chosen as a
parameter (256, 128, 64, or 32 bits).
Signals
Tables 34 through 38 list the I/O signals used in the receiver core. The
active low signals are indicated by _n.
Table 34. SPI-4.2 Receive Interface
Signal
Direction
Description
rdclk
LVDS Input
(clock pin)
SPI-4.2 differential receive clock. Ideally a 50% duty cycle.
rctl
LVDS Input
(data pin)
SPI-4.2 differential receive control. When high, the word on rdat is a control
word. When low, the word on rdat is a payload word. rctl runs at 2 × rdclk
MHz.
rdat[15:0] LVDS Input
(data pin)
SPI-4.2 differential receive data bus. Bus carries packets/cells or in-band
control words. rdat runs at 2 × rdclk MHz.
LVTTL Output
(data pin)
SPI-4.2 receive status clock. This signal does not use a global clock out pin, it
uses a regular LVTTL data pin.
rstat[1:0] LVTTL Output
(data pin)
SPI-4.2 receive status channel. Used to indicate the upstream device’s FIFO
buffers.
rsclk
Table 35. Atlantic Receive Interface (Slave Source) (Part 1 of 2)
Signal
Direction
Description
a0_arxclk
Input
Clock
a0_arxreset_n
Input
Active low reset to all internal logic, synchronous to the
a0_arxclk domain.
a0_arxdav
Output
FIFO buffer has at least FTL words to read.
a0_arxena
Input
Enable
a0_arxdat[ATLDW-1:0](1)
Output
Data bus
a0_arxval
Output
Data valid
a0_arxsop
Output
Start of packet
a0_arxeop
Output
End of packet
a0_arxmty[ATLMTY-1:0](2)
Output
Number of invalid octets on the data bus
a0_arxerr
Output
Data error
106
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Table 35. Atlantic Receive Interface (Slave Source) (Part 2 of 2)
Signal
Direction
Description
.
.
.
an_arxclk (3)
Input
Clock
an_arxreset_n(3)
Input
Active low reset to all internal logic, synchronous to the
an_arxclk domain.
an_arxdav(3)
Output
FIFO buffer has at least FTL words to read.
an_arxena(3)
Input
Enable
an_arxdat(3)[ATLDW-1:0](1)
Output
Data bus
an_arxval(3)
Output
Data valid
an_arxsop(3)
Output
Start of packet
an_arxeop(3)
Output
End of packet
an_arxmty(3)[ATLMTY-1:0](2) Output
Output
an_arxerr(3)
Number of invalid octets on the data bus
Data error
Notes from Table 35:
(1)
(2)
(3)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
n is equal to the number of ports.
Table 36. Internal Receiver Core Configuration Signals Note (1)
Signal
Direction
4
Description
Almost empty—starving to hungry threshold for each PHY port
Input
Almost full—hungry to satisfied threshold for each PHY port
rxCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and framing occurs.
rxFTL[n-1:0](2) Input
FIFO buffer threshold low watermark
Notes from Table 36:
(1)
(2)
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
For 128-bit configurations, n is equal to log2(FIFO buffer size per port/(data path width × 2)). For 64- and 32-bit
configurations, n is equal to log2(FIFO buffer size per port/data path width).
Altera Corporation
107
Specifications-MPHY
Input
rxAF[n-1:0](2)
Individual Buffers
rxAE[n-1:0](2)
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Table 37. Core Receive Status Signals
Signal
Direction
Description
dip4_err
Output
The DIP-4 calculated over the rdat line does not match the DIP-4 value in the
control line. Single system clock (rrefclk) tick wide pulse.
msop_err
Output
Missing SOP
meop_err
Output
Missing EOP
sop8_err
Output
SOP violation. Two SOPs occurred less than eight tdat cycles apart.
mp_erradr[7:0]
Output
Address qualifier for meop_err and msop_err flags
paddr_err
Output
Port address error. Attempting to write to an non-existent port.
rsfrm
Input
When asserted, the rsfrm signal forces the receiver status channel into
framing mode. This can be used to indicate that the receiver requires retraining.
rxfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
.
.
.
rxfifo_oflwn(1) Output
rxfifo_uflw0
Indicates that the FIFO buffer has overflowed, and data has been lost.
Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Synchronous to the Atlantic interface clock.
.
.
.
rxfifo_uflwn(1) Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Synchronous to the Atlantic interface clock.
Note from Table 37:
(1)
n is equal to the number ports.
Table 38. Global Receive Signals
Signal
Direction
Description
rrefclk
Output
Derived from rdclk, depends on data path width.
rxreset_n
Input
Active low reset to all internal logic, synchronized to the rrefclk domain
Table 39 shows the DPA signals used by the receiver.
108
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
1
POS-PHY Level 4 MegaCore Function
Only applicable when using the DPA circuitry of a
Stratix GX device.
Table 39. DPA Status Signals (Receiver Only)
Signal
dpa_error
Direction
Output
dpa_force_unlock Input
Description
Error flag to indicate that the DPA circuitry could not find byte alignment
Forces the DPA circuitry and PLL to unlock and retrain
dpa_locked
Output
When this signal is high, it indicates that the DPA aligner has aligned to the
training pattern
dpa_lvds_locked
Output
When this signal is high, it indicates that the DPA PLL has locked
Transmitter
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a transmitter. Figure 52 on page 110 shows the
blocks and signals that comprise the transmitter.
4
109
Specifications-MPHY
Individual Buffers
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Figure 52. Transmitter Block Diagram
(1)
a0_atxclk
Transmitter
a0_atxreset_n
a0_atxena
a0_atxdav
Atlantic
FIFO
Buffer
a0_atxdat[ATLDW-1:0] (2)
(2
Atlantic
Interface
a0_atxsop
a0_atxeop
a0_atxmty[ATLMTY-1:0] (3)
a0_atxerr
dip2_err
tstat_sync
txfifo_oflw0
txfifo_uflw
Core
Status
Signals
a1_atxclk
txfifo_uflw
a1_atxreset_n
txfifo_uflw
a1_atxena
txfifo_uflw
...
a1_atxdav
Atlantic
FIFO
Buffer
txfifo_uflw
a1_atxdat[ATLDW-1:0] (2)
a1_atxsop
Atlantic
Interface
a1_atxeop
a1_atxmty[ATLMTY-1:0] (3)
trefclk
a1_atxerr
txreset_n
txfifo_oflw1
a2_atxclk
tdclk
tctl
SERDES
POS-PHY
Level 4
Block
a2_atxreset_n
a2_atxena
tdat[15:0]
a2_atxdav
Atlantic
FIFO
Buffer
a2_atxdat[ATLDW-1:0] (2)
a2_atxsop
Atlantic
Interface
a2_atxeop
SPI-4.2
Interface
a2_atxmty[ATLMTY-1:0] (3)
a2_atxerr
txfifo_oflw2
(4)
...
tsclk
tstat[1:0]
an_atxclk
an_atxreset_n
an_atxena
an_atxdav
Atlantic
FIFO
Buffer
an_atxdat[ATLDW-1:0] (2)
an_atxsop
Atlantic
Interface
an_atxeop
an_atxmty[ATLMTY-1:0] (3) (4)
an_atxerr
txfifo_oflwn
Notes:
(1)
(2)
(3)
(4)
110
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
n is equal to the number of ports.
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Clock & Data
The transmitter requires three clock domains: one for the Atlantic
interface side, one for the SPI-4.2 interface side, and one for the status
clock domain.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is serialized to either:
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
■
■
■
Figure 53 shows the data flow within the transmitter.
Figure 53. Transmitter Data Flow
SPI-4.2 Interface
High-Speed
Interface (1)
& Serializer
Atlantic Interface
(Master Sink)
Control Word
Insertion
& DIP-4
Scheduler
&
Training
Pattern
Insertion
From
FIFO Buffer
4
Note:
(1)
The high-speed interface is only present for full- and half-size configurations.
High-Speed Interface & Serializer
Data words are sent on the tdat data bus at 2×tdclk rate. Payload data
words contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form
the second byte. Bit 15 is the MSB, and bit 8 is the LSB of the first byte. Bit
7 is the MSB, and bit 0 is the LSB of the second byte.
For full- and half-size configurations, an ALTLVDS function is used to
serialize the words into input high-speed tdat/tctl lines.
Altera Corporation
111
Specifications-MPHY
Individual Buffers
FIFO Buffer
Status & Management
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Figure 54 on page 112 shows the transmitter output port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an output clock.
For the output clock (tdclk), the user should not use the LVDS output
clock pins, but should use an appropriate LVDS data pair instead. The
tdclk pin can be treated as a data pin, because the SERDES is preloaded
with a binary 1010 pattern that guarantees an appropriate skew between
the clock and data.
1
The ALTLVDS macro does not require a reset.
Figure 54. Transmitter Output Port Configuration
Serializer
tdat0
SERDES
.
.
.
tdat7
128, 64 (1)
rxdat
SERDES
8, 4 (2)
rxctl
tdat8
SERDES
.
.
.
Demultiplexer
tdat15
SERDES
tctl
SERDES
tdclk
trefclk
SERDES
PLL
Notes:
(1)
(2)
Depends on selected data path width.
The deserialisation factor is 8 for full-size, or 4 for half-size configurations.
For quarter-rate configurations, an ALTDDRIO function is used to
serialize the words into input high-speed tdat/tctl lines.
112
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Control Word Insertion & DIP-4
This block inserts control words into the data path, and performs DIP-4
insertion.
An EOP abort condition can be generated on the SPI-4.2 interface by
asserting an_atxerr with a valid an_atxeop on the Atlantic interface.
This condition is the only one for which the EOP abort bit can be set in the
control word.
1
n represents the port number.
Scheduler
The scheduler block receives decoded status channel information. It uses
this information to determine which FIFO buffers are starving, hungry, or
satisfied. A port can become active if that channel status is starving or
hungry, and the FIFO buffer indicates that it contains some data.
A round-robin priority-based scheduler serves the starving FIFO buffers
first. When no starving FIFO buffers remain, the hungry FIFO buffers get
served.
When a selected FIFO buffer is starving, the scheduler requests the
number of remaining elements in the FIFO buffer or MaxBurst1,
whichever is less. If the selected FIFO buffer is hungry, the scheduler
requests the number of remaining elements in the FIFO buffer or
MaxBurst2, whichever is less. The training pattern is not inserted at EOP,
but is inserted at the end of the burst request.
This block inserts the training pattern at a scheduled interval defined by
the maximum training sequence interval parameter. If the training pattern
is asserted on the status channel, the core continuously sends training
patterns. The training pattern is sent out ALPHA (α) times.
1
Altera Corporation
If α = 0, the training pattern is not sent at MaxT, but still responds
to the framing pattern. The tstat_sync signal is observed as
low in this state.
113
Specifications-MPHY
Training Pattern Insertion
4
Individual Buffers
To ensure equality, the scheduler does not select a new FIFO buffer until
it has fulfilled the amount requested by the FIFO buffer being served; a
request can encompass many packets depending on the requested
amount. If the FIFO buffer runs dry, the scheduler serves another FIFO
buffer.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
The training sequence includes one IDLE control word, plus α×20 words.
The twenty words are separated into ten consecutive tdat words of
16’h0FFF with tctl of 1’b1, followed by ten consecutive tdat words of
16’hF000 with tctl of 1’b0. The user should expect some IDLEs before
and after the training sequence.
1
This feature is used to support dynamic alignment on adjacent
receivers.
FIFO Buffer Status & Management
This block monitors the tstat line (status channels) for DIP-2 or loss of
frame (LOF) errors. If a DIP-2 error occurs, the dip2_err signal is
asserted. The scheduler table is cleared when a DIP-2 error occurs. The
current transfer is not interrupted because the transfer is based on
MB1/MB2. If the status channel has not recovered by the time MB1/MB2 is
transmitted, it transmits IDLEs until a valid frame of status is received,
and the scheduler table is refreshed. The block forwards the extracted
status information (when requested) to the scheduler block. The DIP-2
error is cleared at the next tstat framing sequence.
When a DIP-2 error occurs, all the queues in the scheduler are cleared, and
the system recovers on its own (the current transfer continues to
completion).
FIFO Buffer
The individual FIFO buffer per port mode configures the POS-PHY
Level 4 core to use a single Atlantic FIFO buffer for each port.
■
■
■
■
■
■
114
Single transmit slave-source Atlantic interface per buffer on the user
end
Configurable FIFO buffer size, all buffers are configured to the same
depth and width
Supports a maximum of:
–
Four ports for full-size (128-bit) configurations
–
Ten ports for half-size (64-bit) configurations
–
Ten ports for quarter-rate (32-bit) configurations
Support for crossing clock domains
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
–
Optional packet-based data available (dav) signal assertion
Atlantic interface data width conversion
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
The advantage of the individual FIFO buffer per port mode is that each
Atlantic interface can be accessed in parallel and independently, thus
avoiding head of line blocking. For POS-PHY Level 4 transmitters,
scheduling logic decodes the incoming status channel and decides which
FIFO buffer (port) to serve.
1
Since the number of ports increases the LE utilization
directly, this buffer mode is not well suited for applications
with a large number of ports.
Figure 55 shows the data flow within the transmitter’s FIFO buffer.
Figure 55. Transmitter FIFO Buffer Data Flow
Atlantic Interface
(Master Sink)
To
Main Core
Atlantic Interface
(Slave Sink)
Atlantic
FIFO Buffer
Converter
Block
From User
Atlantic FIFO Buffer
This block expands the data path to the FIFO buffer width by a factor of
two. The function of this block depends on the Atlantic interface data
width chosen as a parameter.
Signals
Altera Corporation
Tables 40 through 44 list the I/O signals used in the core. The active low
signals are indicated by _n.
115
Specifications-MPHY
Converter Block
4
Individual Buffers
FIFO buffers are used for clock decoupling between the atxclk and the
trefclk clock signals. A dedicated FIFO buffer is instantiated for each
port in the POS-PHY Level 4 core, and is user configurable. The read and
write sides of the FIFO buffer operate on different clock domains. The
FIFO buffers are dual Atlantic interface slaves.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Table 40. SPI-4.2 Transmit Interface
Signal
Direction
Description
tdclk
LVDS Output
(data pin)
SPI-4.2 differential transmit clock. Ideally a 50% duty cycle. This signal uses
the data pin to produce the output clock to match the skew with tdat[15:0],
tctl
LVDS Output
(data pin)
SPI-4.2 differential transmit control. When high, the word on tdat is a control
word. When low, the word on tdat is a payload word. tctl runs at 2 × tdclk
MHz.
tdat[15:0] LVDS Output
(data pin)
tsclk
LVTTL Input
(clock pin)
tstat[1:0] LVTTL Input
(data pin)
SPI-4.2 differential transmit data bus. Bus carries packets/cells or in-band
control words. tdat runs at 2 × tdclk MHz.
SPI-4.2 transmit status clock.
SPI-4.2 transmit status channel. Used to indicate the downstream device’s
FIFO buffers.
Table 41. Atlantic Transmit Interface (Part 1 of 2)
Signal
Direction
Description
a0_atxclk
Input
Clock
a0_atxreset_n
Input
Active low reset to all internal logic, synchronous to the
atxclk domain
a0_atxdav
Output
FIFO buffer has at least FTH words to be written.
a0_atxena
Input
Enable
a0_atxdat[ATLDW-1:0](1)
Input
Data bus
a0_atxsop
Input
Start of packet
a0_atxeop
Input
End of packet
a0_atxmty[ATLMTY-1:0](2)
Input
Number of invalid octets on the data bus
a0_atxerr
Input
Data error
.
.
.
an_atxclk(3)
Input
Clock
an_atxreset_n(3)
Input
Active low reset to all internal logic, synchronous to the
an_arxclk domain.
an_atxdav(3)
Output
FIFO buffer has at least FTL words to read.
an_atxena(3)
Input
Enable
an_atxdat(3) [ATLDW-1:0](1) Output
116
Data bus
Altera Corporation
Specifications – Multi-PHY with Individual FIFO Buffer per Port
POS-PHY Level 4 MegaCore Function
Table 41. Atlantic Transmit Interface (Part 2 of 2)
Signal
Direction
Description
an_atxsop(3)
Output
Start of packet
an_atxeop(3)
Output
End of packet
an_atxmty(3)[ATLMTY-1:0](2) Output
Output
an_atxerr(3)
Number of invalid octets on the data bus
Data error
Notes from Table 41:
(1)
(2)
(3)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
n is equal to the number of ports.
Table 42. Core Transmit Status Signals
Signal
Direction
Description
dip2_err
Output
The DIP-2 calculated for the FIFO buffer stat line does not match the DIP-2
provided. Single FIFO buffer stat (trefclk) clock tick wide pulse.
tstat_sync
Output
Indicates that the status channel is synchronized with proper framing. Asserted
low for improper configuration of status channel.
txfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
Synchronous to the Atlantic interface clock.
.
.
.
txfifo_oflwn(1) Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
.
.
.
txfifo_uflwn(1) Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Note from Table 42:
(1)
n is equal to the number ports.
Table 43. Global Transmit Signals (Part 1 of 2)
Signal
trefclk
Altera Corporation
Direction
Input
Description
Reference for tdclk.
117
Specifications-MPHY
Output
Individual Buffers
txfifo_uflw0
4
Indicates that the FIFO buffer has overflowed, and data has been lost.
Synchronous to the Atlantic interface clock.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Individual FIFO Buffer
Table 43. Global Transmit Signals (Part 2 of 2)
Signal
txreset_n
Direction
Input
Description
Active low reset to all internal logic. Must be synchronous to trefclk.
Table 44. Internal Transmitter Core Configuration Signals Note (1)
Signal
Direction
Description
Transmit Status (Read)
txALPHA[7:0]
Input
Number of training pattern sequence repetitions
txCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and framing occurs.
txFTH[n-1:0](2) Input
FIFO buffer threshold high watermark
txFTL[n-1:0](2) Input
FIFO buffer threshold low watermark
txMAXT[15:0]
Input
Training sequence interval
txMB1[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
starving.
txMB2[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
hungry.
Notes from Table 44:
(1)
(2)
118
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
n is equal to the FIFO buffer size per port/(data path width × 2).
Altera Corporation
Specifications – Multi-PHY with Shared
FIFO Buffer & Embedded Addressing
Overview
This chapter describes multi-PHY configurations using the shared FIFO
buffer with embedded addressing mode. This mode configures the POSPHY Level 4 core to use a single Atlantic FIFO buffer which is shared
among all ports using an embedded 8-bit address for each port. These
configurations are available in three versions (full size, half size, and
quarter rate).
Functional
Description
The POS-PHY Level 4 core functions either as a transmitter source where
data flows from the Atlantic interface to the SPI-4 interface, or as a receiver
sink where data flows from the SPI-4 interface to the Atlantic interface.
1
The transmitter is always configured as the source, the receiver
is always configured as the sink. In order for the core to act as a
full-duplex, bidirectional transceiver, you need to instantiate one
of each configuration.
For POS-PHY Level 4 core receivers, the shared FIFO buffer mode means
that the Atlantic-side logic cannot selectively pick a port to access. Instead,
data bursts from all ports are stored collectively into one physical buffer,
and the ordering of the data bursts is maintained in the order in which
they were received on the SPI-4.2 bus. The FIFO buffer status channel
generated by the POS-PHY Level 4 receiver reflects the relative fill level of
the physical FIFO buffer, for all ports as opposed to a per-port basis.
Altera Corporation
119
Specifications-MPHY
The following sections list the features for the receiver and transmitter,
assuming a full-featured configuration.
Embedded Address
For POS-PHY Level 4 core transmitters, the order in which data bursts are
transmitted on the SPI-4.2 bus is ultimately dictated by the Atlantic-side
logic. When using this mode, user-defined logic is required to schedule
the ports to be transmitted. The data burst sent is the next data burst in the
FIFO buffer regardless of its port. In order to prevent overflows on the
receiving end, the POS-PHY Level 4 transmitter decodes the incoming
FIFO buffer status channel, and makes its transmission decision based on
the worst-case port. For example, if one port out of ten is satisfied, the
transmitter does not transmit because the FIFO buffer may contain data
bursts for that port. Thus, the FIFO status of one port can block
transmission to other ports in the system.
4
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Receiver
■
■
■
■
■
Accepts packets (or cells) from the SPI-4.2 interface
Control word processing
Diagonal interleaved parity (DIP-4) parity error detection
Fixed SOP alignment to the most significant byte lane
FIFO buffer status management
Transmitter
■
■
■
■
■
Receiver
Inserts training sequence
Sends data packets (or cells) on the SPI-4.2 interface
Inserts control words
Generates DIP-4 parity
FIFO buffer status management
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a receiver. Figure 56 on page 120 shows the
blocks and signals that comprise the receiver.
Figure 56. Receiver Block Diagram
(3)
Receiver
rrefclk
rxreset_n
DPA
Signals
(1)
dpa_locked
dpa_error
dpa_lvds_locked
dpa_force_unlock
rdclk
rctl
rdat[15:0]
SPI-4.2
Interface
rsclk
a0_arxclk
a0_arxreset_n
a0_arxena
SERDES
(2)
a0_arxadr[7:0]
a0_arxdav
ALT
DDRIO
POS-PHY
Level 4
Block
Atlantic
FIFO
Buffer
msop_err
sop8_err
a0_arxval
a0_arxeop
a0_arxmty[ATLMTY-1:0] (5)
dip4_err
meop_err
Atlantic
Interface
a0_arxsop
rstat[1:0]
rsfrm
Core
Status
Signals
a0_arxdat[ATLDW-1:0] (4)
a0_arxerr
Receiver
Status
Processor
rxfifo_uflw0
mp_erradr[7:0]
rxfifo_oflw0
Notes:
(1)
(2)
(3)
(4)
(5)
120
The DPA signals are only valid if the dynamic phase alignment parameter is enabled.
Serializer/deserializer block.
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Clock & Data
The receiver requires two global clock domains: one for the Atlantic
interface side, and one for the SPI-4.2 interface side.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is deserialized to either:
■
■
■
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
For rates above 311 Mbps, the Stratix GX (including an embedded DPA
macro), Stratix and APEX II devices contain a dedicated full custom
SERDES (ALTLVDS function) implemented in hard silicon (True-LVDS™
I/Os). For rates below 250 Mbps, Flexible-LVDS™ I/O pins are used.
1
A fast PLL is required for the ALTLVDS SERDES.
Figure 57 shows the data flow within the receiver.
Figure 57. Receiver Data Flow
SPI-4.2 Interface
FIFO Buffer
Status & Management
SOP
Alignment
& Atlantic
Conversion
4
To
FIFO Buffer
From
FIFO Buffer
Note:
(1)
Altera Corporation
The high-speed interface is only present for full- and half-size configurations.
121
Specifications-MPHY
Control Word
Processing
& DIP-4
Embedded Address
High-Speed
Interface (1)
& Deserializer
Atlantic Interface
(Master Source)
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
High-Speed Interface & Deserializer
Data words arrive on the rdat bus at 2×rdclk rate. Payload data words
contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form the
second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least
significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB
of the second byte.
For full- and half-size configurations, an ALTLVDS function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/8, and
1/4 the rdat data rate depending on application.
Figure 58 on page 122 shows the receiver input port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an internal clock.
The rxpll_outclock (rrefclk) is the main clock that drives the
internal logic elements for the receiver.
1
The ALTLVDS macro does not require a reset.
Figure 58. Receiver Input Port Configuration
Deserializer
rdat0
SERDES
.
.
.
rdat7
SERDES
rdat8
SERDES
.
.
.
TDM
8, 4 (2)
txctl
rdat15
SERDES
rctl
SERDES
rdclk
128, 64 (2)
txdat
PLL
x W/J (1)
rxpll_outclock
Notes:
(1)
(2)
122
W = 2; J = 8 (full size), J=4 (half size)
Depends on selected data path width.
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
For quarter-rate configurations, the ALTDDRIO function is used to
deserialize the input high-speed rdat/rctl lines into words at 1/2 the
rdat data rate depending on application.
Control Word Processing & DIP-4
This block analyses the input data stream, and checks the output of the
running DIP-4 calculation.
The data word on the bus can be either a control word or payload. If the
word currently on the bus is a control word, this block verifies that its
DIP-4 nibble is equal to the DIP-4 calculated over the previous payload
packet by checking the output of the running DIP-4 calculation. If the
running DIP-4 calculation (calculated over the previous payload packet)
does not match the DIP-4 nibble contained in the control word, dip4_err
is asserted. A DIP-4 error on an EOP control word causes the packet to be
marked with an error (the a0_arxerr signal on the Atlantic interface is
asserted at EOP).
This block also checks for SOP violations, where SOPs occur less than eight
cycles apart. A violation drives the sop8_err signal high. This signal
remains high for one rrefclk clock cycle, and is self-clearing.
If the number of bytes in a packet is odd, the last byte in the data word
[7:0] is set to all 0s. If the number of bytes in a packet is odd, but the last
byte [7:0] is not set to 0, the packet is marked with an error (the
a0_arxerr signal on the Atlantic interface is asserted at EOP).
For further information on the DIP-4, refer to the System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer
Devices, available at www.oiforum.com.
SOP Alignment & Atlantic Conversion
This block locates the SOP in the current data words and aligns the data to
ensure that valid data is contiguous (no IDLEs) before sending it to the
FIFO buffer. This procedure involves three steps:
1.
Altera Corporation
The control words are shifted to one end of the data bus, and data is
packed together at the other end. The control words are now
considered null data.
123
Specifications-MPHY
f
4
Embedded Address
The training pattern is treated as IDLEs and discarded. The training
pattern has no internal function because the data entering the main core is
already byte aligned. The same applies for reserved control words and
extended addressing.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
2.
The null data is removed by overlaying new valid data into the null
data locations in a compaction buffer.
3.
The SOP is now aligned to the most significant byte with contiguous
valid data in the data word. When either an entire word is filled or
an EOP is received, the word is transferred to the buffer.
For 128- or 64-bit data paths the data word is expanded times two, so the
compaction buffer never overflows.
FIFO Buffer Status & Management
This block manages the rstat line. FIFO buffer usage statistics are taken
from the FIFO buffer and processed using the user-defined AE and AF
parameters. This block also inserts the DIP-2 running calculation.
When the rsfrm signal is asserted, the status channel contains only the
framing pattern. When the rsfrm signal is deasserted, the status channel
is enabled.
1
This is a method to manually request training from the
adjacent device.
FIFO Buffer
The shared FIFO buffer with embedded addressing mode configures the
POS-PHY Level 4 core to use a single Atlantic FIFO buffer, where for each
data word a tag is carried containing address information.
■
■
■
■
■
■
■
124
Single receive slave-sink Atlantic interface on the user end
Configurable FIFO buffer size
Support for crossing clock domains
Supports interleaved packets
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
–
Optional packet-based data available (dav) signal assertion
Atlantic interface error checking
–
Missing or spurious SOP/EOP detection and correction
Atlantic interface data width conversion
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
In receive direction, the address passes through the FIFO buffer with the
data, and is decoded by user logic. The single FIFO buffer with embedded
addressing supports interleaved packets. An interleaved packet occurs
when, for example, a packet from port X is sent, and then a packet from
port Y is sent before port X has gotten the EOP signal. This interleaving is
achieved by changing the a0_arxadr in the middle of the packet.
1
Head of line blocking occurs in this buffer mode. Head-of-line
blocking occurs when the port for a data burst at the head of the
buffer queue is not free (i.e., it is satisfied or as reached FTH).
This data burst blocks the queue and does not allow the bursts
behind it to proceed even if their respective ports are free (i.e., are
hungry or starving, or have reached FTL).
Figure 59 shows the data flow within the receiver’s FIFO buffer.
Figure 59. Receiver FIFO Buffer Data Flow
Atlantic Interface
(Slave Sink)
From
Main Core
Clock Domain
Border
Atlantic
Error
Checker
Atlantic
FIFO
Buffer
Atlantic Interface
(Slave Source)
Converter
Block
To User Logic
4
This block performs error checking, and recovery on data and control
signals before they are written to the Atlantic FIFO buffer. It checks for
missing SOP and EOP markers, at each port. If these markers are found to
be missing, their respective msop_err and meop_err signals are driven
high. These signals remain high for one rrefclk clock cycle, and are selfclearing. These error conditions do not correlate directly—in terms of
latency—to the data coming out of the FIFO buffer.
Altera Corporation
125
Specifications-MPHY
Atlantic FIFO Error Checker
Embedded Address
To FIFO Buffer Status & Management
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Missing SOP
If incoming data contains one or more EOPs without corresponding SOPs
(see Figure 60), the block deasserts the enable after the last EOP (see
Figure 61). This deassertion indicates that the current data between the
SOP to EOP transition is a valid packet, and that everything following the
EOP is discarded until the next SOP is received. None of the packets are
marked as errored, so it is up to the user logic to determine which cells or
packets have been dropped.
Figure 60. Missing SOP Input Timing Diagram
clk
Missing SOP
ena
sop
eop
err
Figure 61. Missing SOP Output Timing Diagram
clk
ena
sop
eop
err
1
126
Certain conditions within the internal core logic may cause
part of the missing SOP to merge with the previous good
packet. If such a merger occurs, no more than 64 bytes are
added.
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Missing EOP
Figure 62 shows that if one or more extra SOPs are received before an EOP
is received, the SOP signal going to the FIFO buffer is negated and the data
is concatenated with the previous packet. Figure 63 shows that the ERR
signal is asserted to indicate a corrupt packet.
Figure 62. Missing EOP Input Timing Diagram
Packet A
Packet B
clk
ena
sop
eop
err
1
Internal core logic may not allow for perfect packet
concatenation. Therefore, the resulting corrupt packet size is
equal to: packet A+ packet B ± 32 bytes.
Figure 63. Missing EOP Output Timing Diagram
4
clk
sop
eop
err
Atlantic FIFO Buffer
The FIFO buffer is used for clock decoupling between the a0_arxclk and
the rrefclk clock signals. A dedicated FIFO buffer is instantiated, and is
user configurable. The read and write sides of the FIFO buffer operate on
different clock domains. The FIFO buffer is a dual Atlantic interface slave.
Altera Corporation
127
Specifications-MPHY
Embedded Address
ena
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Crossing Clock Domains
To cross from the receiver core clock rate to the user-specific clock rate, a
FIFO buffer is placed between the clocks to perform statistical averaging
of smaller packets.
Converter Block
This block reduces the FIFO buffer width by a factor of two. The function
of this block depends on the Atlantic interface data width chosen as a
parameter (256, 128, 64, or 32 bits).
Signals
Tables 45 through 49 list the I/O signals used in the receiver core. The
active low signals are indicated by _n.
Table 45. SPI-4.2 Receive Interface
Signal
Direction
Description
rdclk
LVDS Input
(clock pin)
SPI-4.2 differential receive clock. Ideally a 50% duty cycle.
rctl
LVDS Input
(data pin)
SPI-4.2 differential receive control. When high, the word on rdat is a control
word. When low, the word on rdat is a payload word. rctl runs at 2 × rdclk
MHz.
rdat[15:0] LVDS Input
(data pin)
SPI-4.2 differential receive data bus. Bus carries packets/cells or in-band
control words. rdat runs at 2 × rdclk MHz.
LVTTL Output
(data pin)
SPI-4.2 receive status clock. This signal does not use a global clock out pin, it
uses a regular LVTTL data pin.
rstat[1:0] LVTTL Output
(data pin)
SPI-4.2 receive status channel. Used to indicate the upstream device’s FIFO
buffers.
rsclk
Table 46. Atlantic Receive Interface
Signal
Direction
Description
a0_arxclk
Input
Clock
a0_arxreset_n
Input
Active low reset to all internal logic, synchronous to the
a0_arxclk domain.
a0_arxdav
Output
FIFO buffer has at least FTL words to read.
a0_arxena
Input
Enable
128
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Table 46. Atlantic Receive Interface
Signal
Direction
Description
a0_arxadr[7:0]
Output
Port Address
a0_arxdat[ATLDW-1:0](1)
Output
Data bus
a0_arxval
Output
Data valid
a0_arxsop
Output
Start of packet
a0_arxeop
Output
End of packet
a0_arxmty[ATLMTY-1:0](2) Output
Output
a0_arxerr
Number of invalid octets on the data bus
Data error
Notes from Table 46:
(1)
(2)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Table 47. Internal Receiver Core Configuration Signals Note (1)
Signal
Direction
Description
rxAE[n-1:0](2)
Input
Almost empty—starving to hungry threshold for each PHY port
rxAF[n-1:0](2)
Input
Almost full—hungry to satisfied threshold for each PHY port
rxCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and
framing occurs.
rxFTL[n-1:0](2)
Input
FIFO buffer threshold low watermark
Notes from Table 47:
(1)
(2)
Signal
Direction
Description
dip4_err
Output
The DIP-4 calculated over the rdat line does not match the DIP-4 value in
the control line. Single system clock (rrefclk) tick wide pulse.
msop_err
Output
Missing SOP
meop_err
Output
Missing EOP
sop8_err
Output
SOP violation. Two SOPs occurred less than eight tdat cycles apart.
mp_erradr[7:0]
Output
Address qualifier for meop_err and msop_err flags
rsfrm
Input
When asserted, the rsfrm signal forces the receiver status channel into
framing mode. This can be used to indicate that the receiver requires
retraining.
Altera Corporation
129
Specifications-MPHY
Table 48. Core Receive Status Signals (Part 1 of 2)
4
Embedded Address
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
For 128-bit configurations, n is equal to log2(FIFO buffer size per port/(data path width × 2)). For 64- and 32-bit
configurations, n is equal to log2(FIFO buffer size per port/data path width).
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Table 48. Core Receive Status Signals (Part 2 of 2)
Signal
Direction
Description
rxfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
rxfifo_uflw0
Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Table 49. Global Receive Signals
Signal
Direction
Description
rrefclk
Output
Derived from rdclk, depends on data path width.
rxreset_n
Input
Active low reset to all internal logic, synchronized to the rrefclk domain
Table 50 shows the DPA signals used by the receiver.
1
Only applicable when using the DPA circuitry of a
Stratix GX device.
Table 50. DPA Status Signals (Receiver Only)
Signal
dpa_error
Direction
Output
dpa_force_unlock Input
Description
Error flag to indicate that the DPA circuitry could not find byte alignment
Forces the DPA circuitry and PLL to unlock and retrain
dpa_locked
Output
When this signal is high, it indicates that the DPA aligner has aligned to
the training pattern
dpa_lvds_locked
Output
When this signal is high, it indicates that the DPA PLL has locked
Transmitter
130
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a transmitter. Figure 64 on page 131 shows the
blocks and signals that comprise the transmitter.
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Figure 64. Transmitter Block Diagram
(1)
Transmitter
a0_atxclk
dip2_err
Core
Status tstat_sync
Signals txfifo_uflw0
a0_atxreset_n
a0_atxena
a0_atxdav
trefclk
a0_atxadr[7:0]
txreset_n
POS-PHY
Level 4
Block
Atlantic
FIFO
Buffer
tdclk
tctl
SPI-4.2
Interface
a0_atxdat[ATLDW-1:0] (2)
Atlantic
Interface
a0_atxsop
a0_atxeop
SERDES
a0_atxmty[ATLMTY-1:0] (3)
tdat[15:0]
a0_atxerr
txfifo_oflw0
tsclk
tstat[1:0]
Notes:
(1)
(2)
(3)
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Clock & Data
The transmitter requires three clock domains: one for the Atlantic
interface side, one for the SPI-4.2 interface side, and one for the status
clock domain.
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits running at 1/2 the LVDS data rate (for special applications—
maximum 250 Mbps)
Figure 65 on page 132 shows the data flow within the transmitter.
Altera Corporation
131
Specifications-MPHY
■
■
■
4
Embedded Address
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is serialized to either:
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Figure 65. Transmitter Data Flow
SPI-4.2 Interface
Atlantic Interface
(Master Sink)
High-Speed
Interface (1)
& Serializer
Control Word
Insertion
& DIP-4
Scheduler
&
Training
Pattern
Insertion
From
FIFO Buffer
FIFO Buffer
Status & Management
Note:
(1)
The high-speed interface is only present for full- and half-size configurations.
High-Speed Interface & Serializer
Data words are sent on the tdat data bus at 2×tdclk rate. Payload data
words contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form
the second byte. Bit 15 is the MSB, and bit 8 is the LSB of the first byte. Bit
7 is the MSB, and bit 0 is the LSB of the second byte.
For full- and half-size configurations, an ALTLVDS function is used to
serialize the words into input high-speed tdat/tctl lines.
Figure 66 on page 133 shows the transmitter output port configuration: 16
LVDS data pins, 1 LVDS control pin, 128- or 64-bit internal data path, 8or 4-bit internal control path, and an output clock.
For the output clock (tdclk), the user should not use the LVDS output
clock pins, but should use an appropriate LVDS data pair instead. The
tdclk pin can be treated as a data pin, because the SERDES is preloaded
with a binary 1010 pattern that guarantees an appropriate skew between
the clock and data.
1
132
The ALTLVDS macro does not require a reset.
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Figure 66. Transmitter Output Port Configuration
Serializer
tdat0
SERDES
.
.
.
tdat7
128, 64 (1)
rxdat
SERDES
8, 4 (2)
rxctl
tdat8
SERDES
.
.
.
Demultiplexer
tdat15
SERDES
tctl
SERDES
tdclk
trefclk
SERDES
PLL
Notes:
(1)
(2)
Depends on selected data path width.
The deserialisation factor is 8 for full-size, or 4 for half-size configurations.
4
This block inserts control words into the data path, and performs DIP-4
insertion.
An EOP abort condition can be generated on the SPI-4.2 interface by
asserting a0_atxerr with a valid a0_atxeop on the Atlantic interface.
This condition is the only one for which the EOP abort bit can be set in the
control word.
Altera Corporation
133
Specifications-MPHY
Control Word Insertion & DIP-4
Embedded Address
For quarter-rate configurations, an ALTDDRIO function is used to
serialize the words into input high-speed tdat/tctl lines.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Scheduler
The scheduler block inserts the training patterns at each MaxT. It also
controls the amount of data that is read from the Atlantic FIFO buffer. The
transmitter determines whether to transmit idles, MaxBurst2 bytes, or
MaxBurst1 bytes.
Since the shared Atlantic FIFO buffer with embedded addressing mode
contains complete and/or partial bursts for all ports, the scheduler cannot
selectively choose a port to transmit. Instead, the scheduler uses the
decoded incoming status channel information and considers the worstcase status to be the effective status for every port. For example, in a tenport system, if one port indicates it is satisfied, the scheduler considers all
ten ports to be satisfied and does not transmit any data from the Atlantic
FIFO buffer because it may contain bursts destined for the satisfied port.
Similarly, if one port is hungry and the others are starving, the scheduler
considers all ten ports to be hungry and directs the transmitter to transmit
MaxBurst2 ×16 bytes. The Atlantic FIFO buffer is read MaxBurt2 ×16
equivalent amount of times regardless of the port addresses for the bursts
being read. Ultimately, the order and length of the bursts on the SPI-4.2
bus is dictated by the order of the bursts written to the shared Atlantic
FIFO buffer. Therefore, the application logic writing to the Atlantic FIFO
buffer must ensure that the desired amount of data for each port is written
in the desired sequence. The following rules must be followed:
1.
At least 16 bytes must be written for each port before switching ports
(unless a burst is terminated with an EOP). This is required to
comply with the 16-byte minimum burst rule imposed by the SPI-4.2
specification.
2.
If MaxBurst1 and MaxBurst2 bytes are to be transmitted for each
port, then MaxBurst1 and MaxBurst2 bytes must be written to the
Atlantic FIFO buffer before switching to another port.
3.
When the burst mode parameter is enabled, data must be written in
multiples of burst size bytes before switching ports, unless
terminated with an EOP.
1
134
In all cases, any number of clock cycles may exist between
each write, but the appropriate number of writes must occur
before switching ports.
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Training Pattern Insertion
This block inserts the training pattern at a scheduled interval defined by
the maximum training sequence interval parameter. If the training pattern
is asserted on the status channel, the core continuously sends training
patterns.The training pattern is sent out ALPHA (α) times.
1
If α = 0, the training pattern is not sent at MaxT, but still responds
to the framing pattern. The tstat_sync signal is observed as
low in this state.
The training sequence includes one IDLE control word, plus α×20 words.
The twenty words are separated into ten consecutive tdat words of
16’h0FFF with tctl of 1’b1, followed by ten consecutive tdat words of
16’hF000 with tctl of 1’b0. The user should expect some IDLEs before
and after the training sequence.
1
This feature is used to support dynamic alignment on adjacent
receivers.
FIFO Buffer Status & Management
Altera Corporation
135
Specifications-MPHY
When a DIP-2 error occurs, all the queues in the scheduler are cleared, and
the system recovers on its own (the current transfer continues to
completion).
4
Embedded Address
This block monitors the tstat line (status channels) for DIP-2 or loss of
frame (LOF) errors. If a DIP-2 error occurs, the dip2_err signal is
asserted. The scheduler table is cleared when a DIP-2 error occurs. The
current transfer is not interrupted because the transfer is based on
MB1/MB2. If the status channel has not recovered by the time MB1/MB2 is
transmitted, it transmits IDLEs until a valid frame of status is received,
and the scheduler table is refreshed. The block forwards the extracted
status information (when requested) to the scheduler block. The DIP-2
error is cleared at the next tstat framing sequence.
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
FIFO Buffer
The shared FIFO buffer with embedded addressing mode configures the
POS-PHY Level 4 core to use a single Atlantic FIFO buffer, where for each
data word a tag is carried containing address information.
■
■
■
■
■
Single transmit slave-source Atlantic interface on the user end
Configurable FIFO buffer size
Support for crossing clock domains
FIFO status interface
–
Overflow error indication
–
Underflow warning indication
–
Status outputs for used and available space in the FIFO buffer
–
Configurable FIFO threshold low (FTL) and FIFO threshold high
(FTH)
–
Optional packet-based data available (dav) signal assertion
Atlantic interface data width conversion
The status channel processor selects the worst-case status, and applies it
to the instantiated single-FIFO buffer. The user logic provides an address
corresponding to its destination port.
1
In the transmit direction, the single FIFO buffer with embedded
addressing does not support interleaved packets.
1
Head-of-line blocking occurs in this buffer mode.
In the case of back pressure, if the transmitter becomes aware that one port
cannot accept data, it transitions to send IDLEs until the status channel
indicates that it can accept data. The transmitter cannot switch to another
port because data is head-of-line blocked in the FIFO buffer.
Figure 67 shows the data flow within the transmitter’s FIFO buffer.
Figure 67. Transmitter FIFO Buffer Data Flow
Atlantic Interface
(Master Sink)
To
Main Core
136
Atlantic Interface
(Slave Sink)
Atlantic
FIFO Buffer
Converter
Block
From User
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
POS-PHY Level 4
Atlantic FIFO Buffer
The FIFO buffer is used for clock decoupling between the atxclk and the
trefclk clock signals. A dedicated FIFO buffer is instantiated, and is
user configurable. The read and write sides of the FIFO buffer operate on
different clock domains. The FIFO buffer is a dual Atlantic interface slave.
Converter Block
This block expands the data path to the FIFO buffer width by a factor of
two. The function of this block depends on the Atlantic interface data
width chosen as a parameter.
Signals
Tables 51 through 55 list the I/O signals used in the core. The active low
signals are indicated by _n.
Table 51. SPI-4.2 Transmit Interface
Signal
Direction
Description
tdclk
LVDS Output
(data pin)
SPI-4.2 differential transmit clock. Ideally a 50% duty cycle.This signal uses
the data pin to produce the output clock to match the skew with tdat[15:0],
tctl
LVDS Output
(data pin)
SPI-4.2 differential transmit control. When high, the word on tdat is a control
word. When low, the word on tdat is a payload word. tctl runs at 2 × tdclk
MHz.
LVTTL Input
(clock pin)
tstat[1:0] LVTTL Input
(data pin)
SPI-4.2 transmit status clock.
SPI-4.2 transmit status channel. Used to indicate the downstream device’s
FIFO buffers.
Table 52. Atlantic Transmit Interface (Part 1 of 2)
Signal
Direction
Description
a0_atxclk
Input
Clock
a0_atxreset_n
Input
Active low reset to all internal logic, synchronous to the
atxclk domain
a0_atxdav
Output
FIFO buffer has at least FTH words to be written.
Altera Corporation
137
Embedded Address
tsclk
4
SPI-4.2 differential transmit data bus. Bus carries packets/cells or in-band
control words. tdat runs at 2 × tdclk MHz.
Specifications-MPHY
tdat[15:0] LVDS Output
(data pin)
POS-PHY Level 4 MegaCore Function User Guide Specifications – Multi-PHY with Shared FIFO Buffer &
Table 52. Atlantic Transmit Interface (Part 2 of 2)
Signal
Direction
Description
a0_atxena
Input
Enable
a0_atxadr[7:0]
Input
Port Address
a0_atxdat[ATLDW-1:0](1)
Input
Data bus
a0_atxsop
Input
Start of packet
a0_atxeop
Input
End of packet
a0_atxmty[ATLMTY-1:0](2) Input
Input
a0_atxerr
Number of invalid octets on the data bus
Data error
Notes from Table 52:
(1)
(2)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Table 53. Core Transmit Status Signals
Signal
Direction
Description
dip2_err
Output
The DIP-2 calculated for the FIFO buffer stat line does not match the
DIP-2 provided. Single FIFO buffer stat (trefclk) clock tick wide pulse.
tstat_sync
Output
Indicates that the status channel is synchronized with proper framing.
Asserted low for improper configuration of status channel.
txfifo_oflw0
Output
Indicates that the FIFO buffer has overflowed, and data has been lost.
Synchronous to the Atlantic interface clock.
txfifo_uflw0
Output
Indicates that the FIFO buffer is empty, and the read request is ignored.
Table 54. Global Transmit Signals
Signal
Direction
Description
trefclk
Input
Reference for tdclk.
txreset_n
Input
Active low reset to all internal logic. Must be synchronous to trefclk.
138
Altera Corporation
Specifications – Multi-PHY with Shared FIFO Buffer & Embedded Addressing
Table 55. Internal Transmitter Core Configuration Signals
Signal
Direction
POS-PHY Level 4
Note (1)
Description
Transmit Status (Read)
txALPHA[7:0]
Input
Number of training pattern sequence repetitions
txCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and framing
occurs.
txFTH[n-1:0](2) Input
FIFO buffer threshold high watermark
txFTL[n-1:0](2) Input
FIFO buffer threshold low watermark
txMAXT[15:0]
Input
Training sequence interval
txMB1[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
starving.
txMB2[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
hungry.
Notes from Table 55:
(1)
(2)
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
n is equal to the FIFO buffer size per port/(data path width × 2).
4
139
Specifications-MPHY
Embedded Address
Altera Corporation
Specifications – Multi-PHY with
Virtual FIFO Buffer Segments &
Buffer Management
Overview
This chapter describes multi-PHY configurations using the virtual FIFO
segments and buffer management mode. This mode configures the POSPHY Level 4 core to use a single buffer that is logically segmented to
provide a separate virtual FIFO buffer per port. These configurations are
only available in one version (i.e., full size).
Functional
Description
The POS-PHY Level 4 core functions either as a transmitter source where
data flows from the Atlantic interface to the SPI-4 interface, or as a receiver
sink where data flows from the SPI-4 interface to the Atlantic interface.
1
The transmitter is always configured as the source, the receiver
is always configured as the sink. In order for the core to act as a
full-duplex, bidirectional transceiver, you need to instantiate one
of each configuration.
The following sections list the features for the receiver and transmitter,
assuming a full-featured configuration.
Receiver
Accepts packets (or cells) from the SPI-4.2 interface
Control word processing
Diagonal interleaved parity (DIP-4) parity error detection
Fixed SOP alignment to the most significant byte lane
FIFO buffer status management
4
Transmitter
■
■
■
■
■
Receiver
Altera Corporation
Inserts training sequence
Sends data packets (or cells) on the SPI-4.2 interface
Inserts control words
Generates DIP-4 parity
FIFO buffer status management
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a receiver. Figure 68 on page 142 shows the
blocks and signals that comprise the receiver.
141
Specifications-MPHY
Buffer Manager
■
■
■
■
■
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 68. Receiver Block Diagram
(3)
rrefclk
rxreset_n
dpa_locked
DPA
dpa_error
Signals dpa_lvds_locked[16:0]
(1)
dpa_force_unlock
SPI-4.2
Interface
rdclk
rctl
rdat[15:0]
rsclk
Receiver
SERDES
(2)
POS-PHY
Level 4
Block
ALT
DDRIO
rstat[1:0]
rsfrm
Core
Status
Signals
dip4_err
sop8_err
paddr_err
msop_err
mp_erradr[7:0]
meop_err
Buffer
Manager
a0_arxclk
a0_arxreset_n
a0_arxena
a0_arxadr[7:0]
a0_arxdat[ATLDW-1:0] (4)
Atlantic
a0_arxval
Interface
a0_arxdav
a0_arxsop
a0_arxeop
a0_arxmty[ATLMTY-1:0] (5)
a0_arxerr
bm_active_arxport [3:0]
bm_arxlev[7:0]
bm_arxport [3:0]
bm_stat_arxport[3:0]
bm_stat_arxlev[7:0]
bm_stat_arxdav
bm_err_arxport[3:0]
bm_rxoflw
bm_rxuflw
bm_rxready
Notes:
(1)
(2)
(3)
(4)
(5)
The DPA signals are only valid if the dynamic phase alignment parameter is enabled.
Serializer/deserializer block.
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Clock & Data
The receiver requires two global clock domains: one for the Atlantic
interface side, and one for the SPI-4.2 interface side.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is deserialized to 128 bits running
at a frequency of 1/8 the LVDS data rate.
For rates above 311 Mbps, the Stratix GX (including an embedded DPA
macro), Stratix and APEX II devices contain a dedicated full custom
SERDES (ALTLVDS function) implemented in hard silicon (True-LVDS™
I/Os). For rates below 250 Mbps, Flexible-LVDS™ I/O pins are used.
1
A fast PLL is required for the ALTLVDS SERDES.
Figure 69 on page 143 shows the data flow within the receiver.
142
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Figure 69. Receiver Data Flow
SPI-4.2 Interface
Atlantic Interface
(Master Source)
High-Speed
Interface &
Deserializer
Control Word
Processing
& DIP-4
SOP
Alignment
& Atlantic
Conversion
FIFO Buffer
Status & Management
To
Buffer Manager
From
Buffer Manager
High-Speed Interface & Deserializer
Data words arrive on the rdat bus at 2×rdclk rate. Payload data words
contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form the
second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least
significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB
of the second byte.
An ALTLVDS function is used to deserialize the input high-speed
rdat/rctl lines into words at 1/8 of the rdat data rate.
4
The rxpll_outclock (rrefclk) is the main clock that drives the
internal logic elements for the receiver.
1
Altera Corporation
The ALTLVDS macro does not require a reset.
143
Specifications-MPHY
Buffer Manager
Figure 70 on page 144 shows the receiver input port configuration: 16
LVDS data pins, 1 LVDS control pin, 128-bit internal data path, 8-bit
internal control path, and an internal clock.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 70. Receiver Input Port Configuration
Deserializer
rdat0
SERDES
.
.
.
rdat7
SERDES
rdat8
SERDES
.
.
.
128
txdat
TDM
8
txctl
rdat15
SERDES
rctl
SERDES
rdclk
PLL
x W/J (1)
rxpll_outclock
Note:
(1)
W = 2; J = 8
Control Word Processing & DIP-4
This block analyses the 128-bit input data stream, and checks the output
of the running DIP-4 calculation.
The data word on the bus can be either a control word or payload. If the
word currently on the bus is a control word, this block verifies that its
DIP-4 nibble is equal to the DIP-4 calculated over the previous payload
packet by checking the output of the running DIP-4 calculation. If the
running DIP-4 calculation (calculated over the previous payload packet)
does not match the DIP-4 nibble contained in the control word, dip4_err
is asserted. A DIP-4 error on an EOP control word causes the packet to be
marked with an error (the a0_arxerr signal on the Atlantic interface is
asserted at EOP).
This block also checks for SOP violations, where SOPs occur less than eight
cycles apart. A violation drives the sop8_err signal high. This signal
remains high for one rrefclk clock cycle, and is self-clearing.
144
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
If the number of bytes in a packet is odd, the last byte in the data word
[7:0] is set to all 0s. If the number of bytes in a packet is odd, but the last
byte [7:0] is not set to 0, the packet is marked with an error (the
a0_arxerr signal on the Atlantic interface is asserted at EOP).
The training pattern is treated as IDLEs and discarded. The training
pattern has no internal function because the data entering the main core is
already byte aligned. The same applies for reserved control words and
extended addressing.
If the destination address is invalid (i.e., larger than the calendar
multiplier parameter), the paddr_err line is asserted.
f
For further information on the DIP-4, refer to the System Packet Interface
Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer
Devices, available at www.oiforum.com.
SOP Alignment & Atlantic Conversion
This block locates the SOP in the current data words and aligns the data to
ensure that valid data is contiguous (no IDLEs) before sending it to the
FIFO buffer. This procedure involves three steps:
1.
The control words are shifted to one end of the data bus, and data is
packed together at the other end. The control words are now
considered null data.
2.
The null data is removed by overlaying new valid data into the null
data locations in a compaction buffer.
For 128-bit data paths the data word is expanded times two, so the
compaction buffer never overflows.
FIFO Buffer Status & Management
This block manages the rstat line. FIFO buffer usage statistics are taken
from the FIFO buffer and processed using the user-defined AE and AF
parameters. This block also inserts the DIP-2 running calculation.
When the rsfrm signal is asserted, the status channel contains only the
framing pattern. When the rsfrm signal is deasserted, the status channel
is enabled.
Altera Corporation
145
Specifications-MPHY
The SOP is now aligned to the most significant byte with contiguous
valid data in the data word. When either an entire word is filled or
an EOP is received, the word is transferred to the buffer.
Buffer Manager
3.
4
POS-PHY Level 4 MegaCore Function User Guide
1
Buffer Manager
Specifications – Multi-PHY with Virtual FIFO Buffer
This is a method to manually request training from the
adjacent device.
The Atlantic FIFO buffer manager is designed to act as a common multiport FIFO buffer structure for the POS-PHY Level 4 Megacore function.
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Single Atlantic interface
Support for up to 16 ports
Support for dual clock domains
Continuously updated active port status outputs for dav, readable
space (rlev), and writeable space (wlev)
Polled inactive port status outputs for dav, rlev, and wlev
Two threshold control inputs per port to enable hysteresis in dav
assertion/de-assertion
Threshold based dav assertion
User specified total memory allocated
Dynamic port memory segment sizing
Configurable Atlantic data width
Optional 2x data width conversion
Optional 1/2 data width conversion
Optional sop/eop error correction and err assertion based on missing
or spurious sop/eop
Overflow/underflow status outputs
Functional Description
The buffer manager uses a single memory with portions allocated to each
port as configured by the user. The memory is managed in a linked list
format. All status and pointer information is stored in memory. Both clock
domains have a single active port at all times as chosen by the
bm_arxport input. The active port has continuously updated
bm_arxlev and bm_rxuflw status information, as well as continuously
updated a0_arxdav output. For inactive ports, polled
bm_stat_arxlev and bm_stat_arxdav status information is
displayed on status outputs in a round robin fashion. Figure 71 on
page 147 shows the buffer manager block diagram.
146
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Figure 71. Buffer Manager Block Diagram
Receive Clock Domain
wside
init
Transmit Clock Domain
Initialization
rdside
init
Status
Next Available Address FIFO Buffer
Error Checking
Write
Memory
Read
Start/End of Packet Error Checking
The state machine in Figure 72 on page 148 shows all possible conditions
where the msop_err and meop_err outputs are asserted.
Altera Corporation
147
Specifications-MPHY
By default, if the err signal input is asserted at any time during a packet
transmission, the err signal output is held asserted until the end of packet
is detected. This property is implemented to conform to the Atlantic
interface specification.
4
Buffer Manager
Packet checking ensures that only properly formatted packets are passed
through the buffer manager, while partial and errored packets are
discarded. The error checking module—with the checkpkt input
asserted—corrects start- and end-of-packet errors before writing packets
into the buffer manager. For a missing start of packet (where two EOPs are
received before the next SOP), the data after the first EOP is dropped until
the subsequent SOP is received. For a missing end of packet (where two
SOPs are received before the next EOP), the second SOP is suppressed, an
EOP is inserted in the correct position, and the err signal is asserted.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 72. Packet Checker State Machine
eop &!sop
msop=1
sop &!eop & mty!=0
meop=1
IDLE
sop &!eop
meop=1
MEOP
ar
op
!e
& p=1
op o
!s ms
p
so
& p=1
p o
eo me
sop & eop
meop=1
sop & eop
meop=1
xm
m ty!=
eo 0
p= &
1 !eo
MSOP
p
sop & !eop
meop=1
BUSY
Memory Structure
The memory structure for the buffer manager is maintained as a linked list
using two separate memories, a data memory and a descriptor memory.
The data memory is split into uniformly sized segments. The total number
of segments is equal to 256. Each location has a descriptor that is stored in
the descriptor memory. The descriptor holds information for start and end
of packet, mty for the packet, Atlantic error, the number of written
locations in the segment, and a pointer to the next data segment for the
particular port. Figure 73 on page 149 shows the memory structure.
The total number of segments assigned to a particular port is
stat_port_size=int (256/number of ports). The total number of
segments that can be written before overflow occurs is
stat_port_size-1.
148
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Figure 73. Memory Structure
Descriptor Memory
Segment 0 Descriptor
Segment 1 Descriptor
Data Memory
Segment 0
Segment 1
Segment n-1 Descriptor
0x0
0x(segment depth)
0x(2)(segment depth)
0x(n-2)(segment depth)
Segment n-1
0x(n-1)(segment depth)
SOP EOP MTY ERR CNT NEXT
Write
The write module writes data into the descriptor and data memories
according to the values in the write descriptor memory. The write
descriptor memory holds the pointer and descriptor information for the
data segment currently being written for each port. The sequence of
events for packets being written to the data memory is as follows:
2.
When a SOP is received, the SOP field in the write descriptor is
asserted and the CNT field is incremented to 1.
3.
For each subsequent write, the CNT field is incremented to track the
fill level of the current segment.
4.
When the current segment is filled or an EOP is received, the address
of the next free segment is read from the free segment FIFO buffer.
The address for the next free segment is written with the write
descriptor into the descriptor memory. All the fields for the write
descriptor are cleared except the current field which is loaded with
the address of the new current segment (next free segment.)
5.
When a total of stat_port_size-1 segments have been written to
a particular port, the port is deemed full and subsequent write
operations to that port will cause the buffer manager to signal an
overflow.
149
4
Specifications-MPHY
On reset, an initial data segment is assigned to each port (segment 0
is assigned to port 0, segment 1 is assigned to port 1, etc.)
Buffer Manager
Altera Corporation
1.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 74 shows an example where the descriptor memory contents for a
single packet span three data segments. The first 64 transfers of the packet
with the SOP are written to segment 0x0. The second 64 transfers are
written to segment 0x27. The rest of the packet—22 transfers plus
EOP/MTY—is written to segment 0x35.
Figure 74. Descriptor Memory Example
Descriptor Memory
0x0
1
0
0
0
64 0x27
0
0
0
0
64 0x35
0
1
2
0
22 0x45
...
...
...
...
...
0x27
......
0x35
0x45
Read
The read module reads data from the descriptor and data memories
according to the values in the read descriptor memory. The read
descriptor memory holds the pointer and descriptor information for the
data segment currently being read for each port. The sequence of events
for packets being read from the data memory is as follows:
150
1.
On reset, an initial data segment is assigned to each port. The current
field in the read descriptor memory is loaded with this address.
2.
For the first segment or when the port has been emptied, the current
read descriptor is taken directly from the descriptor RAM.
Otherwise, the locally stored copy is used.
3.
Each time data is read from the current segment, the CNT field is
decremented.
4.
When the CNT field reaches 0, the new segment descriptor—pointed
to by the next field in the read descriptor—is loaded into the read
descriptor. The segment memory is released by writing the segment
address into the next address FIFO.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Next Available Address FIFO Buffer
The write module assigns data to the next available memory segment as
specified by the next available address FIFO buffer. Addresses are
released by the read module by writing them back into the FIFO buffer. At
reset, the next available address FIFO buffer is initialized by connecting
the write interface to a counter and overwriting each location in sequence.
The write pointer is reset to 0 and the read pointer is reset to 2×(number
of ports)+1 to account for the first addresses that are used as linked list
initialization values.
Status
At reset, the number of writeable segments or write level for a given port
is equal to stat_port_size-1. The number of readable segments or
read level at reset is equal to 0 for all ports. As data is written into the
buffer manager for a particular port, the status module updates and
displays status information through the polled status and active status
outputs. Active status outputs are updated continuously while polled
status outputs are displayed as they are polled.
Dual Clock Domain Status
For updating the read and write level between clock domains, an
increment value is passed which represents the number of new memory
segments that have been written to or read since the last update. The
increment value is added to the current value to obtain an updated level
value. The increment values are passed with a flag that is metastable
hardened.
■
■
Active port is changed
Active port is removed
When the active port is changed, the status of the newly active port is
inserted into the polling sequence. For example, if the output polling
sequence follows a pattern of 0, 1, 2, 3, 8, 4, 5… and the active port is
changed to port 8, port 4 automatically becomes the next port for polled
status output.
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151
Buffer Manager
The buffer manager performs its status polling in round robin fashion,
where port status is polled in sequence. However, the polling sequence
can be interrupted by the following occurrences:
4
Specifications-MPHY
Polled Status Outputs
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
When the active port is removed from the polling sequence, the active port
is re-added to the polling sequence exactly seven clock cycles after the
active port is changed.
Underflow
The buffer manager enters the underflow state for a given port if the
a0_arxena is asserted while empty. In the case of underflow, the
bm_rxuflw status output is asserted for a single clock cycle and the
a0_arxval output is deasserted to signal no valid data exists on the
Atlantic interface.
Initialization
Resetting the buffer manager involves clearing all of the flops in the
design, as well as initializing all the memories to a known state. On reset,
the initialization module initializes the buffer manager using the
following sequence:
1.
Deassert the ready status output.
2.
Reset all flops.
3.
Reset the level increment RAMs to 0 for all ports.
4.
Reset the read level RAMs to 0 for all ports.
5.
Reset the write level RAMs to the stat_port_size-1 for all ports.
6.
Initialize the next available address FIFO buffer.
7.
Initialize the descriptor RAMs in the write and read modules.
8.
Release flops from reset.
9.
Assert the ready status output.
Atlantic Interface
The Atlantic interface is a standard Atlantic slave-source interface that
allows the user to specify data and address port widths. The data port
width can be selected as either 128 or 256 bits.
The width of the address port is always equal to the width of the receive
address port.
152
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Figure 75 through Figure 81 show the interface timing. The dark blue
shading represents “don’t care” states.
Figure 75. Active Port Status Timing Diagram
a0_arxclk
0
bm_active_arxport
Active
Port
Status
Outputs
dav status port 0
a0_arxdav
level status port 0
bm_arxlev
0
Atlantic
Input bm_arxport
Figure 76. Active Port Status with Multiple Transitions in the bm_arxport Signal
Note (1)
a0_arxclk
0
1
2
3
4
5
bm_active_arxport
dav status
for port ...
1
2
3
4
5
0
1
2
3
4
5
bm_arxlev
lev status
for port ...
Atlantic
Input
bm_arxport
0
1
2
3
4
5
Note:
(1)
The active port status outputs are loaded three clock cycles after the bm_arxport output transitions.
Altera Corporation
153
4
Buffer Manager
0
a0_arxdav
Specifications-MPHY
Active
Port
Status
Outputs
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
0
a0_arxval
a0_arxadr
a0_arxdat
Atlantic
Outputs
a0_arxeop
a0_arxsop
a0_arxena
Atlantic
Inputs
bm_arxport
bm_arxlev
a0_arxdav
Active
Port
Status
Outputs
bm_active_arxport
a0_arxclk
0
f
0
0
1
2
3
a
c
(1)
f
e
Figure 77. Single Short Packet Transfer
Note:
(1)
154
A single packet, that spans exactly one segment, is written for port 0. The bm_arxlev output is updated on the
following clock edge.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
Figure 78. Multiple Short Packet Transfers with Port Switching
POS-PHY Level 4
Note (1)
a0_arxclk
0
1
2
bm_active_arxport
Active
Port
Status
Outputs
a0_arxdav
f
e
d
1
2
f
e
f
e
d
bm_arxlev
0
bm_arxport
Atlantic
Inputs
a0_arxena
a0_arxsop
a0_arxeop
Atlantic
Outputs
a0_arxadr
0
1
0
a0_arxval
Note:
(1)
4
Buffer Manager
Altera Corporation
155
Specifications-MPHY
The bm_arxlev output is loaded for the port specified by the bm_arxport input three clock cycles after the
bm_arxport input transitions. The bm_arxlev is updated for the active port each time an EOP is read.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
11
a0_arxval
a0_arxadr
a0_arxeop
a0_arxsop
a0_arxdat
Atlantic
Outputs
Atlantic
Inputs
a0_arxena
bm_arxport
bm_arxlev
a0_arxdav
Active
Port
Status
Outputs
bm_active_arxport
a0_arxclk
0
f
0
0
0
1
2
3
d
e
f
e
(1)
10
d
(2)
Figure 79. Single Large Packet Transfer Spanning Two Memory Segments
Notes:
(1)
(2)
156
A full segment is read from the first memory segment. No EOP is read. The bm_arxlev output is updated on the
next clock edge.
The EOP is read to end the packet transfer. The bm_arxlev output is updated on the next clock edge.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Figure 80. Packet Interleaving
a0_arxclk
0
1
0
1
bm_active_arxport
Active
Port
Status
Outputs
a0_arxdav
f
e
f
e
bm_arxlev
0
1
0
1
bm_arxport
Atlantic
Inputs
a0_arxena
a0_arxsop
a0_arxeop
Atlantic
Outputs
0
1
2
0
1
2
3
4
3
4
a0_arxdat
0
1
0
1
a0_arxadr
4
a0_arxval
157
Specifications-MPHY
Buffer Manager
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
1
0
0
1
Active bm_err_arxport
Port
Error
Outputs
bm_rxuflw
a0_arxval
a0_arxadr
a0_arxeop
Atlantic
Outputs
a0_arxsop
a0_arxena
Atlantic
Inputs
bm_arxport
bm_arxlev
a0_arxdav
Active
Port
Status
Outputs
bm_active_arxport
a0_arxclk
0
0
6
0
5
4
f
1
1
3
0
0
0
2
1
0
(1)
(2)
Figure 81. Underflow Timing Diagram
Notes:
(1)
(2)
158
The a0_arxena input is asserted when the bm_arxlev output goes low (zero).
The bm_rxuflw output is asserted for port 0.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
Figure 82. Polling Status Outputs Timing Diagram
POS-PHY Level 4
Notes (1),(2)
a0_atxclk/
a0_arxclk
6
bm_active_atxport/
bm_active_arxport
Active
Port
Status
Outputs
bm_stat_atxport/
bm_stat_arxport
a
b
c
0
8
0
d
7
e
f
8
1
2
0
f
e
a
2
3
7
4
5
6
9
a
bm_stat_atxdav/
bm_stat_arxdav
bm_stat_atxlev/
bm_stat_arxlev
3
f
a
9
6
3
f
Notes:
(1)
(2)
Polled port status is given in a round-robin fashion. Ports are removed from the polling sequence if they are
currently active, or if they were active within the last seven clock cycles.
For all ports: FTL = 7.
Signals
Tables 56 through 60 list the I/O signals used in the receiver core. The
active low signals are indicated by _n.
4
Signal
Direction
Description
rdclk
LVDS Input
(clock pin)
SPI-4.2 differential receive clock. Ideally a 50% duty cycle.
rctl
LVDS Input
(data pin)
SPI-4.2 differential receive control. When high, the word on rdat is a control
word. When low, the word on rdat is a payload word. rctl runs at 2 × rdclk
MHz.
rdat[15:0] LVDS Input
(data pin)
SPI-4.2 differential receive data bus. Bus carries packets/cells or in-band
control words. rdat runs at 2 × rdclk MHz.
LVTTL Output
(data pin)
SPI-4.2 receive status clock. This signal does not use a global clock out pin, it
uses a regular LVTTL data pin.
rstat[1:0] LVTTL Output
(data pin)
SPI-4.2 receive status channel. Used to indicate the upstream device’s FIFO
buffers.
rsclk
Altera Corporation
159
Specifications-MPHY
Buffer Manager
Table 56. SPI-4.2 Receive Interface
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Table 57. Atlantic Receive Interface (Slave Source)
Signal
Direction
Description
a0_arxclk
Input
Clock
a0_arxreset_n
Input
Active low reset to all internal logic, synchronous to the
arxclk domain.
a0_arxdav
Output
FIFO buffer has at least FTL words to read.
a0_arxena
Input
Enable
a0_arxadr[7:0]
Output
Port address
a0_arxdat[ATLDW-1:0](1)
Output
Data bus
a0_arxval
Output
Data valid
a0_arxsop
Output
Start of packet
a0_arxeop
Output
End of packet
a0_arxmty[ATLMTY-1:0](2)
Output
Number of invalid octets on the data bus
a0_arxerr
Output
Data error
bm_active_arxport[3:0]
Output
Buffer manager active receive port
bm_arxlev[7:0]
Output
Buffer manager level for active receive port
bm_arxport[3:0]
Input
Buffer manager receive port select input
bm_err_arxport[3:0]
Output
Buffer manager receive error port qualifier output
bm_stat_arxdav
Output
Buffer manager polled arxdav status for port stat_arxport
bm_stat_arxlev[7:0]
Output
Buffer manager polled arxlev status for port stat_arxport
bm_stat_arxport[3:0]
Output
Buffer manager polled receive status port
bm_rxoflw
Output
Buffer manager receive overflow. Synchronous to rrefclk.
bm_rxready
Output
Buffer manager initialization complete. Low during
initialization, goes high when the buffer manager is ready to
accept Atlantic data.
bm_rxuflw
Output
Buffer manager receive underflow
Notes from Table 57:
(1)
(2)
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Table 58. Internal Receiver Core Configuration Signals (Part 1 of 2)
Signal
Direction
Note (1)
Description
rxAE[n-1:0](2)
Input
Almost empty—starving to hungry threshold for each PHY port
rxAF[n-1:0](2)
Input
Almost full—hungry to satisfied threshold for each PHY port
160
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
Table 58. Internal Receiver Core Configuration Signals (Part 2 of 2)
Signal
Direction
POS-PHY Level 4
Note (1)
Description
rxCALM[7:0]
Input
Number of repeated FIFO buffer calculations before DIP-2 and
framing occurs.
rxFTH[n-1:0](2)
Input
FIFO buffer threshold high watermark
rxFTL[n-1:0](2)
Input
FIFO buffer threshold low watermark
Notes from Table 58:
(1)
(2)
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
n is equal to the number of FIFO buffer elements.
Table 59. Core Receive Control & Status Signals
Signal
Direction
Description
Output
The DIP-4 calculated over the rdat line does not match the DIP4 value in the control line. Single system clock (rrefclk) tick wide
pulse.
msop_err
Output
Missing SOP
meop_err
Output
Missing EOP
sop8_err
Output
SOP violation. Two SOPs occurred less than eight tdat cycles
apart.
mp_erradr[7:0]
Output
Address qualifier for meop_err and msop_err flags
paddr_err
Output
Port address error. Attempting to write to an non-existent port.
rsfrm
Input
When asserted, the rsfrm signal forces the receiver status
channel into framing mode. This can be used to indicate that the
receiver requires retraining.
Buffer Manager
Table 60. Global Receive Signals
Signal
Direction
Description
rrefclk
Output
Derived from rdclk, depends on data path width.
rxreset_n
Input
Active low reset to all internal logic, synchronized to the rrefclk domain
Altera Corporation
4
161
Specifications-MPHY
dip4_err
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Table 61 shows the DPA signals used by the receiver.
1
Only applicable when using the DPA circuitry of a
Stratix GX device.
Table 61. DPA Status Signals (Receiver Only)
Signal
Direction
Description
dpa_error
Output
Error flag to indicate that the DPA circuitry could not find byte alignment
dpa_force_unlock
Input
Forces the DPA circuitry and PLL to unlock and retrain
dpa_locked
Output
When this signal is high, it indicates that the DPA aligner has aligned
to the training pattern
dpa_lvds_locked[16:0] Output
Transmitter
When this signal is high, it indicates that the DPA PLL has locked
This section gives a block-by-block description of how the POS-PHY
Level 4 core functions as a transmitter. Figure 83 shows the blocks and
signals that comprise the transmitter.
Figure 83. Transmitter Block Diagram
(1)
Transmitter
trefclk
txreset_n
tdclk
tctl
tdat[15:0]
SPI-4.2
Interface
tsclk
tstat[1:0]
dip2_err
Core Status
Signals
tstat_sync
SERDES
POS-PHY
Level 4
Block
Buffer
Manager
a0_atxclk
a0_atxreset_n
a0_atxena
a0_atxadr[3:0]
Atlantic
a0_atxdat[ATLDW-1:0] (2)
Interface
a0_atxdav
a0_atxsop
a0_atxeop
a0_atxmty[ATLMTY-1:0] (3)
a0_atxerr
bm_active_atxport[3:0]
bm_atxlev[7:0]
bm_stat_atxport[3:0]
bm_stat_atxlev[7:0]
bm_stat_atxdav
bm_err_atxport[3:0]
bm_txoflw
bm_txuflw
bm_txready
Notes:
(1)
(2)
(3)
162
Each ellipse represents an Atlantic interface.
ATLDW stands for the Atlantic data path width parameter, which is user selectable.
ATLMTY = log2(ATLDW/8).
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Clock & Data
The transmitter requires two clock domains: one for the Atlantic interface
side, and one for the SPI-4.2 interface side.
The data is received on LVDS pins. The data associated with the clock is
double data rate (DDR). The 16-bit bus is serialized to 128 bits running at
a frequency of 1/8 the LVDS data rate
Figure 84 shows the data flow within the transmitter.
Figure 84. Transmitter Data Flow
SPI-4.2 Interface
High-Speed
Interface &
Serializer
Atlantic Interface
(Master Sink)
Control Word
Insertion
& DIP-4
Scheduler
&
Training
Pattern
Insertion
From
Buffer Manager
FIFO Buffer
Status & Management
4
An ALTLVDS function is used to serialize the words into input highspeed tdat/tctl lines.
Figure 85 on page 164 shows the transmitter output port configuration: 16
LVDS data pins, 1 LVDS control pin, 128-bit internal data path, 8-bit
internal control path, and an output clock.
Altera Corporation
163
Buffer Manager
Data words are sent on the tdat data bus at 2×tdclk rate. Payload data
words contain two bytes. Bits [15:8] form the first byte, and bits [7:0] form
the second byte. Bit 15 is the MSB, and bit 8 is the LSB of the first byte. Bit
7 is the MSB, and bit 0 is the LSB of the second byte.
Specifications-MPHY
High-Speed Interface & Serializer
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
For the output clock (tdclk), the user should not use the LVDS output
clock pins, but should use an appropriate LVDS data pair instead. The
tdclk pin can be treated as a data pin, because the SERDES is preloaded
with a binary 1010 pattern that guarantees an appropriate skew between
the clock and data.
1
The ALTLVDS macro does not require a reset.
Figure 85. Transmitter Output Port Configuration Note (1)
Serializer
tdat0
SERDES
.
.
.
tdat7
128
SERDES
rxdat
8
rxctl
tdat8
SERDES
.
.
.
Demultiplexer
tdat15
SERDES
tctl
SERDES
tdclk
trefclk
SERDES
PLL
Note:
(1)
The deserialisation factor is 8.
Control Word Insertion & DIP-4
This block inserts control words into the data path, and performs DIP-4
insertion.
An EOP abort condition can be generated on the SPI-4.2 interface by
asserting a0_atxerr with a valid a0_atxeop on the Atlantic interface.
This condition is the only one for which the EOP abort bit can be set in the
control word.
164
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Scheduler
The scheduler block receives decoded status channel information. It uses
this information to determine whether the FIFO buffer is starving, hungry,
or satisfied. A port can become active if that channel status is starving or
hungry, and the FIFO buffer indicates that it contains some data.
A round-robin priority-based scheduler serves the starving FIFO buffers
first. When no starving FIFO buffers remain, the hungry FIFO buffers get
served.
When a selected FIFO buffer is starving, the scheduler requests MB1. If the
selected FIFO buffer is hungry, the scheduler requests MB2. If the FIFO
buffer runs empty during its active timeslot, the scheduler ends the
current request and moves on to the next port to be served. The training
pattern is not inserted at EOP, but is inserted at the end of the burst
request.
To ensure equality, the scheduler does not select a new FIFO buffer until
it has fulfilled the amount requested by the FIFO buffer being served; a
request can encompass many packets depending on the requested
amount.
Training Pattern Insertion
This block inserts the training pattern at a scheduled interval defined by
the maximum training sequence interval parameter. If the training pattern
is asserted on the status channel, the core continuously sends training
patterns.The training pattern is sent out ALPHA (α) times.
The training sequence includes one IDLE control word, plus α×20 words.
The twenty words are separated into ten consecutive tdat words of
16’h0FFF with tctl of 1’b1, followed by ten consecutive tdat words of
16’hF000 with tctl of 1’b0. The user should expect some IDLEs before
and after the training sequence.
1
Altera Corporation
This feature is used to support dynamic alignment on adjacent
receivers.
165
4
Buffer Manager
If α = 0, the training pattern is not sent at MaxT, but still responds
to the framing pattern. The tstat_sync signal is observed as
low in this state.
Specifications-MPHY
1
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
FIFO Buffer Status & Management
This block monitors the tstat line (status channels) for DIP-2 or loss of
frame (LOF) errors. If a DIP-2 error occurs, the dip2_err signal is
asserted. The scheduler table is cleared when a DIP-2 error occurs. The
current transfer is not interrupted because the transfer is based on
MB1/MB2. If the status channel has not recovered by the time MB1/MB2 is
transmitted, it transmits IDLEs until a valid frame of status is received,
and the scheduler table is refreshed. The block forwards the extracted
status information (when requested) to the scheduler block. The DIP-2
error is cleared at the next tstat framing sequence.
When a DIP-2 error occurs, all the queues in the scheduler are cleared, and
the system recovers on its own (the current transfer continues to
completion).
Buffer Manager
The Atlantic FIFO buffer manager is designed to act as a common multiport FIFO buffer structure for the POS-PHY Level 4 Megacore function.
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
166
Single Atlantic interface
Support for up to 16 ports
Support for dual clock domains
Continuously updated active port status outputs for dav, readable
space (rlev), and writeable space (wlev)
Polled inactive port status outputs for dav, rlev, and wlev
Two threshold control inputs per port to enable hysteresis in dav
assertion/de-assertion
Threshold based dav assertion
User specified total memory allocated
Dynamic port memory segment sizing
Configurable Atlantic data width
Optional 2x data width conversion
Optional 1/2 data width conversion
Optional sop/eop error correction and err assertion based on missing
or spurious sop/eop
Underflow/overflow status outputs
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Functional Description
The buffer manager uses a single memory with portions allocated to each
port as configured by the user. The memory is managed in a linked list
format. All status and pointer information is stored in memory. Both clock
domains have a single active port at all times as chosen by the a0_atxadr
input. The active port has continuously updated bm_atxlev and
bm_txoflw status information, as well as continuously updated
a0_atxdav output. For inactive ports, a separate set of signals,
bm_stat_atxlev and bm_stat_atxdav, are used to display status
information in a round robin fashion. Figure 86 shows the buffer manager
block diagram.
Figure 86. Buffer Manager Block Diagram
Receive Clock Domain
wside
init
Transmit Clock Domain
Initialization
rdside
init
Status
Next Available Address FIFO Buffer
4
Memory
Read
167
Specifications-MPHY
Altera Corporation
Write
Buffer Manager
Error Checking
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Start/End of Packet Error Checking
Packet checking ensures that only properly formatted packets are passed
through the buffer manager, while partial and errored packets are
discarded. The error checking module—with the checkpkt input
asserted—corrects start- and end-of-packet errors before writing packets
into the buffer manager. For a missing start of packet (where two EOPs are
received before the next SOP), the data after the first EOP is dropped until
the subsequent SOP is received. For a missing end of packet (where two
SOPs are received before the next EOP), the second SOP is suppressed, an
EOP is inserted in the correct position, and the err signal is asserted.
By default, if the err signal input is asserted at any time during a packet
transmission, the err signal output is held asserted until the end of packet
is detected. This property is implemented to conform to the Atlantic
interface specification.
The state machine in Figure 87 shows all possible conditions where the
msop_err and meop_err outputs are asserted.
Figure 87. Packet Checker State Machine
eop &!sop
msop=1
sop &!eop & mty!=0
meop=1
IDLE
sop &!eop
meop=1
MEOP
ar
op
!e
& p=1
op o
!s ms
p
so
& p=1
p o
eo me
sop & eop
meop=1
sop & eop
meop=1
xm
m ty!=
eo 0
p= &
1 !eo
MSOP
p
sop & !eop
meop=1
168
BUSY
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Memory Structure
The memory structure for the buffer manager is maintained as a linked list
using two separate memories, a data memory and a descriptor memory.
The data memory is split into uniformly sized segments. The total number
of segments is equal to 256. Each location has a descriptor that is stored in
the descriptor memory. The descriptor holds information for start and end
of packet, mty for the packet, Atlantic error, the number of written
locations in the segment, and a pointer to the next data segment for the
particular port. Figure 88 shows the memory structure.
The total number of segments assigned to a particular port is
stat_port_size=int (256/number of ports). The total number of
segments that can be written before overflow occurs is
stat_port_size-1.
Figure 88. Memory Structure
Descriptor Memory
Segment 0 Descriptor
Segment 1 Descriptor
Data Memory
Segment 0
Segment 1
Segment n-1 Descriptor
0x0
0x(segment depth)
0x(2)(segment depth)
0x(n-2)(segment depth)
Segment n-1
0x(n-1)(segment depth)
4
The write module writes data into the descriptor and data memories
according to the values in the write descriptor memory. The write
descriptor memory holds the pointer and descriptor information for the
data segment currently being written for each port. The sequence of
events for packets being written to the data memory is as follows:
Altera Corporation
1.
On reset, an initial data segment is assigned to each port (segment 0
is assigned to port 0, segment 1 is assigned to port 1, etc.)
2.
When a SOP is received, the SOP field in the write descriptor is
asserted and the CNT field is incremented to 1.
169
Buffer Manager
Write
Specifications-MPHY
SOP EOP MTY ERR CNT NEXT
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
3.
For each subsequent write, the CNT field is incremented to track the
fill level of the current segment.
4.
When the current segment is filled or an EOP is received, the address
of the next free segment is read from the free segment FIFO buffer.
The address for the next free segment is written with the write
descriptor into the descriptor memory. All the fields for the write
descriptor are cleared except the current field which is loaded with
the address of the new current segment (next free segment.)
5.
When a total of stat_port_size-1 segments have been written to
a particular port, the port is deemed full and subsequent write
operations to that port will cause the buffer manager to signal an
overflow.
Figure 89 shows an example where the descriptor memory contents for a
single packet span three data segments. The first 64 transfers of the packet
with the SOP are written to segment 0x0. The second 64 transfers are
written to segment 0x27. The rest of the packet—22 transfers plus
EOP/MTY—is written to segment 0x35.
Figure 89. Descriptor Memory Example
Descriptor Memory
0x0
1
0
0
0
64 0x27
0
0
0
0
64 0x35
0
1
2
0
22 0x45
...
...
...
...
...
0x27
......
0x35
0x45
Read
The read module reads data from the descriptor and data memories
according to the values in the read descriptor memory. The read
descriptor memory holds the pointer and descriptor information for the
data segment currently being read for each port. The sequence of events
for packets being read from the data memory is as follows:
170
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
1.
On reset, an initial data segment is assigned to each port. The current
field in the read descriptor memory is loaded with this address.
2.
For the first segment or when the port has been emptied, the current
read descriptor is taken directly from the descriptor RAM.
Otherwise, the locally stored copy is used.
3.
Each time data is read from the current segment, the CNT field is
decremented.
4.
When the CNT field reaches 0, the new segment descriptor—pointed
to by the next field in the read descriptor—is loaded into the read
descriptor. The segment memory is released by writing the segment
address into the next address FIFO.
Next Available Address FIFO Buffer
The write module assigns data to the next available memory segment as
specified by the next available address FIFO buffer. Addresses are
released by the read module by writing them back into the FIFO buffer. At
reset, the next available address FIFO buffer is initialized by connecting
the write interface to a counter and overwriting each location in sequence.
The write pointer is reset to 0 and the read pointer is reset to 2×(number
of ports)+1 to account for the first addresses that are used as linked list
initialization values.
Status
For updating the read and write level between clock domains, an
increment value is passed which represents the number of new memory
segments that have been written to or read since the last update. The
increment value is added to the current value to obtain an updated level
value. The increment values are passed with a flag that is metastable
hardened.
Altera Corporation
171
Specifications-MPHY
Dual Clock Domain Status
4
Buffer Manager
At reset, the number of writeable segments or write level for a given port
is equal to stat_port_size-1. The number of readable segments or
read level at reset is equal to 0 for all ports. As data is written into the
buffer manager for a particular port, the status module updates and
displays status information through the polled status and active status
outputs. Active status outputs are updated continuously while polled
status outputs are displayed as they are polled.
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Polled Status Outputs
The buffer manager performs its status polling in round robin fashion,
where port status is polled in sequence. However, the polling sequence
can be interrupted by the following occurrences:
■
■
Active port is changed
Active port is removed
When the active port is changed, the status of the newly active port is
inserted into the polling sequence. For example, if the output polling
sequence follows a pattern of 0, 1, 2, 3, 8, 4, 5… and the active port is
changed to port 8, port 4 automatically becomes the next port for polled
status output.
When the active port is removed from the polling sequence, the active port
is re-added to the polling sequence exactly seven clock cycles after the
active port is changed.
Overflow
The buffer manager enters the overflow state for a given port if the
a0_atxena is asserted while full. A port is deemed full when it contains
exactly stat_port_size-1 full segments. In the case of overflow, the
bm_txoflw status output is asserted for a single clock cycle and the data
attempted to be written to the buffer manager is discarded.
Initialization
Resetting the buffer manager involves clearing all of the flops in the
design, as well as initializing all the memories to a known state. On reset,
the initialization module initializes the buffer manager using the
following sequence:
172
1.
Deassert the ready status output.
2.
Reset all flops.
3.
Reset the level increment RAMs to 0 for all ports.
4.
Reset the read level RAMs to 0 for all ports.
5.
Reset the write level RAMs to the stat_port_size-1 for all ports.
6.
Initialize the next available address FIFO buffer.
7.
Initialize the descriptor RAMs in the write and read modules.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
8.
Release flops from reset.
9.
Assert the ready status output.
POS-PHY Level 4
Atlantic Interface
The Atlantic interface is a standard Atlantic slave-sink interface that
allows the user to specify data and address port widths. The data port
width is limited to base 2 numbers greater than 8 bits. The address port
width is not limited.
Figure 90 through Figure 96 show the interface timing. The dark blue
shading represents “don’t care” states.
Figure 90. Active Port Status Timing Diagram
3 Cycles
a0_atxclk
0
bm_active_atxport
Active
Port
Status
Outputs
dav status port 0
a0_atxdav
4
level status port 0
bm_atxlev
0
a0_atxadr
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173
Specifications-MPHY
Buffer Manager
Atlantic
Input
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 91. Active Port Status with Multiple Transitions in the a0_atxadr Signal
Note (1)
a0_atxclk
a0_atxclk
0
bm_active_atxport
bm_active_atxport
Active
Active
Port
Port
Status
Status
Outputs
Outputs
0
a0_atxdav
a0_atxdav
0
bm_atxlev
bm_atxlev
Atlantic
Atlantic
Input
a0_atxadr
Input
a0_atxadr
0
0
1
1
0
1
0
1
0
1
2
2
3
3
1
2
1
2
1
2
4
4
2
2
2
3
3
3
3
4
3
4
3
4
5
4
4
4
5
5
5
5
5
dav status
davfor
status
port ...
for port ...
5
lev status
lev for
status
port ...
for port ...
5
Note:
(1)
174
The active port status outputs are updated three clock cycles after the a0_atxadr input transitions.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
3
2
f
0
a
c
f
(1)
(2)
e
Figure 92. Single Short Packet Transfer
1
4
0
a0_atxdat
a0_atxeop
a0_atxsop
Atlantic
Inputs
a0_atxena
0
a0_atxadr
bm_atxlev
a0_atxdav
Active
Port
Status
Outputs
bm_active_atxport
a0_atxclk
(1)
(2)
A single packet, that spans exactly one segment, is written for port 0.
Three clock cycles after that segment is filled, the bm_atxlev output is updated.
Altera Corporation
175
Specifications-MPHY
Buffer Manager
Notes:
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 93. Multiple Short Packet Transfers with Port Switching
Note (1)
a0_atxclk
0
1
2
bm_active_atxport
Active
Port
Status
Outputs
a0_atxdav
f
e
d
1
2
f
e
f
e
d
bm_atxlev
0
a0_atxadr
a0_atxena
Atlantic
Inputs
a0_atxsop
a0_atxeop
Note:
(1)
176
The bm_atxlev output is loaded for the port specified by the a0_atxadr input three clock cycles after the
a0_atxadr input transitions. The bm_atxlev output is updated for the active port each time an EOP is received.
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
3
2
f
0
d
e
f
(1)
10
(2)
11
e
(3)
d
(4)
Figure 94. Single Large Packet Transfer Spanning Two Memory Segments
1
4
0
a0_atxdat
a0_atxeop
a0_atxsop
Atlantic
Inputs
a0_atxena
0
a0_atxadr
bm_atxlev
a0_atxdav
Active
Port
Status
Outputs
bm_active_atxport
a0_atxclk
(1)
(2)
(3)
(4)
A full segment is written to fill the first memory segment. No EOP is received.
An EOP is received to end the packet transfer.
The bm_atxlev output is updated three clock cycles after the first segment is filled.
The bm_atxlev output is updated again three clock cycles after the EOP is received.
Altera Corporation
177
Specifications-MPHY
Buffer Manager
Notes:
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Figure 95. Packet Interleaving
a0_atxclk
0
1
0
1
bm_active_atxport
Active
Port
Status
Outputs
a0_atxdav
f
e
f
e
bm_atxlev
1
0
0
1
a0_atxadr
a0_atxena
Atlantic
Inputs
a0_atxsop
a0_atxeop
0
1
2
0
1
2
3
4
3
4
a0_atxdat
178
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
f
6
0
1
3
0
1
0
2
0
5 1
4 0
(1)
0
1
3
0
0
2
1
0
Figure 96. Overflow Timing Diagram
0
bm_txoflw
0
bm_err_atxport
Active
Port
Error
Outputs
a0_atxeop
a0_atxsop
a0_atxena
Atlantic
Inputs
1
a0_atxadr
6
5
bm_atxlev
a0_atxdav
Active
Port
Status
Outputs
0
bm_active_atxport
a0_atxclk
4
(1)
f
1
0
Buffer Manager
Note:
(1)
At this point, four consecutive packets are written to port 0, however, port 0 has only three segments available.
Overflow occurs and is indicated on the active port error outputs.
Altera Corporation
179
Specifications-MPHY
1
4
POS-PHY Level 4 MegaCore Function User Guide
Signals
Specifications – Multi-PHY with Virtual FIFO Buffer
Tables 62 through 66 list the I/O signals used in the core. The active low
signals are indicated by _n.
Table 62. SPI-4.2 Transmit Interface
Signal
Direction
Description
tdclk
LVDS Output
(data pin)
SPI-4.2 differential transmit clock. Ideally a 50% duty cycle.
tctl
LVDS Output
(data pin)
SPI-4.2 differential transmit control. When high, the word on tdat is a control
word. When low, the word on tdat is a payload word. tctl runs at 2 × tdclk
MHz.
tdat[15:0] LVDS Output
(data pin)
LVTTL Input
(clock pin)
tsclk
tstat[1:0] LVTTL Input
(data pin)
SPI-4.2 differential transmit data bus. Bus carries packets/cells or in-band
control words. tdat runs at 2 × tdclk MHz.
SPI-4.2 transmit status clock.
SPI-4.2 transmit status channel. Used to indicate the downstream device’s
FIFO buffers.
Table 63. Atlantic Transmit Interface (Part 1 of 2)
Signal
Direction
Description
a0_atxclk
Input
Clock
a0_atxreset_n
Input
Active low reset to all internal logic, synchronous to the
a0_atxclk domain
a0_atxdav
Output
FIFO buffer has at least FTH words to be written.
a0_atxena
Input
Enable
a0_atxadr[3:0]
Input
Port Address
a0_atxdat[ATLDW-1:0]
Input
Data bus
a0_atxsop
Input
Start of packet
a0_atxeop
Input
End of packet
a0_atxmty[ATLMTY-1:0]
Input
Number of invalid octets on the data bus
a0_atxerr
Input
Data error
bm_active_atxport[3:0] Output
Buffer manager active transmit port
bm_atxlev[7:0]
Output
Buffer manager level for active transmit port
bm_err_atxport[3:0]
Output
Buffer manager transmit error port qualifier output
bm_stat_atxdav
Output
Buffer manager polled a0_atxdav status for port
stat_atxport
180
Altera Corporation
Specifications – Multi-PHY with Virtual FIFO Buffer Segments & Buffer Management
POS-PHY Level 4
Table 63. Atlantic Transmit Interface (Part 2 of 2)
Signal
Direction
Description
bm_stat_atxlev[7:0]
Output
Buffer manager polled bm_atxlev status for port
stat_atxport
bm_stat_atxport[3:0]
Output
Buffer manager polled transmit status port
bm_txoflw
Output
Buffer manager transmit overflow
bm_txuflw
Output
Buffer manager transmit underflow. Synchronous to trefclk.
bm_txready
Output
Buffer manager initialization complete. Low during initialization,
goes high when the buffer manager is ready to accept Atlantic
data.
Table 64. Core Transmit Status Signals
Signal
Direction
Description
dip2_err
Output
The DIP-2 calculated for the FIFO buffer stat line does not match
the DIP-2 provided. Single FIFO buffer stat (trefclk) clock tick
wide pulse.
tstat_sync
Output
Indicates that the status channel is synchronized with proper
framing. Asserted low for improper configuration of status channel.
4
Direction
Description
trefclk
Input
Reference for tdclk.
txreset_n
Input
Active low reset to all internal logic. Must be synchronous to trefclk.
Table 66. Internal Transmitter Core Configuration Signals (Part 1 of 2)
Signal
Direction
Note (1)
Description
Transmit Status (Read)
txALPHA[7:0]
Altera Corporation
Input
Number of training pattern sequence repetitions
181
Buffer Manager
Signal
Specifications-MPHY
Table 65. Global Transmit Signals
POS-PHY Level 4 MegaCore Function User Guide
Specifications – Multi-PHY with Virtual FIFO Buffer
Table 66. Internal Transmitter Core Configuration Signals (Part 2 of 2)
Signal
txCALM[7:0]
Direction
Input
Note (1)
Description
Number of repeated FIFO buffer calculations before DIP-2 and framing
occurs.
txFTH[n-1:0](2) Input
FIFO buffer threshold high watermark. Available space left for writes.
txFTL[n-1:0](2) Input
FIFO buffer threshold low watermark. Available space for reads.
txMAXT[15:0]
Input
Training sequence interval
txMB1[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
starving.
txMB2[6:0]
Input
Number of 16-byte words that can be transmitted when the FIFO buffer is
hungry.
Notes:
(1)
(2)
182
These signals are used in the MegaWizard Plug-In wrapper to modify the parameters that do not affect the netlist.
n is equal to the number of FIFO buffer elements.
Altera Corporation
Appendix–Pin Constraints
& Board Design
Pin Constraints
The pinouts for the APEX II, Stratix, and Stratix GX device families
include dedicated True-LVDS clock input pins located on either the
RXCLK_IN1n/p bank, or the RXCLK_IN2n/p bank. All pins for the
receiver must be kept on the same bank. These True-LVDS banks require
a clean, filtered power supply.
Board Design
Configuration
For detailed board layout guidelines, refer to the High-Speed Board Layout
Guidelines Application Note, AN224, available at www.altera.com.
For detailed board layout guidelines in Stratix devices, refer to the Using
High-Speed Differential I/O Interfaces in Stratix Devices Application Note,
AN202, available at www.altera.com.
For detailed board layout guidelines—including the decoupling scheme
for the high-speed PLLs—in APEX II devices, refer to the Using High-Speed
I/O Standards in APEX II Devices Application Note, AN166, available at
www.altera.com.
1
AN202 and AN166 both specify pin limitations on either side of
the True-LVDS banks, refer to the High-Speed Interface Pin
Location sections of these application notes for further details.
A parallel combination of 0.1, 0.01, and 0.001µF capacitors should be used
to decouple the high-speed PLL power and ground planes.
If the status lines are not shifted by 180 degrees as per the SPI-4 Phase 2
specification, the sampling window can be shifted internally. For rstat
lines, this shift is accomplished by sampling on the negative edge of
rsclk instead of the positive edge. The tstat lines can also be flopped
out on the negative edge to phase shift the data for the adjacent device.
As for True-LVDS traces running at 700 Mbps, the standard board layout
guidelines for laying out high-speed True-LVDS traces should apply.
Altera Corporation
183
5
Appendix
For the output clock (tdclk), the user should not use the True-LVDS
output clock pins, but should use an appropriate True-LVDS data pair
instead. Clock pins can be treated as data pins, because the SERDES is
preloaded with a 1010 pattern that guarantees an appropriate skew
between the clock and data.
Insert Doc Title
Appendix–Pin Constraints & Board Design
1
184
Special attention should be given to status channel lines to
ensure setup and hold time requirements are met. Trace lengths
should match.
Altera Corporation
Appendix–Static &
Dynamic Phase Alignment
Static vs
Dynamic
Alignment
The SPI-4.2 standard specifies two mechanisms for receiving data from
the physical layer: static and dynamic alignment. Both follow the same
electrical specifications, but differ in their timing requirements.
Static Alignment
Static alignment is more traditional in that it calls for a specific setup and
hold time at the receiver. The implementation in the SPI-4.2 specification
is complicated by the double data rate (DDR) clock. The actual sampling
edge is implied by a synthesized clock related to the input reference. In the
specification, the receiver timing is bound by a maximum differential
between the clock and data, or frame signals. The receiver sampling
window has a fixed relationship to the input clock reference.
The timing margin for a statically-aligned system is calculated by
subtracting all of the delays from the overall period of the clock. These
delays include:
■
■
■
Transmitter clock-to-data skews
Receiver sampling windows
Jitter components
The remaining time is allocated to the connection between parts. All of the
differential delays between traces—caused by factors such as board
routing, transmission line effects, and connector skews—consume this
margin of time. Static alignment is appropriate for areas where such
factors can be well controlled. For example, the connection between
adjacent devices is generally short, and can be controlled— at layout
time—to within a few millimeters.
Figure 97 on page 186 shows an example of static alignment.
5
Appendix
Altera Corporation
185
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Figure 97. Static Alignment Timing Diagram
Clock
Data 1
Data 2
Inferred
Sample Clock
Receiver Sampling
Window
Dynamic Alignment
Dynamic alignment is an extension of the sampling paradigm that allows
for greater skew between the inputs. In this case, the common clock
reference is used to launch the data from the transmitter. At the receiver,
the frequency (hence sampling rate) is known, but the actual phase of the
data is not. Each receiver channel looks at its incoming data and chooses
an appropriate sampling point, at that sampling rate. Additional logic
may be required to account for the skews in sampling the data. These
skews arise when the data is realigned in time to reconstitute the data as
it was originally sent.
The timing margin for a dynamically-aligned system generally excludes
the differential skews between data leads. In this case, the timing margin
is calculated from the clock frequency by subtracting the receiver
sampling window, jitter components, and any sampling errors introduced
into the receiver. Transmitter output delays or skews, or interconnection
skews can be ignored because the receiver sampling algorithm
compensates for them.
Dynamic alignment is appropriate where the skews between signals
cannot be controlled. This is common where signals pass through
multiple connectors, or where devices can be interchanged. It typically
provides a much larger timing margin than static alignment.
Figure 98 on page 187 shows an example of dynamic alignment.
186
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
Figure 98. Dynamic Alignment Timing Diagram
Clock
Data 1
Inferred
Sample Clock
Phase Aligned
Sample for
Data 1
Phase Delay
Data 2
Phase Aligned
Sample for
Data 2
Altera
Solutions
Phase Delay
Altera supports both static and dynamic alignment as a system solution.
Static Alignment
The APEX II, Stratix, and Stratix GX device families have built-in highspeed interface macros. Using DDR clocking, these macros allow the
devices to receive data at rates exceeding 800 Mbps. Built-in logic within
the macros is used to present this data to the core logic—at lower
frequencies—for subsequent protocol processing. A reference sampling
clock is used to recover the data. This sampling clock is selected at design
time, and cannot be changed when the device is operating.
5
Appendix
Altera Corporation
187
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Dynamic Phase Alignment (DPA)
DPA technology has been developed to address the inadequacies of static
alignment methods. The goal of DPA is to allow devices to actively
respond to changes in the operational board skew. Devices equipped with
DPA continuously check the incoming data and adjust the phase of the
clock to align with it. Several industry standards responsible for defining
chip-to-chip interfaces, including System Packet Interface (SPI) 4.2, have
recognized the value of DPA, and have included or recommended it in
their specifications.
Every Stratix GX receiver channel features an embedded DPA block
(located in I/O banks 1 and 2). A complete, FPGA-integrated hard-silicon
DPA solution offers several benefits to system designers. It is
implemented for each data channel, such that each channel receives its
own phase-adjusted clock. This individual alignment for each channel
minimizes the chance for errors introduced by mismatches in signal
propagation paths. Also, it does not require a training mode; rather, it
continuously realigns the clock to the data during device operation. The
training patterns specified by standards such as SPI-4.2 are supported, but
no training pattern is required when using DPA with other interfaces.
The POS-PHY Level 4 core utilizes an integrated DPA block on its
receiving path, between the high-speed serial bus and the parallel bus.
The functions of this DPA block include: data deserialization and clock
division, dynamic phase alignment, and byte alignment.
The Stratix GX device family has embedded dynamic phase alignment
(DPA) macros that can support two POS-PHY Level 4 receivers in the
1SGX24 and 1SGX40 devices. The 1SGX10 device has a single DPA macro.
The POS-PHY Level 4 DPA block makes use of the DPA capability of
Stratix GX devices, supporting data rates of up to 1 Gbps. The DPA block
can be configured to support 17 hi-speed channels, and internal data
widths in excess of 64 or 128 bits.
Features
■
■
■
■
■
■
188
Dynamic clock-data synchronization (phase alignment) to
compensate the clock-channel and channel-channel skew
Dynamic byte alignment using training patterns
Supports the SPI-4.2 protocol
Corrects the data skew difference of up to +/- 2.25 bits (4.5 bits)
Supports SERDES factor of 8 and 4
Supports data rates from 415 to 1000 Mbps
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
Functional Description
The DPA block takes in the serial hi-speed phase/channel/byte
misaligned serial data, and outputs the phase/channel/byte aligned
parallel data and clock.
The block consists of the following sub-blocks: an ALTLVDS receiver
Megafunction (with the DPA feature enabled), a byte aligner, and an 8:4
deserializer (needed to achieve deserialization factor of 4). It also consists
of three status signals: locked, error, and lvds_locked, and one
control signal: force_unlock. See Figure 99.
Figure 99. DPA Block Diagram
Note (1)
clk_out
clk_in
x2
PLL
clk x 2
reset
Serial
Data
data_in
ALTLVDS
Receiver
Megafunction
(with DPA)
16+1
data_out
128+
align
Byte
Aligner
8:4
Deserializer
data_out_algn
(2)
128+
16+1
16+1
Parallel
Data
data : 2
128+/64+
error
locked
force_unlock
lvds_locked
Status/
Control
Signals
DPA
Notes:
(1)
(2)
The width of the data path for the data_out, data_out_algn, and data:2 signals depends on the SERDES
factor.
Exists only for a deserialization factor of 4.
ALTLVDS_Receiver Megafunction
Altera Corporation
189
5
Appendix
The ALTLVDS Receiver Megafunction performs the phase equalization
(data and clock), the deserialization and the bit slipping (per channel) if
requested by the byte aligner sub-block, via the Align signal (one bit for
each channel). The ALTLVDS_RX Megafunction is generated by the
MegaWizard Plug-in Manager in the Quartus II software.
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Byte Aligner
The byte aligner sub-block aligns the parallel data (channel by channel). It
pulses the Align signal until all channels are aligned (based on the
training patterns). For every Align pulse, the ALTLVDS_RX
Megafunction sub-block shifts the data on the corresponding channel by
one bit.
Alignment is done once at start-up, and whenever requested by the POSPHY Level 4 processor by asserting the force_unlock signal.
1
If lock cannot be achieved after the state machine has
received many force_unlock signals, it is a good
indication that the LVDS is not locked on some or all
channels, that the lvds_locked signal was deasserted
during training, or that the lvds_locked signal is asserted
but the channel-to-channel skew is greater than the
maximum supported skew.
The byte aligner works serially with one state machine serving all
channels.
If alignment cannot be achieved due to, for example, a skew between data
channels greater than +/-2.25 bits, the byte aligner asserts the error
signal.
The byte aligner state machine begins the alignment process once the
ALTLVDS_RX Megafunction asserts the lvds_locked signal (high).
During the alignment process, the byte aligner does not monitor the
lvds_locked signal, and should it become deasserted (low) during
alignment, the output data may be misaligned. The user can monitor the
dip4_err signal and assert force_unlock in response to misalignment.
190
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
POS-PHY Level 4 Training Pattern
The POS-PHY Level 4 training pattern consists of ten 0s and ten 1s (or ten
1s and ten 0s, depending on the channel), repeating ALPHA times. There
are 16 data channels and 1 control channel. The training pattern is shown
in Table 67.
Table 67. Training Pattern
Cycle
Control
(Channel 16)
Data (Channel 15 ... 0)
1
(idle)
1
0
X
X
0
0
0
0
0
0
0
0
0
A
B
C
D
2-11
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
12-21
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
For example, for a serialization factor of 8, the parallel data (ideally bytealigned) looks as shown in Table 68 (assuming ALPHA > 2).
Table 68. Training Pattern Example
Cycle
Control
[7:0]
Data
(Channel 15 ... 0 , bit [7:0])
Ch16
Ch15
Ch14
Ch13
Ch12
Ch11
...
Ch0
0
11111111
00000000
00000000
00000000
00000000
11111111
...
11111111
1
11000000
00111111
00111111
00111111
00111111
11000000
...
11000000
2
00001111
11110000
11110000
11110000
11110000
00001111
...
00001111
3
11111100
00000011
00000011
00000011
00000011
11111100
...
11111100
4
00000000
11111111
11111111
11111111
11111111
00000000
...
00000000
5
11111111
00000000
00000000
00000000
00000000
11111111
...
11111111
...
...
...
...
...
...
...
...
...
Since the training pattern is 20 bits long, a complete cycle lasts for 5 clock
cycles (2 training patterns or 40’hFF_C0_0F_FC_00), before the data
repeats (assuming ALPHA > 2).
5
8:4 Deserializer
Altera Corporation
191
Appendix
The 8:4 deserializer sub-block is required to support a deserialization
factor of 4, for 64-bit configurations only. It consists of a PLL and 4-bit
demultiplexers, one for each channel.
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Signals
Table 69 describes the signals for the DPA macro.
Table 69. DPA Signals (Receiver Only)
Signal
Direction
Description
Configuration Requirement
reset_n
Input
Active Low Reset.
All Modes
rx_in [16:0]
Input
Serial Data (with skew)
All Modes
rx_inclock
Input
Serial Clock (with skew)
All Modes
rx_out [S*16:0](1)
Output
Parallel data (no skew, byte aligned)
All modes
rx_outclock
Output
Parallel clock
All modes
locked
Output
Phase and byte alignment achieved
All modes
Force realignment
All modes
Input
force_unlock
lvds_locked [16:0]
Output
ALTLVDS_RX is locked
All modes
error
Output
Byte alignment cannot be achieved
All modes
Notes from Table 69:
(1)
S is equal to SERDES factor.
f
For more information on using dynamic phase alignment, refer to AN236:
Using Source-Synchronous Signaling with DPA in Stratix GX Devices.
f
For more information on the Stratix GX device family, refer to the: Stratix
GX FPGA Family Data Sheet.
AC Timing
Analysis
Specifications for this interface allow two sets of timing relationships
between the sender and receiver: static and dynamic mode. In the static
alignment mode, all data obeys a common set of timing parameters (e.g.
set up and hold times with respect to a sampling clock). In the dynamic
alignment mode, a per-bit timing relationship applies.
This section describes the timing analysis for various configurations and
components. These timing components are referenced to Figure 100 on
page 193. This figure shows the timing path as related to the paths
followed by the clock and data signals through the user’s system.
Figure 101 on page 193 references the timing values to the clock and data
edges.
192
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
Figure 100. Timing Analysis Model
Channel Distortion
Data Dependent Jitter
(Deterministic)
Board Effects
Buffer Distortion
(Duty Cycle)
Data Sampling Window
Serializer
for
Serializer
Data
Channel
Buffer Distortion
(Duty Cycle)
Channel-to-Channel
Skew Relative to Clock
Serializer
for
Source
Synchronous
Clock
PLL
Random (Intrinsic)
Jitter
Jitter Attenuation/Pass-Through
plus Intrinsic Jitter
Fast
PLL
Reference Point B
Reference Point A
Clock Source
Jitter
Clock
Source
Figure 101. Timing Diagram
Clock Placement
Internal Clock
Synchronization
Transmitter
Output Data
TCCS
TCCS/2
Receiver
Input Data
5
SW
Altera Corporation
Appendix
1
The calculations follow those in OIF2000.088.4, Appendix D
Sample LVDS Timing Budgets.
193
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
APEX II Timing
Table 70 analyses the component contributions and derives the overall
timing budget for system contributions between points A and B in
Figure 100 on page 193.
Table 70. Altera Transmitter to “Specification” Receiver at 700 Mbps
Parameter
Total Budget
Clock period
1400 ps
Reference
700 MHz – 2%
Transmitter
Clock-to-data skew
400 ps
Transmit channel-to-channel
skew (TCCS), ref AN166,
Table 12
Clock duty cycle distortion
30 ps
2% of period, ref AN120 Table
6, tDUTY
Data duty cycle distortion
30 ps
2% of period, ref AN120 Table
6, tDUTY
Data jitter (random, including data dependencies) 80 ps
assumed from
OIF2000.088.4 Table D.1
540 ps
Subtotal
Receiver
Sampling error
610 ps
Tsampling, OIF2000.088.4
Table 6.8a
Relative jitter
80 ps
assumed from
OIF2000.088.4 Table D.1
690 ps
Subtotal
System margin
170 ps
Table 71. “Specification” Transmitter to APEX II Receiver at 700 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
Reference
1400 ps
Transmitter
Clock-to-data skew
560 ps
Includes all factors (T_dia +
T_dib), OIF2000.088.4 Table
6.8a
Clock duty cycle distortion
Data duty cycle distortion
Data jitter
194
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
Table 71. “Specification” Transmitter to APEX II Receiver at 700 Mbps (Part 2 of 2)
Parameter
Total Budget
Reference
560 ps
Subtotal
Receiver
Sampling error
350 ps
SW, ref AN166 Table 11
Relative jitter
100 ps
PLL output jitter, AN166 Table
tbd
450 ps
Subtotal
System margin
390 ps
Table 72. APEX II Transmitter to APEX II Receiver at 700 Mbps
Parameter
Total Budget
Clock period
Reference
1400 ps
Transmitter
Clock-to-data skew
400 ps
Transmit channel-to-channel
skew (TCCS), ref AN166,
Table 12
Clock duty cycle distortion
30 ps
2% of period, ref AN120 Table
6, tDUTY
Data duty cycle distortion
30 ps
2% of period, ref AN120 Table
6, tDUTY
Data jitter
80 ps
assumed from
OIF2000.088.4 Table D.1
540 ps
Subtotal
Receiver
Sampling error
350 ps
SW, ref AN166 Table 11
Relative jitter
100 ps
PLL output jitter, AN166 Table
tbd
Subtotal
System margin
450 ps
5
410 ps
Appendix
Altera Corporation
195
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Stratix Timing
Table 73 analyses the component contributions and derives the overall
timing budget for system contributions between points A and B in
Figure 100 on page 193.
Table 73. Altera Stratix Transmitter to “Specification” Receiver at 700 Mbps
Parameter
Total Budget
Clock period
Reference
1429 ps
Transmitter
Clock-to-data skew
200 ps
Stratix Data Sheet, Table 172.
Transmit channel-to-channel
skew
Clock duty cycle distortion
143 ps
Stratix Data Sheet, Table 173.
45-55%
Data duty cycle distortion
143 ps
Stratix Data Sheet, Table 173.
45-55%
Data jitter (random, including data dependencies) 80 ps
assumed from
OIF2000.088.4 Table D.1
566 ps
Subtotal
Receiver
Sampling error
553 ps
Sampling window in center of
UI
Relative jitter
80 ps
assumed from
OIF2000.088.4 Table D.1
634 ps
Subtotal
System margin
229 ps
Table 74. “Specification” Transmitter to Stratix Receiver at 700 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
Reference
1400 ps
Transmitter
Clock-to-data skew
200 ps
assumed from
OIF2000.088.4 Table D.1
Clock duty cycle distortion
0 ps
Clock is regenerated on
positive edge in Stratix
receiver
196
Altera Corporation
Appendix–Static & Dynamic Phase Alignment
POS-PHY Level 4 MegaCore Function (POSPHY4) User
Table 74. “Specification” Transmitter to Stratix Receiver at 700 Mbps (Part 2 of 2)
Parameter
Total Budget
Reference
Data duty cycle distortion
143 ps
assumed from
OIF2000.088.4 Table D.1
45-55%
Data jitter
80 ps
assumed from
OIF2000.088.4 Table D.1
423 ps
Subtotal
Receiver
Sampling error
440 ps
Stratix Data Sheet, Table 172.
Sampling window in center of
UI
Relative jitter
0 ps
Include in SW
440 ps
Subtotal
System margin
565 ps
Table 75. Stratix Transmitter to Stratix Receiver at 700 Mbps (Part 1 of 2)
Parameter
Total Budget
Clock period
Reference
1400 ps
Transmitter
Clock-to-data skew
200 ps
Stratix Data Sheet, Table 172.
Transmit channel-to-channel
skew
Clock duty cycle distortion
0 ps
Clock is regenerated on
positive edge in Stratix
receiver
Data duty cycle distortion
143 ps
Stratix Data Sheet, Table 173.
45-55%
Data jitter
80 ps
assumed from
OIF2000.088.4 Table D.1
5
423 ps
Subtotal
Sampling error
440 ps
Relative jitter
0 ps
Subtotal
Altera Corporation
Stratix Data Sheet, Table 172.
Sampling window in center of
UI
Include in SW
440 ps
197
Appendix
Receiver
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
Appendix–Static & Dynamic Phase
Table 75. Stratix Transmitter to Stratix Receiver at 700 Mbps (Part 2 of 2)
Parameter
System margin
f
198
Total Budget
Reference
565 ps
For timing information on the SPI-4 Phase 2 interface, refer to the Optical
Internetworking Forum (OFI), System Packet Interface Level 4 (SPI-4) Phase
2: OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.0,
January 2001.
Altera Corporation