PCI32 Nios Target
MegaCore Function
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
1.4.0
Document Version:
1.4.0 rev 1
Document Date: December 2002
PCI32 Nios Target MegaCore Function User Guide
Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
A-UG-PCI32-1.5
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
PCI32 Nios® Target MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the core features.
Refer to the readme file for late-breaking information that is not
available in this user guide.
Table 1. User Guide Revision History
Date
How to Find
Information
December, 2002
Stratix GX device information added. Core verification
section added. Register information changes. SOPC Builder
selection re-written.
August, 2002
Cyclone™ device information added..
July, 2002
Changes to register information.
April, 2002
Stratix™ device information added.
February, 2002
OpenCore® Plus information added. Nios development kit
updated to version 2.0.
October, 2001
Initial release.
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Altera Corporation
Description
™
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
PCI32 Nios Target MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The PCI32 Nios Target MegaCore Function User Guide uses the typographic
conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Device Family Support ....................................................................................................................9
Introduction ....................................................................................................................................10
New in Version 1.4.0 ......................................................................................................................10
Features ...........................................................................................................................................10
General Description .......................................................................................................................11
OpenCore & OpenCore Plus Hardware Evaluation .................................................................11
Getting Started ............................................................................................................................................13
Software Requirements .................................................................................................................13
Design Flow ....................................................................................................................................13
Download & Install the Function ................................................................................................13
Obtaining MegaCore Functions ...........................................................................................13
Install the MegaCore Files ....................................................................................................14
MegaCore Directory Structure .............................................................................................14
Set Up Licensing .............................................................................................................................16
Append the License to Your license.dat File ......................................................................16
Specify the Core’s License File in the Quartus II Software ..............................................17
PCI32 Nios Target Walkthrough .................................................................................................17
Create a New Quartus II Project ..........................................................................................18
Select & Configure the Nios Soft Core ................................................................................19
Configure the PCI32 Nios Target MegaCore Function ....................................................28
Exercise the Custom Core .............................................................................................................35
Simulate using the Reference Design .........................................................................................35
Walkthrough for ModelSim VHDL Simulator ..................................................................36
Walkthrough for Verilog HDL Simulators .........................................................................37
Specifications ..............................................................................................................................................41
Functional Description ..................................................................................................................41
DMA Engine ...........................................................................................................................41
Read Cycles from External Memory on the PCI Bus ........................................................42
DMA Write Cycles to External Memory on PCI Bus ........................................................43
OpenCore Plus Time-Out Behavior ....................................................................................44
Altera Corporation
vii
Contents
Parameters .......................................................................................................................................44
Signals ..............................................................................................................................................45
PCI Bus Signals .......................................................................................................................45
Avalon Bus Signals ................................................................................................................48
Memory Map ..................................................................................................................................50
Registers ..........................................................................................................................................50
Messaging Registers ..............................................................................................................52
DMA Registers .......................................................................................................................63
Data Register ...........................................................................................................................64
PCI Command Registers .......................................................................................................65
PCI Interface ...................................................................................................................................66
PCI Bus Commands ...............................................................................................................66
PCI Configuration Registers .................................................................................................67
Commands Issued from the PCI Side .................................................................................73
Core Verification ............................................................................................................................74
Simulation Testing .................................................................................................................74
Hardware Testing ..................................................................................................................74
Appendix A—Nios Application Programming Interface ...............................................................75
Basic Functions ...............................................................................................................................76
Generic Read/Write Functions ............................................................................................76
Specific Memory, Configuration, & I/O Read Write Functions .....................................80
PCI Target Mailbox Functions .....................................................................................................87
Interrupt Functions ........................................................................................................................87
Miscellaneous Functions ...............................................................................................................89
Supported Commands ..................................................................................................................89
Appendix B—PCI Testbench ...................................................................................................................93
Pre-Synthesis Design Flow ...........................................................................................................94
Post-Synthesis Design Flow .........................................................................................................99
Functional Description ..................................................................................................................99
Master Transactor ................................................................................................................101
Target Transactor .................................................................................................................107
Bus Monitor ..........................................................................................................................110
Clock Generator (clk_gen) ..................................................................................................110
Pull Up ...................................................................................................................................111
Appendix C—The Software Example ................................................................................................113
Directories .....................................................................................................................................113
Inc ...........................................................................................................................................113
Src ...........................................................................................................................................113
Walkthrough .................................................................................................................................113
Appendix D—OpenCore Plus Evaluation .........................................................................................117
About OpenCore Plus Hardware Evaluation ..........................................................................117
OpenCore Plus Licensing ...........................................................................................................119
viii
Altera Corporation
About this Core
1
Table 4 provides information about this release of the PCI32 Nios Target
MegaCore function.
Table 4. PCI32 Nios Target Release Information
Item
Version
Device Family
Support
1.4.0
Release Date
November 2002
Ordering Code
IP-PCI/MT32-N/T
Product ID(s)
0089
Vendor ID(s)
6AF8 (Standard)
6AF9 (Time-Limited)
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
About this Core
Release
Information
About this Core
PCI32 Nios Target MegaCore Function User Guide
Table 5 shows the level of support offered by the PCI32 Nios Target
MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Stratix GX
™
Support
Preliminary
Cyclone
Preliminary
Stratix™
Preliminary
Excalibur™
™
Full
HardCopy
Full
ACEX® 1K
Full
™
APEX II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX 10KE
Full
Other device families
No support
Introduction
The Altera PCI32 Nios Target MegaCore function connects a peripheral
component interconnect (PCI) bus to the Nios soft core embedded
processor system via the Avalon™ bus.
New in Version
1.4.0
■
■
■
Support for StratixGX devices
Improved direct memory access (DMA) engine
Support for Quartus® II native synthesis.
Features
■
Interface between the PCI bus and the Nios soft core embedded
processor
PCI 32-bit, 33-MHz master/target interface with host bridge
capability
Application programming interface (API) supplied for the Nios soft
core embedded processor
Behavioral RTL models for simulation in VHDL and Verilog HDL
simulators
DMA directly from FIFO buffers to PCI memory
Messaging registers generate interrupts to Nios and PCI peripherals
Easy-to-use wizard-driven interface that allows you to customize
your application
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■
■
■
10
Altera Corporation
GettingAbout this Core
PCI32 Nios Target MegaCore Function User Guide
■
General
Description
The Altera PCI32 Nios Target MegaCore function connects a peripheral
component interconnect (PCI) bus to the Nios soft core embedded
processor system via the Avalon bus (see Figure 1). The Avalon bus is an
Altera parameterized interface bus, which is a set of predefined signal
types that connects one or more intellectual property (IP) blocks. For
example, the Nios soft core embedded processor uses the Avalon bus to
interconnect the CPU, peripherals, memory, and external I/O ports.
Figure 1. PCI32 Nios Target MegaCore Function
PCI Bus
f
PCI32 Nios
Target
MegaCore
Function
Avalon Bus
For more information on the Nios soft core embedded processor system,
refer to the Nios documentation, which is supplied with the Nios
development kit.
The PCI32 Nios Target MegaCore function comprises a 32-bit Nios target
on one side and a 32-bit, 33-MHz PCI master/target on the other side.
The PCI32 Nios Target MegaCore function uses the established Altera PCI
MegaCore function technology. The core is a Nios peripheral, which you
can instantiate into your embedded processor system using the SOPC
Builder. The core can be used as a master or target on the PCI bus, and can
be parameterized to act as a PCI host bridge.
OpenCore &
OpenCore Plus
Hardware
Evaluation
Altera Corporation
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus® II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed before making a purchase decision. However, you cannot generate
device programming files.
11
1
About this Core
■
■
PCI testbench with the following features:
–
Easy-to-use simulation environment for any standard VHDL or
Verilog HDL simulator
–
Open source VHDL and Verilog HDL files
–
Flexible PCI bus functional model to verify your application that
uses the PCI32 Nios Target MegaCore function
–
Simulates all basic PCI transactions including memory
reads/writes, I/O reads/writes, and configuration reads/writes
Reference design suitable for simulation
Supports OpenCore® Plus hardware evaluation
About this Core
PCI32 Nios Target MegaCore Function User Guide
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that includes Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
f
12
For more information on OpenCore Plus hardware evaluation, see
“OpenCore Plus Time-Out Behavior” on page 44 and “Appendix D—
OpenCore Plus Evaluation” on page 117.
Altera Corporation
Getting Started
Software
Requirements
The PCI32 Nios Target requires the following software:
Quartus II software, version 2.1 SP1 (or higher)
SOPC Builder version 2.6.1
ModelSim simulation tool, version 5.5e (or higher)
1
Design Flow
Download &
Install the
Function
2
Getting Started
■
■
■
This walkthrough requires the Nios embedded processor
version 2.2.
The PCI32 Nios Target design flow involves the following steps:
1.
Download and install your MegaCore function.
2.
Generate a custom MegaCore function.
3.
Exercise your custom MegaCore function.
4.
Simulate using the reference design.
Before you can start using the the PCI32 Nios Target MegaCore function,
you must obtain the MegaCore files and install them on your PC. The
following instructions describe this process.
Obtaining MegaCore Functions
If you have Internet access, you can download the PCI32 Nios Target
MegaCore function from the Altera web site at http://www.altera.com.
Follow the instructions below to obtain the PCI32 Nios Target MegaCore
function via the Internet. If you do not have Internet access, you can obtain
the PCI32 Nios Target MegaCore function from your local Altera
representative.
Altera Corporation
1.
Open your web browser and connect to
http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose PCI and Bus Interfaces from the Technology drop-down list
box.
13
Getting Started
PCI32 Nios Target MegaCore Function User Guide
4.
Type PCI32 Nios Target in the Keyword Search box.
5.
Click Go.
6.
Click the link for the Altera PCI32 Nios Target MegaCore function in
the search results table. The product description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
I Agree at the bottom of the page.
9.
Follow the instructions on the PCI32 Nios Target download and
installation page to download the function and save it to your hard
disk.
Install the MegaCore Files
To install the MegaCore files, follow the instructions below:
1.
Click Run (Start menu).
2.
Type <path>\<filename>, where <path> is the location of the
downloaded MegaCore function and <filename> is the file name of
the core. Click OK.
3.
Follow the online instructions to finish installation.
MegaCore Directory Structure
Altera MegaCore function files are organized into several directorys (see
Figure 2).
1
14
The MegaCore directory structure can contain several MegaCore
products. Additionally, Altera updates MegaCore files from
time to time. Therefore, Altera recommends that you do not save
your project-specific files in the MegaCore directory structure.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
Figure 2. MegaCore Directory Structure (1), (2), (3)
megacore
pci32_nios_target-<version>
Contains the PCI32 Nios target MegaCore function files and documentation.
doc
Contains the documentation for the core.
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
2
nios_system_example
Contains the Nios soft core embedded processor example directory.
nios_system_hw
Contains the Nios soft core embedded processor hardware example for use with
the PCI32 Nios Target Add-on Kit.
nios_system_sw
Contains the Nios soft core embedded processor software example for simulation.
sim_lib
Contains the simulation models provided with the core.
modelsim
Contains the precompiled libraries for the ModelSim simulation tool.
vip_models
Contains the precompiled libraries for the Visual IP software.
testbench
Contains the VHDL and Verilog HDL testbench directories (see Appendix B).
Notes:
(1)
(2)
(3)
Altera Corporation
For more information on OpenCore Plus evaluation, see “Appendix D—OpenCore
Plus Evaluation” on page 117.
The nios_system_example directories are used by the PCI32 Nios Target Add-On
Kit.
For more information on the PCI32 Nios Target Add-on Kit, contact your Altera
representative.
15
Getting Started
lib_time_limited
Contains the OpenCore Plus encrypted lower-level design files.
After installing the MegaCore function, you should set a user library in the
Quartus II software that points to this directory. This library allows you to access
all the necessary MegaCore files.
Getting Started
Set Up
Licensing
PCI32 Nios Target MegaCore Function User Guide
You can use the Altera OpenCore feature to compile and simulate the
PCI32 Nios Target MegaCore function, allowing you to evaluate it before
purchasing a license. You can simulate your PCI32 Nios Target design in
the Quartus II software using the OpenCore feature. However, you must
obtain a license from Altera before you can generate programming files or
EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in
third-party EDA tools.
After you purchase a license for PCI32 Nios Target, you can request a
license file from the Altera web site at http://www.altera.com/licensing
and install it on your PC. When you request a license file, Altera e-mails
you a license.dat file. If you do not have Internet access, contact your local
Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the PCI32 Nios Target, you must
already have the Quartus II software installed on your PC with
licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the PCI32 Nios Target license file in a text editor. The file
should contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the PCI32 Nios Target license file and
paste it into the Quartus II license file.
1
16
Do not delete any FEATURE lines from the Quartus II license
file.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
5.
GettingGetting Started
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
PCI32 Nios
Target
Walkthrough
2
Create a text file with the FEATURE line and save it to your hard disk.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
This section describes the design flow using the Nios soft core embedded
processor, the PCI32 Nios Target MegaCore function, and the Quartus II
development system. Altera provides a MegaWizard Plug-Ins with the
PCI32 Nios Target MegaCore function, which you can use within the
Quartus II software. Using a wizard allows you to create or modify design
files that instantiate a MegaCore function. You can then instantiate the
design file generated by the wizard in your project.
The PCI32 Nios Target MegaCore function walkthrough involves the
following steps:
Altera Corporation
17
Getting Started
1.
Getting Started
PCI32 Nios Target MegaCore Function User Guide
1.
Create a new Quartus II Project.
2.
Select and configure the Nios soft core embedded processor.
3.
Configure the PCI32 Nios Target MegaCore function.
Create a New Quartus II Project
Before you begin creating a core, you must create a new Quartus II project.
With the New Project wizard, you specify the working directory for the
project, assign the project name, and designate the name of the top-level
design entity. You will also specify the PCI32 Nios Target user library. To
create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software if you prefer.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory <project directory> for your project.
5.
Specify the name of the project <project name>.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\pci32_nios_target-<version>\lib\ into the
Library name box, where <path> is the directory in which you
installed the PCI32 Nios Target. The default installation directory is
c:\MegaCore.
1
9.
For the OpenCore Plus PCI32 Nios Target type
<path>\pci32_nios_target<version>\lib_time_limited\ into the Library name
box.
Click Add.
10. Click OK.
11. Click Next.
18
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
12. Click Finish.
You are finished creating your new Quartus II project.
Select & Configure the Nios Soft Core
1.
Choose SOPC Builder (Tools menu).
2.
Enter the system name, example, and choose Verilog or VHDL (see
Figure 3).
Getting Started
Figure 3. Enter System Name
3.
f
Altera Corporation
2
Click OK.
For more information on the following selections refer to the Nios
Embedded Processor System Builder Tutorial in your
Altera\Excalibur\nios_tutorial directory.
19
Getting Started
PCI32 Nios Target MegaCore Function User Guide
4.
On the System Contents tab select Altera Nios <version> CPU. Click
Add (see Figure 6).
Figure 4. Add a Nios CPU
20
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
5.
GettingGetting Started
Click Finish (see Figure 5).
Figure 5. CPU Wizard
2
Getting Started
1
Altera Corporation
The default CPU name, <cpu instance name>, is nios_0.
21
Getting Started
PCI32 Nios Target MegaCore Function User Guide
6.
On the System Contents tab select On-Chip Memory, ‘RAM or
‘ROM’. Click Add (see Figure 6).
Figure 6. Add a ROM Block
1
22
The SOPC Builder assigns names to each peripheral; do not
change these names for this walkthrough.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
7.
GettingGetting Started
Under Memory Type, select ROM (read-only). Select the data width
(32 bits) and the total memory size (20 Kbytes) (see Figure 9). Click
Next. Click Finish.
Figure 7. ROM Wizard
2
Getting Started
Altera Corporation
23
Getting Started
PCI32 Nios Target MegaCore Function User Guide
8.
On the System Contents tab select On-Chip Memory, ‘RAM or
‘ROM’. Click Add (see Figure 6).
Figure 8. Add a RAM Block
24
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
9.
GettingGetting Started
Under Memory Type, select RAM (readable). Select the data width
(32 bits) and the total memory size (2 Kbytes) (see Figure 9). Click
Next. Click Finish.
Figure 9. RAM Wizard
2
Getting Started
Altera Corporation
25
Getting Started
PCI32 Nios Target MegaCore Function User Guide
10. On the System Contents tab select UART (RS-232 serial port)
(Communication menu). Click Add (see Figure 10).
Figure 10. Add a UART
26
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
11. In the UART wizard select the baud rate, parity, data bits, and stop
bits (see Figure 9). Click Next. Click Finish.
Figure 11. UART Wizard
2
Getting Started
12. On the System Contents tab select Altera PCI32 Nios Target
Component or Altera Time Limited PCI32 Nios Target Component
(Other menu). Click Add (see Figure 10).
1
Altera Corporation
This walkthrough uses the Altera PCI32 Nios Target
Component.
27
Getting Started
PCI32 Nios Target MegaCore Function User Guide
Figure 12. Add a PCI32 Nios Target MegaCore Function
The PCI32 Nios Target wizard starts.
1
pci32_nios_target_component_0 is the name, <instance>, that
the wizard gives to your PCI32 Nios Target peripheral.
Configure the PCI32 Nios Target MegaCore Function
1
The MegaWizard Plug-In only allows you to select legal values,
and warns you of any invalid values.
To configure the PCI32 Nios Target MegaCore function, perform the
following steps:
1.
f
28
Select your desired configuration for the PCI configuration registers
(see Figure 13). Click Next.
For more information on the PCI configuration registers see “PCI
Configuration Registers” on page 67.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
Figure 13. PCI Configuration Registers
2
Getting Started
2.
Select your advanced features. Figure 14 shows the advanced
features available with the MegaCore function, (i.e., interrupt
capabilities, master features, and BAR0).
You can select whether to use an interrupt pin, or not. If you check
the Use Interrupt Pin box, the interrupt pin register has a value of
01 H, which indicates that the interrupt signal (i.e., intan) is used.
Otherwise, the interrupt pin register is set to 00, which indicates that
no interrupts are used.
The function can be used as a host bridge application. Selecting the
Use in Host Bridge Application option hardwires the master enable
bit of the command register (bit[2]) to a value of 1, which
permanently enables the master functionality of the MegaCore
function. Additionally, the Use in Host Bridge Application option
also allows the master device to generate configuration read and
write transactions to the internal configuration space. With the Use
in Host Bridge Application option, the same logic and software
routines used to access the configuration space of other PCI devices
on the bus can also configure the PCI32 Nios Target MegaCore
function configuration space.
1
Altera Corporation
To perform configuration transactions to internal
configuration space, the idsel signal must be connected
following the PCI specification requirements.
29
Getting Started
PCI32 Nios Target MegaCore Function User Guide
Additionally, the disable master latency timer option allows you to
disable the latency timer timeout feature. If the latency timer timeout
is disabled, the master continues the burst transaction even if the
latency timer has expired and the gntn signal is removed. This
feature is useful in systems in which breaking up long data transfers
in small transactions yields undesirable side effects.
1
Using the disable master latency timer option violates the
PCI specification; and therefore should only be used in
embedded applications where the designer can control the
entire system configuration. In addition, using the disable
master latency timer option can result in increased latency
for other master devices on the system. If the increased
latency results in undesirable effects, this option should not
be used.
The MegaCore function implements one 32-bit BAR using BAR0
register, which reserves 2 KByte of memory space.
In addition to allowing normal BAR operation where the system
writes the base address value during system initialization, the
MegaCore function allows the base address of the BAR to be
hardwired using the Hardwire BAR option. When hardwiring the
BAR, the BAR address is implemented as a read-only value supplied
to the MegaCore function through the parameter value. System
software cannot overwrite a base address that is hardwired.
Click Next.
Figure 14. Choose Advanced Features
3.
Select an input constraint file by browsing to the local directory
where your input constraint file is saved (see Figure 15).
You can use Quartus II constraint files to ensure that the PCI32 Nios
30
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PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
Target MegaCore function achieves PCI specification timing
requirements in Altera devices. The constraint files contain logic
option settings, as well as device, PCI pin, timing, clique, and
location assignments for PCI32 Nios Target MegaCore function logic.
When you have chosen a specific Altera device and are ready to
assign pin locations, the constraint files should be incorporated into
your design. Devices supported in the Quartus II software use a
compiler settings file (.csf) and an entity settings file (.esf).
2
Figure 15. Generate Project Specific Constraint Files
Getting Started
4.
Enter the name of your project. If the project is partitioned into
multiple devices, enter the name of the device that contains the
PCI32 Nios Target MegaCore function.
5.
Enter the project hierarchy for the PCI32 Nios Target MegaCore
function instance. For example, if you create a PCI32 Nios Target
function instance named pci_top through the wizard, and
instantiated pci_top:inst in your project top, the hierarchical name of
the MegaCore function is pci_top:inst.
6.
Browse to the directory where you would like to save your project
constraint file(s) and enter the name of the output file. Choose
Generate Constraint Files Now.
The Tcl file that the wizard generates can be saved into any project
directory. The Tcl file contains all necessary information to create a
CSF and ESF. To generate a project specific CSF and ESF—after
generating a project specific Tcl file with the wizard—run the Tcl
script through the Quartus II Tcl console while the PCI project is
active.
Altera Corporation
31
Getting Started
PCI32 Nios Target MegaCore Function User Guide
f
Refer to Quartus II Help for more information on using Tcl in the
Quartus II software.
7.
Click Next to view the summary screen.
8.
The summary screen lists the design files that the wizard creates, and
the product ordering code for the MegaCore function targeted in
your design (see Figure 16). You need the product ordering code
when you want to license the MegaCore function. Click Finish.
Figure 16. Design Files
32
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
9.
GettingGetting Started
You are returned to the SOPC Builder (see Figure 17). Click Next.
Figure 17. SOPC Builder
2
Getting Started
Altera Corporation
33
Getting Started
PCI32 Nios Target MegaCore Function User Guide
10. Click Next. Apply the following function and module settings (see
Figure 18):
Reset Location to onchip_memory_0 (ROM),
Vector Table to onchip_memory_1 (RAM),
Program Memory to onchip_memory_0 (ROM),
Data Memory to onchip_memory_1 (RAM).
Figure 18. Function and Module Settings
11. Click Next.
12. Click Generate.
13. When generation has completed, click Finish.
34
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
Exercise the
Custom Core
f
GettingGetting Started
The MegaWizard Plug-In generates a software example that can run on
the Nios embedded processor to exercise your bridge hardware. You can
compile the software example and upload it your hardware or use it in
simulation with the ModelSim simulation tool. The software example file,
pci32_nios_target.c, is created when you create a custom megafunction
and is in the <cpu instance name>_sdk\src directory.
For more information on the software example, see “Appendix C—The
Software Example” on page 113.
2
1.
Select Programs > Altera > Nios <version>> Nios SDK Shell. Change
to the <cpu instance name>_sdk\src directory.
2.
At the bash prompt type nb pci32_nios_target.cr
This generates an .srec file, which you can upload onto your
hardware.
To convert the .srec file into a file you can simulate, type the following
command at the bash prompt:
nios-convert --width=32 pci32_nios_target.srec
onchip_memory_0_lane0.datr
1
Simulate using
the Reference
Design
Altera provides reference designs—one that you can simulate in VHDL in
the ModelSim simulation tool, one in Verilog HDL that you can simulate
in the Visual IP software. The Nios system in the reference design has the
following attributes:
■
■
■
Altera Corporation
If you are using the Nios development kit version 2.1, type the
following command:
nios-convert --width=32 pci32_nios_target.srec
onchip_memory_0_lane0_chunk_4096.dat
20 Kbytes of ROM
2 Kbytes of RAM
A UART
35
Getting Started
To compile the software example and create an .srec file, perform the
following steps:
Getting Started
PCI32 Nios Target MegaCore Function User Guide
Walkthrough for ModelSim VHDL Simulator
This walkthrough uses the VHDL reference design. This walkthrough
takes you through all of the steps necessary to build an environment that
simulates the behavior of the PCI32 Nios Target MegaCore function and
Altera-provided reference design using the ModelSim PE, or SE VHDL
simulators.
f
Altera provides Visual IP models for all other Altera-supported VHDL
simulators. Refer to AN 169 (Simulating the PCI MegaCore Function
Behavioral Models) for more information.
1
This walkthrough assumes that you know how to use the
ModelSim PE or SE VHDL simulator.
Table 6 describes the files used in this walkthrough; the files are located in
the following directory:
<megacore path>:\pci32_nios_target\testbench\VHDL\example\.
Table 6. Files Used in ModelSim Walkthrough
File
Description
mstr_tranx.vhd
This file contains the master transactor code. The INITIALIZATION
section has the parameters set to simulate the reference design. The
USER COMMANDS section has the PCI commands that are executed during
simulation.
trgt_tranx.vhd
The file contains the target transactor code. The address_lines and
mem_hit_range settings are set to simulate the reference design.
trgt_tranx_mem_init.dat
This files is the memory initialization file for the target transactor.
altera_pci32_nios_target_tb.vhd
This top-level file instantiates the testbench module files, the wrapper file
that instantaites the PCI32 Nios Target MegaCore function, and the
reference design file. The idsel signal of the function is connected to
address bit 11 and the idsel signal of the target transactor is connected
to address bit 17.
pci_nios_top.vhd
Wrapper file that instantiates the Nios core and the PCI 32 Nios Target
Megacore function.
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PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
To execute the walkthrough, perform the following steps:
1.
Run the ModelSim software.
2.
Change your working directory, by typing the following command:
cd <megacore path>/sim_lib/modelsimr
3.
Type the following command in the simulator Console window:
2
do pci32_nios_target_vhdl_sim.tclr
a.
Choose the Simulations command (Options menu).
b.
Select the Assertions option.
c.
Turn off the Warnings option.
1
You can view and edit pci32_nios_target_vhdl_sim.tcl
to match a different design.
Walkthrough for Verilog HDL Simulators
Altera provides Visual IP models for all Altera-supported Verilog HDL
simulators. This walkthrough uses the Verilog HDL reference design and
the ModelSim simulation tool. This walkthrough takes you through all of
the steps necessary to build an environment that simulates the behavior of
the PCI32 Nios Target MegaCore function and Altera-provided reference
design using the Visual IP software.
To use this walkthrough, you should have installed the Visual IP software
version 4.3 or later on your PC.
Altera Corporation
1
This walkthrough assumes that you know how to use the
Visual IP software. For more information point your web
browser to
http://www.altera.com/products/ip/altera/visual_ip.html.
1
You must ensure the value of your PC’s environment variable
<VIP_MODELS_DIR> is set to <megacore path>:\sim_lib\vipmodels.
37
Getting Started
While the simulation is running, disable the warning assertion of the
ModelSim simulator, by performing the following steps:
Getting Started
PCI32 Nios Target MegaCore Function User Guide
Table 6 describes the files used in this walkthrough; the files are located in
the following directory:
<megacore path>:\pci32_nios_target\testbench\verilog\example\
Table 7. Files Used in Verilog HDL Simulator Walkthrough
File
Description
mstr_tranx.v
This file contains the master transactor code. The INITIALIZATION section has the
parameters set to simulate the reference design. The USER COMMANDS section has
the PCI commands that will be executed during simulation.
trgt_tranx.v
The file contains the target transactor code. The address_lines and
mem_hit_range settings are set to simulate the reference design.
trgt_tranx_mem_init.dat This files is the memory initialization file for the target transactor.
altera_tb.v
This top-level file instantiates the testbench module files, the wrapper file that
instantaites the PCI32 Nios Target MegaCore function, and the reference design file.
The idsel signal of the PCI32 nios target MegaCore function is connected to
address bit 29 and the idsel signal of the target transactor is connected to address
bit 30.
pci_nios_top.v
Wrapper file that instantiates the Nios core and the PCI 32 Nios Target Megacore
function.
To execute the walkthrough, perform the following steps:
1.
Run the ModelSim software.
2.
Change your working directory, by typing the following command:
cd <megacore path>
/pci32_nios_target/sim_lib/modelsimr
3.
Type the following command in the simulator Console window:
do pci32_nios_target_verilog_sim.tcl r
4.
38
Simulate altera_pci32_nios_target_tb.vhd and run the simulation
for 200 µs to see the PCI transactions with the reference design.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingGetting Started
2
Getting Started
Altera Corporation
39
Notes:
Specifications
Functional
Description
Figure 19 shows the PCI32 Nios Target MegaCore function block
diagram.
Figure 19. Block Diagram
32-bit PCI
Master/Target
Interface
DMA Engine
Host/Arbiter
1
Nios Soft
Core
Embedded
Processor
Nios
Target
Interface
Avalon Bus
Interrupt
Controller
PCI operation is a transfer initiated on the PCI bus. Nios
operation is defined by a transaction initiated on the Avalon bus
and is always through the DMA.
DMA Engine
The PCI32 Nios Target MegaCore function uses a DMA engine to control
transfers between the Nios soft core embedded processor and the PCI bus.
DMA operations are for direct data transfers between an internal first-in
first-out (FIFO) buffer and the PCI bus.
The DMA engine resumes broken transfers under the following
situations:
Altera Corporation
3
Memory Map &
Specifications
Registers
PCI Bus
Upstream/
Downstream
FIFO Buffers
41
Specifications
PCI32 Nios Target MegaCore Function User Guide
■
■
■
When the target sends a disconnect, with or without data
When the target attempts a a retry
When the latency expired time is reached
The number of resumes is set to 31. If this number exceeds 31, the
DMA_retry_timeout is set to 1. If the master abort or the target abort
occurs, the transfer is stopped and the register bit is set accordingly.
You can read the remaining number of transfers, by reading the TCR
register.
Read Cycles from External Memory on the PCI Bus
The PCI32 Nios Target MegaCore function acts as a PCI master on the PCI
bus to perform a data transfer from the PCI bus to Avalon bus (see
Figure 20). The core stores the data read in the downstream FIFO buffer.
The core sets the bits in the status register and generates an interrupt on
the Avalon bus to signal that the PCI transfer is complete. The size of the
downstream to upstream FIFO buffer is 16 double words (DWORDs). If
transfers larger than the FIFO are required, the transactions must be
repeated for the remaining data. Up to 16 DWORDs (64 bytes) can be
transferred with each transfer.
1
A DWORD is 32-bits.
Figure 20. PCI Master Read
Control
Control
Control
Control
Nios Soft
Core
Embedded
Processor
DMA Engine
Interrupt
32-bit PCI
Master/Target
Interface
PCI Bus
Data
42
Interrupt
Nios Target
Interface
Data
Downstream
FIFO Buffer
Data
Avalon Bus
Data
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingSpecifications
DMA Write Cycles to External Memory on PCI Bus
The PCI32 Nios Target MegaCore function acts as a PCI master on the PCI
bus to perform a data transfer from the Avalon bus to the PCI bus (see
Figure 21). The Avalon bus writes the data to be transferred to the
upstream FIFO buffer. Writing the command to the DMA triggers the core
to transfer the data by generating PCI write cycles. The core sets the bits
in the status register and generates an interrupt on the Avalon bus to
signal that the PCI transfer is complete. Up to 16 DWORDs can be
transferred with each transaction.
3
Specifications
Altera Corporation
43
Specifications
PCI32 Nios Target MegaCore Function User Guide
Figure 21. PCI Master Write
Control
Control
Control
Control
Nios Soft
Core
Embedded
Processor
DMA Engine
Interrupt
32-bit PCI
Master/Target
Interface
PCI Bus
Data
Interrupt
Nios
Target
Interface
Data
Upstream
FIFO Buffer
Data
Avalon Bus
Data
If transfers larger than the FIFO buffer are required, the data must be split
and the transaction must be repeated with the remaining data.
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
■
The current PCI master transaction finishes; no others occur.
The PCI32 Nios Target cannot write new values to the mailbox
The Avalon interrupt status register and PCI interrupt status register
timed_out bits indicate when the PCI32 Nios Target times out, see
the “Avalon Interrupt Status Register (AISR)” on page 55, and the
“PCI Interrupt Status Register (PISR)” on page 60.
A time limited PCI32 Nios Target runs for approximately 30 minutes for a
33 MHz Nios clock (5.940 × 10+10 clock cycles).
f
Parameters
For more information on OpenCore Plus hardware evaluation, see
“Appendix D—OpenCore Plus Evaluation” on page 117.
The PCI32 Nios Target MegaCore function’s features and options are
defined via parameters, which are set using the MegaWizard Plug-In.
Parameters allow customization of the PCI32 Nios Target MegaCore
function, thus, designers can meet specific application requirements. For
example, the parameters define read-only and read or write PCI
configuration space, as well as setup optional features specific to the
PCI32 Nios Target MegaCore function. When generating a MegaCore
instance via the wizard, parameters can be customized from default
settings to application-specific settings.
44
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Signals
Table 8 shows the PCI32 Nios Target MegaCore function’s global signals.
Table 8. Global Signals
Name
Type
Active
Description
avl_rst
Input
Low
Reset for the Nios soft core embedded processor.
avl_clk
Input
–
Avalon bus clock.
pci_rst
Input
Low
Reset for the PCI interface.
pci_clk
Input
–
PCI bus clock.
timed_out
Output
High
Timed-out signal. Indicates when the core has timed out with
the OpenCore Plus evaluation license (OpenCore Plus
hardware evaluation only).
PCI Bus Signals
The following PCI signals are used by the PCI32 Nios Target MegaCore
function:
■
Altera Corporation
Input—Standard input-only signal.
Output—Standard output-only signal.
Bidirectional—Tri-state input/output signal.
Sustained tri-state (STS)—Signal that is driven by one agent at a time
(e.g., device or host operating on the PCI bus). An agent that drives a
sustained tri-state pin low must actively drive it high for one clock
cycle before tri-stating it. Another agent cannot drive a sustained
tri-state signal any sooner than one clock cycle after it is released by
the previous agent.
Open-drain—Signal that is wire-ORed with other agents. The signaling
agent asserts the open-drain signal, and a weak pull-up resistor
deasserts the open-drain signal. The pull-up resistor may require two
or three PCI bus clock cycles to restore the open-drain signal to its
inactive state.
45
3
Specifications
■
■
■
■
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 9 summarizes the PCI bus signals that provide the interface
between the PCI32 Nios Target MegaCore function and the PCI bus.
Table 9. PCI Interface Signals (Part 1 of 2)
Name
Type
Active
Description
clk
Input
–
Clock. The clk input provides the reference signal for all other
PCI interface signals, except rstn and intan.
rstn
Input
Low
Reset. The rstn input initializes the PCI interface circuitry and
can be asserted asynchronously to the PCI bus clk edge.
When active, the PCI output signals are tri-stated and the
open-drain signals, such as serrn, float.
gntn
Input
Low
Grant. The gntn input indicates to the PCI bus master device
that it has control of the PCI bus. Every master device has a
pair of arbitration lines (gntn and reqn) that connect directly
to the arbiter.
reqn
Output
Low
Request. The reqn output indicates to the arbiter that the PCI
bus master wants to gain control of the PCI bus to perform a
transaction.
ad[31:0]
Tri-State
–
Address/data bus. The ad[31:0] bus is a time-multiplexed
address/data bus; each bus transaction consists of an address
phase followed by one or more data phases. The data phases
occur when irdyn and trdyn are both asserted.
cben[3:0]
Tri-State
Low
Command/byte enable. The cben[3:0] bus is a timemultiplexed command/byte enable bus. During the address
phase, this bus indicates the command; during the data phase,
this bus indicates byte enables.
par
Tri-State
–
Parity. The par signal is even parity across the 32 least
significant address/data bits and four least significant
command/byte enable bits. In other words, the number of 1s on
ad[31:0], cben[3:0], and par equal an even number. The
parity of a data phase is presented on the bus on the clock
following the data phase.
idsel
Input
High
Initialization device select. The idsel input is a chip select for
configuration transactions.
framen
STS
Low
Frame. The framen signal is an output from the current bus
master that indicates the beginning and duration of a bus
operation. When framen is initially asserted, the address and
command signals are present on the ad and cben buses. The
framen signal remains asserted during the data operation and
is deasserted to identify the end of a transaction.
46
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Table 9. PCI Interface Signals (Part 2 of 2)
Name
Type
Active
Description
STS
Low
Initiator ready. The irdyn signal is an output from a bus
master to its target and indicates that the bus master can
complete the current data transaction. In a write transaction,
irdyn indicates that the address bus has valid data. In a read
transaction, irdyn indicates that the master is ready to accept
data.
devseln
STS
Low
Device select. Target asserts devseln to indicate that the
target has decoded its own address and accepts the
transaction.
trdyn
STS
Low
Target ready. The trdyn signal is a target output, indicating
that the target can complete the current data transaction. In a
read operation, trdyn indicates that the target is providing
valid data on the address bus. In a write operation, trdyn
indicates that the target is ready to accept data.
stopn
STS
Low
Stop. The stopn signal is a target device request that indicates
to the bus master to terminate the current transaction. The
stopn signal is used in conjunction with trdyn and devseln
to indicate the type of termination initiated by the target.
perrn
STS
Low
Parity error. The perrn signal indicates a data parity error. The
perrn signal is asserted one clock following the par and
par64 signals or two clocks following a data phase with a
parity error. The PCI functions assert the perrn signal if a
parity error is detected on the par signal and the perrn bit (bit
6) in the command register is set.
serrn
Open-Drain Low
System error. The serrn signal indicates system error and
address parity error. The PCI functions assert serrn if a parity
error is detected during an address phase and the serrn
enable bit (bit 8) in the command register is set.
intan
Open-Drain Low
Interrupt A. The intan signal is an active-low interrupt to the
host and must be used for any single-function device requiring
an interrupt capability. The PCI32 Nios Target MegaCore
function asserts intan only when the local side asserts the
lirqn signal.
Altera Corporation
47
3
Specifications
irdyn
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 10 shows the host interface signals.
Table 10. Host Interface Signals
Name
Type
Active
Description
host_gnt[15:0] Output
Low
Grant signal. Te master asserts host_gnt to grant access to
the PCI bus.
host_req[15:0] Input
Low
Request signal. The master asserts host_req to gain access
to the PCI bus.
host_inta
Input
Low
Interrupt pin A. This interrupt is passed to the Nios soft core
embedded processor.
host_intb
Input
Low
Interrupt pin B. This interrupt is passed to the Nios soft core
embedded processor.
host_intc
Input
Low
Interrupt pin C. This interrupt is passed to the Nios soft core
embedded processor.
host_intd
Input
Low
Interrupt pin D. This interrupt is passed to the Nios soft core
embedded processor.
Avalon Bus Signals
Table 9 summarizes the Avalon bus signals that provide the interface
between the PCI32 Nios Target MegaCore function and the Avalon bus.
The PCI32 Nios Target MegaCore function is a peripheral on the Avalon
bus—it is a slave or target on the Avalon bus with the Nios soft core as the
master. All control signals are generated by the Nios soft core, except the
wait_from_the_<peripheral>, which is generated by the peripheral to
force wait states on the Avalon bus while it gets the data ready and the
irq_from_the_<peripheral>.
48
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
1
The varaible <peripheral> is the name the wizard gives to the
PCI32 Nios Target MegaCore function when you add it to the
Nios system module.
Table 11. Avalon Bus Signals
Name
Type
Active
Description
Input
High
Peripheral select signal from the Nios soft
core to the PCI32 Nios Target MegaCore
function. Enables peripheral.
readn_to_the_<peripheral>
Input
Low
Read enable from the Nios soft core to the
PCI32 Nios Target MegaCore function.
writen_to_the_<peripheral>
Input
Low
Write enable from the Nios soft core to the
PCI32 Nios Target MegaCore function.
byteenablen_to_the_<peripheral>[3:0]
Input
Low
Byte enables from the Nios soft core to the
PCI32 Nios Target MegaCore function.
Selects which bytes are active on the
Avalon bus for this transaction.
wait_from_the_<peripheral>
Output
High
Wait signal that generates wait states on
the Avalon bus, so the peripheral has
extra time to access and present data.
irq_from_the_<peripheral>
Output
High
Interrupt from the PCI32 Nios Target
MegaCore function to the Nios soft core,
which generates an interrupt to the Nios
soft core, if interrupts are enabled in the
PCI32 Nios Target MegaCore Function.
readdata_from_the_<peripheral>[31:0]
Output
High
Data from the PCI32 Nios Target
MegaCore Function to the Nios soft core.
writedata_to_the_<peripheral>[31:0]
Input
High
Data from the Nios soft core to the PCI32
Nios Target MegaCore function.
address_to_the_<peripheral>[8:0]
Output
High
Address for read or write operations from
the Nios soft core to the PCI32 Nios Target
MegaCore function.
Altera Corporation
49
3
Specifications
chipselect_to_the_<peripheral>
Specifications
PCI32 Nios Target MegaCore Function User Guide
Memory Map
BAR0 of the core configuration register is reserved for the memorymapped registers (internal registers and the DMA descriptor FIFO buffer).
Table 12 shows the address map for BAR0.
Table 12. Address Maps for BAR0
PCI Address Offset
Registers
Local Address Offset
Address Description
000h-0FFh
100h-1FFh
Nios Target configuration registers.
100h-1FFh
200h-2FFh
Messaging registers.
200h-2FFh
300h-3FFh
DMA registers.
300h-4FFh
400h-5FFh
Host configuration registers.
The registers control the behavior of a particular transaction in master
mode or in target mode operations. The registers can be accessed by the
Avalon bus and the PCI bus. Figure 22 shows the control registers.
Figure 22. Control Registers
Write
PCI Bus
PCI Master
Target 32 bit
Read
Control
Registers
Read
Nios
Target
Interface
Nios Soft
Core
Embedded
Processor
Avalon Bus
DMA Engine
The following information is stored in the control registers:
■
■
■
■
■
50
Bridge configuration and status
PCI transaction starting address
Amount of data to be transferred on to the PCI
Type of transaction to be initiated on the PCI bus
–
I/O
–
Memory
–
Configuration
Direction of the PCI transaction
–
Read
–
Write
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Table 13 shows the abbreviations that are used for the register attributes.
Table 13. Register Abbreviations
Abbreviation
Description
RW
Read/ write.
RO
Read only.
WO
Write only.
RC
Read only. Read clears the bits.
W1S
Write 1 set. Writing 1 sets the bit, writing 0 has no effect.
W1C
Write. Writing 1 clears the bit.
Table 14 shows the registers.
Table 14. Register Map
PCI Offset
Avalon Offset
Clock Domain
Mnemonic
Description
208h
PCI
MR0
Mailbox register 0—Avalon to PCI
bus.
10Ch
20Ch
Avalon
MR1
Mailbox register 1—PCI to Avalon
bus.
–
210h
Avalon
AICR
Avalon interrupt control register.
–
214h
Avalon
AISR
Avalon interrupt status register.
–
218h
PCI
PICR
PCI interrupt control register.
21Ch
PCI
PISR
PCI interrupt status register.
–
304h
PCI
PAR
PCI address register.
–
30Ch
PCI
TCR
Transfer count register.
–
0h
Avalon
DRU and DRD
FIFO entry.
–
04h
PCI
PCR
PCI command register.
11Ch-11Fh
Altera Corporation
3
Specifications
108h
51
Specifications
PCI32 Nios Target MegaCore Function User Guide
Messaging Registers
The core contains two 32-bit mailbox registers for passing on messages
between the Avalon and PCI bus. MR0 passes messages from the Avalon
to the PCI bus and generates PCI interrupts (if PCI interrupts are enabled);
MR1 passes messages from the PCI to the Avalon bus and generates
Avalon interrupts (if Avalon interrupts are enabled). Table 15 shows the
messaging registers.
Table 15. Messaging Registers
PCI Offset
–
Avalon Offset
Clock Domain
Mnemonic
–
–
200h-207h
Description
Reserved
108h
208h
PCI
MR0
Mailbox register 0—Avalon to PCI bus.
10Ch
20Ch
PCI
MR1
Mailbox register 1—PCI to Avalon bus.
–
210h
Avalon
AICR
Avalon interrupt control register.
–
214h
Avalon
AISR
Avalon interrupt status register.
–
218h
PCI
PICR
PCI interrupt control register.
21Ch
PCI
11Ch-11Fh
–
220h-2FFh
PCI interrupt status register.
PISR
–
–
Reserved.
Mailbox Register 0—Avalon to PCI Interface (MR0)
The mailbox register 0—Avalon to PCI (MR0) can be used to pass
command and status information from the Avalon to the PCI bus.
The Avalon interface can write to the mailbox register 0, then an interrupt
on the PCI interface is generated (if PCI interrupts are enabled). Table 16
shows the mailbox register 0.
Table 16. Mailbox Register 0 (MR0)
Data Bit
31: 0
Mnemonic PCI Attribute
MAIL0
RC
Avalon Attribute
W1S
Default
0
Definition
32-bit mailbox register 0.
Mailbox Register 1—PCI to Avalon Interface (MR1)
The mailbox register 1—PCI to Avalon (MR1) passes command and status
information from the PCI to the Avalon bus.
52
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The PCI interface can write to the mailbox register 1, then an interrupt on
the Avalon bus is generated (if enabled). Table 17 shows the mailbox
register 1.
Table 17. Mailbox Register 1 (MR1)
Data Bit
31: 0
Mnemonic PCI Attribute
MAIL1
W1S
Avalon Attribute
RC
Default
0
Definition
32-bit mailbox register 1.
3
Specifications
Altera Corporation
53
Specifications
PCI32 Nios Target MegaCore Function User Guide
Avalon Interrupt Control Register (AICR)
The Avalon interrupt control register (AICR) controls the assertion of PCI
and Avalon interrupts. The AICR provides all interrupt status signals to
the interrupt handler. Any master on the PCI or Avalon bus can access the
AICR. Table 18 shows the Avalon interrupt control register.
Table 18. Avalon Interrupt Control Register (AICR)
Data Bit
0
Mnemonic
PCI
Attribute
–
–
Avalon
Attribute
Default
–
Definition
Reserved.
1
Avalon_int_en
–
RW
0
Avalon interrupt enable. When set to
1 interrupts to the Avalon bus can be
individually controlled; when 0 all
interrupts to the Avalon bus are
disabled.
2
Avalon_MB_int_en
–
RW
0
Mailbox interrupt enable. A 1
enables the generation of the
Avalon interrupt, when the PCI bus
writes to the mailbox register 0 and
1. A 0 disables the generation of the
Avalon interrupt.
5:3
–
–
–
Reserved.
6
Avalon_ERR_int_en
–
RW
0
Avalon error interrupt enable. A 1
enables the generation of the
Avalon interrupt, when any Avalon
error occurs during the transaction
defined by the AvalonERR_pend
status bit in the AISR. A 0 disables
the generation of the Avalon
interrupt.
7
Avalon_DMA_int_en
–
RW
0
Avalon DMA interrupt enable. A 1
enables the generation of DMA
terminal count interrupts on the
Avalon bus. A 0 disables the
generation of the DMA interrupts on
the Avalon bus.
8
Avalon_Host_int_en
–
RW
1
Host interrupt enable (PCI interface
interrupt). A 1 enables the
generation of the hosts interrupts. A
0 disables the generation of the
hosts interrupts.
31:9
54
–
–
–
–
Reserved.
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Avalon Interrupt Status Register (AISR)
The Avalon interrupt status register (AISR) indicates the status of the
Avalon interrupts. The AISR provides all interrupt status signals to the
interrupt handler. If the Avalon interrupt is asserted the interrupt handler
must read this address to find the source of the interrupt. Table 19 shows
the AISR.
Table 19. Avalon Interrupt Status Register (AISR) (Part 1 of 4)
Data
Bit
Mnemonic
PCI
Attribute
Avalon
Attribute
Default
Definition
AvalonINT_pend
–
W1C
0
Avalon interrupt pending. A 1
indicates that the Avalon
interrupt is active.
1
AMBINT_pend
–
W1C
0
Avalon mailbox interrupt
pending. A 1 indicates that the
Avalon interrupt is active.
2
ADMATC_pend
–
W1C
0
DMA terminal count interrupt
pending. A 1 when the DMA tc
interrupt is active on the Avalon
interface. Active when DMA_tc is
high.
3
AvalonERR_pend
–
W1C
0
Avalon error pending. A 1
indicates that an error has
occurred during the Avalon
transfer. The error is shown on
one or several pins 28:18. A 0
indicates that no Avalon error is
pending to be processed.
6:4
–
–
–
–
Reserved.
7
Arbiter_present
–
RO
1
Arbiter present. A 1 indicates
that an arbiter is present in the
code; A 0 indicates that no
arbiter is present
8
Host_intA_pend
–
W1C
0
Host interrupt #A pending. A 1
indicates that the host receives
an interrupt on channel #A.
9
Host_intB_pend
–
W1C
0
Host Interrupt #B pending. A 1
indicates that the host receives
an interrupt on channel #B.
10
Host_intC_pend
–
W1C
0
Host interrupt #C pending. A 1
indicates that the host receives
an interrupt on channel #C.
Altera Corporation
55
3
Specifications
0
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 19. Avalon Interrupt Status Register (AISR) (Part 2 of 4)
Data
Bit
Mnemonic
PCI
Attribute
Avalon
Attribute
Default
11
Host_intD_pend
–
W1C
12
ocp_core
–
RO
–
OpenCore Plus status:
0 = non-time limited core
1 = time limited core.
13
timed_out
–
RO
–
For OpenCore Plus hardware
evaluation:
0 = Core is active
1 = Core has timed out, transfers
are disabled.
For non-time limited cores
timed_out = 0.
14
Transfer_type
–
W1C
0
Command transfer type.
1 = write (upstream);
0 = read (downstream).
15
Master_disc_data
–
W1C
0
A PCI master transaction from
the core was disconnected,
which triggers an interrupt error if
it is enabled.
1 = disconnected;
0 = normal operation.
16
Master_disc_no_data
–
W1C
0
Master was disconnected
without data, which triggers an
interrupt error if it is enabled.
1 = disconnected;
0 = normal operation.
17
Master_timeout
–
W1C
0
Master was timed out, which
triggers an interrupt error if it is
enabled.
1 = timed out;
0 = normal operation.
18
Master_invalid_cmd
–
W1C
0
Master was not properly
configured, which triggers an
interrupt error if it is enabled.
1 = incorrect read;
0 = normal operation. (1)
56
0
Definition
Host interrupt #D pending. A 1
indicates that the host receives
an interrupt on channel #D.
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Table 19. Avalon Interrupt Status Register (AISR) (Part 3 of 4)
Data
Bit
19
Mnemonic
Avalon_addr_error
20
21
–
Up_fifo_overflow
22
23
DMA_retry_timeout
–
Avalon
Attribute
W1C
–
–
–
0
–
W1C
–
–
Default
W1C
Avalon was addressed on an
empty register, which triggers an
interrupt error if it is enabled.
1 = incorrect access;
0 = normal operation.
–
0
–
W1C
0
Reserved.
Upstream FIFO buffer overflow,
which triggers an interrupt error if
it is enabled.
1 = overflow;
0 = normal operation.
–
0
Definition
Reserved.
Downstream FIFO buffer
overflow, which triggers an
interrupt error if it is enabled.
1 = overflow;
0 = normal operation.
3
DMA retry timeout. A 1 indicates
that the DMA transfer has been
broken too many times (more
than 31) and the DMA engine
has given up on the transaction.
0 = normal operation.
25
Master_Abort
–
W1C
0
The PCI master has aborted the
transaction, which triggers an
interrupt error if it is enabled.
1 = abort occurred;
0 = normal operation.
26
Target_Abort
–
W1C
0
The PCI target has aborted the
transaction, which triggers an
interrupt error if it is enabled.
1 = abort occurred;
0 = normal operation.
27
System_error
–
W1C
0
The PCI core has signaled a
system error, which triggers an
interrupt error if it is enabled.
1 = system error occurred;
0 = normal operation.
Altera Corporation
57
Specifications
24
–
Down_fifo_ overflow
PCI
Attribute
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 19. Avalon Interrupt Status Register (AISR) (Part 4 of 4)
Data
Bit
Mnemonic
PCI
Attribute
Avalon
Attribute
Default
Definition
28
Parity_error
–
W1C
0
The PCI core has signaled a
parity error, which triggers an
interrupt error if it is enabled.
1 = parity error occurred;
0 = normal operation.
29
PCI_retry
–
W1C
0
The PCI core has signaled a
retry.
1 = retry has occurred;
0 = normal operation. (2)
30
Avalon_latency_expired
–
W1C
0
Avalon bus timer expired.
1 = timer has expired;
0 = normal operation. (3)
31
–
–
–
–
Reserved.
Notes:
(1)
(2)
(3)
58
Typically the TCR was not set, or no data was written into the FIFO buffer.
This bit is for information only, the retry is automatically executed by the DMA controller.
The timer prevents a deadlock, in case the core refuses to release the Avalon bus
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PCI Interrupt Control Register (PICR)
The PCI interrupt control register (PICR) controls the assertion of the PCI
and Avalon interrupts. Any master on PCI or the Avalon interface can
access the PICR. Table 20 shows the PICR.
Table 20. PCI Interrupt Control Register (PICR)
Data
Bit
0
3:1
4
6
7
31:8
PCI_int_en
PCI
Attribute
RO
–
APMB_int_en
PCIERR_int_en
–
Altera Corporation
RW
Default
0
–
RO
0
RW
–
RO
–
–
PCI error interrupt enable. When 1,
enables the generation of the PCI interrupt
when any PCI error occurred during the
transaction defined by the PCIERR_pend
status bit in the PISR; when 0, disables the
generation of the PCI interrupt.
–
0
–
Reserved.
Avalon-PCI mailbox interrupt enable.
When 1, enables the generation of the PCI
interrupt, when written a non-zero value in
mailbox register; when 0, disables the
generation of the PCI interrupt.
0
RW
Definition
PCI interrupt enable. When 1, enables the
generation of the PCI interrupt; when 0,
disables the generation of the PCI
interrupt.
–
RW
RO
–
PDMA_int_en
Avalon
Attribute
Reserved.
PCI DMA interrupt enable. When 1,
enables the generation of DMA interrupts
on PCI; when 0, disables the generation of
DMA interrupts on PCI.
–
Reserved.
59
3
Specifications
5
Mnemonic
Specifications
PCI32 Nios Target MegaCore Function User Guide
PCI Interrupt Status Register (PISR)
The PCI interrupt status register (PISR) controls the assertion of PCI and
Avalon interrupts. The PISR provides all interrupt status signals to the
interrupt handler. Any master using the PCI or the Avalon interface can
access the PISR. Table 21 shows the PISR.
Table 21. PCI Interrupt Status Register (PISR) (Part 1 of 3)
Data
Bit
Mnemonic
PCI
Attribute
Avalon
Attribute
Default
Definition
0
PCIINT_pend
W1C
RO
0
PCI interrupt pending.
1 = PCI interrupt is active;
0 = interrupt is inactive
1
PMBINT_pend
W1C
RO
0
PCI mailbox interrupt pending.
1 = PCI mailbox Interrupt is
active.
2
PDMAINT_pend
W1C
RO
0
PCI DMA TC interrupt pending.
1 = DMA interrupt is active.
Active when DMA_tc is high.
3
PCIERR_pend
W1C
RO
0
PCI error pending. When 1, an
error has occurred during the
PCI transfer; the interrupt
handler must read the PCI
configuration status register
and clear the appropriate bits.
Any one of the following PCI
status register bits can assert
this bit: mstr_abrt,
tar_abrt, and
det_par_err.
When 0, no PCI error is pending
to be processed.
11 :4
–
–
Reserved.
12
ocp_core
W1C
–
–
OpenCore Plus status:
0 = non-time limited core
1 = time limited core.
13
timed_out
W1C
–
–
For OpenCore Plus hardware
evaluation:
0 = Core is active
1 = Core has timed out,
transfers are disabled.
For non-time limited cores
timed_out = 0.
60
–
–
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Table 21. PCI Interrupt Status Register (PISR) (Part 2 of 3)
Data
Bit
Mnemonic
PCI
Attribute
Avalon
Attribute
Default
Definition
14
Transfer_type
W1C
RO
0
Command transfer type.
1 = write (Avalon);
0 = read (PCI).
15
Master_disc_data
W1C
RO
0
Master was disconnected with
data.
1 = disconnected;
0 = normal operation.
16
Master_disc_no_data
W1C
RO
0
Master was disconnected
without data.
1 = disconnected;
0 = normal operation.
17
Master_timeout
W1C
RO
0
Master was timed out.
1 = timed out;
0 = normal operation.
18
Master_invalid_cmd
W1C
RO
0
Master was not properly
configured.
1 = incorrect read;
0 = normal operation.
19
Avalon_addr_error
W1C
RO
0
Avalon was addressed on an
empty register.
1 = incorrect access;
0 = normal operation.
20
Avalon_wr_err
W1C
RO
0
Avalon had read access when
the core was not ready.
1 = incorrect access;
0 = normal operation.
21
Up_fifo_overflow
W1C
RO
0
Avalon FIFO buffer overflow.
1 = overflow;
0 = normal operation.
23
–
Down_fifo_ overflow
Altera Corporation
–
W1C
–
RO
–
0
Specifications
22
3
Reserved.
PCI FIFO buffer overflow.
1 = overflow;
0 = normal operation.
61
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 21. PCI Interrupt Status Register (PISR) (Part 3 of 3)
Data
Bit
Mnemonic
24
DMA_retry_timeout
25
Master_Abort
26
PCI
Attribute
–
Avalon
Attribute
Default
Definition
W1C
0
DMA retry timeout. A 1
indicates that the DMA transfer
has been broken too many
times (more than 31) and the
DMA engine has given up on
the transaction.
W1C
RO
0
PCI master has aborted the
transaction.
1 = abort occurred;
0 = normal operation.
Target_Abort
W1C
RO
0
PCI target has aborted the
transaction.
1 = Abort occurred;
0 = normal operation.
27
System_error
W1C
RO
0
PCI core has signaled a system
error.
1 = System error occurred;
0 = normal operation.
28
Parity_error
W1C
RO
0
PCI core has signaled a parity
error.
1 = parity error occurred;
0 = normal operation.
29
PCI_retry
W1C
RO
0
PCI core has signalled a retry.
1 = retry has occurred;
0 = normal operation.
30
Avalon_latency_expired
W1C
RO
0
Avalon bus timer expired.
1 = timer has expired;
0 = normal operation.
0 = normal operation.
31
62
–
–
–
–
Reserved.
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PCI32 Nios Target MegaCore Function User Guide
DMA Registers
Table 22 shows the DMA registers.
Table 22. DMA Registers
PCI Offset
Avalon Offset
Clock Domain
–
300h
PCI
–
304h
PCI
–
308h
–
30Ch
–
310h-3FFh
Mnemonic
Description
Reserved.
PAR
–
PCI
PCI address register.
Reserved.
TCR
–
Transfer count register.
Reserved.
PCI Address Register (PAR)
The PCI address register (PAR) is a 32-bit register, which contains the
address of the current PCI transfer initiated by the DMA engine. The
register is incremented after every data phase on the PCI bus to keep track
of the transfer address.
When setting up the DMA register the PAR must be written last. Table 23
shows the PAR.
Table 23. PCI Address Register (PAR)
Data Bit Mnemonic PCI Attribute
31:0
PAR
Altera Corporation
–
Avalon Attribute
RW
Default
0
Definition
32-bit counter. The DMA increments
this register. The Avalon interface can
only set the base value.
63
Specifications
The PCI bus memory transfer initiated by the DMA engine must begin at
a DWORD boundary.
3
Specifications
PCI32 Nios Target MegaCore Function User Guide
Transfer Count Register (TCR)
The transfer count register (TCR) holds the byte count for the current PCI
transfer. It decrements by 4 DWORDs after every data transfer on the PCI
bus. The TCR is a 17-bit register. Table 24 shows the TCR.
Table 24. Transfer Count Register (TCR)
Data Bit
Mnemonic
1:0
BCR
16:2
BCR
31:17
PCI
Attribute
–
Avalon
Attribute
–
RO
–
RW
–
Default
0
GND.
0
–
Definition
14-bit down counter.
–
Reserved.
Data Register
Table 25 shows the data register.
Table 25. Data Register
PCI Offset
–
Avalon Offset
0h
Clock Domain
Avalon
Mnemonic
Description
DRU and DRD FIFO entry.
Data Register (DRU and DRD)
The data register is a view of the data port. All data is written to that port
and then stored in the FIFO buffer. Table 26 shows the data register (DRU
and DRD).
Table 26. Data Register (DRU and DRD)
Data Bit
31:0
64
Mnemonic
Data
PCI
Attribute
–
Avalon
Attribute
WO/RO
Default
Unknown
Definition
Data in/out.
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PCI32 Nios Target MegaCore Function User Guide
PCI Command Registers
Table 27 shows the PCI command registers.
Table 27. PCI Command Register
PCI Offset
Avalon Offset
–
04h
–
08h-FFh
Clock Domain
PCI
Mnemonic
Description
PCI command register.
PCR
–
Reserved.
The PCI command register holds the command to be processed, including
the PCI command.
PCI Command Register (PCR)
Table 28 shows the PCI command register (PCR).
3
Table 28. PCI Command Register (PCR)
03:00
Mnemonic
11:08
–
Data
07:04
–
Byte_en
31:12
Altera Corporation
PCI
Attribute
–
Avalon
Attribute
RW
–
–
–
Default
0
Specifications
Data Bit
Definition
PCI command.
–
–
–
–
RW
Reserved.
Byte mask.
Reserved.
65
Specifications
PCI Interface
PCI32 Nios Target MegaCore Function User Guide
This section describes the PCI interface specifications, including the
supported PCI configuration registers and bus commands.
1
For the registers that are set in the MegaWizard Plug-In see
“Configure the PCI32 Nios Target MegaCore Function” on page
28.
PCI Bus Commands
Table 29 shows the PCI bus commands that can be initiated or responded
to by the PCI32 Nios Target MegaCore function.
Table 29. PCI Bus Command Support Summary
cben[3:0] Value
Bus Command Cycle
Master
Target
0000
Interrupt acknowledge
Ignored
No
0001
Special cycle
Ignored
Ignored
0010
I/O read
Yes
Yes
0011
I/O write
Yes
Yes
0100
Reserved
Ignored
Ignored
0101
Reserved
Ignored
Ignored
0110
Memory read
Yes
Yes
0111
Memory write
Yes
Yes
1000
Reserved
Ignored
Ignored
1001
Reserved
Ignored
Ignored
1010
Configuration read
Yes
Yes
1011
Configuration write
Yes
Yes
1100
Memory read multiple (1)
Yes
Yes
1101
Dual address cycle (DAC)
No
No
1110
Memory read line (1)
No
Yes
1111
Memory write and invalidate (1)
No
Yes
Note:
(1)
The memory read multiple and memory read line commands are treated as
memory reads. The memory write and invalidate command is treated as a memory
write. The local side sees the exact command on the l_cmdo[3:0] bus with the
encoding shown in Table 29.
During the address phase of a transaction, the cben[3:0] bus is used to
indicate the transaction type. See Table 29.
The PCI32 Nios Target MegaCore function’s PCI interface responds to
standard memory read/write, cache memory read/write, and
configuration read/write commands.
66
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PCI32 Nios Target MegaCore Function User Guide
In master mode, the core can initiate transactions of standard memory
read/write, I/O read/write, and configuration read/write commands.
Additionally, it is the responsibility of the local-side interface to ensure
that proper address and byte enable combinations are used during I/O
read/write cycles.
PCI Configuration Registers
Each logical PCI bus device includes a block of 64 configuration DWORDs
reserved for the implementation of its configuration registers. The format
of the first 16 DWORDs is defined by the PCI Special Interest Group
(PCI SIG) PCI Local Bus Specification, Revision 2.2.
Table 30 shows the defined 64-byte configuration space. The registers
within this range are used to identify the device, control PCI bus
functions, and provide PCI bus status. The shaded areas indicate registers
that are supported by the PCI32 Nios Target MegaCore function.
Table 30. PCI Bus Configuration Registers
Byte
3
2
0
00
Device ID
Vendor ID
04
Status Register
Command Register
08
0C
Class Code
BIST
Header Type
Revision ID
Latency Timer
10
Base Address Register 0
14
Base Address Register 1
18
Base Address Register 2
1C
Base Address Register 3
20
Base Address Register 4
24
Base Address Register 5
28
2C
Subsystem Vendor ID
Expansion ROM Base Address Register
34
Reserved
38
3C
Cache Line Size
Card Bus CIS Pointer
Subsystem ID
30
Altera Corporation
1
Specifications
Address
(h)
3
Capabilities
Pointer
Reserved
Maximum
Latency
Minimum Grant
Interrupt Pin
Interrupt Line
67
Specifications
PCI32 Nios Target MegaCore Function User Guide
Table 31 summarizes the supported configuration registers. Unused
registers produce a zero when read, and they ignore a write operation.
Read/write refers to the status at runtime, i.e., from the perspective of
other PCI bus agents. Designers can set some of the read-only registers
when creating a custom PCI design by setting the MegaCore function
parameters through the MegaWizard Plug-In. For example, the designer
can change the device ID register value from the default value through the
MegaWizard Plug-In. The specified default state is defined as the state of
the register when the PCI bus is reset.
Table 31. Supported Configuration Registers Address Map
Address Offset
(h)
Range
Reserved (h)
Bytes
Used/Reserved
Read/Write
Mnemonic
Register Name
00
00-01
2/2
Read
ven_id
Vendor ID.
02
02-03
2/2
Read
dev_id
Device ID.
04
04-05
2/2
Read
comd
Command.
06
06-07
2/2
Read
status
Status.
08
08-08
1/1
Read
rev_id
Revision ID.
09
09-0B
3/3
Read
class
Class code.
0D
0D-0D
1/1
Read
lat_tmr
Latency timer.
0E
0E-0E
1/1
Read
header
Header type.
10
10-13
4/4
Read/write
bar0
Base address register
zero.
2C
2C-2D
2/2
Read
sub_ven_id Subsystem vendor ID.
2E
2E-2F
2/2
Read
sub_id
Subsystem ID.
3C
3C-3C
1/1
Read
int_ln
Interrupt line.
3D
3D-3D
1/1
Read
int_pin
Interrupt pin.
3E
3E-3E
1/1
Read/write
min_gnt
Minimum grant.
3F
3F-3F
1/1
Read/write
max_lat
Maximum latency.
Vendor ID Register
Vendor ID is a 16-bit read-only register that identifies the manufacturer of
the device. The value of this register is assigned by the PCI SIG; the default
value of this register is the Altera vendor ID value, which is 1172 H.
However, you can change the value of the vendor ID register to your PCI
SIG-assigned vendor ID value. See Table 32.
68
Altera Corporation
GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Table 32. Vendor ID Register Format
Data Bit
Mnemonic
Read/Write
15:0
ven_id
Read
Device ID Register
Device ID is a 16-bit read-only register that identifies the device. The value
of this register is assigned by the manufacturer (e.g., Altera for the PCI32
Nios Target MegaCore function). See Table 33.
Table 33. Device ID Register Format
Data Bit
Mnemonic
Read/Write
15:0
dev_id
Read
Command Register
Table 34. Command Register Format
Data
Bit
Mnemonic
Read/Write
Definition
0
io_ena
Read/write
I/O access enable. When high, io_ena lets the function respond to the PCI
bus I/O accesses as a target.
1
mem_ena
Read/write
Memory access enable. When high, mem_ena lets the function respond to
the PCI bus memory accesses as a target.
2
mstr_ena
Read/write
Master enable. When high, mstr_ena allows the function to request
mastership of the PCI bus. Bit 2 is hardwired to "1" when PCI master host
bridge options are enabled through the MegaWizard Plug-In.
3
Unused
–
–
5:4
Unused
–
–
6
perr_ena
Read/write
Parity error enable. When high, perr_ena enables the function to report
parity errors via the perrn output.
7
Unused
–
–
8
serr_ena
Read/write
System error enable. When high, serr_ena allows the function to report
address parity errors via the serrn output. However, to signal a system
error, the perr_ena bit must also be high.
15:9
Unused
–
–
Altera Corporation
69
3
Specifications
Command is a 16-bit read/write register that provides basic control over
the ability of the PCI function to respond to the PCI bus and/or access it.
See Table 34.
Specifications
PCI32 Nios Target MegaCore Function User Guide
Status Register
Status is a 16-bit register that provides the status of bus-related events.
Read transactions from the status register behave normally. However,
write transactions are different from typical write transactions because
bits in the status register can be cleared but not set. A bit in the status
register is cleared by writing a logic one to that bit. For example, writing
the value 4000 H to the status register clears bit 14 and leaves the rest of
the bits unchanged. The default value of the status register is 0400 H. See
Table 35.
70
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GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Table 35. Status Register Format
Data
Bit
Mnemonic
Read/Write
Definition
Unused
–
Reserved.
7:4
Unused
–
Reserved.
8
dat_par_rep
Read/write
Reported data parity. When high, dat_par_rep indicates that during
a read transaction the function asserted the perrn output as a master
device, or that during a write transaction the perrn output was
asserted as a target device. This bit is high only when the perr_ena
bit (bit 6 of the command register) is also high. This signal is driven to
the local side on the stat_reg[0] output.
10:9
devsel_tim
Read
Device select timing. The devsel_tim bits indicate target access
timing of the function via the devseln output. The PCI32 Nios Target
MegaCore function is a slow target devices (i.e.,
devsel_tim = B"10").
11
tabort_sig
Read/write
Signaled target abort. This bit is set when a local peripheral device
terminates a transaction. The function automatically sets this bit if it
issued a target abort after the local side asserted lt_abortn. This bit
is driven to the local side on the stat_reg[1] output.
12
tar_abrt_rec
Read/write
Target abort. When high, tar_abrt_rec indicates that the function
in master mode has detected a target abort from the current target
device. This bit is driven to the local side on the stat_reg[2] output.
13
mstr_abrt
Read/write
Master abort. When high, mstr_abrt indicates that the function in
master mode has terminated the current transaction with a master
abort. This bit is driven to the local side on the stat_reg[3] output.
14
serr_set
Read/write
Signaled system error. When high, serr_set indicates that the
function drove the serrn output active, i.e., an address phase parity
error has occurred. The function signals a system error only if an
address phase parity error was detected and serr_ena was set. This
signal is driven to the local side on the stat_reg[4] output.
15
det_par_err
Read/write
Detected parity error. When high, det_par_err indicates that the
function detected either an address or data parity error. Even if parity
error reporting is disabled (via perr_ena), the function sets the
det_par_err bit. This signal is driven to the local side on the
stat_reg[5] output.
Altera Corporation
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3
Specifications
3:0
Specifications
PCI32 Nios Target MegaCore Function User Guide
Revision ID Register
Revision ID is an 8-bit read-only register that identifies the revision
number of the device. The value of this register is assigned by the
manufacturer. See Table 36.
Table 36. Revision ID Register Format
Data Bit
Mnemonic
Read/Write
7:0
rev_id
Read
Class Code Register
Class code is a 24-bit read-only register divided into three sub-registers:
base class, sub-class, and programming interface. Refer to the PCI Local
Bus Specification, Revision 2.2 for detailed bit information. See Table 37.
Table 37. Class Code Register Format
Data Bit
Mnemonic
Read/Write
23:0
class
Read
Subsystem Vendor ID & Subsystem ID Register
Subsystem vendor ID and subsystem ID registers are used to uniquely
identify the expansion board or subsystem where the PCI device resides.
Subsystem vendor ID is a 16-bit read-only register that identifies add-in
cards from different vendors that have the same PCI controller.
Subsystem vendor IDs can be obtained from the PCI SIG. See Table 38.
Table 38. Subsystem Vendor ID Register Format
Data Bit
Mnemonic
Read/Write
15:0
sub_ven_id
Read
Table 39 shows the subsytem vendor ID register format.
Table 39. Subsystem ID Register Format
72
Data Bit
Mnemonic
Read/Write
15:0
sub_id
Read
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GettingSpecifications
PCI32 Nios Target MegaCore Function User Guide
Interrupt Pin Register
The interrupt pin register is an 8-bit read-only register that defines the PCI
function PCI bus interrupt request line to be intan. The default value of
the interrupt pin register is 01 H. See Table 40.
Table 40. Interrupt Pin Register Format
Data Bit
Mnemonic
Read/Write
Definition
7:0
int_pin
Read
Interrupt pin register
Minimum Grant Register
The minimum grant register is an 8-bit read-only register that defines the
length of time the function would like to retain mastership of the PCI bus.
The value set in this register indicates the required burst period length in
250-ns increments. See Table 41.
3
Table 41. Minimum Grant Register Format
Mnemonic
Read/Write
7:0
min_gnt
Read
Specifications
Data Bit
Maximum Latency Register
The maximum latency register is an 8-bit read-only register that defines
the frequency with which the function would like to gain access to the PCI
bus. See Table 42.
Table 42. Maximum Latency Register Format
Data Bit
Mnemonic
Read/Write
7:0
max_lat
Read
Commands Issued from the PCI Side
The PCI can read to or write from the registers by reading to or writing
from the correct address.
Altera Corporation
73
Specifications
PCI32 Nios Target MegaCore Function User Guide
PCI Bus to Avalon Bus Transfer
The PCI bus can write a command to the mailbox. The command is
interpreted by the Avalon bus, which sets up the DMA engine to start the
transfer.
Avalon Bus to PCI Bus Transfer
You can initiate a data transfer from the Avalon bus by writing to the
mailbox. The command is then interpreted by the software, which sends
data to the FIFO buffer and sets the DMA. The data comes from the PCI
master; never from the PCI target.
Core
Verification
Core verification involves hardware testing and simulation testing.
Simulation Testing
Altera carried out extensive gate-level tests of the PCI32 Nios Target with
APEX 20KE, Stratix, Mercury and preliminary models of Cyclone and
StratixGX devices.
Hardware Testing
Altera tested the PCI32 Nios Target for correct operation with the
following hardware:
■
■
■
An EPXA10 development board at 10 MHz
A PCI32 Nios Target Kit adapter board and a Nios development
board in a PC at 33 MHz.
An APEX PCI 20KC1000 development board in a PC at 33 MHz.
Altera carried out the following tests:
■
■
74
Enumaration of PCI devices present on the PCI bus.
Access to a custom-designed PCI Master Target card (APEX PCI
20KE400) with the following tests:
–
Configuration read and write
–
Memory read and write (single cycle and up to 16-cycle bursts)
–
IO read and write
–
Mailbox read and write to and from the PCI
–
Interrupt capture from the PCI bus
Altera Corporation
Appendix A—Nios
Application Programming
Interface
Altera provides an application programming interface (API) in source
code form, for using the PCI32 Nios Target MegaCore function. The API
is a C language include file with structure declarations and functions. The
file is called pci32_nios_target_api.h and is in the inc directory.
You can turn on the debug option by uncommenting the line //#define
AUK_A2P_DEBUG 1.
The functions are listed and described in Tables 43 to 46. The following
sections show the API’s syntax.
f
For more information on the Nios embedded processor, refer to the Nios
Embedded Processor Software Development Reference Manual.
Memory Map &
Registers
Table 43. Basic Functions Note (1)
Function
Description
Read PCI target configuration registers.
TargPci<size>Wr
Write PCI target configuration registers.
TargPci<size>ConfRd
Read PCI target configuration registers.
TargPci<size>ConfWr
Write PCI target configuration registers.
TargPciIO<size>Rd
Read PCI target I/O registers.
TargPciIO<size>Wr
Write PCI target I/O registers.
TargPciMem<size>Rd
Read PCI target memory registers.
TargPciMem<size>Wr
Write PCI target memory registers.
4
Appendix A
TargPci<size>Rd
Note:
(1)
<size> can be DWord (32-bits), Word (16-bits), or Byte (8-bits).
Table 44. PCI Target Mailbox Functions
Function
Altera Corporation
Description
writeMailbox
Write mailbox.
readMailbox
Read mailbox.
3
75
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
Table 45. Interrupt Functions
Function
Description
EnableBrdgAvlInterrupts
DisableBrdgAvlInterrupts
Enable and disable Nios target interrupts
EnableBrdgPCIInterrupts
DisableBrdgPCIInterrupts
Enable and disable PCI interrupts
Table 46. Miscellaneous Functions
Function
Basic Functions
Description
enum_pci_bus
Enumerate PCI bus agents.
ReadAllRegs
Reads all of the control and status registers.
reportAISRvalue
Status register print report.
This section contains generic read/write functions and specific memory,
config and I/O read/write functions.
Generic Read/Write Functions
Use these generic functions to build specific read and write functions, they
are not intended to be called directly.
76
1
For the read and write functions the values pointed to by
rdValPtr or wrValPtr can be a single byte, word, or DWORD;
or an array of bytes, words, or DWORDs from 1 to 16 in size.
1
If a command spans multiple lines you should still type or use in
one line.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciDWordRd
Reads DWORDs, (32-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
int TargPciDWordRd(int np_usersocket
*brdg, int pcicmd, int pciAddr, DWORD
*rdValPtr, int numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on the PCI bus,
commands are defined in the include file.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to array of DWORDs to store
values read from the PCI bus.
numtrans—number of DWORDs to read from the PCI
bus, this number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register otherwise returns 0.
TargPciDWordWr
Writes DWORDs, (32-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Altera Corporation
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4
Appendix A
Returns:
int TargPciDWordWr(int np_usersocket *brdg,
int pcicmd, int pciAddr, DWORD *wrValPtr,
int numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on the PCI bus,
commands are defined in the include file.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of DWORDs containing
values to write.
numtrans—number of DWORDs to write to the PCI bus.
This number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register otherwise returns 0.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
TargPciWordRd
Reads words, (16-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
int TargPciWordRd(int np_usersocket *brdg,
int pcicmd, int pciAddr, WORD *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on PCI bus,
commands are defined in the include file.
pciAddr—address to place on PCI bus.
rdValPtr—pointer to array of words to store values read
from PCI bus.
numtrans—number of words to read from PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciWordWr
Writes words, (16-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
78
int TargPciWordWr(int np_usersocket *brdg,
int pcicmd, int pciAddr, WORD *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on the PCI bus,
commands are defined in the include file.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of words containing values to
write.
numtrans—number of words to write to the PCI bus, this
number must not exceed the size of the array pointed to by
rdValPtr, or the size of the FIFO buffer.
On error returns value of Avalon interrupt status register
otherwise returns 0.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciByteRd
Reads bytes, (8-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
int TargPciByteRd(int np_usersocket *brdg,
int pcicmd, int pciAddr, BYTE *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on the PCI bus,
commands are defined in the include file.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to array of bytes to store values read
from the PCI bus.
numtrans—number of bytes to read from the PCI bus,
this number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns value of Avalon interrupt status register,
otherwise returns 0.
TargPciByteWr
Writes bytes, (8-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Altera Corporation
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4
Appendix A
Returns:
int TargPciByteWr(int np_usersocket *brdg,
int pcicmd, int pciAddr, BYTE *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pcicmd—PCI bus command to place on the PCI bus,
commands are defined in the include file.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of bytes containing values to
write.
numtrans—number of bytes to write to the PCI bus, this
number must not exceed the size of the array pointed to by
rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
Specific Memory, Configuration, & I/O Read Write Functions
TargPciDWordConfRd
Reads configuration DWORDs, (32-bit values), from the PCI device on the
PCI bus.
Syntax:
Parameters:
Returns:
80
int TargPciDWordConfRd(int np_usersocket
*brdg, char card_Device_Number, char
function_Number, char reg_addr, DWORD
*rdValPtr);
*brdg—Pointer to the bridge.
card_Device_Number—a number between 11 and 31
corresponding to the device idsel line. Find this by using
the emun_pci_bus function then passing in
device_Number[x][1].
function_Number—for multi function PCI devices only,
valid range 0 to 8.
reg_addr—configuration register address, valid range 0
to 256. You should ensure reg_addr is divisible by 4 for
DWORD access.
rdValPtr—pointer to an array of DWORDs, which stores
the values read from the PCI bus.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciDWordConfWr
Reads configuration DWORDs, (32-bit values), from the PCI device on the
PCI bus.
Syntax:
Parameters:
Returns:
int TargPciDWordConfWr(int np_usersocket
*brdg, char card_Device_Number, char
function_Number, char reg_addr,DWORD
*wrValPtr);
*brdg—Pointer to the bridge.
card_Device_Number—a number between 11 and 31
corresponding to the device idsel line. Find this by using
the emun_pci_bus function then passing in
device_Number[x][1].
function_Number—for multi function PCI devices only,
valid range 0 to 8.
reg_addr—configuration register address, valid range 0
to 256. You should ensure reg_addr is divisible by 4 for
DWORD access.
wrValPtr—pointer to array of DWORDs containing
values to write.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciMemDWordRd
Reads memory DWORDs, (32-bit values), from PCI device on PCI bus.
Syntax:
Returns:
Altera Corporation
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4
Appendix A
Parameters:
int TargPciMemDWordRd(int np_usersocket
*brdg, int pciAddr, DWORD *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to an array of DWORDs to store
values read from PCI bus.
numtrans—number of DWORDs to read from PCI bus,
this number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
TargPciMemDWordWr
Writes memory DWORDs, (32-bit values), to the PCI device on the PCI
bus.
Syntax:
Parameters:
Returns:
int TargPciMemDWordWr(int np_usersocket
*brdg, int pciAddr, DWORD *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to an array of DWORDs containing
values to write.
numtrans—number of DWORDs to write to the PCI bus,
this number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciMemWordRd
Reads memory words, (16-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
82
int TargPciMemWordRd(int np_usersocket
*brdg, int pciAddr, WORD *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to an array of words to store values
read from PCI bus.
numtrans—number of words to read from the PCI bus,
this number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciMemWordWr
Writes memory words, (16-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
int TargPciMemWordWr(int np_usersocket
*brdg, int pciAddr, WORD *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to an array of word containing values
to write.
numtrans—number of words to write to PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciMemByteRd
Reads memory bytes, (8-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Altera Corporation
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4
Appendix A
Returns:
int TargPciMemByteRd(int np_usersocket
*brdg, int pciAddr, BYTE *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to array of bytes to store values read
from PCI bus.
numtrans—number of bytes to read from PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
TargPciMemByteWr
Writes memory bytes, (8-bit values), to PCI device on PCI bus.
Syntax:
Parameters:
Returns:
int TargPciMemByteWr(int np_usersocket
*brdg, int pciAddr, BYTE *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of bytes containing values to
write.
numtrans—number of bytes to write to PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciIODWordRd
Writes IO DWORDs, (32-bit values), to PCI device on PCI bus.
Syntax:
Parameters:
Returns:
84
int TargPciIODWordRd(int np_usersocket
*brdg, int pciAddr, DWORD *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of DWORDs containing
values to write.
numtrans—number of DWORDs to write to PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciIODWordWr
Writes IO DWORDs, (32-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
int TargPciIODWordWr(int np_usersocket
*brdg, int pciAddr, DWORD *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of DWORDs containing
values to write.
numtrans—number of DWORDs to write to PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciIOWordRd
Reads IO words, (16-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Altera Corporation
85
4
Appendix A
Returns:
int TargPciIOWordRd(int np_usersocket
*brdg, int pciAddr, WORD *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
rdValPtr—pointer to array of words to store values read
from PCI bus.
numtrans—number of words to read from PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
TargPciIOWordWr
Writes IO words, (16-bit values), to PCI device on PCI bus.
Syntax:
Parameters:
Returns:
int TargPciIOWordWr(int np_usersocket
*brdg, int pciAddr, WORD *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on PCI bus.
wrValPtr—pointer to array of words containing values to
write.
numtrans—number of words to write to PCI bus, this
number must not exceed the size of the array pointed to by
rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
TargPciIOByteRd
Reads IO bytes, (8-bit values), from the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
86
int TargPciIOByteRd(int np_usersocket
*brdg, int pciAddr, BYTE *rdValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on PCI bus.
rdValPtr—pointer to array of bytes to store values read
from PCI bus.
numtrans—number of bytes to read from PCI bus, this
number must not exceed the size of the array pointed to by
rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
TargPciIOByteWr
Writes IO bytes, (8-bit values), to the PCI device on the PCI bus.
Syntax:
Parameters:
Returns:
PCI Target
Mailbox
Functions
int TargPciIOByteWr(int np_usersocket
*brdg, int pciAddr, BYTE *wrValPtr, int
numtrans);
*brdg—Pointer to the bridge.
pciAddr—address to place on the PCI bus.
wrValPtr—pointer to array of bytes containing values to
write.
numtrans—number of bytes to write to the PCI bus, this
number must not exceed the size of the array
pointed to by rdValPtr or the size of the FIFO buffer.
On error returns the value of the Avalon interrupt status
register, otherwise returns 0.
writeMailbox
Writes a 32-bit value to the Nios soft core to the PCI mailbox.
Syntax:
Parameters:
Returns:
int writeMailbox(np_usersocket *brdg);
*brdg—Pointer to the bridge.
None
readMailbox
4
Reads a 32-bit value to the Nios soft core to the PCI mailbox.
Interrupt
Functions
int writeMailbox(np_usersocket *brdg);
*brdg—Pointer to the bridge.
Value contained in the Avalon mailbox
EnableBrdgAvlInterrupts
Sets the Avalon interrupt control register, and enables all of the core
Avalon interrupts.
You should edit this function to enable only the desired interrupts.
Syntax:
Parameters:
Returns:
Altera Corporation
Appendix A
Syntax:
Parameters:
Returns:
int EnableBrdgAvlInterrupts(np_usersocket
*brdg);
*brdg—Pointer to the bridge.
None
87
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
DisableBrdgAvlInterrupts
Sets the Avalon interrupt control register, and disables all of the core
Avalon interrupts.
Syntax:
Parameters:
Returns:
int DisableBrdgAvlInterrupts(np_usersocket
*brdg);
*brdg—Pointer to the bridge.
None
EnableBrdgPCIInterrupts
Sets the PCI interrupt control register, and enables all of the core PCI
interrupts.
You should edit this function to enable only the desired interrupts.
Syntax:
Parameters:
Returns:
int EnableBrdgPCIInterrupts(np_usersocket
*brdg);
*brdg—Pointer to the bridge.
None
DisableBrdgPCIInterrupts
Sets the PCI interrupt control register, and disables all of the core PCI
interrupts.
Syntax:
Parameters:
Returns:
88
int DisableBrdgPCIInterrupts(np_usersocket
*brdg);
*brdg—Pointer to the bridge.
None
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
Miscellaneous
Functions
GettingAppendix A—Nios Application Programming
enum_pci_bus
Checks the PCI bus for the presence of devices on the bus.
Starts by setting idsel bit 0, AD(11), to do configuration read of card ID,
which checks for the PCI device. If the master abort indicates no device, it
increments the idsel value and retries. Keeps checking until
MAXDEVICES number of devices identified or all 21 possible idsel bits
tried.
Results are written to device_Number array.
device_Number array holds the PCI device data identified by
enum_pci_bus
device_Number[x,1] is word with idsel bit set for device
device_Number[x,2] is the (Device ID , Vendor ID) value for device
Syntax:
Parameters:
Returns:
int enum_pci_bus(np_usersocket *brdg);
*brdg—Pointer to the bridge.
None
ReadAllRegs
Reads all the core status and control registers and prints their value
(AISR;ACR;PCR;TCR;PAR;DCSR).
Syntax:
Parameters:
Returns:
int ReadAllRegs(int np_usersocket *brdg);
*brdg—Pointer to the bridge.
0
reportAISRvalue
4
Prints the status of the Avalon interrupt status register
Parameters:
Returns:
Supported
Commands
Altera Corporation
int reportAISRvalue(int np_usersocket *brdg,
int AISRval);
*brdg—Pointer to the bridge.
AISRval—Value of the Avalon interrupt status register, as
returned by read or write functions
0
There are two main sets of commands to implement. The ones that are
directly translated to PCI commands and the ones used to configure the
bridge (such as DMA registers, access to the status or control registers).
You can access the internal registers by reading from or writing to the
register location.
89
Appendix A
Syntax:
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
The PCI32 Nios Target MegaCore function supports the following
commands:
■
■
■
■
■
Writing to a bridge configuration register
Reading a bridge configuration/status register
Writing a command on or sending data to the PCI bus
Reading data from the PCI bus
Error handling
Writing to a Bridge Configuration Register
To write to a bridge configuration register, perform the following steps:
1.
Execute a write cycle from the Avalon bus.
2.
Set up the register values on the data bus.
3.
Set up the address on the address bus.
Reading a Bridge Configuration/Status Register
To read a bridge configuration/status register, perform the following
steps:
1.
Execute a read command on the Avalon bus.
2.
Set the address on the address bus.
3.
The bridge outputs the register value on the output data bus.
Writing a Command on or Sending Data to the PCI bus
To write a command or send data to the PCI bus, perform the following
steps:
90
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix A—Nios Application Programming
1.
Execute a write command on the Avalon bus.
2.
Set the DRU address on the address bus.
3.
Put the data on the data bus and write data to DRU.
4.
Repeat step 2 if there is more consecutive data to transfer.
5.
Put the PCI address on the data bus and the PAR address on the
address bus.
6.
Write the transfer size (in multiple of 4 bytes) in the TCR.
7.
Put the command on the data bus and the PCR address on the
address bus. The Avalon bus sends an interrupt (if enabled), when
the transfer is finished.
8.
Write the status register to clear the interrupt.
Reading Data from the PCI Bus
To read data from the PCI bus, perform the following steps:
Execute a write command on the Avalon bus.
2.
Put the PCI address on the data bus and the PAR address on the
address bus.
3.
Write the transfer size (in multiple of 4 bytes) in the TCR.
4.
Put the command on the bus and the PCR address on the bus.
4
When the command is completed, the PCI32 Nios Target MegaCore
function interrupts the Avalon bus if the corresponding interrupt is
enabled, or you can poll the AISR to check for completion.
5.
Write the interrupt control and status register to clear the interrupt
(ensure that the interrupt corresponds to the data transfer).
6.
Read data from address DRU.
7.
Repeat step 7 for the amount of data that was transferred.
Error Handling
The following errors can occur:
Altera Corporation
91
Appendix A
1.
Appendix A—Nios Application Programming Interface PCI32 Nios Target MegaCore Function User Guide
■
■
92
PCI command error. This occurs when the command sent to the core
was incorrect—the PCR or the TCR was incorrectly set.
Discarding the current command. If a PCI target issues a disconnect
or the PCI timer times out without sending data, the current
command is discarded and the data is flushed from the FIFO buffer.
Altera Corporation
Appendix B—PCI Testbench
The PCI testbench facilitates the design and verification of systems that
implement the Altera PCI32 Nios Target MegaCore function. You can
build a behavioral simulation environment by using the components of
the testbench and your VHDL or Verilog HDL application design.
Figure 23 shows the block diagram of testbench.
Figure 23. Testbench Block Diagram
Blue blocks are provided in the testbench.
Testbench
Testbench Modules
PCI Bus
Master
Transactor
Altera Device
Avalon Bus
Target
Transactor
Bus
Monitor
PCI32 Nios
Target
MegaCore
Function
Nios Soft
Core
Embedded
Processor
Clock Generator
Pull Ups
5
Altera Corporation
Appendix B
Figure 24 shows the directory structure of the testbench.
93
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 24. Testbench Directory Structure
<MegaCore path>/testbench
VHDL
Contains files for the VHDL flow.
source
Contains VHDL source files of the testbench modules and reference designs for the PCI Nios target MegaCore function.
example
Contains the top-level file and modified testbench modules required to simulate the reference design for
the PCI Nios target MegaCore function.
Verilog
Contains files for the Verilog HDL flow.
source
Contains Verilog HDL source files of the testbench modules and reference designs for the PCI Nios target MegaCore function.
example
Contains the top-level file and modified testbench modules required to simulate the reference design for
the PCI Nios target MegaCore function.
The testbench provides a fast and efficient way for developing and testing
designs that use the PCI32 Nios Target MegaCore function. The testbench
is a functional simulation environment that allows you to verify the PCI
transactions used in your application with other PCI agents. To use the
testbench, you should have a basic understanding of PCI bus architecture
and operations.
You can use the testbench to perform pre- and post-synthesis simulation
of your application.
Pre-Synthesis
Design Flow
94
■
Perform pre-synthesis simulation by instantiating the behavioral
model of a PCI32 Nios Target MegaCore function in the top-level file
of the testbench.
■
Perform post-synthesis simulation by instantiating a VHDL Output
File (.vho) or Verilog Output File (.vo) generated by the Quartus II
software in the top-level file of the testbench.
Figure 25 shows the pre-synthesis design flow you should follow when
working with the testbench.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
Figure 25. Pre-Synthesis Flow
1. Set up the simulation environment to use any
of the Altera PCI MegaCore behavioral models.
2. Configure your Nios system including the PCI32
Nios target MegaCore function.
3. Specify the initialization parameters in the
master transactor model.
4. Add your PCI test commands to the user section
of the master transactor model.
5. Modify the memory range of the target
transactor model as needed for your application.
6. Create the top-level file that instantiates the PCI
testbench blocks, the PCI32 Nios target
MegaCore function and the rest of your design.
7. Compile the testbench files in your choice of
simulator.
8. Simulate the PCI transactions with your design.
5
Appendix B
Altera Corporation
95
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
The following steps give more detail on the flow shown in Figure 25.
1.
Altera provides encrypted behavioral models for the PCI32 Nios
Target MegaCore function.
2.
Specify the PCI32 Nios Target MegaCore function parameters, by
using the Nios system and PCI32 Nios Target wizards, and generate
a VHDL or Verilog HDL wrapper file that instantiates the function.
Instantiate this wrapper file in your top-level testbench file.
3.
Set the initialization parameters, which are defined in the master
transactor model source code. These parameters control the address
space reserved by the target transactor model and other PCI agents
on the PCI bus.
Figure 26 shows the INITIALIZATION section of the master
transactor source code in VHDL and Verilog HDL.
Figure 26. Master Transactor Model Initialization Section
VHDL (mstr_tranx.vhd)
Verilog HDL (mstr_tranx.v)
--********************************
//**********************************
-- INITIALIZATION
// INITIALIZATION
--*********************************
//**********************************
-- System Reset
96
// System
Reset
rstn <= '0';
rstn <= 1'b0 ;
idle_cycle(10);
idle_cycle(10);
rstn <= '1';
rstn <= 1'b1 ;
idle_cycle(3);
idle_cycle(3);
-- Configuration Space Parameters
// Configuration Space
command_reg <= x"00000147";
command_reg <= 32'h00000147 ;
targ_tranx_bar0 <= x"20000000";
targ_tranx_bar0 <= 32'h20000000 ;
targ_tranx_bar1 <= x"fffff2C0";
targ_tranx_bar1 <= 32'hfffff2C0 ;
Parameters
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
4.
The master transactor defines the procedures (VHDL) or tasks
(Verilog HDL) needed to initiate PCI transactions in your testbench.
Add the commands that correspond to the transactions you want to
implement in your tests in the master transactor model source code.
5.
Modify the target transactor model memory range. The target
transactor instantiates a 1-Kbyte memory array by default. On reset,
this memory array is initialized by the trgt_tranx_mem_init.dat file.
You can modify the memory instantiated by the target transactor
model by changing the address_lines value and the
mem_hit_range value (to correspond to the value specified by
address_lines). For example, if address_lines is 1024, the
target transactor instantiates a 1-KByte memory array that
corresponds to a memory hit range of 000-3FFh.
Figure 27 shows the address_lines and mem_hit_range
parameters of the target transactor model source code in VHDL and
Verilog HDL.
5
Appendix B
Altera Corporation
97
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 27. Target Transactor Model address_lines & mem_hit_range
Parameters
VHDL (trgt_tranx.vhd)
.
.
CONSTANT mem_hit_range : std_logic_vector(31 DOWNTO 0) := x"000003FF";
CONSTANT address_lines : integer := 1024;
--Must be a power of 2
CONSTANT io_hit_range : std_logic_vector(31 DOWNTO 0) := x"0000000F";
.
.
file_open(f, "trgt_tranx_mem_init.dat",read_mode);
.
.
Verilog HDL (trgt_tranx.v)
.
.
parameter address_lines = 1024;
parameter[31:0] mem_hit_range = 32'h000003FF;
parameter[31:0] io_hit_range = 32'h0000000F;
.
.
$readmemh("trgt__tranx_mem_init.dat",temp_bit_array);
.
.
6.
98
Create a top-level testbench file that instantiates the testbench
elements and the PCI32 Nios Target MegaCore function(s), and
connect all the signals. To simplify this process, the testbench
includes sample top-level files that instantiate all of the elements.
These files are located in the <megacore path>:
/pci32_nios_target/testbench/<language>/example directory where
<language> is VHDL or Verilog. Modify the appropriate top-level
sample file by replacing top_local with your application design.
Figure 28 shows the top-level testbench example in VHDL and
Verilog HDL.
Altera Corporation
GettingAppendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 28. Top-Level Testbench Example
VHDL (altera_pci32_nios_target_tb.vhd)
Verilog HDL (altera_pci32_nios_target_tb.v)
--*********************************************
//********************************************
-- Top-Level File of Altera PCI Testbench
// Top-Level File of Altera PCI Testbench
--*********************************************
//*********************************************
entity altera_tb is
module altera_tb ();
end altera_tb;
.
architecture behavior of altera_tb is
.
.
mstr_tranx u0 (..),
.
trgt_tranx u1 (..),
u0:mstr_tranx (..);
monitor u2 (..),
u1:trgt_tranx
pull_up u3 (..),
(..);
u2:monitor (..);
clk_gen u4 (..),
u3:pull_up
(..);
pci_nios_top u5 (..),
u4:clk_gen
(..);
.
u5:pci_nios_top
.
(..);
endmodule
.
.
end behavior;
Post-Synthesis
Design Flow
Functional
Description
Compile the test files in your simulator, including the testbench
modules located in the <megacore path>:
/pci32_nios_target/testbench/vhdl/source directory, your Nios
simulation files, the PCI32 Nios Target MegaCore function, and the
top-level testbench file created in step 6.
8.
Simulate the testbench for the desired time period.
After you license the PCI32 Nios Target MegaCore function(s) you can
perform post-synthesis simulation. To perform post-synthesis simulation,
you must first generate the .vo or .vho of your design that includes the
function. After you generate .vo or .vho files for your design, follow steps
3 through 8 described in “Pre-Synthesis Design Flow” on page 94.
Refer to the Quartus II Help for a description of the design flow using .vo
or .vho files.
5
This section describes the blocks used by testbench including master
commands, setting and controlling target termination responses, bus
parking, and PCI bus speed settings. Refer to Figure 23 for a block
diagram of the testbench. The testbench has the following blocks:
Appendix B
f
7.
■
Altera Corporation
Master transactor
99
Appendix B—PCI Testbench
■
■
■
■
■
■
PCI32 Nios Target MegaCore Function User Guide
Target transactor
Bus monitor
Clock generator
Arbiter
Pull ups
Local reference design
The testbench is supplied as VHDL or Verilog HDL source code. If your
application uses a feature that is not supported by the testbench, you can
modify the source code to add new features. You can also modify the
existing behavior to fit your application needs.
Table 47 shows the PCI bus transactions that can be initiated or responded
by the testbench.
Table 47. PCI Testbench PCI Bus Transaction Support
Transactions
Master Transactor
Target Transactor
Local Master
Local Target
I/O read
v
v
v
v
I/O write
v
v
v
v
Memory read
v
v
v
v
Memory write
v
v
v
v
Configuration read
v
v
Configuration write
v
v
Interrupt acknowledge cycle
Memory read multiple
Memory write multiple
Dual address cycle
Memory read line
Memory write and invalidate
Table 48 shows the testbench’s target termination support. The master
transactor and the local master respond to the target terminations by
terminating the transaction gracefully and releasing the PCI bus.
Table 48. Testbench Target Termination Support
Features
Master Transactor
Target Transactor
Local Master
Local Target
Target abort
v
Target retry
v
v
v
v
Target disconnect
v
v
v
v
100
v
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
Master Transactor
The master transactor simulates the master behavior on the PCI bus. It
serves as an initiator of PCI transactions for the testbench. The master
transactor has three main sections (see Figure 29). All sections are clearly
marked in the master transactor source code.
■
■
■
PROCEDURES (VHDL) or TASKS (Verilog HDL)
INITIALIZATION
USER COMMANDS
5
Appendix B
Altera Corporation
101
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 29. Master Transactor Examples
102
VHDL (mstr_tranx.vhd)
Verilog HDL (mstr_tranx.v)
--**********************************************
//**********************************
-- PROCEDURES
// TASKS
--**********************************************
procedure cfg_wr(..)
.
.
//**********************************
task cfg_wr;
.
.
procedure cfg_rd(..)
.
.
procedure mem_wr_64(..)
.
.
task cfg_rd;
.
.
task mem_wr_64;
.
.
--********************************
//**********************************
-- INITIALIZATION
// INITIALIZATION
--*********************************
//**********************************
-- System Reset
// System
rstn <= '0';
rstn <= 1'b0 ;
idle_cycle(10);
idle_cycle(10);
rstn <= '1';
rstn <= 1'b1 ;
idle_cycle(3);
idle_cycle(3);
-- Configuration Space Parameters
// Configuration Space Parameters
command_reg <= x"00000147";
command_reg <= 32'h00000147 ;
bar0 <= x"10000000";
bar0 <= 32'h10000000 ;
bar1 <= x"fffff3C0";
bar1 <= 32'hfffff3C0 ;
bar2 <= x"55000000";
bar2 <= 32'h55000000 ;
targ_tranx_bar0 <= x"20000000";
targ_tranx_bar0 <= 32'h20000000 ;
targ_tranx_bar1 <= x"fffff2C0";
targ_tranx_bar1 <= 32'hfffff2C0 ;
--************************
-- USER COMMANDS
//************************
// USER COMMANDS
--************************
//************************
cfg_wr(x"10000004",command_reg,"0000");
cfg_wr(32'h10000004, command_reg, 4'b0000);
cfg_wr(x"10000010",bar0,"0000");
cfg_wr(32'h10000010, bar0, 4'b0000);
cfg_wr(x"10000014",bar1,"0000");
cfg_wr(32'h10000014, bar1, 4'b0000);
cfg_wr(x"10000018",bar2,"0000");
cfg_wr(32'h10000018, bar2, 4'b0000);
cfg_wr(x"20000010",targ_tranx_bar0,"0000");
cfg_wr(32'h20000010, targ_tranx_bar0, 4'b0000);
cfg_wr(x"20000014",targ_tranx_bar1,"0000");
cfg_wr(32'h20000014, targ_tranx_bar1, 4'b0000);
cfg_rd(x"10000004");
.
.
mem_wr_64(x"10000000",x"0000000200000001",1);
.
.
mem_rd_64(x"10000000",1);
.
.
mem_wr_32(x"10000000",x"00000001",1);
.
.
end behavior;
cfg_rd(32'h10000004);
.
.
mem_wr_64(32'h10000000, 64'h0000000200000001, 1);
.
.
mem_rd_64(32'h10000000,1);
.
.
mem_wr_32(32'h10000000,32'h00000001,1);
.
.
endmodule
Rreset
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
PROCEDURES or TASKS Section
The PROCEDURES (VHDL) or TASKS (Verilog HDL) section defines the
events that are executed for the user commands supported by the master
transactor. The events written in the PROCEDURES or TASKS section
follow the phases of a standard PCI transactions as defined by the PCI
specification, including:
■
■
■
■
Address phase
Turnaround phase (read transactions)
Data phases
Turnaround phase
The master transactor terminates the PCI transactions in the following
cases:
■
■
■
The PCI transaction has successfully transferred all the intended data.
The PCI target terminates the transaction prematurely with a target
retry, disconnect, or abort as defined in the PCI Local Bus
Specification, Revision 2.2.
A target does not claim the transaction resulting in a master abort.
The bus monitor informs the master transactor of a successful data
transaction or a target termination. Refer to the source code, which shows
how the master transactor uses these termination signals from the bus
monitor.
The testbench master transactor PROCEDURES or TASKS events
implement basic PCI transaction functionality. If your application
requires different functionality, modify the events to change the behavior
of the master transactor. Additionally, you can create new procedures or
tasks in the master transactor using the existing events as an example.
INITIALIZATION Section
Altera Corporation
103
5
Appendix B
This user-defined section defines the parameters and reset length of your
PCI bus on power-up. Specifically, the system should reset the bus and
write the configuration space of the PCI agents. You can modify the
master transactor INITIALIZATION section to match your system
requirements by changing the time the system reset is asserted and
modifying the data written in the configuration space of the PCI agents.
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
USER COMMANDS Section
The master transactor USER COMMANDS section contains the commands
that initiate the PCI transactions you want to run for your tests. The list of
events that are executed by these commands is defined in the
PROCEDURES or TASKS section. Customize the USER COMMANDS section to
execute the sequence of commands as needed to test your design.
Table 49 shows the commands the master transactor supports.
Table 49. Supported Master Transactor Commands
Command Name
Action
cfg_rd
Performs a configuration read
cfg_wr
Performs a configuration write
mem_wr_32
Performs a 32-bit memory write
mem_rd_32
Performs a 32-bit memory read
io_rd
Performs an I/O read
io_wr
Performs an I/O write
cfg_rd
The cfg_rd command performs single-cycle PCI configuration read
transactions with the address provided in the command argument.
104
Syntax:
cfg_rd(address)
Arguments:
address
Transaction address. The address must be
in hexadecimal radix.
Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
cfg_wr
The cfg_wr command performs single-cycle PCI configuration write
transactions with the address, data, and byte enable provided in the
command arguments.
Syntax:
cfg_wr(address, data, byte_enable)
Arguments:
address
Transaction address. The address must be
in hexadecimal radix.
data
Transaction data. The data must be in
hexadecimal radix.
byte_enable Transaction byte enable. The byte enable
value must be in hexadecimal radix.
mem_wr_32
The mem_wr_32 command performs a memory write with the address
and data provided in the command arguments. This command can
perform a single-cycle or burst 32-bit memory write depending on the
number of DWORDs provided in the command argument.
■
■
The mem_wr_32 command performs a single-cycle 32-bit memory
write if the DWORD value is 1.
The mem_wr_32 command performs a burst-cycle 32-bit memory
write if the DWORD value is greater than 1. In a burst transaction, the
first data phase uses the data value provided in the command. The
subsequent data phases use values incremented sequentially by 1
from the data provided in the command argument.
mem_wr_32(address, data, dword)
Arguments:
address
Transaction address. This value must be in
hexadecimal radix.
data
Data used for the first data phase.
Subsequent data phases use a value
incremented sequentially by 1. This value
must be in hexadecimal radix.
dword
Altera Corporation
The number of DWORDs written during
the transaction. A value of 1 indicates a
single-cycle memory write transaction. A
value greater than 1 indicates a burst
transaction. This value must be an integer.
105
5
Appendix B
Syntax:
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
mem_rd_32
The mem_rd_32 command performs a memory read with the address
provided in the command argument. This command can perform singlecycle or burst 32-bit memory read depending on the value of the dword
argument.
■
■
If the dword value is 1, the command performs a single-cycle
transaction.
If the dword value is greater than 1, the command performs a burst
transaction.
Syntax:
mem_rd_32(address, dword)
Arguments:
address
Transaction address. This value must be in
hexadecimal radix.
dword
The number DWORDs read during the
transaction. A value of 1 indicates a singlecycle memory read transaction. A value
greater than 1 indicates a burst
transaction. This value must be an integer.
io_wr
The io_wr command performs a single-cycle memory write transaction
with the address and data provided in the command arguments.
Syntax:
io_wr(address, data)
Arguments:
address
Transaction address. This value must be in
hexadecimal radix.
data
Data written during the transaction. This
value must be in hexadecimal radix.
io_rd
The io_rd command performs single-cycle I/O read transactions with
the address provided in the command argument.
106
Syntax:
io_rd(address)
Arguments:
address
Transaction address. This value must be in
hexadecimal radix.
Altera Corporation
GettingAppendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Target Transactor
The target transactor simulates the behavior of a target agent on the PCI
bus. The master transactions from the PCI32 Nios Target MegaCore
function under test should be addressed to the target transactor. The
target transactor operates in 32- or 64-bit mode. The target transactor
implements only the necessary portion of the standard PCI configuration
space, i.e., BAR0. See Table 50.
Table 50. Target Transactor Configuration Address Space
Configuration Register
BAR0
Configuration Address Offset
x10
The base address registers define the target transactor address space. See
Table 51.
Table 51. Target Transactor Address Space Allocation
Configuration Register Address Space Type
BAR0
Memory Mapped
Block Size
1 KBytes
Address Offset
000-3FF
The memory range reserved by BAR0 is defined by the address_lines
and mem_hit_range settings in the target transactor source code.
As with all PCI agents, the target transactor idsel signal should be
connected to one of the PCI address bits in the top-level file of the PCI
testbench for configuration transactions to occur on BAR0.
To model different target terminations, the target transactor has the
following three input signals:
■
■
■
Figure 30 shows the USER COMMANDS section of the master transactor that
shows an example of how to use the target termination signals for the
target transactor.
Altera Corporation
107
5
Appendix B
trgt_tranx_retry—The target transactor retries the memory
transaction if trgt_tranx_retry is set to 1.
trgt_tranx_discA—The target transactor terminates the memory
transaction with data if trgt_tranx_discA is set to 1.
trgt_tranx_discB—The target transactor terminates the memory
transaction with a disconnect without data if trgt_tranx_discB is
set to 1.
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 30. USER COMMANDS Section
VHDL (mstr_tranx.vhd)
Verilog HDL (mstr_tranx.v)
.
.
.
trgt_tranx_retry <= '1';
.
mem_wr_64(x"20000000",x"0000000200000001",5);
trgt_tranx_retry <= '1';
mem_wr_64(32'h20000000,64'h0000000200000001,5);
trgt_tranx_retry <= '0';
.
trgt_tranx_retry <= '0';
.
trgt_tranx_disca <= '1';
.
trgt_tranx_disca <= '1';
.
mem_rd_64(x"20000000",1);
mem_rd_64(32'h20000000,1);
trgt_tranx_disca <= '0';
.
trgt_tranx_disca <= '0';
.
.
.
trgt_tranx_discb <= '1';
mem_rd_64(x"20000000",5);
trgt_tranx_discb <= '0';
trgt_tranx_discb <= '1';
mem_rd_64(32'h20000000,5);
trgt_tranx_discb <= '0';
.
.
.
.
The target transactor has two main sections:
■
■
FILE IO
PROCEDURES (VHDL) or TASKS (Verilog HDL)
Figure 31 shows the FILE IO and PROCEDURES/TASKS sections of the
target transactor.
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GettingAppendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
Figure 31. Target Transactor
VHDL (trgt_tranx.vhd)
Verilog HDL (trgt_tranx.v)
--************************************************* //*****************************************************
-- FILE IO
// FILE IO
--************************************************* //*****************************************************
.
.
.
.
file_open(f, "trgt_tranx_mem_init.dat",read_mode);
.
$readmemh("trgt_tranx_mem_init.dat",temp_bit_array);
.
.
always
process(..)
begin
.
begin:main
.
.
.
.
--************************************************* if (!framen & cben[3:0] == 4'b0111 & mem_hit)
-- PROCEDURES
begin
--************************************************* mem_wr;
.
.
.
.
procedure mem_wr is
end
//*****************************************************
.
.
procedure mem_rd is
// TASKS
//*****************************************************
.
.
begin
.
.
.
end
end task
task mem_wr;
if (framen = '0' and cben (3 downto 0) = "0111" and .
mem_hit = '1') then
task mem_rd;
mem_wr;
.
.
.
FILE IO
Altera Corporation
109
5
Appendix B
Upon reset, this section initializes the target transactor memory array with
the contents of the trgt_tranx_mem_init.dat file, which must be in the
project’s working directory. Each line in the trgt_tranx_mem_init.dat file
corresponds to a memory location and the first line corresponds to offset
"000". The number of lines defined by the address_lines parameter
in the target transactor source code should be equal to number of lines in
the trgt_tranx_mem_init.dat file. If the number of lines in
trgt_tranx_mem_init.dat file is less than the number of lines defined by
the address_lines parameter, the remaining lines in the memory array
are initialized to 0.
Appendix B—PCI Testbench
PCI32 Nios Target MegaCore Function User Guide
PROCEDURES or TASKS
The PROCEDURES section (VHDL) or the TASKS section (Verilog HDL)
define the events to be executed for the decoded PCI transaction. These
sections are fully documented in the source code. You can modify the
procedures or tasks to introduce different variations in the PCI
transactions as required by your application. You can also create new
procedures or tasks that are not currently implemented in the target
transactor by using the existing procedures or tasks as an example.
Bus Monitor
The bus monitor displays PCI transactions and information messages to
the simulator’s console window and in the log.txt file when an event
occurs on the PCI bus. The bus monitor also sends the PCI transaction
status to the master transactor. The bus monitor reports the following
messages:
■
■
■
■
■
■
Target retry
Target abort
Target terminated with disconnect-A (target terminated with data)
Target terminated with disconnect-B (target terminated without
data)
Master abort
Target not responding
The bus monitor reports the target termination messages depending on
the state of the trdyn, devseln, and stopn signals during a transaction.
The bus monitor reports a master abort if devseln is not asserted within
four clock cycles from the start of a PCI transaction. It reports that the
target is not responding if trdyn is not asserted within 16 clock cycles
from the start of the PCI transaction. You can modify the bus monitor to
include additional PCI protocol checks as needed by your application.
Clock Generator (clk_gen)
The clock generator, or clk_gen, module generates the PCI clock for the
testbench. This module generates a 66-Mhz clock if the
pciclk_66Mhz_enable parameter is set to true in the testbench toplevel file, otherwise, it generates a 33-Mhz clock. The default value of
pciclk_66Mhz_enable is true.
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PCI32 Nios Target MegaCore Function User Guide
GettingAppendix B—PCI Testbench
Pull Up
This module pulls up the ad, cben, framen, irdyn, trdyn, stopn,
devseln, perrn, and serrn signals of the PCI bus to weak high. This
action is necessary to ensure that these signals are never floating or
unknown during your simulation.
5
Appendix B
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Notes:
Appendix C—The Software
Example
6
Appendix C
This appendix walks you through the software example
(pci32_nios_target_api.c), describes its operation.
Directories
The inc and src directories, in the <cpu instance name>_sdk directory,
contain files associated with the software example.
Inc
The inc directory contains two include files, which are used by the
software example. The main file is called pci32_nios_target_api.h, the
secondary file is called pcihdr.h.
Pcihdr.h contains some references of all the company codes, PCI types
and subtypes. They are used to convert a hexadecimal number located at
some of the configuration registers of any PCI device into a company
name and its code class.
The pci32_nios_target_api.h file contains subroutines that you need to
access the bridge. Their aim is to eliminate the need to know the exact
transfer sequence between the Nios processor and the bridge when
transferring data or performing common setups (e.g., setting up the
interrupt register).
For more information on the functions, see “Appendix A—Nios
Application Programming Interface” on page 75.
Src
The wizard creates the software example into the src directory, when you
generate your system.
Walkthrough
The software example has two different modes of operation: an RTL
simulation mode, and a hardware mode. The software example only runs
a simple test that comprises the enumeration of all the PCI devices on the
bus and reports each vendor name and any other information.
1
Altera Corporation
The software example is only a guide; you can achieve many
other types of transfers if you modify it.
113
Appendix C—The Software Example
PCI32 Nios Target MegaCore Function User Guide
To run in the hardware mode, uncomment the line #define
HARDWARETEST 1.
1
If the statement is left commented, the Nios soft core
attempts to read and write to a memory located on the
target. It does not work in hardware unless you have such a
target.
The following section walks through the example and explains each part:
■
The following three define statements concern a target on the system
(e.g., a FLEX PCI Development Board connected to the PCI slot):
–
TARGET_BAR0—the base address of the memory mapped
memory. It is always mapped to BAR0
–
TARGET_BAR1—the base address of the I/O mapped memory.
It is always mapped to BAR1
–
TARGET_ID—the idsel number to which any target board
should answer. On the PCI32 Nios Target Adapter board, it is 30
(PMC slot) or 31 (PCI slot)
–
The next two statements concern the bridge:
–
NIOS_BAR0—the base address of the 2KB of memory that are
mapped for the bridge. It is always mapped to BAR0
–
NIOS_ID—the idsel number of the bridge. It is 11 in all
examples provided with the core
The example performs the following actions:
■
■
■
Prints a revision string
Configures the bridge (the configure_bridge function is near the
end of the file)
–
Reads its BAR0 value
–
Writes the value from the define back into that register
–
Reads BAR0 again, checking the value has been set
–
Reads the configuration register
–
Writes back to it, changing the bottom bits (enabling memory
access and I/O access)
–
Reads back for checking
Checks for the presence of PCI devices on the bus and reports them.
The enum_pci_bus puts the result of the search into a table called
device_number, which keeps track only of the present device and
stores its position
In hardware mode, the example reports the name of the vendor and type
of card for each device that was found. The relevant subroutines are at the
end of the file and use the pcihdr.h file to map the number to a name or
code class.
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Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
Appendix C—The Software Example
In simulation mode, the software example performs the following actions:
■
Configures the PCI target (a similar process to the
configure_target), and configures BAR1 on top of BAR0
Transfers data as according to the following order:
–
Set n_trans to a value. This is the length of the transfer (in cycles)
–
Generates a data table (d_val_t) for as many cycles as you have
to transfer
–
Writes the data
–
Reads back the data (which is stored in d_res_t)
–
Compares the data sent to the data read
The software example performs the data transfer for the following
functions:
■
■
■
■
■
■
Altera Corporation
Memory DWORD (1, 2, and 16 transfers)
Memory WORD (1, 2, and 16 transfers)
Memory BYTE (1, 2, and 16 transfers)
IO DWORD (1 transfer)
IO WORD (1 transfer)
IO BYTE (1 transfer)
115
Appendix C
■
6
Notes:
Appendix D—OpenCore
Plus Evaluation
This appendix covers the following topics:
About
OpenCore Plus
Hardware
Evaluation
About OpenCore Plus Hardware Evaluation
OpenCore Plus Licensing
Getting Started
7
The OpenCore Plus hardware evaluation versions of the MegaCore
functions are functionally equivalent to the standard versions, except:
■
The OpenCore Plus hardware evaluation versions operate for only a
predetermined number of clock cycles, after which the core is
disabled in a predefined manner.
■
One extra output signal, timed_out, switches from low to high
when the core has been disabled.
The time-out logic uses approximately 100 logic elements and runs at over
150 MHz. Therefore, it should not limit the performance of most designs.
MegaCore functions that support the OpenCore Plus hardware
evaluation feature have an additional library that contains the timelimited versions of all source files required for compilation. For this
reason, two sets of source files install in the installation directory for each
MegaCore function:
Altera Corporation
■
lib—Standard library, which contains source files for the standard
version of the core. This version is not time-limited; however, using
this library, you cannot generate programming files without first
purchasing a license.
■
lib_time_limited—Time-limited library, which contains time-limited
source files for the OpenCore Plus hardware evaluation version of the
core. This version times out after a predefined number of clock cycles.
You must obtain a free license from the Altera web site to use this
version for generating programming files.
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Appendix D
■
■
■
Appendix D—OpenCore Plus Evaluation
PCI32 Nios Target MegaCore Function User Guide
When you compile one or more time-limited MegaCore functions in your
design, the free OpenCore Plus license allows you to generate an SRAM
Object File (.sof). You can use the .sof to program an Altera device, but
only with the Quartus II Programmer and a download cable For more
information on the Quartus II Programmer, refer to the Quartus II Help.
After programming a device, the MegaCore function(s) operates normally
for a predetermined number of clock cycles, after which the output signals
from the function generate a constant known signal instead of their
designed functionality. When the function has timed-out, you must
reprogram or reconfigure the Altera device to reset the function and
continue hardware verification. Figure 32 shows the OpenCore Plus
design flow.
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Altera Corporation
PCI32 Nios Target MegaCore Function User Guide
Appendix D—OpenCore Plus Evaluation
Figure 32. OpenCore Plus Design Flow
Install the OpenCore Plus Hardware
Evaluation Version of the MegaCore
Function
Obtain a Free License from the Altera
Web Site to Enable the OpenCore
Plus Hardware Evaluation Versions
7
Set the Parameters of the Standard
Version Using the Wizard
Appendix D
Evaluate the Standard Version Using
the Quartus II Software
Simulate the Standard Version in
Third-Party RTL Simulation Software
Set the Parameters of the TimeLimited Version Using the Wizard
Compile the Design in the Quartus II
Software & Generate Programming
Files
Program/Configure the Devices with
the Time-Limited Programming Files
& Verify Operation
Purchase a License for the Standard
Version
Verify the Standard Version on the
Board & Ship the Product
OpenCore Plus
Licensing
You must request a license file from the Altera web site to enable the
OpenCore Plus feature. Your license file is sent to you via e-mail; follow
the instructions given in the e-mail to install the license.
1
The OpenCore Plus license allows you to generate programming
files, but does not allow you to generate Verilog HDL (.vo) or
VHDL (.vho) gate-level netlist files.
The license file enables the compilation of the time-limited versions in the
Quartus II software. After the license expires, you can obtain another
license file from the Altera web site and install it to continue compiling
time-limited versions.
Altera Corporation
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Notes: