NCO Compiler
MegaCore Function User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
2.0.2
Document Version:
2.0.2 rev. 1
Document Date: November 2002
Copyright
NCO Compiler MegaCore Function User Guide
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-NCOCPMPILER-2.2
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
NCO Compiler MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 9 for a complete list of the core features,
including new features in this release.
Refer to the NCO Compiler readme file for late-breaking information
that is not available in this user guide.
Table 1. User Guide Revision History
Date
Altera Corporation
Description
November 2002,
v2.0.2
Updated the screen shots. Made some formatting and
organization changes. Minor wording changes to several
sections.
July 2002
Minor modifications for v2.0.1 of the core. Core now displays
a single DSP Builder library for OpenCore® and
OpenCore Plus in the Simulink Library Browser.
May 2002
Updated functional description. Added DSP Builder,
OpenCore Plus, and licensing information. Removed
reference designs and replaced with example designs.
Updated all screen shots. Made formatting and organization
changes.
September 2001
Updated the screen shots and reference design figures. Made
some formatting and organization changes. Minor wording
changes to several sections.
April 2001
Updated the description of the NCO compiler installation
directory. Made minor text and formatting changes.
April 2000
Version 1.0 of the user guide.
iii
NCO Compiler MegaCore Function User Guide
How to Find
Information
Use the Adobe Acrobat Find feature to search the text of a PDF
document. Click the binoculars toolbar icon to open the Find dialog
box.
Bookmarks serve as an additional table of contents in PDF
documents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
■
■
■
■
How to Contact
Altera
About this User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For technical support on this product, go to
http://www.altera.com/mysupport. For additional information about
Altera products, consult the sources shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
About this User Guide
Typographic
Conventions
NCO Compiler MegaCore Function User Guide
The NCO Compiler User Guide uses the typographic conventions shown in
Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
NCO Compiler MegaCore Function User Guide
Abbreviations
& Acronyms
vi
AHDL
CORDIC
DSP
EAB
EDA
ESB
FSK
IF
IP
LE
NCO
PLD
PSK
QFSK
SFDR
SNR
About this User Guide
Altera hardware description language
coordinate rotation digital computer
digital signal processing
embedded array block
electronic design automation
embedded system block
frequency shift keying
intermediate frequency
intellectual property
logic element
numerically controlled oscillator
programmable logic device
phase shift keying
quaternary frequency shift keying
spurious free dynamic range
signal-to-noise ratio
Altera Corporation
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Abbreviations & Acronyms .......................................................................................................... vi
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 2.0.2 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
DSP Builder Support .............................................................................................................11
OpenCore & OpenCore Plus Hardware Evaluation .........................................................12
Performance ....................................................................................................................................13
Getting Started ............................................................................................................................................15
System Requirements ....................................................................................................................15
Design Flow ....................................................................................................................................15
Download & Install the Core ........................................................................................................16
Downloading the NCO Compiler MegaCore Function ...................................................16
Installing the NCO Compiler Files ......................................................................................17
NCO Compiler Directory Structure ....................................................................................18
Set Up Licensing .............................................................................................................................19
Append the License to Your license.dat File ......................................................................19
Specify the Core’s License File in the Quartus II Software ..............................................20
NCO Compiler Walkthrough .......................................................................................................20
Create a New Quartus II Project ..........................................................................................21
Launch the MegaWizard Plug-In Manager .......................................................................22
Specify Algorithm & Other Parameters ..............................................................................23
Specify Implementation ........................................................................................................24
View Resource Estimate ........................................................................................................27
Specify Simulation Output Files ..........................................................................................28
Using the MATLAB Model & Testbench ...................................................................................29
Using NCO Compiler with Simulink & DSP Builder ...............................................................30
Altera Corporation
vii
Contents
Simulate Using HDL Models .......................................................................................................31
VHDL Simulation in ModelSim Simulators ......................................................................31
Verilog HDL Simulation in ModelSim Simulators ...........................................................32
Verilog HDL Simulation in Verilog-XL ..............................................................................33
Compile & Place & Route the Design .........................................................................................33
Perform Synthesis Compilation & Post-Routing Simulation ..................................................34
Configuring a Device .....................................................................................................................35
Specifications ..............................................................................................................................................37
Introduction to NCOs ....................................................................................................................37
Spectral Purity ........................................................................................................................37
Output Frequency Bounds ...................................................................................................38
Functional Description ..................................................................................................................39
Architectures ...........................................................................................................................40
Large ROM Architecture ..............................................................................................40
Small ROM Architecture ...............................................................................................41
CORDIC Architecture ...................................................................................................41
Multiplier-Based Architecture .....................................................................................42
Frequency Modulation ..........................................................................................................43
Phase Modulation ..................................................................................................................43
Phase Dithering ......................................................................................................................43
Timing Diagrams ...................................................................................................................44
DSP Builder Feature & Simulation Support ......................................................................46
OpenCore Plus Time-Out Behavior ....................................................................................46
Core Verification ............................................................................................................................47
Signals ..............................................................................................................................................48
MegaWizard Plug-In .....................................................................................................................48
Example Designs ........................................................................................................................................49
Example Design 1 ..........................................................................................................................49
Example Design 2 ..........................................................................................................................50
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the NCO Compiler
MegaCore function.
Table 4. NCO Compiler Release Information
Item
Version
Description
2.0.2
Release Date
November 15, 2002
Ordering Code
IP-NCO
Product ID(s)
0014
Vendor ID(s)
6AF8 (Standard)
6AF9 (Time-Limited)
Device Family Support
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support.
■
■
■
Altera Corporation
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may
stillbe undergoing timing analysis for the device family; may be used
in production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
03_about_this_core.fm Page 10 Wednesday, January 22, 2003 2:01 PM
NCO Compiler MegaCore Function User Guide
About this Core
Table 5 shows the level of support offered to each of the Altera device
families by the NCO Compiler v2.0.2 MegaCore function.
Table 5. Device Family Support
Device Family
Support Level
Cyclone™
Full
Stratix™
Full
Stratix GX
Full
Mercury™
Full
Excalibur™
Full
HardCopy™
Full
ACEX® 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera® NCO Compiler MegaCore function generates numerically
controlled oscillators (NCOs) customized for Altera devices. You can use
the NCO Compiler wizard interface to implement a variety of NCO
architectures, including ROM-based, CORDIC-based, and multiplierbased. The wizard also includes time and frequency domain graphs that
dynamically display the functionality of the NCO based on your
parameter settings.
New in Version
2.0.2
■
■
Supports the Cyclone™ and Stratix™ GX device families
Support for MATLAB version 6.5 and Simulink version 5.0
Features
■
Optimized for multiple device architectures (Stratix, Mercury™,
Cyclone, APEX™ 20K, FLEX 10K, ACEX®, and FLEX® 6000)
Supports multiple NCO architectures:
–
Multiplier-based implementation using Stratix DSP blocks or
LEs (single cycle and multi-cycle)
–
Parallel/serial CORDIC-based implementation using logic
elements (LEs) with multiple pipeline levels
–
ROM-based implementation using device embedded array
blocks (EABs), embedded system blocks (ESBs), or external ROM
Supports single or dual outputs (sine/cosine)
Allows variable width frequency modulation input
Allows variable-width phase modulation input
■
■
■
■
10
Altera Corporation
About this Core
NCO Compiler MegaCore Function User Guide
■
■
General
Description
1
About this Core
■
User-defined frequency resolution, angular precision, and
magnitude precision
Generates simulation files
–
VHDL model and testbench
–
Verilog HDL model and testbench
–
MATLAB model and testbench
–
Quartus® II Vector Files
Includes dual-output oscillator and quaternary frequency shift
keying (QFSK) modulator example designs
A numerically controlled oscillator (NCO) synthesizes a discrete-time,
discrete-valued representation of a sinusoidal waveform. Designers
typically use NCOs in communication systems. In such systems, they are
used as quadrature carrier generators in I-Q mixers, in which baseband
data is modulated onto the orthogonal carriers in one of a variety of ways
(see Figure 1).
Designers also use NCOs in all-digital phase-locked-loops for carrier
synchronization in communications receivers, or as standalone frequency
shift keying (FSK) or phase shift keying (PSK) modulators. In these
applications, the phase or the frequency of the output waveform varies
directly according to an input data stream.
Figure 1. Simple Modulator
I
Constellation
Mapper
FIR
Filter
Q
cos(wt)
NCO
IF Signal
sin(wt)
FIR
Filter
You can use the NCO Compiler MegaCore function to create NCOs for
use in communications designs.
Altera Corporation
11
NCO Compiler MegaCore Function User Guide
About this Core
DSP Builder Support
DSP system design in Altera programmable logic devices requires both
high-level algorithms and HDL development tools. The Altera DSP
Builder, which you can purchase as a separate product, integrates the
algorithm development, simulation, and verification capabilities of The
MathWorks MATLAB and Simulink system-level design tools with
VHDL synthesis and simulation of Altera development tools.
DSP Builder allows system, algorithm, and hardware engineers to share a
common development platform. The DSP Builder shortens DSP design
cycles by helping you create the hardware representation of a DSP design
in an algorithm-friendly development environment. You can combine
existing MATLAB functions and Simulink blocks with Altera DSP Builder
blocks to link system-level design and implementation with DSP
algorithm development. The DSP Builder consists of libraries of blocks as
shown in Figure 2.
12
Altera Corporation
About this Core
NCO Compiler MegaCore Function User Guide
Figure 2. DSP Builder Blocks in Simulink Library Browser
1
About this Core
DSP Builder version 2.0.0 and higher provides modular support for Altera
DSP cores, including NCO Compiler. The MATLAB software
automatically detects cores that support DSP Builder and the cores appear
in the Simulink Library Browser.
f
For more information on using DSP Builder with NCO Compiler, see
“DSP Builder Feature & Simulation Support” on page 46.
OpenCore & OpenCore Plus Hardware Evaluation
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
Altera Corporation
13
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that include Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
1
f
If you are simulating a time-limited MegaCore function using
the DSP Builder and Simulink, i.e., in software, the core
operation does not time out.
For more information on OpenCore Plus hardware evaluation using
NCO Compiler, see “OpenCore Plus Time-Out Behavior” on page 46
and AN 176: OpenCore Plus Hardware Evaluation of MegaCore
Functions.
Performance
Table 6 provides performance statistics for the NCO function
implemented in a Stratix EP1S20F780C6 device.
Table 6. NCO Function Performance
Algorithm
Accumulator
Width
Angular
Precision
Magnitude
Precision
LEs
M4K RAM DSP Blocks
fMAX
Multiplier-Based
32
16
18
66
4
1
232.45
Small ROM
32
14
16
265
16
0
269.11
Parallel CORDIC
32
14
14
1,608
0
0
313.48
Large ROM
32
12
12
62
64
0
288.18
Getting Started
System
Requirements
■
A PC running the Windows 98/NT/2000 operating system.
■
Quartus II software version 2.0 or higher
■
The MATLAB software version 6.0 or higher (optional)
■
DSP Builder version 2.0 or higher (optional)
Once you have purchased a license for NCO Compiler, the design flow
involves the following steps:
1
Altera Corporation
2
Getting Started
Design Flow
The instructions in this section require the following minimum hardware
and software:
If you have not purchased a license, you can test-drive the core
for free using the OpenCore or OpenCore Plus feature. Refer to
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions
for more information on the OpenCore Plus feature.
1.
Build your system using MATLAB and Simulink.
2.
Download and install the NCO Compiler function.
3.
Set up licensing. This step is not required if you are test-driving the
core using the OpenCore feature, however, you do need to obtain
and install an OpenCore Plus license to test-drive the core using this
feature.
4.
Create a custom variation of the NCO Compiler using the core’s
wizard.
5.
Implement the rest of your system using the Altera Hardware
Description Language (AHDL), VHDL, Verilog HDL, or schematic
entry.
6.
Use the NCO Compiler wizard-generated simulation models to
confirm your custom core’s operation.
7.
Compile your design and perform place-and-route.
15
NCO Compiler MegaCore Function User Guide
Download &
Install the Core
Getting Started
8.
Perform system verification.
9.
Configure or program Altera devices with the design.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Downloading the NCO Compiler MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at http://www.altera.com. Follow the instructions
below to obtain the NCO Compiler via the Internet. If you do not have
Internet access, you can obtain the NCO Compiler from your local Altera
representative.
16
1.
Open your web browser and connect to
http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Signal Processing (DSP) from the Technology drop-down
list box.
4.
Type NCO Compiler in the Keyword Search box.
5.
Click Go.
6.
Click the link for the Altera NCO Compiler MegaCore function in
the search results table. The product description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
I Agree at the bottom of the page.
9.
Follow the instructions on the NCO Compiler download and
installation page to download the function and save it to your hard
disk.
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
Installing the NCO Compiler Files
To install the NCO Compiler, perform the following steps:
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The NCO Compiler Installation dialog box appears.
Follow the on-screen instructions to finish installation.
4.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically
<path>\nco_compiler-v2.0.2\lib) as a user library in the Quartus II
software to access the core in the MegaWizard Plug-In Manager.
Search for “User Libraries” in Quartus II Help for instructions on
how to add these libraries.
2
17
Getting Started
Altera Corporation
1.
NCO Compiler MegaCore Function User Guide
Getting Started
NCO Compiler Directory Structure
Figure 3 shows the directory structure for the NCO Compiler.
Figure 3. NCO Compiler Directory Structure
<path>/MegaCore/nco_compiler-v<version>
doc
Contains the NCO Compiler user guide (this document) in Adobe Acrobat Portable Document
Format (.pdf) as well as other documentation.
lib
Library folder for Quartus II synthesis. You should indicate this folder as a user library in the
Quartus II software before attempting to use the NCO Compiler.
lib_time_limited
Library folder for time-limited (OpenCore Plus) version of the core for Quartus II synthesis.
You should indicate this folder as a user library in the Quartus II software before attempting to
use the time-limited version of the NCO Compiler.
example_designs
Contains example design files for the NCO Compiler.
design1
Contains a dual-output oscillator example design.
design2
Contains a QFSK modulator example design.
sim_lib
Contains the simulation library files.
matlab
Contains the MATLAB libraries for simulation.
verilog
Contains the Verilog HDL libraries for simulation.
vhdl
Contains the VHDL libraries for simulation.
18
Altera Corporation
Getting Started
Set Up
Licensing
NCO Compiler MegaCore Function User Guide
You can use Altera’s OpenCore evaluation software to compile and
simulate the NCO Compiler MegaCore function in the Quartus II
software, allowing you to evaluate it before purchasing a license.
However, you must obtain a license from Altera before you can generate
programming files or EDIF, VHDL, or Verilog HDL gate-level netlist files
for simulation in third-party EDA tools.
1
If you want to use the OpenCore Plus feature, you must request a free
license file from the licensing page of the Altera web site
(http://www.altera.com/licensing) to enable it. Your license file is sent
to you via e-mail; follow the instructions below to install the license
file.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the NCO Compiler, you must
already have the Quartus II software installed on your PC, with
licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
Altera Corporation
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the NCO Compiler license file in a text editor. The file should
contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the NCO Compiler license file and
paste it into a new line in the Quartus II license file.
19
2
Getting Started
After you purchase a license for NCO Compiler, you can request a license
file from the Altera web site at http://www.altera.com/licensing and
install it on your PC. When you request a license file, Altera e-mails you a
license.dat file. If you do not have Internet access, contact your local
Altera representative.
NCO Compiler MegaCore Function User Guide
1
5.
Getting Started
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
NCO Compiler
Walkthrough
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
This walkthrough explains how to create an NCO using the Altera NCO
Compiler wizard and the Quartus II software. As you go through the
wizard, each page is described in detail. When you are finished generating
an NCO, you can incorporate it into your overall project.
You can use Altera’s OpenCore evaluation feature to compile and
simulate the MegaCore functions, allowing you to evaluate the NCO
Compiler before deciding to purchase a license. However, you must
purchase a license before you can generate programming files or EDIF,
VHDL, or Verilog HDL gate-level netlist files for simulation in third-party
EDA tools.
20
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
This walkthrough consists of the following steps:
■
■
■
■
■
■
“Create a New Quartus II Project” on page 21
“Launch the MegaWizard Plug-In Manager” on page 22
“Specify Algorithm & Other Parameters” on page 23
“Specify Implementation” on page 24
“View Resource Estimate” on page 27
“Specify Simulation Output Files” on page 28
Create a New Quartus II Project
2
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project. This walkthrough
uses the directory c:\qdesigns\nco_compiler-v2.0.2.
5.
Specify the name of the project. This walkthrough uses
nco_compiler-v2.0.2.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\nco_compiler-v2.0.2\lib\ (or <path>\nco_compilerv2.0.2\lib_time_limited\ to use the OpenCore Plus-capable
version) into the Library name box, where <path> is the directory in
which you installed the NCO Compiler. The default installation
directory is c:\MegaCore.
9.
Click Add.
10. Click OK.
Altera Corporation
21
Getting Started
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the NCO Compiler user library. To create a new
project, perform the following steps:
NCO Compiler MegaCore Function User Guide
Getting Started
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the NCO Compiler. The wizard lets you
specify the NCO precision, sinusoid generation, simulation files, etc.
Perform the following steps to launch the wizard and begin generating a
filter:
1.
Choose Tools > MegaWizard Plug-In Manager.
2.
Select Create a new custom megafunction variation (default).
3.
Click Next.
4.
Expand the Signal Processing folder under Installed Plug-Ins by
clicking the “+” next to the name.
5.
Expand the Signal Generation folder under Signal Processing.
6.
Click NCO Compiler v <version number> (either the standard
version or the time-limited one).
7.
Choose the device family you wish to target.
8.
Choose the output file type for your design; the MegaWizard Plug-In
Manager supports AHDL, VHDL, and Verilog HDL.
9.
Type the name of the output file (i.e., nco).
Figure 4 on page 23 shows the MegaWizard Plug-In Manager after
you have made these settings.
10. Click Next.
22
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
Figure 4. Choose NCO Compiler in the MegaWizard Plug-In Manager
2
Getting Started
You are now ready to set the options for your custom NCO Compiler.
Specify Algorithm & Other Parameters
Specify the NCO architecture parameters, including the generation
algorithm, precision, phase dithering, and output frequency. As you
adjust the NCO parameters, you can view the effects on the NCO
graphically in the Frequency Domain Response and Time Domain
Response tabs. See Figure 5.
The NCO Compiler wizard generated the spectral plot shown in Figure 5
by computing a 2,048-point FFT of bit-accurate time-domain data. Before
performing the FFT, the wizard windows the data using a Kaiser window
of length 2,048.
1
f
You can zoom by pressing the left mouse key on the plot and
drawing a box around the area of interest. Right-click the plot to
restore the view to its full range.
Refer to “Architectures” on page 40 and “Phase Dithering” on page 43 for
more information about these options.
When you are finished setting parameters, click the Implementation tab.
Altera Corporation
23
NCO Compiler MegaCore Function User Guide
Getting Started
Figure 5. Specify NCO Parameters
Specify Implementation
Specify the implementation settings for your custom NCO, including the
frequency modulation, phase modulation, outputs, and target device
family. For some algorithms, e.g., multiplier-based, you can also make
device-specific settings such as whether to implement the core in LEs or
other hardware. The Implementation tab displays the options that apply
to the algorithm you chose in the Parameters tab.
f
Refer to “Frequency Modulation” on page 43 and “Phase Modulation” on
page 43 for more information about these options.
Figure 6 shows the Implementation tab for the small and large ROM
algorithms.
24
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
Figure 6. Specify Implementation (Small & Large ROM Algorithms)
2
Getting Started
Figure 7 shows the Implementation tab for the CORDIC algorithm. You
can choose a parallel or serial CORDIC implementation and specify the
number of pipeline levels.
Altera Corporation
25
NCO Compiler MegaCore Function User Guide
Getting Started
Figure 7. Specify Implementation (CORDIC Algorithm)
Figure 8 shows the Implementation tab for the Multiplier-Based
algorithm. If you choose the multiplier-based algorithm and the Stratix
device family, you can use the dedicated Stratix DSP block circuitry to
implement the algorithm. If you choose multiplier-based and do not
target Stratix devices, the Quartus II software implements the NCO using
LEs.
26
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
Figure 8. Specify Implementation (Multiplier-Based Algorithm)
2
Getting Started
When you are finished setting parameters, click the Resource Usage tab.
View Resource Estimate
The NCO wizard dynamically estimates the resource usage of your
custom NCO based on the parameters you specify. See Figure 9.
When you are finished viewing the estimates, click the Simulation
Output tab.
Altera Corporation
27
NCO Compiler MegaCore Function User Guide
Getting Started
Figure 9. View Resource Estimate
Specify Simulation Output Files
Choose the simulation output files for the wizard to output. You can
choose Verilog HDL, VHDL, and MATLAB models and testbenches, as
well as Quartus II Vector Files. See Figure 10.
28
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
Figure 10. Specify Simulation Output Files
2
Getting Started
Click Next to view a summary of the files the wizard will generate.
Click Finish when you are done specifying parameters. The wizard
generates output files.
Once you have created an NCO function using the wizard, you can
simulate the simulation output files and/or integrate it into your design.
The wizard outputs a Text Design File (.tdf), VHDL Design File (.vhd), or
Verilog Design File (.v), and a Symbol File (.sym). You can use the
Quartus II software or other EDA tools to create your design.
Using the
MATLAB Model
& Testbench
Altera Corporation
If you turn on the MATLAB Simulation Model and Testbench option in
the wizard, the NCO Compiler outputs a bit-accurate MATLAB model
<variation name>.m, which you can use to model the behavior of your
custom variation in the MATLAB software. The model takes a vector of
phase increment values as input and outputs sine or sine and cosine
values as vectors, depending on whether you selected dual or single
output, respectively, in the wizard. The length of the output vector(s) is
equal to the length of the input phase increment vector. If you selected
frequency or phase modulation inputs in the wizard, they will also be
expected as input vectors by the MATLAB function.
29
NCO Compiler MegaCore Function User Guide
Getting Started
The wizard also creates the file <variation name>_tb.m. This file creates the
stimuli for the MATLAB model to generate waveforms with the frequency
you specified in the wizard, and plots the results in both the time and
frequency domains. You can modify this testbench to provide vector
stimuli as desired.
1
Spectral analysis is performed by windowing the data with a
2,048 length Kaiser window before performing a 2,048 point FFT.
The NCO Compiler wizard also integrates this type of spectral
analysis.
To model your NCO in the MATLAB software, perform the steps below.
1.
Run the MATLAB software.
2.
In the MATLAB Command Window, change to the working folder
for your project.
3.
Perform the simulation.
–
Type help <variation name> r at the command prompt to view
the input and output vectors that are required to run the
MATLAB model as a standalone M-function. Create your input
stimuli and make a function call to <variation name>.m. For
example:
phi = 276188392 * ones(1,2048) ;
[sinvalues,cosvalues] = <variation name>(phi);
or
–
f
Using NCO
Compiler with
Simulink &
DSP Builder
30
Run the provided testbench by typing the name of the testbench,
<variation name>_tb at the command prompt.
For more information on MATLAB and Simulink, refer to The Math
Works web site at http://www.mathworks.com.
You can use Simulink blocks, Altera DSP Builder blocks, and NCO
Compiler to build a model of your design in the Simulink software. Refer
to “DSP Builder Support” on page 11, “DSP Builder Feature & Simulation
Support” on page 46, and the DSP Builder User Guide for more
information.
Altera Corporation
Getting Started
Simulate Using
HDL Models
NCO Compiler MegaCore Function User Guide
This section describes the simulation process for the wizard-generated
VHDL and Verilog HDL simulation models.
VHDL Simulation in ModelSim Simulators
Altera provides a library of precompiled models that you can use to
simulate your NCO design with ModelSim simulators versions 5.5e or
higher. The precompiled library, nco_lib, is located in the directory
<installation path>\nco_compiler-v2.0.2\sim_lib\vhdl\modelsim.
2
Getting Started
If you turn on the VHDL Simulation Model and Testbench wizard
option, the NCO Compiler generates the files in Table 7:
Table 7. Wizard-Generated VHDL Simulation Files
File
Description
<variation name>_st_model.vhd
Top-level VHDL design file.
<variation name>_tb.vhd
VHDL testbench.
<variation name>_VHDL_tb.tcl
ModelSim tcl script to run the
simulation.
To simulate your design in VHDL in the ModelSim software perform the
following steps:
1.
Run the ModelSim software.
2.
Change to the project directory you specified in the NCO compiler
wizard.
3.
Choose Execute Macro (Macro menu).
4.
Select <variation name>_VHDL_tb.tcl and click Open.
The macro compiles the required design files from the library, simulates
the design, and outputs the results to the ModelSim Waveform viewer.
The results of the simulation are also output to the text files
fsin_o_vhdl_<variation name>.txt and fcos_o_vhdl_<variation name>.txt
for further analysis if desired.
Verilog HDL Simulation in ModelSim Simulators
Altera provides a library of precompiled models that you can use to
simulate your NCO design with ModelSim simulators versions 5.5e or
higher. The precompiled library, nco_lib_ver, is located in the directory
<installation path>\nco_compiler-v2.0.0\sim_lib\verilog\modelsim.
Altera Corporation
31
NCO Compiler MegaCore Function User Guide
Getting Started
If you turn on the Verilog HDL Simulation Model and Testbench wizard
option, the NCO Compiler generates the files in Table 8 for use with
ModelSim:
Table 8. Wizard-Generated Verilog HDL Simulation Files for ModelSim
File
Description
<variation name>_st_model.v
Top-level Verilog HDL design file.
<variation name>_tb.v
Verilog HDL testbench.
<variation name>_VGL_tb.tcl
ModelSim tcl script to run the simulation.
To simulate your design in VHDL in the ModelSim software on a PC
perform the following steps:
1.
Run the ModelSim software.
2.
Change to the project directory you specified in the NCO compiler
wizard.
3.
Choose Execute Macro (Macro menu).
4.
Select <variation name>_VGL_tb.tcl and click Open.
The macro compiles the required design files from the library, simulates
the design, and outputs the results to the ModelSim Waveform viewer.
The results of the simulation are also output to the text files
fsin_o_ver_<variation name>.txt and fcos_o_ver_<variation name>.txt for
further analysis if desired.
Verilog HDL Simulation in Verilog-XL
Altera also provides an encrypted Verilog-XL simulation library located
in the <installation path>\nco_compiler-v2.0.2\sim_lib\verilog\
verilogXL directory.
If you turn on the Verilog HDL Simulation Model and Testbench option
in the wizard, the NCO compiler generates the files in Table 9 for
Verilog-XL:
Table 9. Wizard-Generated Verilog HDL Simulation Files for Verilog-XL
File
32
Description
<variation name>_st_mdel_xl.v
Verilog-XL top-level model file.
<variation name>_tb.v
Verilog HDL testbench.
<variation name>_list.f
Verilog-XL file compilation list.
Altera Corporation
Getting Started
NCO Compiler MegaCore Function User Guide
To simulate your design in Verilog-XL, perform the following steps:
1.
Change to the project directory you specified in the NCO Compiler
wizard.
2.
Copy the files in the directory <installation path>\nco_compilerv2.0.2\sim_lib\verilog\verilogXL\nco_lib_ver to your project
directory.
3.
To run the provided testbench, type the following command at the
command prompt:
The simulation results are output to the text files fsin_o_ver_<variation
name>.txt and fcos_o_ver_<variation name>.txt for analysis.
Compile &
Place & Route
the Design
Perform
Synthesis
Compilation &
Post-Routing
Simulation
The following steps explain how to compile and simulate your design in
the Quartus II software, and how to use the test vector configuration file.
1.
Click on Processing > Start, and select Start Analysis and
Synthesis.
2.
Under Assignments > Settings > Simulator Settings, enter the
Modes and Simulator Options as desired. In the Source of Vector
Stimuli box, enter <variation name>.vec, or browse to select your
own stimuli file.
3.
Click on Processing > Run Simulation.
As a standard feature, Altera’s Quartus II software works seamlessly with
tools from all EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic.
1
After you have licensed the MegaCore function, you can use the
NativeLink™ feature to integrate the Quartus II software with
other EDA tools easily. See Quartus II Help for details.
The following sections describe the design flow to compile and simulate
your custom MegaCore design with the Quartus II software and a thirdparty EDA tool. To synthesize your design in a third-party EDA tool and
perform post-route simulation, perform the following steps:
1.
Altera Corporation
Create your custom design instantiating an NCO Compiler
MegaCore function.
33
Getting Started
Verilog <variation name>_tb.v -v <variation
name>_st_model_xl.v -v ./nco_lib_ver/220model.v -y
./nco_lib_ver/*.vp r
2
NCO Compiler MegaCore Function User Guide
2.
Getting Started
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the MegaCore instantiation as a black box by either
setting attributes or ignoring the instantiation.
1
For more information on setting compiler options in your
third-party EDA tool, refer to the Quartus II Nativelink
Guidelines.
3.
After compilation, generate a hierarchical netlist file in your thirdparty EDA tool.
4.
Open your netlist file in the Quartus II software.
5.
Specify the Compiler settings in the Assignments > Settings dialog
box, or use the Compiler Settings wizard.
6.
In the Settings dialog box, specify the user libraries for the project
and the order in which the Compiler searches the libraries.
7.
In the Settings dialog box, specify the EDA Tool Settings for the
project.
1
8.
In the EDA Tool Input Settings dialog box, make sure that the
relevant tool name or option is selected from the Design
Entry/Synthesis Tool list. Depending on the type of output file
you want, specify Verilog HDL output settings, or VHDL output
settings, and the simulation tool in the Simulation Tool Name list
Compile your design.
The Quartus II Compiler synthesizes and performs place-and-route
on your design, and generates the programming files.
9.
Configuring a
Device
34
Import your Quartus II-generated output files (.edo, .vho, .vo, or
.sdo) into your third-party EDA tool for post-route, device-level, and
system-level simulation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must license the function before
you can generate configuration files.
Altera Corporation
Specifications
Introduction to
NCOs
An NCO synthesizes a discrete-time, discrete-valued representation of a
sinusoidal waveform. There are many ways to synthesize a digital
sinusoid. For example, a popular method is to accumulate phase
increments to generate an angular position on the unit circle and then use
the accumulated phase value to form an address to a ROM look-up table
to perform the polar-to-cartesian transformation. You can reduce the
ROM size by using multipliers. Multipliers provide an exponential
decrease in memory usage for a given precision but require more logic.
When deciding which NCO implementation to use in programmable
logic, you should consider several factors, including the spectral purity,
frequency resolution, performance, throughput, and required device
resources. Often, you need to trade off between some or all of these
factors.
Spectral Purity
Typically, the spectral purity of an oscillator is measured by its signal-tonoise ratio (SNR) and its spurious free dynamic range (SFDR). The SNR of
a digitally synthesized sinusoid is a ratio of the signal power relative to
the unavoidable quantization noise inherent in its discrete-valued
representation. SNR is a direct result of the finite precision with which
NCO represents the output sine and cosine waveforms. Increasing the
output precision results in an increased SNR. The following equation
estimates the SNR of a given sinusoid with output precision b:
SNR = 6b – 1.8 (dB)
Each additional bit of output precision leads to an additional 6 dB in SNR.
Altera Corporation
35
3
Specifications
Another method uses the coordinate rotation digital computer (CORDIC)
algorithm to determine, given a phase rotation, the sine and cosine values
iteratively. The CORDIC algorithm takes an accumulated phase value as
input and then determines the cartesian coordinates of that angle by a
series of binary shifts and compares. In all methods, the frequency at
which the phase increment accumulates and the size of that input phase
increment relative to the maximum size of the accumulator directly
determines the normalized sinusoidal frequency.
NCO Compiler MegaCore Function User Guide
Specifications
The SFDR of a digital sinusoid is the power of the primary or desired
spectral component relative to the power of its highest-level harmonic
component in the spectrum. Harmonic components manifest themselves
as spikes or spurs in the spectral representation of a digital sinusoid and
occur at regular intervals and are also a direct consequence of finite
precision. However, the effect of the spurs is often severe because they can
cause substantial intermodulation products and undesirable replicas of
the mixed signal in the spectrum, leading to poor reconstruction of the
signal at the receiver.
The direct effect of finite precision varies between architectures, but the
effect is augmented because, due to resource usage constraints, the NCO
does not usually use the full accumulator precision in the polar-tocartesian transformation. You can mitigate truncation effects with phase
dithering, in which the truncated phase value is randomized by a
sequence. This process removes some of the periodicity in the phase,
reducing the spur magnitude in the sinusoidal spectrum by up to 12 dB.
To observe the effects of particular parameter settings, you must simulate
the MegaCore variation. The wizard’s spectral plot allows you to view the
effects as you change parameters without regenerating the wizard output
files and rerunning simulation.
Output Frequency Bounds
The maximum frequency sinusoid that an NCO can generate is bounded
by the Nyquist criterion to be half the operating clock frequency.
Additionally, the throughput affects the maximum output frequency of
the NCO. If the NCO outputs a new set of sinusoidal values every clock
cycle, the maximum frequency is the Nyquist frequency. If, however, the
implementation requires additional clock cycles to compute the values,
the maximum frequency must be further divided by the number of cycles
per output.
36
Altera Corporation
Specifications
Functional
Description
NCO Compiler MegaCore Function User Guide
The NCO Compiler allows you to generate a variety of NCO architectures.
You can create your custom NCO using a wizard-driven interface that
includes both time- and frequency-domain analysis tools. The custom
NCO outputs a sinusoidal waveform in two’s complement
representation.
The waveform for the generated sine wave is defined by the following
equation:
s ( nT ) = A sin ( 2π ( f O + f F M )nT + φPM + φ DIT H )
where:
■
■
■
Figure 11 shows a block diagram of a generic NCO.
Figure 11. Generic NCO Block Diagram
φ INC
φ FM
NCO
φ PM
sine
cosine
Internal Dither φDITH
The generated output frequency, fo for a given phase increment, φinc is
determined by the equation:
φinc f clk
f o = -----------------Hz
M
2
where M is the accumulator precision and fclk is the clock frequency of the
core in Hz.
Altera Corporation
37
3
Specifications
■
■
■
T is the operating clock period
fO is the unmodulated output frequency based on the input value
φINC
fFM is a frequency modulating parameter based on the input value
φFM
φPM is the phase modulation input value
φDITH is the internal dithering value
A is 2 N-1 where N is the magnitude precision
NCO Compiler MegaCore Function User Guide
Specifications
The minimum possible output frequency waveform is generated for the
case where φinc= 1. This case is also the smallest observable frequency at
the output of the NCO, also known as the frequency resolution of the NCO,
fres given in Hz by the equation:
f clk
- Hz
f r es = ------M
2
For example, if a 100 MHz clock drives an NCO with an accumulator
precision of 32 bits, the frequency resolution of the oscillator is 0.0233 Hz.
If you want an output frequency of 6.25 MHz from this oscillator, then you
should apply an input phase of
6
× 10 32
6.25
-----------------------× 2 = 268435456
6
100 × 10
as the input phase increment to the NCO. The NCO Compiler wizard
automatically calculates this value, given the parameters you choose. The
wizard also sets the value of the phase increment in all testbenches and
vector source files it generates.
The angular precision of an NCO is the phase angle precision before the
polar-to-cartesian transformation. The magnitude precision is the precision
to which the sine and/or cosine of that phase angle can be represented.
The effects of reduction or augmentation of the angular, magnitude,
accumulator precision on the synthesized waveform vary across NCO
architectures and for different fo/fclk ratios. You can view these effects in
the NCO Compiler wizard time and frequency domain graphs as you
change the NCO parameters.
Architectures
The NCO Compiler supports the large ROM, small ROM, CORDIC, and
multiplier-based architectures.
Large ROM Architecture
Use the large ROM architecture if your design requires very high speed
sinusoidal waveforms, and your design can use large quantities of
internal programmable logic device (PLD) memory. In this architecture,
the ROM stores the full 360 degrees of both the sine and cosine
waveforms. The output of the phase accumulator addresses the ROM.
38
Altera Corporation
Specifications
NCO Compiler MegaCore Function User Guide
Because the PLD’s internal memory holds all possible output values for a
given angular and magnitude precision, the generated waveform has the
highest spectral purity for that parameter set (assuming no dithering). The
large ROM architecture also uses the fewest logic elements (LEs) for a
given set of precision parameters.
Small ROM Architecture
Use the small ROM architecture if you cannot use a lot of PLD memory
but low LE usage and high output frequency are a high priority for your
system. In a small ROM architecture, the device memory only stores 45
degrees of the sine and cosine waveforms. All other output values are
derived from these values based on the position of the rotating phasor on
the unit circle.
Because a small ROM implementation is more likely to have periodic
value repetition, the resulting waveform’s SFDR is generally lower than
that of the large ROM architecture. However, you can often mitigate this
reduction in SFDR with phase dithering. See “Phase Dithering” on
page 41 for more information on this option.
The CORDIC algorithm, which can calculate trigonometric functions such
as sine and cosine, provides a high-performance solution for very-high
precision oscillators in systems in which internal PLD memory is at a
premium. The CORDIC algorithm is based on the concept of complex
phasor rotation by multiplication of the phase angle by successively
smaller constants. In digital hardware, the multiplication is by powers of
two only. Therefore, the algorithm can be implemented efficiently by a
series of simple binary shift and additions/subtractions.
In an NCO, the CORDIC algorithm must compute the sine and cosine of
an input phase value by iteratively shifting the phase angle to
approximate the cartesian coordinate values for the input angle. At the
end of the CORDIC iteration, the x and y coordinates for a given angle
represent the cosine and sine of that angle, respectively. See Figure 12.
Altera Corporation
39
Specifications
CORDIC Architecture
3
NCO Compiler MegaCore Function User Guide
Specifications
Figure 12. CORDIC Rotation for Sine & Cosine Calculation
y
dy
sin ø
x
dx
With the NCO Compiler, you can choose between serial and parallel
CORDIC architectures. You an use the parallel CORDIC architecture to
create a very high-performance, high-precision oscillator—implemented
entirely in LEs—with a throughput of one output sample per clock cycle.
You can trade off the performance, resource usage, and initial latency
using the wizard’s pipeline parameter.
The serial CORDIC architecture uses fewer resources than the parallel
CORDIC. However, its throughput is reduced by a factor equal to the
magnitude precision. For example, if you select a magnitude precision of
N bits in the wizard, the output sample rate and the Nyquist frequency is
reduced by a factor of N. This architecture is implemented entirely in LEs
and is useful if your design requires low frequency, high precision
waveforms.
Multiplier-Based Architecture
The multiplier-based architecture uses multipliers to reduce memory
usage. You can choose to implement the multipliers in dedicated
multiplier circuitry in device families that support this feature. You
always have the option to implement the multipliers in logic elements.
The wizard also provides an option to reduce the throughput by a factor
of two in a dual-output NCO. This setting halves the resources required
by the waveform generation unit, and the NCO outputs a sample every
two clock cycles.
40
Altera Corporation
Specifications
NCO Compiler MegaCore Function User Guide
Frequency Modulation
In the NCO Compiler wizard, you can add an optional frequency
modulator to your custom NCO variation. You can use the frequency
modulator to vary the oscillator output frequency about a center
frequency set by the input phase increment. This option is useful for
applications in which the output frequency is tuned relative to a freerunning frequency, for example in all-digital phase-lock-loops.
You can also use the frequency modulation input to switch the output
frequency directly, for example, to implement frequency shift keying
(FSK) modulators like the quaternary FSK modulator in “Example Design
1” on page 49. You can set the frequency modulation resolution input in
the wizard; it must be less than or equal to the phase accumulator
precision. The NCO Compiler also provides an option to increase the
modulator pipeline level; however, the effect of the increase on the
performance of the NCO varies across NCO architectures and variations.
Phase Modulation
Phase Dithering
All digital sinusoidal synthesizers suffer from the effects of finite
precision, which manifests itself as spurs in the spectral representation of
the output sinusoid. Because of angular precision limitations, the derived
phase of the oscillator tends to be periodic in time and contributes to the
presence of spurious frequencies. You can reduce noise at these
frequencies by introducing a random signal of suitable variance into the
derived phase, thereby reducing the likelihood of identical values over
time. Adding noise into the data path raises the overall noise level within
the oscillator, but tends to reduce the noise localization and can provide
significant improvement in SFDR.
Altera Corporation
41
3
Specifications
You can use the wizard to add an optional phase modulator to your NCO
variation, allowing dynamic phase shifting of the NCO output
waveforms. This option is particularly useful if you want an initial phase
offset in the output sinusoid. You can also use the option to implement
efficient phase shift keying (PSK) modulators in which the input to the
phase modulator varies according to a data stream. You set the resolution
and pipeline level of the phase modulator in the wizard. The input
resolution must be greater than or equal to the specified angular precision.
NCO Compiler MegaCore Function User Guide
Specifications
The extent to which you can reduce spur levels is dependent on many
factors. The likelihood of repetition of derived phase values and resulting
spurs, for a given angular precision, is closely linked to the ratio of the
clock frequency to the desired output frequency. An integral ratio clearly
results in high-level spurious frequencies, while an irrational relationship
is less likely to result in highly correlated noise at harmonic frequencies.
The Altera NCO Compiler allows you to finely tune the variance of the
dither sequence for your chosen algorithm, specified precision, and clock
frequency to output frequency ratio, and dynamically view the effects on
the output spectrum graphically. See “Example Design 1” on page 49 for
an example using phase dithering and its effect on the spectrum of the
output signal.
Timing Diagrams
Figure 13 shows a timing diagram with a single clock cycle per output
sample. All NCO architectures—except serial CORDIC and multi-cycle
multiplier-based architectures—output a sample every clock cycle. After
the clock enable is asserted, the oscillator outputs the sinusoidal samples
at a rate of 1 sample per clock cycle, following an initial latency of L clock
cycles. The exact value of L varies across architectures and
parameterizations.
42
Altera Corporation
Specifications
NCO Compiler MegaCore Function User Guide
Figure 13. Single-Cycle per Output Timing Diagram
clk
reset
clken
phi_inc_i 268435456
0
fsin_o
126
fcos_o
48
89 116 126 116
116 89 48
0
89 48
0
-49 -90
-49 -90
-90 -49
-90 -49
0
48
0
89 116 126
Figure 14 shows the timing diagram for a 2-cycle multiplier-based NCO
architecture. After the clock enable is asserted, the oscillator outputs the
sinusoidal samples at a rate of 1 sample for every 2 clock cycles, following
an initial latency of L clock cycles. The exact value of L depends on the
parameters that you set.
Figure 14. 2-Cycle Multiplier-Based Architecture Timing Diagram
clk
reset
clken
phi_inc_i 268435456
0
fsin_o
0
fcos_o
48
126
116
89
89
116
126
48
0
116
-49
89
48
0
-49
-90
-90
-117
-127
-117
-90
-49
Figure 15. Serial CORDIC Timing Diagram
clk
reset
clken
phi_inc_i
fsin_o
fcos_o
268435456
0
127
Altera Corporation
127
1
49
90
116
126
116
89
49
-1
-49
126
116
89
49
-1
-49
-90
-116
-126
-116
43
Specifications
Figure 15 shows the timing diagram for a serial CORDIC NCO
architecture. After the clock enable is asserted, the oscillator outputs
sinusoidal samples at a rate of 1 sample per N clock cycles, where N is the
magnitude precision set in the wizard. There is also an initial latency of L
clock cycles; the exact value of L depends on the parameters that you set.
Figure 15 shows the case where N = 8.
3
NCO Compiler MegaCore Function User Guide
Specifications
DSP Builder Feature & Simulation Support
You can create Simulink Model Files (.mdl) using NCO Compiler and DSP
Builder blocks. DSP Builder supports all NCO Compiler options.
After you create your model, you can perform simulation. DSP Builder
supports the simulation types shown in Table 10 for NCO Compiler.
Table 10. NCO Compiler Simulation File Support in DSP Builder
Simulation Type
Simulation Flow
Precompiled ModelSim model
for RTL functional simulation
The DSP Builder SignalCompiler block generates a ModelSIm Tcl script and a
VHDL testbench on-the-fly.
VHDL Output File (.vho) models You can generate a .vho after you have purchased a license for your
for timing simulation
MegaCore function. Refer to the “VHDL Output File (.vho)“ topic in Quartus II
Help for more information.
Visual IP Models
Not Supported
Quartus II simulation
The DSP Builder SignalCompiler block generates a Quartus II simulation
vector file on-the-fly.
1
f
If you are using the time-limited version of the NCO Compiler in
your Model File, simulation does not time out. The core only
times out if you are performing hardware evaluation as
described in “OpenCore Plus Time-Out Behavior” on page 44.
For more information on DSP Builder, see “DSP Builder Support” on
page 11.
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
■
fsin_o is driven low
fcos_o is driven low
timed_out is driven from low to high
A time-limited NCO Compiler runs for approximately 30 minutes for a
150 MHz clock (exactly 270,000,000,000 clock cycles of the clock input
clk).
f
44
For more information on OpenCore Plus hardware evaluation, see
“OpenCore & OpenCore Plus Hardware Evaluation” on page 12 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
Altera Corporation
Specifications
NCO Compiler MegaCore Function User Guide
Core
Verification
Before releasing a version of the NCO Compiler, Altera runs a
comprehensive regression test that executes the wizard to create the
instance files. Next, Verilog HDL and VHDL testbenches are created and
the results are compared to the MATLAB software using ModelSim
simulators to exercise the Verilog HDL and VHDL models.
The regression suite covers various parameters such as architecture
options, frequency modulation, phase modulation, and precision.
Figure 16 shows the regression flow.
Figure 16. Regression Flow
Perl
Script
Parameter
Sweep
Compare
Results
NCO Compiler
Wizard
3
Altera Corporation
MATLAB
Verilog HDL
VHDL
Synthesis
Structure
Output
File
Output
File
Output
File
Output
File
Specifications
Testbench
All Languages
45
NCO Compiler MegaCore Function User Guide
Signals
Specifications
The NCO Compiler function has the signals shown in Table 11.
Table 11. NCO Compiler Signals
Signal
MegaWizard
Plug-In
Direction
Description
clk
Input
Clock.
reset
Input
Active-high reset.
clken
Input
Active high clock enable.
phi_inc_i
Input
Input phase increment. Set the precision in the
wizard.
freq_mod_i
Input
(optional) Frequency modulation input. Set the
precision in the wizard.
phase_mod_i
Input
(optional) Phase modulation input. Set the precision
in the wizard.
fsin_o
Output
Output sine value. Set the precision in the wizard.
fcos_o
Output
Output cosine value. Set the precision in the wizard.
timed_out
Output
Signal used for OpenCore Plus hardware
evaluation.
You can launch the MegaWizard Plug-In Manager from within the
Quartus II software, or you can run it from the command line. The NCO
Compiler wizard generates an instance of the megafunction that you can
instantiate in your design. When you finish going through the wizard, it
generates the following files:
■
■
■
■
■
AHDL Text Design File (.tdf), VHDL Design File (.vhd), or Verilog
Design File (.v) used to instantiate an instance of the NCO function in
your design
Symbol File (.sym) used to instantiate the function into a schematic
design
MATLAB models that you can use to simulate the NCO functionally
Verilog HDL testbench used for simulation
VHDL testbench and top-level simulation design file
The wizard-generated testbenches use the specified desired clock and
output frequencies.
46
Altera Corporation
Example Designs
Example
Design 1
Example design 1 is a high-precision, dual-output oscillator for use in an
intermediate frequency (IF) I-Q modulator. The design targets the Altera
EP1S20F780C6 Stratix device. The top-level design file is <installation
directory>\nco_compiler-v2.0.2\example_designs\design1\
design1.bdf. The oscillator meets the following specifications:
■
■
■
■
SFDR: 110 dB
Output Sample Rate: 200 MSPS
Output Frequency: 21 MHz
Frequency Resolution: 0.05 Hz
To meet these requirements, the design uses the following wizard
settings:
Multiplier-based algorithm—By using the dedicated multiplier
circuitry in Stratix devices, the NCO architectures that implement
this algorithm can provide very high performance.
■
Clock rate of 200 MHz and 32-bit phase accumulator precision—These
settings yield a frequency resolution of 46 mHz.
■
Angular and magnitude precision—These settings are critical to meet
the SFDR requirement, while minimizing the required device
resources. Setting the angular precision to 17 bits and the magnitude
precision to 18 bits results in the spectrum shown in Figure 17 (“After
Setting Angular & Magnitude Precision” plot).
■
Dither level—The angular and magnitude precision settings described
above yield an SFDR of approximately 102.8 dB, which is clearly not
sufficient to meet the specification. Using the dither control in the
wizard, the variance of the dithering sequence is increased until the
trade-off point between spur reduction and noise level augmentation
is reached for these particular clock-frequency to output frequency
ratio and precision settings as shown in Figure 17 (“Altera Addition
of Dithering” plot). At a dithering level of 5, the SFDR is
approximately 111.95 dB, which exceeds the specification.
47
4
Example
Designs
Altera Corporation
■
NCO Compiler MegaCore Function User Guide
Example Designs
Figure 17. Angular & Magnitude Precision & Dithering
After Setting Angular & Magnitude Precision
Example
Design 2
After Addition of Dithering
Example design 2 is a quaternary frequency shift keying (QFSK)
modulator for use in a hypothetical transmitter design. The design targets
the Altera EP1S20F780C6 Stratix device. In this type of modulator, the
output frequency of the oscillator varies according to an input symbol
stream, the values of which map to a four-symbol alphabet. The top-level
design file is <installation directory>\nco_compilerv2.0.2\example_designs\design2\design2.bdf. The oscillator meets the
following specifications:
■
■
■
■
SFDR: 80 dB
Output Frequencies:
–
fc - 5.76 MHz
–
fc - 1.92 MHz
–
fc + 1.92 MHz
–
fc – 5.76 MHz
Output Sample Rate: 220 MSPS
Frequency Resolution: 0.06 Hz
Where fc is the free-running output frequency of the NCO.
Table 12 shows the mapping of the symbols to output frequencies,
assuming that the free-running frequency is set to 15.36 MHz by setting
the phase increment of the oscillator to 299866808.
48
Altera Corporation
Example Designs
NCO Compiler MegaCore Function User Guide
Table 12. Symbol Mapping
Binary Symbol
Frequency Modulation Value
10
4182517243
Output Frequency (MHz)
9.60
11
4257483945
13.44
01
37483351
17.28
00
112450053
21.12
To meet these requirements, the design uses the following wizard
settings:
■
Parallel CORDIC algorithm—In the overall hypothetical design, other
system blocks use much of the Stratix device’s internal memory and
DSP blocks; however, logic elements (LEs) are in abundant supply.
The need for a high precision, high performance oscillator that uses
Logic Elements only makes the Parallel CORDIC algorithm a suitable
choice.
■
Phase accumulator precision—The frequency resolution specifications
demand a phase accumulator precision of 32 bits.
■
Frequency modulator precision—To maximize the frequency resolution
of the modulating signal, the resolution of the frequency modulator
is also set to 32 bits of precision.
■
Angular and magnitude precision and dithering—An angular precision
of 14 bits, a magnitude precision of 14 bits, and a dithering level of 8
meet the requirements of 80 dB SFDR for the four possible output
frequencies as shown in Figure 18.
4
Reference
Designs
Altera Corporation
49
NCO Compiler MegaCore Function User Guide
Example Designs
Figure 18. Output Frequencies
Figure 19 shows a segment of the resulting FSK modulated waveform in
the time-domain.
50
Altera Corporation
Example Designs
NCO Compiler MegaCore Function User Guide
Figure 19. FSK Modulated Waveform
4
Reference
Designs
Altera Corporation
51