Excalibur
Stripe Simulator
User Guide
April 2003
Version 1.5
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
UG-EXCFSSIM-1.5
Excalibur Stripe Simulator User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
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About this User Guide
This user guide provides comprehensive information about the Altera®
Excalibur™ Stripe Simulator (ESS).
Table 1 shows the user guide revision history.
Table 1. User Guide Revision History
Date
How to Find
Information
April 2003
Changes to the Solaris environment variables.
October 2002
Changes to the UART connection port number
and the ESS version text (upgrade to 2.2).
September 2002
Amendments to emphasize using VHDL 93
syntax.
August 2002
Amendments to include debugging with Solaris.
June 2002
Minor amendments; inclusion of Mentor Graphics®
XRAY debugger.
April 2002
Version 1.0 release.
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About this User Guide
Excalibur Stripe Simulator User Guide
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Altera Literature
Services
Access
Electronic mail
Non-technical
Telephone hotline
customer service
Fax
Technical support Telephone hotline
Fax
General product
information
USA & Canada
All Other Locations
[email protected] (1)
[email protected] (1)
(800) SOS-EPLD
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7606
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Pacific Time)
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Note:
(1)
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You can also contact your local Altera sales office or sales representative.
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Excalibur Stripe Simulator User Guide
Typographic
Conventions
About this User Guide
The Excalibur Stripe Simulator User Guide uses the typographic conventions
shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Help topics are shown in
quotation marks. Example: “Configuring a Device with the Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
ESS Walkthrough ..........................................................................................................................................9
Introduction ......................................................................................................................................9
Features ...........................................................................................................................................10
Platform & Tool Support ..............................................................................................................10
Memory Initialization ....................................................................................................................11
ARM922T Processor Model ..................................................................................................12
PLD Interface ..........................................................................................................................12
Stripe Functionality ...............................................................................................................13
Using ESS as an Instruction Set Simulator .................................................................................13
Simulation Model Configuration Options .........................................................................14
Debugging a Program Using AXD ......................................................................................16
Debugging a Program using GDB with Insight Interface ................................................23
Using ESS in a Third-Party Logic Simulator ..............................................................................25
Simulating a Design Using ESS ...........................................................................................26
Using a Software Debugger in a Third-Party Logic Simulation Environment .....................30
Setting Up ModelSim ............................................................................................................31
Connecting AXD to ESS in ModelSim ................................................................................33
Connecting the GDB Debugger to ESS in ModelSim .......................................................35
Pins & Signals Supported by ESS ................................................................................................36
Excalibur Stripe Registers Supported by ESS ............................................................................39
Appendix A
Generating Input Files ..............................................................................................................................41
Appendix B
Trace Output Format ..................................................................................................................................43
Trace Level 1 ...................................................................................................................................43
Trace Level 2 ...................................................................................................................................44
Trace Level 3 ...................................................................................................................................44
Appendix C
ESS Version Changes ...............................................................................................................................45
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Notes:
ESS Walkthrough
Introduction
The Excalibur Stripe Simulator (ESS) is a fast stripe simulation model
developed specifically to facilitate the integration of software and
hardware in Excalibur devices. ESS can execute more than 500,000 ARM
instructions per second on a high-performance PC, with high visibility of
the internal processor and stripe registers, PLD-to-stripe and stripe-toPLD bus transactions.
ESS emulates the key functional behavior of the embedded stripe, which
allows you to run operating system applications.
ESS, which is supplied with the Quartus® II software version 2.1 or later,
can be used in three ways:
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For software simulation—you can use the model as an instruction set
simulator, connecting to a software debug tool with full debug
capabilities. In addition, you can easily pipe the character stream
output from the stripe UART to a terminal window, such as telnet.
For hardware simulation—you can instantiate the model in a hardware
design for simulation in a third-party logic simulator, such as the
Model Technology™ ModelSim® simulation tool, to model the
ARM922T™ embedded processor, the stripe peripherals, the stripe
bridges, and the PLD application interface. To instantiate the model
within a design, you use alt_exc_stripe from the library of
parameterisable modules (LPM).
For software/hardware co-simulation—you can connect a software
debugger to the software running on the model's embedded
processor while simulating the hardware design in a third-party logic
simulator.
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ESS Walkthrough
Features
Excalibur Stripe Simulator User Guide
ESS provides the following functionality:
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■
■
A functionally-accurate model of the ARM 922T™ processor
Models the watchdog timer, timer, and interrupt controller
Embedded UART modeled as a character stream device
1
■
■
■
■
■
A mechanism to connect the UART to a terminal window is
provided.
Models the interface to the PLD through the stripe-to-PLD bridge,
PLD-to-stripe bridge, and the PLD application interface
Mechanism to load a flash memory image connected to EBI0 (booting
from flash memory)
Fast mechanism to initialize on-chip SRAM and stripe registers
Interface to appropriate software debuggers according to the
platform used (see Table 4)
Instantiation within a Verilog HDL or VHDL design
See “Pins & Signals Supported by ESS” and “Excalibur Stripe Registers
Supported by ESS” for lists of the stripe registers and pins that ESS
supports.
Platform & Tool
Support
ESS supports the software debug and HDL simulation tools listed in
Table 4.
Table 4. Platforms & Tools Supported by ESS
Platform
10
HDL Simulation Environment
®
Software Debugger
PC
(Windows)
ModelSim Altera Edition, PE for
Verilog HDL designs
ModelSIm SE for Verilog HDL or
VHDL designs
ARM Developers Suite (ADS)
debuggers AXD, ADW
Mentor Graphics® XRAY
debugger
GNU debugger arm_elf_gdb
Solaris
ModelSim® Altera Edition, PE for GNU debugger arm_elf_gdb
Verilog HDL designs
ModelSIm SE for Verilog HDL or
VHDL designs
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Excalibur Stripe Simulator User Guide
Memory
Initialization
ESS Walkthrough
There are two means of initializing ESS:
■
■
Booting from flash memory
Fast initialization of the stripe memory image
Booting from Flash Memory
To simulate booting from flash memory, you need to generate a flash
memory image. The image is an Intel hex format file, which can be
identical to that required to program the flash memory on the EPXA10
development board.
1
When booting from flash memory, a temporary view of the first
32 Kbytes of flash memory is available to allow boot code to
remap the EBI0 memory region to a different address and size in
the address space. For details, see the Quartus II software help
pages on generating a flash memory image, and Appendix A
Generating Input Files.
Fast Initialization of the Stripe Memory Image
Fast initialization of the stripe memory image allows you to initialize
stripe registers and on-chip SRAM without having to simulate running
the boot code. This is consistent with the cycle-accurate full stripe model.
Five initialization files are used. They share a common filename prefix and
use specific extensions, as described in Table 5.
Table 5. Memory Initialization Files
Filename Extension
File Contents
.regs
Embedded stripe register values
.sram0
Memory image representing SRAM0 contents
.sram1
Memory image representing SRAM1 contents
.dpram0
Memory image representing DPRAM0 contents
.dpram1
Memory image representing DPRAM1 contents
1
One of the on-chip SRAM memory regions must be mapped to
physical address 0x0 in the address space. This is because the
ARM922T processor begins execution from address 0x0.
The initialization files can be generated by using either software mode in
the Quartus II software, or the command line utility makeprogfile. See
Appendix A Generating Input Files, for more information.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
ARM922T Processor Model
The ESS model emulates, with functional accuracy, the operation of all 16bit and 32-bit ARM® instructions, all operating modes, and all exceptions.
The memory management unit is modeled to provide the functionality
required to run an operating system using the simulator. However, cache
memory is not modeled.
1
The ARM922T five-stage pipeline is modeled as a flattened,
three-stage pipeline (the execute, memory, and write-back stages
have been merged into one execute stage), with each instruction
executing in one cycle. A model of the pipeline is provided to
allow the ARM code to remap its own memory—the instruction
after the remapping, which has already been fetched and is in the
pipeline, can jump to the next instruction in the remapped
memory.
ESS terminates when all of the following conditions are satisfied:
■
■
■
The ARM processor is executing a branch-to-self instruction
Processor interrupts are disabled
ESS is run from the command line
PLD Interface
ESS provides support for the following modules:
■
■
The PLD application interface to the DPRAM blocks embedded in the
stripe. All DPRAM operation modes are supported
The PLD-to-stripe and stripe-to-PLD bridges
1
■
Posted writes are not modeled
Interrupts, including int_pld, int_timer, and int_uart
When you use ESS as an instruction set simulator outside a logic
simulation environment, writes to the PLD memory region are discarded,
and memory reads return undefined values.
Within a logic simulation environment, you can instantiate the model in a
hardware design using alt_exc_stripe from the LPM by compiling the
wrapper files: alt_exc_stripe_ess.v and ess_hdl.v for Verilog HDL
designs; or alt_exc_stripe_ess.vhd and ess_hdl.vhd for VHDL designs.
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Excalibur Stripe Simulator User Guide
1
ESS Walkthrough
ESS and the PLD are simulated asynchronously, i.e., the ratios
between PLD clock domains and the stripe clock domains
(AHB1 and AHB2) are not honored. This is to allow the ARM
processor in the embedded stripe to execute large fragments of
code without being delayed by the simulation of logic in the PLD
unless there is stripe-to-PLD interaction. When AHB
transactions occur, the stripe and PLD are synchronized to
prevent wait cycles from being inserted.
Stripe Functionality
ESS represents the relative clock domains associated with AHB1 and
AHB2. The model is not cycle-accurate, in that it does not model bus
delays or delays associated with accessing different memory types.
The watchdog timer, timer, and interrupt controller embedded stripe
peripherals are modeled with full functional accuracy. The embedded
UART is modeled as a character stream device, providing a mechanism to
connect the UART’s input and output to a terminal window, which allows
you to run interactive programs.
Using ESS as
an Instruction
Set Simulator
ESS can be used as an instruction set simulator by either running it from
the command line or by using a graphical user interface (GUI) in
conjunction with one of the following debuggers with debug control:
■
■
On either PC or Solaris platforms:
–
GNUPro Tools for ARM debugger, GDB
On PC platforms only:
–
ADS 1.1 debugger, AXD
–
ADS 1.1 debugger, ADW
–
Mentor Graphics® debugger, XRAY for Excalibur
To use ESS, you must always select a memory image. Because the
processor subsystem always starts execution at address 0x0, you can
provide either a flash memory image in Intel hex format or a set of
memory initialization files—see Appendix A Generating Input Files for
details.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
Simulation Model Configuration Options
When you run ESS in a Command Prompt window, typing ess -hr at
the command line displays usage parameters as presented below.
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
--- Help Message ---
Usage:
ess [options] -bf<flash memory image.hex>
ess [options] -fm<basename>
where
-bf
Boot from flash - specify Intel hex format file (flash memory contents)
-fm
Fast memory intialisation - specify filename body
(.regs .sram0 .sram1 .dpram0 & .dpram1 files are generated by ’makeprogfile’)
Options:
-c
Specify Excalibur chip type (xa10|xa4|xa1) (default: xa10)
-d0<dp0_mode>[r]
Specify dpram0 mode as UNUSED | 1xSPx32 | 1xSPx16 | 1xSPx8 |
2xSPx16 | 2xSPx8 | 1xDPx16. (default: 1xSPx32)
Register output by appending r. For example: -d01xSPx32r
-d1<dp1_mode>[r]
Specify dpram1 mode as UNUSED | 1xSPx32 | 1xSPx16 | 1xSPx8 |
2xSPx16 | 2xSPx8 | 1xDPx16. (default: 1xSPx32)
Register output by appending r. For example: -d11xSPx32r
-dc<dp_combined>[r]
Specify dpram combined mode as COMBINEDx64 | COMBINEDx32 |
COMBINEDx16 | COMBINEDx8. Register output by appending r.
Combined mode cannot be used with -d0 and -d1 options.
For example: -dcCOMBINEDx32r
-e<b|l>
Specify processor endianness as big <b> or little <l> (default: little)
-g[port number]
Connect SW debugger via TCP/IP - specify port number
(default: 9998)
-k[term. emulator]
Spawn a terminal emulator to connect to UART
(default: telnet)
-m[port number]
Use UART - connect terminal emulator, specified using
-k option, via TCP/IP port (default: 9001)
-t1[output file]
Enable trace mode for processor & stripe registers
-t2[output file]
Enable trace mode for processor registers only
-t3[output file]
Enable trace mode for stripe registers only
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Excalibur Stripe Simulator User Guide
ESS Walkthrough
Table 6 lists the GUI and command line equivalents for each parameter
used to run ESS as an instruction set simulator.
Table 6. Configuration Options for Using ESS as an Instruction Set Simulator
AXD/ADW/GDB
Option
Command Line
Option
Description
Connect to logic
simulator
N/A
Turn on Connect to logic simulator only when connecting to ESS running
in a logic simulator (ModelSim simulation tool). When Connect to logic
simulator is turned on, all other standard options are not selectable because
they are specified through the logic simulation environment. See “Using a
Software Debugger in a Third-Party Logic Simulation Environment” on page
30.
Chip type
–c<xa10> |
–c<xa4> |
–c<xa1>
Select from XA10, XA4 or XA1 Excalibur devices. Default XA10.
Memory initialization Boot from flash
–bf<filename>
Select an Intel Hex file containing the flash memory image.
Memory initialization Fast memory
–fm<filename body>
Select the filename body of the memory initialization files (.regs, .sram0,
.sram1, .dpram0, .dpram1).
Trace options Trace output level
–t1 | –t2 | –t3
Three forms of trace output are selectable:
Trace 1—Output ARM processor register values after each ARM instruction
is executed and memory writes to all stripe registers.
Trace 2—Output ARM processor register values after each ARM instruction
is executed.
Trace 3—Output memory writes to stripe registers.
Default setting is 0 (no trace output).
Note that enabling trace output severely impairs performance.
Trace options - File
–t1<filename> |
–t2<filename> |
–t3<filename>
The trace output can be output to a file by specifying a filename. If no
filename is specified, but trace output is enabled, the trace information is
piped out to the display: either the command prompt window or the debugger
RDI log window.
Use UART Launch Terminal
Emulator (UART
Options)
Specify Port: (UART
Options)
–k<terminal emulator>
–m<port number>
At the command line, when connecting the UART output to a terminal
emulator, the –m argument must be specified. In addition, –k can be used to
launch a terminal emulator, which by default is telnet. Hence, –k –m spawns
a telnet window that connects using TCP/IP through default port number
9001. You can specify a path to any terminal emulator using –k and any
available port number using –m.
DPRAM configuration - –d0<dp0_mode>[r]
DPRAM0 configuration –d1<dp1_mode>[r]
DPRAM1 configuration –dc<dp_combined>[r]
Specify DPRAM modes as described in usage. Default dp0_mode is
1xSPx32; default dp1_mode is 1xSPx32.
Endianness Little
Big
–e<b|l>
Specify processor endianness as big <b> or little <l>. Endianness is only
selectable when using fast memory initialization files. Default little.
TCP/IP port for GDB
–g <port number>
Selecting –g causes the simulator to initialize and then wait until a debugger
is connected via a TCP/IP connection. The command line argument is
required when using the GNU debugger (GDB). If no port number is
specified for connection, 9998 is used as the default.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
Debugging a Program Using AXD
1
Using debuggers in the ADS toolkit is only supported on PC
platforms.
To debug a program using AXD, ensure that you have generated the
appropriate memory image file and debug symbol file, using the ADS
toolkit to provide debug control. This process is referenced in Appendix
A Generating Input Files.
Configuring AXD to Use the ESS Target
To configure AXD to use ESS as the target simulator, proceed as follows:
1.
Start the AXD software by doing one of the following:
–
–
–
2.
In the AXD software, select ESS as the target simulator, as follows:
a.
b.
c.
16
From the Windows Start menu, choose Programs>ARM
Developer Suite>AXD Debugger.
From the Quartus II software, change to software mode and
choose Launch Debugger (Processing menu). Ensure that the
ARM software toolset is selected: choose General Settings
(Project menu) and click the Toolset Directories tab. See
“Important Notes” at the end of this section.
At the command line prompt, type AXDr. Ensure that the AXD
path is listed in your PATH environment variable.
Choose Configure Target (Options menu) to display the Choose
Target window.
If the target dll ESS-RDI.dll does not appear in the list of target
environments, click Add and open the file ESS-RDI.dll in the
path $QESS_ROOTDIR/bin directory.
Highlight the ESS-RDI.dll target by clicking on it. See Figure 1
on page 17.
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Excalibur Stripe Simulator User Guide
ESS Walkthrough
Figure 1. Choose Target Window
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When you select the ESS target environment, you must
configure it and specify a memory initialization file before
you can proceed with AXD debugging.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
3.
Configure the simulator target: click Configure to display the ESS
Options window for the Altera RDI.
a.
Click the Standard Options tab to modify the memory
initialization settings; see Figure 2.
Figure 2. ESS Options Window—Standard Options
Under Memory initialization, select a memory initialization
method, browse to find the initialization file(s), and click Open.
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Excalibur Stripe Simulator User Guide
b.
ESS Walkthrough
Click the Stripe Options tab to override the default ESS settings.
See Figure 3.
Figure 3. ESS Options Window—Stripe Options
Select the configuration settings you require. Each option is
described in Table 6 on page 15.
–
Click the Advanced Options tab to modify the UART settings;
see Figure 4 on page 20.
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You enable the UART by turning on Use UART in the Stripe
Options tab.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
Figure 4. ESS Options—Advanced Options
Optionally, you can use the advanced options to:
-
Connect to a terminal emulator which is not automatically
launched by ESS
Launch a different terminal emulator (select Launch other)
For example, to launch a version of HyperTerminal, which
allows connection over TCP/IP, you type the following text
in the Launch other text box:
<path>/hypertrm.exe /t 127.0.0.1:9001
1 Ensure that you specify the UART connection port,
which defaults to 9001.
-
20
Connect over a non-default port if port 9001 is already used
on your machine (select Specify port and enter the port
number)
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Excalibur Stripe Simulator User Guide
1
ESS Walkthrough
Turning on Launch terminal emulator under UART
options automatically spawns a new telnet window. The
new window connects to the UART transmit and receive
FIFO buffers; it provides an I/O mechanism to the
embedded UART.
Click OK when you have finished ESS target configuration.
4.
Click OK to close the Choose Target window. Check that the AXD
RDI log (System Output Monitor window) displays the following
banner:
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
5.
You can optionally load the source code debug symbols from an
executable and linkable format (ELF) file: select Load Debug
Symbols (File menu) and choose the file containing the debug
symbols associated with the ARM program source code. Typically,
you would select files with extensions .elf and .axf, which are both
ELF format. The debug symbols are generated by the ADS tools
during the software compilation or assembly. Appendix A
Generating Input Files refers to the appropriate Quartus II software
help pages.
1
In general, ELF files containing debug symbols generated by
the GNU toolset cannot be loaded by ADS debuggers, and
vice versa. In addition, if the debug symbols are not loaded
you only have debug control over the disassembled code.
You can now use AXD to debug the program running on ESS.
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Refer to the AXD software documentation for help on using the AXD
debugger.
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ESS Walkthrough
Excalibur Stripe Simulator User Guide
Important Notes
The following points apply to debugging a program using AXD:
■
A flash memory image typically contains PLD programming data,
and the boot code performs millions of instructions to configure the
PLD through writes to the CONFIG_DATA stripe register. To reduce
the time required to simulate this process, proceed as follows
a.
b.
c.
d.
■
When you launch AXD or ADW from the Quartus II software, the
image associated with the user code and compiled in software mode
is loaded into AXD/ADW automatically. This causes problems when
AXD/ADW targets ESS using a flash memory image, because the
boot loader has yet to map the required devices in the address space.
To overcome the difficulty, do one of the following:
–
–
■
■
22
Return to the Quartus II environment
Change to software mode
Choose Software Build Settings (Processing menu). Click the
CPU tab and remove the name of the slave binary image (SBI) file
from the Flash memory configuration box under Programming
File Generation.
Choose Start Software Build (Processing menu) to rebuild the
flash image.
Start AXD/ADW from outside the Quartus II environment and
load the debug symbols associated with the user code.
Simulate using the fast memory initialization files
If you are simulating using a flash memory image you should load
the debug symbols associated with the user code. Do not load the ELF
file generated by linking the Altera-provided boot code with the user
code.
To reset ESS you should reselect the target as described in Step 2 on
page 16. If you are prompted to reload the previous image, always
select No, and manually reload the debug symbols as described in
Step 5 on page 21.
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Excalibur Stripe Simulator User Guide
ESS Walkthrough
Debugging a Program using GDB with Insight Interface
This section describes how to use GDB with an Insight Interface to debug
a program. Insight is a Tcl/Tk-based GUI for GDB, written by Cygnus.
To debug an ARM program using GDB, ensure that you have generated
the appropriate memory image file and debug symbol file using the GNU
toolkit to provide debug control with the ARM program source code. This
process is referenced in Appendix A Generating Input Files.
To allow GDB to connect to ESS, you need to configure ESS at the
command line, placing the simulation model in a state waiting for
connection from the debugger, as follows:
1.
Start ESS at the command line, using the –g argument. For example,
type:
ess –bf<flash_image.hex> –g –k –m↵
where –k –m automatically launches a Telnet window connected to
the embedded UART transmit and receive FIFO buffers in the ESS
model.
Check that the following message is displayed in the command
prompt:
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
Info: Waiting for connection from Software Debugger ...
2.
Start up GDB with support for the ARM922T processor.
a.
b.
c.
3.
Altera Corporation
Open a Command Prompt window.
At the command line, type: arm-elf-gdb↵.
Check that an empty GDB source window is active.
Load the source code debug symbols: in the GDB Source window,
choose Open (File menu) and choose the file containing the debug
symbols associated with the program source code.
23
ESS Walkthrough
Excalibur Stripe Simulator User Guide
4.
Select ESS as the target simulator.
a.
Choose Target Settings (File menu); see Figure 5.
Figure 5. Target Settings
b.
c.
d.
e.
f.
5.
f
You can now simulate execution of the program on the stripe
simulator.
Refer to the GNU debugger software documentation for help on using
arm-elf-gdb.
1
f
24
In the Target Settings dialogue box, select Remote/TCP from the
Target drop-down box. Set Port to the port number on which the
stripe simulator is waiting for connection; type 9998, unless the
original ESS command line argument -g specifies a non-default
port number. See Table 6 on page 15 for details.
In the Hostname box, type localhost.
Click OK.
In the Source window, select Connect to Target (Run menu)
Check that a dialogue box appears stating that GDB is
successfully connected.
When the debugger connects to ESS, any source code in the
Source window could disappear, because the addresses
associated with the source code symbols might not yet be
mapped in the address space of the stripe simulation model. If
this happens, reselect the appropriate source code file or source
file list in the bottom left hand corner of the Source window.
See “Simulation Model Configuration Options” on page 14 for additional
information.
Altera Corporation
Excalibur Stripe Simulator User Guide
Using ESS in a
Third-Party
Logic
Simulator
ESS Walkthrough
ESS can be instantiated within a Verilog HDL or VHDL design using
alt_exc_stripe from the LPM, and simulated in a third party simulation
tool.
Table 6 lists the HDL simulation parameters used to run ESS in a thirdparty simulator.
Table 7. Configuration Options for Using ESS in a Third-Party Logic Simulator (Sheet 1 of 2)
HDL Simulation Parameter
(alt_exc_stripe)
Description
PROCESSOR="ARM"
DEVICE_SIZE=1000 | 400 | 100
Select from XA10, XA4 or XA1 Excalibur devices. PROCESSOR is
"ARM" and DEVICE_SIZE is 1000 (default),400 or 100.
BOOT_FROM_FLASH="TRUE" | “FALSE”
FLASH_HEX_FILE="filename”
Select an Intel Hex file containing the flash memory image.
BOOT_FROM_FLASH defaults to "TRUE".
USE_INITIALISATION_FILES="TRUE" | “FALSE” (1) (2) Select the filename body of the memory initialization files.
INITIALISATION_FILENAME="filename body”
USE_INITIALISATION_FILES defaults to "TRUE" . The default
INITIALISATION_FILENAME is “memory”.
TRACE_LEVEL=1 | 2 | 3
Three forms of trace output are selectable:
1—Output ARM processor register values after each ARM instruction
is executed and also after memory writes to all stripe registers.
2—Output ARM processor register values after each ARM instruction
is executed.
3—Output memory writes to stripe registers.
Default setting is 0 (no trace output).
Note that enabling trace output severely impairs performance.
TRACE_FILE=""
="filename”
Trace output is directed to the specified file. The trace output file name
must always be specified. TRACE_FILE defaults to ess_trace.out.
USE_UART="TRUE" | “FALSE”
When USE_UART is "TRUE", a Telnet window is launched
automatically. The Telnet window connects to the UART transmit and
recieve FIFO buffers. USE_UART defaults to “TRUE”.
DP0_MODE="UNUSED"
="1×SP×32" etc.
DP1_MODE="UNUSED"
="1×SPξ32" etc.
Select from the following options: “UNUSED”, “1×SP×32”, “1×SP×16”,
“1×SP×8”, “2×SP×16”, “2×SP×8”, “1×DP×16”, “COMBINED×64”,
“COMBINED×32”, “COMBINED×16”, “COMBINED×8”
ENDIAN=”BIG” | ”LITTLE”
Specify processor endianness as BIG or LITTLE (default).
Endianness is only selectable when using fast memory initialization
files.
USE_SW_DEBUGGER="TRUE" | “FALSE”
USE_SW_DEBUGGER is required when you are using AXD, ADW,
or GDB within a logic simulation environment.
USE_SW_DEBUGGER defaults to "FALSE".
CMD_LINE_PARAMETERS=””
Any advanced options (see “Debugging a Program Using AXD” on
page 16) such as specifying which port to connect the software
debugger on, can be specified within a logic simulation environment
using CMD_LINE_PARAMETERS. The argument can contain any
command line argument and overrides any previously defined
parameters. For example, CMD_LINE_PARAMETERS="–g8888"
connects the software debugger using port 8888 instead of the default
9998. See Table 6 on page 15 for details.
Altera Corporation
25
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Table 7. Configuration Options for Using ESS in a Third-Party Logic Simulator (Sheet 2 of 2)
HDL Simulation Parameter
(alt_exc_stripe)
Description
MAX_AHB1_RUNAHEAD=number of cycles
The MAX_AHB1_RUNAHEAD parameter specifies the maximum
number of cycles that can be simulated for each CLK_REF cycle.
MAX_AHB1_RUNAHEAD defaults to 1000. Setting it to 0 improves
performance at the expense of simulation repeatability.
ESS_OPTIONS_FILE="filename"
ESS_OPTIONS_FILE provides a convenient mechanism to
change ESS parameter settings without re-compiling the HDL files.
ESS_OPTIONS_FILE defaults to "ess_options.txt".
To set a parameter, create the file ess_options.txt in the simulation
directory and add text to the file in the format:
ESS_PARAMETER = ESS_VALUE
The following parameters can be set using this mechanism:
USE_SW_DEBUGGER
USE_UART
BOOT_FROM_FLASH
FLASH_HEX_FILE
USE_INITIALISATION_FILES
INITIALISATION_FILENAME
ENDIAN
TRACE_LEVEL
TRACE_FILE
CMD_LINE_PARAMETERS
MAX_AHB1_RUNAHEAD
Note:
(1)
(2)
When you set USE_INITIALISATION_FILES to "TRUE", ESS looks for initialization files with the filename body
specified in INITIALISATION_FILENAME with extensions .regs, .sram0, .sram1, .dpram0, and .dpram1 as
appropriate. The memory initialization mechanism is consistent with that required by the cycle-accurate full stripe
model.
When you set USE_INITIALISATION_FILES to "FALSE", ESS requires BOOT_FROM_FLASH to be "TRUE", and
attempts to load the flash image identified by the FLASH_HEX_FILE parameter as the EBI0 memory region.
Simulating a Design Using ESS
You can use the ModelSim simulation tool to perform a pre-routing
functional simulation of a Verilog HDL or VHDL design for Excalibur
devices using either a PC platform or a Solaris platform. For Solaris
platforms, you need to set up the environment variables first; see “Setting
Up Solaris Environment Variables” on page 27; for PC platforms, you can
proceed with the simulation straightaway; see “Starting the Simulation”
on page 27.
26
Altera Corporation
Excalibur Stripe Simulator User Guide
ESS Walkthrough
Setting Up Solaris Environment Variables
On Solaris platforms, you need to set up the Solaris environment variables
before you can perform a simulation of a Verilog HDL or VHDL design.
You use the following commands to set up the required environment
variables:
setenv QESS_ROOTDIR <ESS install dir>r
setenv QESS_PLATFORM solarisr
setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH}:${QESS_ROOTDIR}/${QESS_PLATFORM}r
1
The ESS installation directory is the same as the Quartus II
software installation directory.
Starting the Simulation
To use the ModelSim simulation tool to perform a pre-routing functional
simulation of a Verilog HDL or VHDL design for Excalibur devices using
ESS, proceed as follows:
1.
Start the ModelSim simulation tool.
2.
Click on Create a Project and specify the project’s home directory
and a project name.
3.
Click OK.
4.
Add the following line to the modelsim.ini file, or to the <project
name>.mpf ModelSim project file, under the VSIM section following
the Veriuser comments line:
Veriuser =
$QESS_ROOTDIR/$QESS_PLATFORM/libess_sspli.so
This provides the path to load objects for Verilog HDL PLI
applications dynamically.
1
When more than one Veriuser line is specified in a file, only
the PLI object(s) specified by the first Veriuser line is loaded.
If a Veriuser line already exists in the file, do one of the following:
a.
Altera Corporation
Remove old PLI application objects by inserting a semi-colon (;)
at the start of the Veriuser line to mark the line as a comment.
Figure 6 on page 28 shows an example project file with the new
Veriuser line added and a previous Veriuser line commented
out.
27
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Figure 6. Modelsim.mpf in Notepad, Specifying One Dynamically-Loaded Object
b.
Add the following text to the existing veriuser list:
$QESS_ROOTDIR/$QESS_PLATFORM/libess_sspli.so
Figure 7 shows an example project file with multiple PLI objects
listed.
Figure 7. Modelsim.mpf in Notepad, Specifying Multiple Dynamically-Loaded Objects
5.
Specify the ESS-specific parameters by creating the file
ess_options.txt in the simulation directory and specifying a line for
each required parameter in the format:
ESS_PARAMETER = ESS_VALUE
Table 7 on page 25 lists the parameters which can be set using this
mechanism.
6.
To create a new work library:
a.
b.
c.
d.
7.
Choose Create a New Library (Design menu).
Under Create, select a new library and a logical mapping to it.
In the Library Name box, type the library name; for example,
work.
Click OK.
Compile the design files:
a.
Choose Compile (Design menu).
For VHDL designs, ensure that the ESS source files, ess_hdl.vhd
and alt_exc_stripe_ess.vhd, are compiled using the VHDL 93
syntax by performing the following steps:
i
28
In the Compile HDL Source Files window, select Default
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Excalibur Stripe Simulator User Guide
b.
c.
d.
e.
f.
ESS Walkthrough
Options. Ensure that the Compiler Options window is
displayed.
ii In the VHDL page, turn on Use 1993 Language Syntax.
iii Click OK to modify either the ModelSim project file (.mpf)
or modelsim.ini.
Select
$QESS_ROOTDIR/eda/sim_lib/excalibur/ess_hdl/ess_hdl.v
(or.vhd) and click Compile.
Choose Compile (Design menu).
Select
$QESS_ROOTDIR/eda/sim_lib/excalibur/lpm/alt_exc_stripe_
ess.v (or .vhd) and click Compile.
Choose Compile (Design menu).
Select the Verilog HDL or VHDL design file(s), and the test
bench file (if you are using a test bench) and click Compile.
The ESS HDL files required for Verilog HDL and VHDL designs are
listed in Table 8.
Table 8. ESS HDL Files
File Name
Simulation model wrapper file for functional simulation
of a Verilog HDL design with ESS.
alt_exc_stripe_ess.vhd
Simulation model wrapper file for functional simulation
of a VHDL HDL design with ESS.
ess_hdl.v
Contains the Verilog HDL modules instantiated by
alt_exc_stripe to model the interface between the
PLD and the embedded stripe.
ess_hdl.vhd
Contains the VHDL components instantiated by
alt_exc_stripe to model the interface between the
PLD and the embedded stripe.
8.
Load your design:
a.
b.
9.
Altera Corporation
Description
alt_exc_stripe_ess.v
Choose Load New Design (Design menu).
Select your top-level design file or test bench file, and click Load.
Simulate the design files:
a.
Ensure that the memory initialization files are in the simulation
directory, and that stimulus is provided for the signals nPOR
and CLK_REF.
b.
Select Run-All (Run menu) to run the simulation.
29
ESS Walkthrough
Excalibur Stripe Simulator User Guide
1
Using a
Software
Debugger in a
Third-Party
Logic
Simulation
Environment
ModelSim OEM does not support VHDL foreign language
interface. To simulate a VHDL design or a VHDL testbench
using ESS, you require the ModelSim SE simulation tool.
ESS can be instantiated within a Verilog HDL or VHDL design using
alt_exc_stripe from the LPM. In addition, by setting the
USE_SW_DEBUGGER parameter, you can connect a software debugger
to the simulation, to control code execution on the processor subsystem.
You can connect a software debugger to ESS in a ModelSim environment
on both PC platforms and Solaris platforms. Table 4 on page 10 shows the
appropriate simulation tools and debuggers for each platform. Table 9
summarizes the process for using a software debugger with ESS in
ModelSim.
Table 9. Process For Using a Software Debugger With ESS in ModelSim
PC Platform Solaris Platform
√
√
√
√
√
√
Set up environment variables; see page 27.
Set up ModelSim
Set up one of the following software debuggers:
– AXD see page 33.
– GDB(1) see page 35
Note:
(1)
30
You can use the GDB debugger on a PC platform or a Solaris platform.
Altera Corporation
Excalibur Stripe Simulator User Guide
ESS Walkthrough
Setting Up ModelSim
To use the ModelSim simulation tool to perform a pre-routing functional
simulation of a Verilog HDL or VHDL design using ESS for Excalibur
devices and maintain debug control over the code execution through a
software debug tool, proceed as follows:
1.
Start the ModelSim simulation tool.
2.
Choose Create a Project (Design menu) and specify the project’s
home directory and a project name.
3.
Click OK.
4.
Add the following line to the modelsim.ini file, or to the <project
name>.mpf ModelSim project file, under the VSIM section after the
Veriuser comments line:
Veriuser =
$QESS_ROOTDIR/$QESS_PLATFORM/libess_sspli.so
This provides the path to load objects for Verilog HDL PLI
applications dynamically.
1
When more than one Veriuser line is specified in a file, only
the PLI object(s) specified by the first Veriuser line is loaded.
If a Veriuser line already exists in the file, do one of the following:
a.
Remove old PLI application objects by inserting a semi-colon (;)
at the start of the Veriuser line to mark the line as a comment.
Figure 8 shows an example project file with the new Veriuser
line added and a previous Veriuser line commented out.
Figure 8. Modelsim.mpf in Notepad, Specifying One Dynamically-Loaded Object
b.
Add the following text to the existing veriuser list:
$QESS_ROOTDIR/bin/libess_sspli.so
Figure 9 shows an example project file with multiple PLI objects
listed.
Altera Corporation
31
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Figure 9. Modelsim.mpf in Notepad, Specifying Multiple Dynamically-Loaded Objects
5.
Specify the ESS-specific parameters by creating the file
ess_options.txt in the simulation directory and specifying a line for
each required parameter in the format:
ESS_PARAMETER = ESS_VALUE
Table 7 on page 25 lists the parameters which can be set using this
mechanism. Set the parameter USE_SW_DEBUGGER to "TRUE" by
including the following line in ess_options.txt:
USE_SW_DEBUGGER = ”TRUE”
6.
Run the Altera debugger initialization macro alteradebugger.do,
which is located in
$QESS_ROOTDIR/eda/sim_lib/excalibur/ess_hdl, by choosing
Execute Macros (Macro menu). This allows communication between
the software debugger and Modelsim.
7.
Compile the appropriate Altera-provided libraries, user design files
and test bench as described in “Using ESS in a Third-Party Logic
Simulator” on page 25.
8.
Load your design:
a.
b.
32
Choose Load New Design (Design menu).
Select your top-level design file or test bench file, and click Load.
Altera Corporation
Excalibur Stripe Simulator User Guide
9.
ESS Walkthrough
Begin running the simulation:
a.
b.
Ensure that the memory initialization files are in the simulation
directory, and that stimulus is provided for signals nPOR and
CLK_REF.
Choose Run –All (Run menu). Check that the following text is
displayed in the ModelSim window:
# Info: Waiting for connection from Software Debugger ...
# Break at alt_exc_stripe_ess.v line <line number>
c.
The simulation waits for a connection from a SW debugger from
port 9998.
Connecting AXD to ESS in ModelSim
1
This software debugger is only supported on PC platforms.
To connect AXD to ESS in a ModelSim environment, proceed as follows:
1.
Start the AXD software.
2.
In AXD, select ESS as the target simulator.
a.
b.
c.
3.
In AXD, configure the simulator target:
a.
b.
Altera Corporation
Select Configure Target (Options menu) to display a Choose
Target window.
If the target dll ESS-RDI.dll does not appear in the list of target
environments, click Add and open the file ESS-RDI.dll in the
path $QESS_ROOTDIR/bin directory.
Highlight the ESS-RDI.dll target by clicking on it.
Click Configure to display the ESS Options window.
Click the Standard Options tab to set up the simulator. See
Figure 10 on page 34.
33
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Figure 10. ESS Options Window—Standard Options
34
c.
Turn on Connect to logic simulator.
d.
Check that the other options in the ESS Options window are not
selectable, because the parameters have already been selected in
the logic simulation environment.
e.
Click OK.
4.
Now you can connect to ESS in a logic simulation environment.
Click OK in the Choose Target window.
5.
Check that Logic Simulator connection successful is
displayed in the AXD RDI window. AXD is now connected to ESS
started in the ModelSim simulation tool.
6.
In AXD, load source code debug symbols (optional): choose Load
Debug Symbols (File menu) and choose the file containing the
debug symbols associated with the ARM program source code.
Altera Corporation
Excalibur Stripe Simulator User Guide
7.
ESS Walkthrough
In AXD, insert appropriate software breakpoints, data watch points
as required.
1
You now have full software debug control over executing
the ARM program.
8.
In AXD, start simulation by selecting Go (Execute menu) or by
single-stepping through instructions or higher level code.
9.
To disconnect AXD from the ModelSim environment, in the
ModelSim window, choose Restart (Run menu).
Connecting the GDB Debugger to ESS in ModelSim
1
The GDB debugger can be used on both PC platforms and Solaris
platforms.
To connect the GDB debugger, arm-elf-gdb, to ESS in a ModelSim
environment, proceed as follows:
1.
Start the GDB debugger software, arm-elf-gdb.
2.
In arm-elf-gdb, choose File (Open), select your debug image and
click OK.
3.
In arm-elf-gdb, choose Connect to target (Run menu), and specify
the following settings: and click OK.
–
–
–
4.
Target: Remote/TCP
Hostname: localhost
Port: 9998
Click OK and check that the window shown in Figure 11 is
displayed, to confirm that the software debugger is now connected
to ESS in the ModelSim environment.
Figure 11. arm-elf-gdb Successful Connection Window
Altera Corporation
35
ESS Walkthrough
Excalibur Stripe Simulator User Guide
1
You now have full software debug control over executing the
ARM program.
5.
In arm-elf-gdb, insert appropriate software breakpoints and data
watch points as required.
6.
In arm-elf-gdb, start simulation of the HDL design by selecting
Continue, Run, Step, Next, Step Asm Inst or Next Asm Inst as
appropriate.
7.
To restart or end co-simulation, you must first disconnect arm-elfgdb from ESS by choosing Run>Disconnect in arm-elf-gdb.
The following points apply to using a software debugger in a third-party
logic simulation environment:
■
■
You must pause and continue simulation using only the software
debugger controls.
When simulation is paused by debugger control, the ModelSim
simulation tool displays:
# Break at <verilog_file_name> line <line_number>.
■
Pins & Signals
Supported by
ESS
The ModelSim simulation tool automatically resumes simulation
when you use the debugger to continue execution, i.e., by using the
Go or Step commands.
At any point during execution, you can use the ModelSim simulation
tool to provide information about data stored in the PLD. You use the
software debugger to view data stored in the embedded stripe.
ESS provides an interface to the PLD through the stripe-to-PLD bridge,
the PLD-to-stripe bridge, and the PLD application interface. No support is
provided for the EBI, SDRAM, or UART ports.
Table 10 lists all pins and signals supported by ESS.
Table 10. Pins and Signals Supported by ESS (Sheet 1 of 3)
Signal
nRESET
36
Source
Input/output
nPOR
Input
BOOT_FLASH
Input
DEBUG_EN
Input
MASTER_HCLK
PLD
MASTER_HADDR[31..0]
stripe
MASTER_HTRANS[1..0]
stripe
Altera Corporation
Excalibur Stripe Simulator User Guide
ESS Walkthrough
Table 10. Pins and Signals Supported by ESS (Sheet 2 of 3)
Signal
MASTER_HWRITE
stripe
MASTER_HSIZE[1..0]
stripe
MASTER_HBURST[2..0]
stripe
MASTER_HWDATA[31..0]
stripe
MASTER_HREADY
PLD
MASTER_HRESP[1..0]
PLD
MASTER_HRDATA[31..0]
PLD
MASTER_HLOCK
stripe
MASTER_HBUSREQ
stripe
MASTER_HGRANT
PLD
SLAVE_HCLK
PLD
SLAVE_HADDR[31..0]
PLD
SLAVE_HTRANS[1..0]
PLD
SLAVE_HWRITE
PLD
SLAVE_HSIZE[1..0]
PLD
SLAVE_HBURST[2..0]
PLD
SLAVE_HWDATA[31..0]
PLD
SLAVE_HREADYI
PLD
SLAVE_HREADYO
stripe
SLAVE_HRESP[1..0]
stripe
SLAVE_HRDATA[31..0]
stripe
SLAVE_HMASTLOCK
PLD
SLAVE_BUSERRINT
stripe
SLAVE_HSELREG
PLD
SLAVE_HSEL
PLD
SLAVE_HCLK
PLD
MASTER_HCLK
PLD
CLK_PLDA[3..0]
PLD
INT_PLD[0] (individual)
PLD
INT_PLD[1] (individual)
PLD
INT_PLD[2] (individual)
PLD
INT_PLD[3] (individual)
PLD
INT_PLD[4] (individual)
PLD
INT_PLD[5] (individual)
INT_EXTPIN
Altera Corporation
Source
PLD
External
INT_UART
stripe
INT_TIMER0
stripe
37
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Table 10. Pins and Signals Supported by ESS (Sheet 3 of 3)
Signal
38
Source
INT_TIMER1
stripe
INT_COMMTX
stripe
INT_COMMRX
stripe
DP0_2_PORTACLK
PLD
DP0_PORTAENA
PLD
DP0_PORTAWE
PLD
DP0_PORTADATAIN
PLD
DP0_PORTAADDR
PLD
DP0_PORTADATAOUT
stripe/PLD
DP0_PORTBCLK
stripe/PLD
DP0_PORTBENA
stripe/PLD
DP0_PORTBWE
stripe/PLD
DP0_PORTBDATAIN
stripe/PLD
DP0_PORTBADDR
stripe/PLD
DP0_PORTBDATAOUT
PLD/stripe
DP1_3_PORTACLK
PLD
DP1_PORTAENA
PLD
DP1_PORTAWE
PLD
DP1_PORTADATAIN
PLD
DP1_PORTAADDR
PLD
DP1_PORTADATAOUT
stripe
DP1_PORTBCLK
stripe/PLD
DP1_PORTBENA
stripe/PLD
DP1_PORTBWE
stripe/PLD
DP1_PORTBDATAIN
stripe/PLD
DP1_PORTBADDR
stripe/PLD
DP1_PORTBDATAOUT
PLD/stripe
DP2_PORTAENA
PLD
DP2_PORTAWE
PLD
DP2_PORTADATAIN
PLD
DP2_PORTAADDR
PLD
DP2_PORTADATAOUT
stripe
DP3_PORTAENA
PLD
DP3_PORTAWE
PLD
DP3_PORTADATAIN
PLD
DP3_PORTAADDR
PLD
DP3_PORTADATAOUT
stripe
Altera Corporation
Excalibur Stripe Simulator User Guide
Excalibur
Stripe
Registers
Supported by
ESS
ESS Walkthrough
ESS provides support for the stripe registers listed in Table 11. Regardless
of whether the register functionality is modeled, all access permissions are
modeled. In addition, with the appropriate trace level setting, as
described in Appendix B Trace Output Format, trace information is
available for memory writes to all stripe registers.
Table 11 shows the registers supported by ESS.
Table 11. Registers Supported by ESS
Offset
Name
Supported
by ESS
000H
Reset and mode
control
040H
I/O control
Yes
080H
Memory map
Yes
100H
Bridge control
No
140H
PLD configuration
Yes
200H
Timer
Yes
280H
UART
Partial
300H
Clock control
Yes
380H
External bus interface
No
400H
SDRAM interface
No
800H
AHB1-2 bridge control
No
A00H
Watchdog
Yes
C00H Interrupt controller
Yes
Altera Corporation
Partial
Notes
All registers modeled except HM bit in BOOT_CR, DPSRAM0_LCR,
and DPSRAM1_LCR.
The PLD configuration master is not modeled. Therefore, data
written to the CONFIG_DATA register is lost. However, the PC bit in
the CONFIG_CONTROL register is set when the CONFIG_DATA
register receives the correct number of words. No cyclic
redundancy checks are performed on the configuration data.
See UART register table for list of supported registers
When writing to the SDRAM_INIT register, the bits PR, LM, LERR
and RF are automatically set to zero, representing completion of the
precharge all command, load mode register command, load
extended mode register command, and refresh register command,
respectively.
39
ESS Walkthrough
Excalibur Stripe Simulator User Guide
Table 12 shows the UART registers supported by ESS.
Table 12. UART Registers Supported by ESS
Offset
40
Name
Access
Supported by ESS
R*
Yes
280H
UART_RSR
284H
UART_RDS
R
Yes
288H
UART_RD
R*
Yes
28CH
UART_TSR
R*
Yes
290H
UART_TD
W
Yes
294H
UART_FCR
R/W
Yes
298H
UART_IES
R/S
Yes
29CH
UART_IEC
R/C
Yes
2A0H
UART_ISR
R
Yes
2A4H
UART_IID
R
Yes
2A8H
UART_MC
R/W
No
2ACH
UART_MCR
R/W
No
2B0H
UART_MSR
R*
No
2B4H
UART_DIV_LO
R/W
No
2B8H
UART_DIV_HI
R/W
No
Altera Corporation
Appendix A
Generating Input Files
All input files can be generated within the Quartus II Software mode
environment. To generate a flash memory image in Intel Hex format, or
simulation model initialization files, refer to the following Quartus II
version 1.1 (or later) help pages:
■
■
■
Altera Corporation
Overview: Creating Flash Programming Files
Creating a Flash Programming File
Alternative Procedure for Creating a Flash Programming File
41
Appendix A Generating Input Files
Excalibur Stripe Simulator User Guide
Notes:
42
Altera Corporation
Appendix B
Trace Output Format
Three levels of trace output are selectable using ESS. An example of each
format is displayed below:
Trace Level 1
Produce text output of ARM processor register values after each ARM
instruction is executed and memory writes to all stripe registers
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
Info: XA10 chip selected - ARM922T RISC processor core.
Info: Excalibur stripe simulation model initialisation ....
Info: Loading hex data (size = 0x00000578) to EXC_DEV_EBI0 (FLASH MEMORY) - offset 0x00000000
Info: Excalibur stripe simulation model initialisation complete.
00000000 EA000005 b pc, #0x14
; (address 0x1C)
r00=00000000 r01=00000000 r02=00000000 r03=00000000 r04=00000000 r05=00000000 r06=00000000 r07=00000000
r08=00000000 r09=00000000 r10=00000000 r11=00000000 r12=00000000 r13=00000000 r14=00000000 r15=0000001C
cpsr=nzcv_IFt_SVC
spsr=nzcv_ift_INV
0000001C E59F42CC ldr r4,
r00=00000000 r01=00000000
r08=00000000 r09=00000000
cpsr=nzcv_IFt_SVC
spsr=nzcv_ift_INV
.
.
00000090 E79DD004 ldr sp,
r00=00000000 r01=00000000
r08=7FFFC000 r09=00000001
cpsr=nzCv_IFt_SVC
spsr=nzcv_ift_INV
[pc, #0x2CC]
r02=00000000 r03=00000000 r04=00000028 r05=00000000 r06=00000000 r07=00000000
r10=00000000 r11=00000000 r12=00000000 r13=00000000 r14=00000000 r15=00000028
[sp, r4, lsl #0x00]
r02=00000000 r03=00000000 r04=00000000 r05=7FFFC0C0 r06=80000781 r07=80000000
r10=7FFFC080 r11=7FFFC683 r12=7FFFC0C0 r13=01000781 r14=00000000 r15=0000009C
Info: Mapping EXC_DEV_EBI0 from 00000000{base=00000000 size=0x0, np=0, en=0}
Mapping EXC_DEV_EBI0 to 80000781{base=80000000 size=0x10000, np=0, en=1}
00000094 E5856000 str r6, [r5, #0x00]
r00=00000000 r01=00000000 r02=00000000 r03=00000000 r04=00000000 r05=7FFFC0C0 r06=80000781 r07=80000000
r08=7FFFC000 r09=00000001 r10=7FFFC080 r11=7FFFC683 r12=7FFFC0C0 r13=01000781 r14=00000000 r15=000000A0
cpsr=nzCv_IFt_SVC
spsr=nzcv_ift_INV
Altera Corporation
43
Appendix B Trace Output Format
Trace Level 2
Excalibur Stripe Simulator User Guide
Produce text output of ARM processor register values after each ARM
instruction is executed.
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
Info: XA10 chip selected - ARM922T RISC processor core.
Info: Excalibur stripe simulation model initialisation ....
Info: Excalibur stripe simulation model initialisation complete.
00000000 EA000005 b pc, #0x14
; (address 0x1C)
r00=00000000 r01=00000000 r02=00000000 r03=00000000 r04=00000000 r05=00000000 r06=00000000 r07=00000000
r08=00000000 r09=00000000 r10=00000000 r11=00000000 r12=00000000 r13=00000000 r14=00000000 r15=0000001C
cpsr=nzcv_IFt_SVC
spsr=nzcv_ift_INV
0000001C E59F42CC ldr r4,
r00=00000000 r01=00000000
r08=00000000 r09=00000000
cpsr=nzcv_IFt_SVC
spsr=nzcv_ift_INV
.
.
00000090 E79DD004 ldr sp,
r00=00000000 r01=00000000
r08=7FFFC000 r09=00000001
cpsr=nzCv_IFt_SVC
spsr=nzcv_ift_INV
[pc, #0x2CC]
r02=00000000 r03=00000000 r04=00000028 r05=00000000 r06=00000000 r07=00000000
r10=00000000 r11=00000000 r12=00000000 r13=00000000 r14=00000000 r15=00000028
[sp, r4, lsl #0x00]
r02=00000000 r03=00000000 r04=00000000 r05=7FFFC0C0 r06=80000781 r07=80000000
r10=7FFFC080 r11=7FFFC683 r12=7FFFC0C0 r13=01000781 r14=00000000 r15=0000009C
00000094 E5856000 str r6, [r5, #0x00]
r00=00000000 r01=00000000 r02=00000000 r03=00000000 r04=00000000 r05=7FFFC0C0 r06=80000781 r07=80000000
r08=7FFFC000 r09=00000001 r10=7FFFC080 r11=7FFFC683 r12=7FFFC0C0 r13=01000781 r14=00000000 r15=000000A0
cpsr=nzCv_IFt_SVC
spsr=nzcv_ift_INV
.
.
Trace Level 3
Produce text output of processor writes to stripe registers.
ARM-Based Excalibur Fast Stripe Model (ESS) - Version 2.2
Copyright (c) Altera Corporation 2002. All rights reserved.
Info: XA10 chip selected - ARM922T RISC processor core.
Info: Excalibur stripe simulation model initialisation ....
Info: Loading hex data (size = 0x00000578) to EXC_DEV_EBI0 (FLASH MEMORY) - offset 0x00000000
Info: Excalibur stripe simulation model initialisation complete.
Info: Mapping EXC_DEV_EBI0 from 00000000{base=00000000 size=0x0, np=0, en=0}
Mapping EXC_DEV_EBI0 to 80000781{base=80000000 size=0x10000, np=0, en=1}
Info: Writing 0x00000001 to register BOOT_CR (Read/Clear access) at address 0x7FFFC000 - new register
bit values {re = 1, hm = 0, bm = 0}
Info: Mapping EXC_DEV_EBI0 from 80000781{base=80000000 size=0x10000, np=0, en=1}
Mapping EXC_DEV_EBI0 to 01000781{base=01000000 size=0x10000, np=0, en=1}
Info: Mapping EXC_DEV_SRAM0 from 00000000{base=00000000 size=0x0, np=0, en=0}
Mapping EXC_DEV_SRAM0 to 00008701{base=00008000 size=0x8000, np=0, en=1}
Info: Writing 0x00040000{ct=0x4, msb=0x0, lsb=0x0} to register CLK_PLL1_NCNT at address 0x7FFFC300
44
Altera Corporation
Appendix C
ESS Version Changes
Table 13 lists the versions of the ESS software.
Table 13. ESS Software Versions
Version
Description
1.0
First version
1.1
MASTER_HWDATA [31..0] is driven as ‘0’ instead of ‘X’
(undefined) in between stripe-to-PLD write transactions.
2.2 (version number now matches the
Quartus II software version)
a
b
Altera Corporation
Correct decode and execution of the LDRSB instruction
Default UART TCP port is 9001 instead of 9000
45
Excalibur Stripe Simulator User Guide
Appendix C ESS Version Changes
Notes:
46
Altera Corporation