8B10B Encoder/Decoder
MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Core Version:
Document Version:
Document Date:
1.3.2
1.3.2 rev1
December 2002
Copyright
8B10B Encoder/Decoder MegaCore Function User Guide
Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-IPED8B10B-1.2
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
8B10B Encoder/Decoder MegaCore® Function.
Table 1 shows the user guide revision history.
Table 1. User Guide Revision History
Date
How to Find
Information
December 2002
Third release of this user guide. Modified the directory
structure.
November 2002
Second release of this user guide. Modified the directory
structure, added release information and device family
support tables.
October 2002
First release of this user guide. Replaces the data sheet
v1.2.0. Added Stratix family support, and compliance with
generic framing procedure (GFP).
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Altera Corporation
Description
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click the binoculars toolbar icon to open the Find dialog
box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
8B10B Encoder/Decoder MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com.
For technical support on this product, go to www.altera.com/mysupport.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
www.altera.com/mysupport/
www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m.
Pacific Time)
Product literature
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
About this User Guide
Typographic
Conventions
8B10B Encoder/Decoder MegaCore Function User Guide
The 8B10B Encoder/Decoder MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Device Family Support ....................................................................................................................9
Introduction ....................................................................................................................................10
New in Version 1.3.2 ......................................................................................................................10
Features ...........................................................................................................................................11
Performance ....................................................................................................................................11
OpenCore Evaluation ....................................................................................................................11
Getting Started ............................................................................................................................................13
Hardware & Software Requirements ..........................................................................................13
Download & Install the Core ........................................................................................................13
Downloading the 8B10B Encoder/Decoder MegaCore Function ..................................13
Installing the 8B10B Encoder/Decoder MegaCore Function Files .................................14
8B10B Encoder/Decoder Directory Structure ...................................................................14
8B10B Encoder/ Decoder Tutorial ..............................................................................................17
Create a New Quartus II Project ..........................................................................................17
Implementing the System .....................................................................................................18
Simulate the Design ...............................................................................................................18
Using the Visual IP Software ........................................................................................18
Synthesize, Compile & Place & Route ................................................................................19
Using Third-Party EDA Tools for Synthesis ..............................................................19
Using the Quartus II Development Tool for Compilation & Place-and-Route ....19
Set Up Licensing .....................................................................................................................20
Append the License to Your license.dat File ..............................................................21
Specify the Core’s License File in the Quartus II Software ......................................21
Perform Post-Route Simulation ...........................................................................................22
Specifications ..............................................................................................................................................23
Functional Description ..................................................................................................................23
Disparity ..................................................................................................................................24
Generic Framing Procedure .................................................................................................24
Character Codes .............................................................................................................................25
Altera Corporation
vii
Contents
Encoder ............................................................................................................................................26
Disparity ..................................................................................................................................27
Cascaded Encoding ...............................................................................................................27
Encoding Latency ...................................................................................................................28
Decoder ............................................................................................................................................29
Cascaded Decoding ...............................................................................................................30
Decoding Latency ..................................................................................................................31
Signals ..............................................................................................................................................31
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 1 provides information about this release of the 8B10B
Encoder/Decoder MegaCore function.
Table 1. 8B10B Encoder/Decoder MegaCore Function Release Information
Item
Version
Device Family
Support
1.3.2
Release Date
December 2002
Ordering Code
IP-ED8B10B
Product IDs
0079
Vendor ID
6AF7
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
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■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
8B10B Encoder/Decoder MegaCore Function User Guide
About this Core
Table 2 shows the level of support offered by the 8B10B Encoder/Decoder
MegaCore function to each of the Altera device families.
Table 2. Device Family Support
Device Family
™
Introduction
Support
Cyclone
Full
Stratix™ GX
Full
Stratix
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX 10K®
Full
Mercury™
Full
Other device families
No support
Encoders and decoders are used for physical layer coding for Gigabit
Ethernet, Fibre Channel, and other applications. The 8b/10b encoder
takes byte inputs, and generates a direct current (DC) balanced stream
(equal number of 1s and 0s) with a maximum run length of 5. Some of the
individual 10-bit codes will have an equal number of 1s and 0s, while
others will have either four 1s and six 0s, or, six 1s and four 0s. In the latter
case, the disparity between 1s and 0s is used as an input to the next 10-bit
code generation, so that the disparity can be reversed, and maintain an
overall balanced stream. For this reason, some 8-bit inputs have two valid
10-bit codes, depending on the input disparity.
The Altera® 8B10B Encoder/Decoder MegaCore® Function is a compact,
high performance core capable of encoding and decoding at Gigabit
Ethernet rates (125 MHz: 1 Gbps). The core is optimized for the Cyclone,
Stratix GX, Stratix, APEX II, APEX 20K, FLEX 10K, and Mercury devices.
New in Version
1.3.2
10
■
Includes the encoder rom patch files
Altera Corporation
About this Core
8B10B Encoder/Decoder MegaCore Function User Guide
■
■
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Performance
Table 3 shows the resource utilization and performance of some 8B10B
Encoder/Decoder MegaCore function configurations. These results were
obtained using the Quartus® II software version 2.1.
Look-up table (LUT)-based implementation of encoder
Industry compatible special character coding
Complies with all applicable standards, including:
–
Institute of Electrical and Electronics Engineers, IEEE 802.3z,
Media Access Control (MAC) Parameters, Physical Layer, Repeater
and Management Parameters for 1000 Mb/s Operation, 1998,
paragraphs 36.2.4.1 to 36.2.4.6.
–
American National Standards Institute, ANSI X3.230, Fibre
Channel Physical and Signaling Interface (FC-PH), 1994.
–
International Telecommunication Union, ITU-T Recommendation
G.7041, Generic Framing Procedure, October 2001.
Table 3. Resource Utilization and Performance
Device
Mode
Logic Elements/
Logic Cells
Memory
fMAX (MHz) (1)
Cyclone
EP1C20F400C6
Encoder
Decoder
107
150
0
0
304.04
304.04
Stratix
EP1S25F780C5
Encoder
Decoder
107
150
0
0
342.23
422.12
APEX 20K
EP20K30ETC144-1
Encoder
Decoder
62
142
2
0
175.32
225.12
Mercury
EP1M120F484C7AES
Encoder
Decoder
61
152
1
0
201.86
367.51
Flex 10K
EPF10K30ETC144-1
Encoder
Decoder
62
149
1
0
138.89
222.22
Note:
(1)
fMAX is for non-cascaded encoders/decoders.
OpenCore
Evaluation
Altera Corporation
The OpenCore® feature lets you test-drive Altera MegaCore functions for
free using the Quartus® II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
11
1
About this Core
Features
Getting Started
Hardware &
Software
Requirements
The instructions in this section require the following hardware and
software:
■
■
This section describes how to obtain an 8B10B Encoder/Decoder
MegaCore function configuration. It explains how to install the core, and
walks you through the process of implementing the configuration in a
design.
Download &
Install the Core
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Downloading the 8B10B Encoder/Decoder MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at www.altera.com. Follow the instructions below to
obtain the 8B10B Encoder/Decoder core via the Internet. If you do not
have Internet access, you can obtain the core from your local Altera
representative.
Altera Corporation
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Communications from the Technology drop-down list box.
4.
Type 8B10B in the Keyword Search box.
5.
Click Go.
13
2
Getting Started
■
■
A PC running the Windows 98/NT/2000 operating system; or a SUN
workstation running the Solaris operating system
Quartus II development tool, version 2.1 or higher
Model TechnologyTM ModelSim®-Altera simulation software, version
5.5a or higher, or
Innoveda Visual IP RTL Simulation Software, version 4.3 or higher
with a compatible simulator
8B10B Encoder/Decoder MegaCore Function User Guide
Getting Started
6.
Click the link for the Altera 8B10B Encoder/Decoder MegaCore
function in the search results table. The product description web
page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
the I Agree button at the bottom of the page.
9.
Follow the instructions on the 8B10B Encoder/Decoder core
download and installation page to download the function and save
it to your hard disk.
Installing the 8B10B Encoder/Decoder MegaCore Function Files
For Windows, perform the following steps:
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The 8B10B Encoder/Decoder Installation dialog box
appears. Follow the on-line instructions to finish installation.
For Solaris systems, perform the following steps:
1.
Download the core, see “Downloading the 8B10B Encoder/Decoder
MegaCore Function” on page 13.
2.
Decompress/untar the package, using the following commands:
gunzip xxx.tar.gz; tar xvf xxx.tar
3.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically
<path>/ed8b10bv1.3.2/lib) as a user library in the Quartus II
software to access the core in the MegaWizard® Plug-In manager.
Search for “User Libraries” in Quartus II Help for instructions on
how to add these libraries.
8B10B Encoder/Decoder Directory Structure
Figure 1 on page 15 shows the directory structure that will be created
when the 8B10B Encoder/Decoder is installed.
14
Altera Corporation
Getting Started
8B10B Encoder/Decoder MegaCore Function User Guide
Figure 1. 8B10B Encoder/Decoder Directory Structure
<path>/ed8b10b-v1.3.2
doc
Contains the core documentation.
lib
Contains the per-configuration netlists.
syn
Contains the encrypted netlists for the 8B10B Encoder/Decoder core.
aot1085_d0_dec8b10b/
Configuration based on parameter choices for the decoder.
flex 10k/
Altera device family supported.
Contains the aot1085_d0_dec8b10b files: .bsf, .e.edf(6), _inst.v,
_inst.vhd, and dec8b10b_wrapper files: .v and .vhd.
mercury/
Altera device family supported.
Contains the aot1085_d0_dec8b10b files: .bsf, .e.vqm, _inst.v,
_inst.vhd, _inst.vhd, and dec8b10b_wrapper files: .v and .vhd.
.stratix/
Altera device supported, includes Stratix, Stratix GX and Cyclone.
Contains the aot1085_d0_dec8b10b files: .bsf, .e.vqm, _inst.v,
_inst.vhd, and dec8b10b_wrapper files: .v and .vhd.
aot1085_e0_enc8b10b/
Configuration based on parameter choices for the encoder.
apex/
Altera device family supported, includes APEX 20K and APEX II.
Contains the aot1085_e0_enc8b10b files: .bsf, .e.vqm, _inst.v,
_inst.vhd, _inst.vhd, and enc8b10b_wrapper files: .v and .vhd.
flex 10k/
Altera device family supported.
Contains the aot1085_e0_enc8b10b files: .bsf, .e.edf, _inst.v,
_inst.vhd, and enc8b10b_wrapper files: .v and .vhd.
mercury/
Altera device family supported.
Contains the aot1085_e0_enc8b10b files: .bsf, .e.vqm, _inst.v,
_inst.vhd, _inst.vhd, and enc8b10b_wrapper files: .v and .vhd.
aot1085_e11_enc8b10b/
Configuration based on parameter choices for the encoder.
Continued on next page
stratix/
Altera device supported, includes Stratix, Stratix GX and Cyclone.
Contains the aot1085_e11_ed8b10b files: .bsf, e.vqm, _inst.v,
_inst.vhd, _inst.vhd, and enc8b10b_wrapper files: .v and .vhd.
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
Symbol files for the Quartus II software used to instantiate the core into a schematic design.
Encrypted HDL netlist file.
Verilog HDL instantiation file.
VHDL instantiation file.
Wrapper files used for stand-alone simulation.
Encrypted electronic design interchange format (EDIF) input file.
Altera Corporation
15
2
Getting Started
apex/
Altera device family supported, includes APEX 20K and APEX II.
Contains the aot1085_d0_dec8b10b files: .bsf(1), .e.vqm(2), _inst.v(3),
_inst.vhd(4), and dec8b10b_wrapper files: .v and .vhd. (5)
8B10B Encoder/Decoder MegaCore Function User Guide
Getting Started
Continued from <path>/ed8b10b-v1.3.2
sim_lib
Contains the simulation models.
aot1085_0_ed8b10b/
Configuration based on parameter choices.
modelsim_verilog/
ModelSim-Altera Verilog HDL models
aot1085_0_dec8b10b
aot1085_0_enc8b10b
lpm_verilog
modelsim_vhdl/
ModelSim-Altera VHDL models
aot1085_0_dec8b10b
aot1085_0_enc8b10b
lpm_vhdl
visual_ip/
Innoveda Visual IP simulation models
aot1085_0_dec8b10b
aot1085_0_enc8b10b
test/
Demonstration testbench
aot1085_11_ed8b10b/
Configuration based on parameter choices.
modelsim_verilog/
ModelSim-Altera Verilog HDL models
aot1085_0_dec8b10b
aot1085_11_enc8b10b
modelsim_vhdl/
ModelSim-Altera VHDL models
aot1085_0_dec8b10b
aot1085_11_enc8b10b
visual_ip/
Innoveda Visual IP simulation models
aot1085_0_dec8b10b
aot1085_11_enc8b10b
test/
Demonstration testbench
16
Altera Corporation
Getting Started
8B10B Encoder/
Decoder
Tutorial
8B10B Encoder/Decoder MegaCore Function User Guide
This tutorial explains how to obtain a configuration of the Altera 8B10B
Encoder/Decoder. Once you have obtained the required configuration,
you can incorporate it into your overall project.
To obtain a customized 8B10B Encoder/Decoder configuration enter a
request at: www.altera.com/mysupport. Your customized core will be emailed to you as an encrypted gate level netlist and secure RTL simulation
model.
This tutorial consists of the following steps:
2
“Create a New Quartus II Project” on page 17
“Implementing the System” on page 18
“Simulate the Design” on page 18
“Synthesize, Compile & Place & Route” on page 19
“Set Up Licensing” on page 20
“Perform Post-Route Simulation” on page 22
Getting Started
■
■
■
■
■
■
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the 8B10B Encoder/Decoder user library. To create
a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
1
7.
Altera Corporation
Steps 7 to 10 only apply to Solaris systems.
Click User Library Pathnames.
17
8B10B Encoder/Decoder MegaCore Function User Guide
Getting Started
8.
Type <path>\ed8b10bv.1.3.2\lib\ into the Library name box,
where <path> is the directory in which you installed the 8B10B
Encoder/Decoder. The default installation directory is
c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project. Figure 1 on
page 15 shows an example project directory structure.
Implementing the System
Once you have your custom 8B10B Encoder/Decoder, you are ready to
implement it. You can use the Quartus II software or other EDA tools to
create your design.
Simulate the Design
As shown in Figure 1 on page 15, the 8B10B MegaCore function offers two
possible configurations for the encoder:
■
■
_0 is optimized for APEX, FLEX 10K, and Mercury devices
_11 is optimized for the Stratix family
Altera provides models you can use for functional verification of the core
within your design. A Verilog HDL demonstration testbench, including
scripts to run it, is also provided. This demonstration testbench, used with
the ModelSim-Altera simulator, demonstrates how to instantiate a model
in a design. To find the simulation models for your selected configuration,
refer to sim_lib directory in Figure 1.
Using the Visual IP Software
The Visual IP software facilitates the use of Visual IP simulation models
with third-party simulation tools. To view a simulation model, you must
have the Visual IP software installed on your system. To download the
software, or for instructions on how to use the software, refer to the Altera
web site at www.altera.com, and search for Visual IP. For examples of
how to use the provided Visual IP model, refer to the sample scripts
included with the demonstration testbench.
18
Altera Corporation
Getting Started
8B10B Encoder/Decoder MegaCore Function User Guide
Synthesize, Compile & Place & Route
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar LogicTM, Mentor
Graphics®, Synopsys, Synplicity®, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
1.
Create your custom design instantiating an 8B10B Encoder/Decoder
core.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the core instantiation as a black box by either
setting attributes or ignoring the instantiation.
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Place-andRoute
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
1.
Select Compile mode (Processing menu).
2.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Specify the input settings for the project.
4.
Altera Corporation
a.
Choose EDA Tool Settings (Project menu).
b.
Select Custom EDIF in the Design entry/synthesis tool list.
c.
Click Settings.
d.
In the EDA Tool Input Settings dialog box, select the relevant
tool name or option from the Design Entry/Synthesis Tool list.
Add your third-party EDA tool-generated netlist file to your project.
19
2
Getting Started
To synthesize your design in a third-party EDA tool, follow these steps:
8B10B Encoder/Decoder MegaCore Function User Guide
f
Getting Started
5.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
6.
Add the pre-synthesized and encrypted .e.vqm file from your
working directory, created by the MegaWizard Plug-In Manager.
7.
Constrain your design as needed.
8.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design.
Refer to Quartus II Help for further instructions on performing
compilation.
Set Up Licensing
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FPGA device. You can use Altera’s
OpenCore evaluation software to compile and simulate the 8B10B
Encoder/Decoder MegaCore function in the Quartus II software,
allowing you to evaluate it before purchasing a license. However, you
must obtain a license from Altera before you can generate programming
files or EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation
in third-party EDA tools.
After you purchase a license for the 8B10B Encoder/Decoder MegaCore
Function, you can request a license file from the Altera web site at
www.altera.com/licensing and install it on your PC. When you request a
license file, Altera e-mails you a license.dat file. If you do not have
Internet access, contact your local Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
20
Before you set up licensing for the 8B10B Encoder/Decoder
MegaCore Function, you must already have the Quartus II
software installed on your PC, with licensing set up.
Altera Corporation
Getting Started
8B10B Encoder/Decoder MegaCore Function User Guide
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrumTM
Synplify®
ModelSim
2.
Open the 8B10B Encoder/Decoder MegaCore Function license file in
a text editor. The file should contain one FEATURE line, spanning
two lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the 8B10B Encoder/Decoder
MegaCore Function license file and paste it into a new line in the
Quartus II license file.
5.
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
Altera Corporation
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
21
Getting Started
1
2
8B10B Encoder/Decoder MegaCore Function User Guide
Getting Started
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
Perform Post-Route Simulation
After you have licensed the core, you can generate EDIF, VHDL, Verilog
HDL, and Standard Delay Output Files from the Quartus II software and
use them with your existing EDA tools to perform functional modeling
and post-routing simulation of your design.
22
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, refer to the
“Using the Quartus II Development Tool for Compilation & Placeand-Route”section. The Quartus II software generates output and
programming files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
Altera Corporation
Specifications
Functional
Description
The core consists of an encoder (ENC8B10B) and a decoder (DEC8B10B),
see Figure 3 on page 24. The encoder encodes one 8-bit byte of data into a
10-bit transmission code, and the decoder decodes a 10-bit code into one
8-bit byte of data. Figure 2 illustrates the bidirectional conversion process.
The eight input bits are named A, B, C, D, E, F, G, H. Bit A is the least
significant bit (LSB), and bit H is the most significant bit (MSB). They are
split into two groups: The five-bit group A, B, C, D, E, and the three-bit
group F, G, H.
The coded bits are named a, b, c, d, e, i, f, g, h, j (the order is not
alphabetical). These bits are also split into two groups: the six-bit group a,
b, c, d, e, i, and the four-bit group f, g, h, j.
Specifications
Figure 2. 8b10b Conversion
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
8b10b
Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB sent last
LSB sent first
In bit serial transmission, the LSB is usually transmitted first, while the
MSB is usually transmitted last.
Altera Corporation
3
23
8B10B Encoder/Decoder MegaCore Function User Guide
Specifications
Disparity
Disparity is the difference between the number of 1s and 0s in the encoded
word.
■
■
■
Neutral disparity indicates the number of 1s and 0s are equal.
Positive disparity indicates more 1s than 0s.
Negative disparity indicates more 0s than 1s.
The core is designed to maintain a neutral average disparity. Average
disparity determines the DC component of a serial line. Running disparity
is a record of the cumulative disparity of every encoded word, and is
tracked by the encoder. To guarantee neutral average disparity, a positive
running disparity must be followed by neutral or negative disparity; a
negative running disparity must be followed by neutral or positive
disparity. If these conditions are not met, the decoder flags an error by
asserting its rderr output.
f
For details on running disparity rules, see the IEEE 802.3z specification,
paragraph 36.2.4.4.
Generic Framing Procedure
The 8B10B Encoder/Decoder core can be used within GFP applications,
see Figure 3 for an example.
Figure 3. 8B10B Encoder/Decoder GFP Typical Application
Ingress
Gigabit
Ethernet
Stream
(8B/10B Encoded)
Egress
Transport Network
8B/10B
Decoder
GFP
Mapper
GFP Data Stream
(64B/65B Encoded)
GFP
Demapper
8B/10B
Encoder
Gigabit
Ethernet
Stream
(8B/10B Encoded)
On ingress to the transport network, if the decoder receives an
unrecognized codeword, such as an illegal codeword or a legal codeword
with a running disparity error, it asserts the rderr signal. By asserting the
rderr signal, the decoder indicates to the mapper that an unrecognized
codeword has been received, the mapper then generates a special control
character, the 10B_ERR code. In addition, the mapper remaps the 8B/10B
codewords into 64B/65B codewords before sending the data to the
transport network.
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Altera Corporation
Specifications
8B10B Encoder/Decoder MegaCore Function User Guide
On egress from the transport network, the demapper encodes the
64B/65B codewords into 8b/10B codewords before sending them to the
encoder. When the encoder receives the 10B_ERR code, it sends out one of
the two 10-bit illegal codewords with neutral disparity: 001111 0001(RD-)
or 110000 1110(RD+), depending on the running disparity.
Character
Codes
In addition to 256 data characters, the 8b/10b code defines thirteen out-ofband indicators, also called special control characters. The 256 data
characters are named Dx.y, and the special control characters are named
Kx.y—except for the special code 10B_ERR (see Table 4 on page 25). The x
value corresponds to the five-bit group, and the y value to the three-bit
group.
The special control characters indicate, for example, whether the data is
idle, test data, or data delimiters. In applications where encoded
characters are transmitted bit-serially, the comma character (K28.5) is
usually used for alignment purposes as its 10-bit code is guaranteed not to
occur elsewhere in the encoded bit stream, except after K28.7 which is
normally only sent during diagnostic.
3
Table 4 lists the special K codes used by the core.
Specifications
Table 4. Character Codes
10-Bit Special K Codes
Equivalent 8-Bit Codes
K28.0
8’b000_11100
K28.1
8’b001_11100
K28.2
8’b010_11100
K28.3
8’b011_11100
K28.4
8’b100_11100
K28.5 (1)
8’b101_11100
K28.6
8’b110_11100
K28.7
8’b111_11100
K23.7
8’b111_10111
K27.7
8’b111_11011
K29.7
8’b111_11101
K30.7
8’b111_11110
10B_ERR
8’b111_11111
Note:
(1)
Altera Corporation
K28.5 is a comma character used for alignment purposes, and to represent the IDLE
code.
25
8B10B Encoder/Decoder MegaCore Function User Guide
Encoder
Specifications
The encoder uses an innovative, proprietary, non-partitioned, memorybased LUT implementation to convert data and identified special 8-bit
codes from 8 bits to 10 bits. See Figure 2 on page 23 for an illustration of
the conversion process.
To encode an 8-bit word, the 8-bit value must be applied to the datain
inputs and the enable input must be asserted (active high).
When one of the thirteen special 10-bit codes is to be inserted, the
equivalent 8-bit code is placed on the datain lines and the kin input is
asserted. The core performs error checking to ensure the out-of-band 8-bit
code is valid. If not, the kerr output is asserted. See Table 4 on page 25 for
a list of the valid K codes.
Idle (K28.5) characters can be automatically inserted when enable is not
asserted by asserting the idle_ins input.
The encoder encodes invalid characters in the same way it encodes Idle
(K28.5) codes. The decoder treats invalid characters as Idle codes.
Figure 4 shows a block diagram of the encoder.
Figure 4. Encoder
clk
kerr
reset_n
kin
enable
dataout [9:0]
valid
idle_ins
datain [7:0]
rdin
rdout
rdcascade
rdforce
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Altera Corporation
Specifications
8B10B Encoder/Decoder MegaCore Function User Guide
Disparity
The running disparity can be forced to positive or negative, allowing the
user to insert a special resynchronization pattern, or disparity errors.
When the rdforce input is asserted, the value on the rdin port is
assumed to be the current running disparity. Setting rdin to 0 forces the
encoder to produce an encoded word with positive or neutral disparity.
Setting rdin to 1 forces the encoder to produce an encoded word with
negative or neutral disparity.
Cascaded Encoding
Altera Corporation
27
3
Specifications
Two encoders can be cascaded to allow for 16-bit word encoding. The
encoders are cascaded by connecting the rdcascade output of the most
significant byte (MSByte) encoder to the rdin input of the least significant
byte (LSByte) encoder, and by connecting the rdout output of the LSByte
encoder to the rdin input of the MSByte encoder. These connections
ensure proper running disparity computation. The rdforce inputs must
be asserted (active high) for the encoders to take into account the value on
the rdin inputs, rather than use their internally generated running
disparity. Both enable inputs must be high or low at the same time. The
kin [1] signal relates to datain[15:8], and kin[0] relates to
datain[7:0]. Figure 5 on page 28 shows two encoders connected
together to perform cascaded encoding.
8B10B Encoder/Decoder MegaCore Function User Guide
Figure 5. Cascaded Encoding
Specifications
Note (1)
clk
reset_n
kin [1:0]
kin [1]
enable
kerr
dataout [9:0]
valid
idle_ins
datain [15:0]
datain [15:8]
rdin
rdout
rdcascade
rdforce
clk
reset_n
kerr
dataout [9:0]
kin [0]
enable
idle_ins
valid
rdout
datain [7:0]
rdin
rdcascade
rdforce
Note:
(1)
The enable, idle_ins, and rdforce signals are set high (logic 1).
Encoding Latency
The encoder is pipelined, thus it takes three clock cycles for a character to
be encoded. The encoded value—corresponding to the values of datain
and kin sampled by the encoder on rising edge n—is output shortly after
rising edge n+2, and is available to be sampled on the rising edge of clock
cycle n+3. (See Figure 6 on page 29).
To enable cascaded encoding, the data paths fed by the rdforce and
rdin inputs are not pipelined. Since rdforce and rdin are normally
only used in cascaded configurations, this should not be a problem.
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Altera Corporation
Specifications
8B10B Encoder/Decoder MegaCore Function User Guide
In cases where the rdforce and rdin inputs are to be used in noncascaded configurations, they should be delayed two clock cycles with
respect to their corresponding datain and kin values. This can be
achieved by inserting two registers in series with each of the inputs to be
delayed, the following example Verilog HDL code shows how to
implement the required delay registers.
Example: Adding delay to rdforce and rdin for non-cascaded
applications:
Figure 6. Encoder Timing Diagram
n
n+1
n+2
n+3
clk
datain,
kin,
enable
a
b
c
d
e
f
g
a
b
c
d
b
c
d
e
dataout
rdforce,
rdin
Decoder
Altera Corporation
a
Data and identified 10-bit special K codes are converted from 10 bits to 8
bits; see Table 4 on page 25 for a list of the valid K codes, and Figure 2 on
page 23 for an illustration of the conversion process.
29
3
Specifications
// The _pre2 registers are set at the same time as datain and kin.
reg rdforce_pre2;
reg rdin_pre2;
// The _pre1 registers provide an extra clock tick of delay
reg rdforce_pre1;
reg rdin_pre1;
always @ (posedge clk) begin
rdforce <= rdforce_pre1;
rdforce_pre1 <= rdforce_pre2;
rdin <= rdin_pre1;
rdin_pre1 <= rdin_pre2;
end
8B10B Encoder/Decoder MegaCore Function User Guide
Specifications
When special 10-bit K codes are received, the special K codes are
translated to 8-bit values, and the kout signal is asserted. The decoder
also checks for invalid 10-bit codes.
When the decoder receives an invalid code, it asserts the kerr signal and
decodes the value to an arbitrary number, according to the rules for
decoding valid codes.
When the idle_del signal is asserted, it deletes all 10-bit words
identified as the special IDLE character of K28.5.
When the receiver detects a disparity error, the rderr signal is asserted.
Figure 7 shows a block diagram of the decoder.
Figure 7. Decoder
clk
valid
reset_n
dataout [7:0]
idle_del
kout
enable
kerr
datain [9:0]
rderr
rdin
rdout
rdforce
rdcascade
Cascaded Decoding
Two decoders can be cascaded to decode two words simultaneously. The
decoders are cascaded—in a similar fashion as the encoders—by
connecting the rdcascade output of the first decoder to the rdin input
of the second decoder, and by connecting the rdout output of the second
decoder to the rdin input of the first decoder. The rdforce inputs of
both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the rdin and
rdforce inputs are not cascaded. If these inputs are to be used in noncascaded decoders, they should be delayed by one clock cycle with respect
to their corresponding datain and kin inputs.
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Altera Corporation
Specifications
8B10B Encoder/Decoder MegaCore Function User Guide
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to
be decoded. The decoded value—corresponding to the value of datain
sampled by the decoder on rising edge n—is output shortly after rising
edge n+1, and is available to be sampled on the rising edge of clock cycle
n+2. (See Figure 6 on page 29).
Figure 8. Decoder Timing Diagram
n
n+1
n+2
n+3
clk
a
datain,
enable
b
dataout,
kout, kerr,
rdout, rderr
Signals
d
e
f
g
a
b
c
d
e
b
c
d
e
f
Tables 5 and 6 list the signals for the encoder and decoder.
Table 5. Encoder Signals (Part 1 of 2)
Signal Name
Direction
Description
clk
Input
Clock. The input is latched, and the result is output on this clock. There
is a three clock cycle latency between the input and output.
reset_n
Input
Active low, reset. Asynchronously resets all registers in the core.
kin
Input
Command byte indicator. When high, indicates that the input is a
command byte, not a data byte.
enable
Input
Enable encoder signal. When high, indicates that the data currently
present on the datain input is to be encoded.
idle_ins
Input
Idle character insert. When high, idle (K28.5) characters are inserted
when enable is not asserted.
datain[7:0]
Input
Data input. This is the 8-bit input word, data or command.
rdin
Input
Running disparity input. When rdforce is high, the value on this pin is
used as the current running disparity instead of the internally generated
one.
Altera Corporation
31
3
Specifications
a
rdforce,
rdin
c
8B10B Encoder/Decoder MegaCore Function User Guide
Specifications
Table 5. Encoder Signals (Part 2 of 2)
Signal Name
Direction
Description
rdforce
Input
Force running disparity. When high, the rdin value overrides the
internally generated running disparity.
kerr
Output
Special K character error. This signal is set high when enable and kin
are high and the value on datain is not a valid special K character.
dataout[9:0]
Output
Data output. This is the 10-bit encoded output.
valid
Output
Valid signal. When high, indicates that a valid encoded word is present
on the dataout output.
rdout
Output
Running disparity output. The current running disparity (after encoding
the word present on the dataout output).
rdcascade
Output
Cascaded Running disparity. Used when encoders are cascaded.
Table 6. Decoder Signals
Signal Name
Direction
Description
clk
Input
Clock. The input is latched, and the result output on this clock. There is
a three clock cycle latency between the input and output.
reset_n
Input
Active low, reset. Asynchronously resets all registers in the core.
idle_del
Input
Idle delete signal. When high, idle words (K28.5) are removed from the
stream (i.e. valid is set low when idle words are received).
enable
Input
Enable decoder signal. When high, indicates that the data currently
present on the datain input is to be decoded.
datain[9:0]
Input
Data input. This is the 10-bit encoded input word.
rdin
Input
Running disparity input. When rdforce is high, the value on this pin is
used as the current running disparity instead of the internally generated
one.
rdforce
Input
Force running disparity. When high, the rdin value overrides the
internally generated running disparity.
valid
Output
Valid signal. When high, indicates that a valid decoded word is present
on the dataout output.
dataout[7:0]
Output
Data output. This is the 8-bit decoded data or command.
kout
Output
Command output. When high, indicates that the output is a command
byte, not a data byte.
kerr
Output
Special K error. Asserted high when an invalid 10-bit word is received.
rderr
Output
Running disparity error. When high indicates the running disparity rules
have been violated.
rdout
Output
Running disparity output. The current running disparity (after decoding
the word present on the dataout output).
rdcascade
Output
Cascaded Running disparity. Used when decoders are cascaded.
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Altera Corporation