DDR SDRAM Controller
MegaCore Function User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
Document Version:
Document Date:
1.2.0
1.2.0 rev 1
March 2003
DDR SDRAM Controller MegaCore Function User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
UG-DDRSDRAM-1.3
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
DDR SDRAM Controller MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the core features,
including new features in this release
Refer to the readme file for late-breaking information and known
issues that are not available in this user guide
Table 1. User Guide Revision History
Date
How to Find
Information
March 2003
Column address strobe (CAS) latency information updated.
February 2003
Cyclone™ and Stratix™ GX device information added. Timing
analysis information improved and moved to Appendix B.
Updated PLL diagrams. Changes to getting started section.
June 2002
First full release. Includes Stratix™ device support information.
March 2002
Preliminary release.
■
■
■
■
Altera Corporation
Description
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box
Bookmarks serve as an additional table of contents
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages
Numerous links, shown in green text, allow you to jump to related
information
iii
About this User Guide
DDR SDRAM Controller MegaCore Function User Guide
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
Access
USA & Canada
All Other Locations
Web site
http://www.altera.com/mysupport
http://www.altera.com/mysupport
FTP site
ftp.altera.com
ftp.altera.com
Telephone hotline (800) 800-EPLD
(6:00 a.m. to 6:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Fax
(408) 544-6401
(408) 544-6401 (1)
Altera Literature
Services
Electronic mail
[email protected] (1)
[email protected] (1)
Non-technical
customer service
Telephone hotline (800) SOS-EPLD
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Fax
(408) 544-7606
(408) 544-7606
Telephone
(408) 544-7104
(408) 544-7104 (1)
Web site
http://www.altera.com
http://www.altera.com
General product
information
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The DDR SDRAM Controller MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Device Family Support ....................................................................................................................9
Introduction ....................................................................................................................................10
New in Version 1.1.0 ......................................................................................................................10
Features ...........................................................................................................................................10
General Description .......................................................................................................................10
Performance ....................................................................................................................................12
Getting Started ............................................................................................................................................13
Software Requirements .................................................................................................................13
Design Flow ....................................................................................................................................13
Download & Install the Function ................................................................................................15
Obtaining the DDR SDRAM Controller MegaCore Function .........................................15
Installing the DDR SDRAM Controller Files .....................................................................16
Directory Structure ................................................................................................................17
Set Up Licensing .............................................................................................................................19
Append the License to Your license.dat File ......................................................................19
Specify the Core’s License File in the Quartus II Software ..............................................20
DDR SDRAM Controller Walkthrough ......................................................................................21
Create a New Quartus II Project ..........................................................................................21
Launch the MegaWizard Plug-In Manager .......................................................................22
Choose the Parameters ..........................................................................................................23
Complete the Custom Core ..................................................................................................32
Using the Reference Design ..........................................................................................................34
Set Up the Reference Design ................................................................................................34
Compile the Reference Design .............................................................................................35
Post-route Simulation ............................................................................................................36
Configure the PLL ..........................................................................................................................36
Behavioral Simulation ...................................................................................................................37
Simulate with the ModelSim VHDL Model .......................................................................37
Simulate with the Visual IP Model ......................................................................................39
Compile & Place-&-Route .............................................................................................................40
Cyclone Devices .....................................................................................................................40
Altera Corporation
vii
Contents
Stratix & APEX II Devices .....................................................................................................41
Timing Analysis .............................................................................................................................42
Perform Post-Route Simulation ...................................................................................................42
License for Configuration .............................................................................................................43
Specifications ..............................................................................................................................................45
Functional Description ..................................................................................................................45
Signals ......................................................................................................................................45
Control Logic Module ...........................................................................................................49
Data Path Module ..................................................................................................................50
Controller Access Operation ........................................................................................................54
Write Operation .....................................................................................................................54
Read Operation ......................................................................................................................56
Refresh Timing .......................................................................................................................58
Initialization Timing ..............................................................................................................59
Miscellaneous SDRAM Settings ..........................................................................................60
PLL Configuration .........................................................................................................................61
APEX II Devices .....................................................................................................................61
Cyclone & Stratix Devices .....................................................................................................62
Core Verification ............................................................................................................................64
Simulation Testing .................................................................................................................65
Hardware Testing ..................................................................................................................65
Board Design Package ...........................................................................................................65
Appendix A—The Quartus II Constraint Settings ............................................................................67
APEX II Devices .............................................................................................................................67
Stratix Devices ................................................................................................................................70
Appendix B—DDR SDRAM Timing Analysis ....................................................................................75
Introduction ....................................................................................................................................75
FPGA-SDRAM Interface ...............................................................................................................75
Write Data Timing .................................................................................................................75
Address & Command Timing ..............................................................................................77
Read Data Capture using DQS ............................................................................................78
Resynchronization of Captured Read Data from the
DQS to the System Clock Domain .......................................................................................78
Appendix C—Board Design Guidelines ..............................................................................................87
General Guidelines ........................................................................................................................87
Decoupling Capacitance ...............................................................................................................89
viii
Altera Corporation
About this Core
1
Specifications
About
this Core
DII Interface
Release
Information
Table 4 provides information about this release of the DDR SDRAM
Controller MegaCore function.
Table 4. DDR SDRAM Controller Release Information
Item
Version
Device Family
Support
1.2.0
Release Date
March 2003
Ordering Code
IP-SDRAM/DDR
Product ID(s)
0055
Vendor ID(s)
6AF7
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
About this Core
DDR SDRAM Controller MegaCore Function User Guide
Table 5 shows the level of support offered by the DDR SDRAM Controller
MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Stratix GX
™
Support
Preliminary
Cyclone
Preliminary
Stratix
Preliminary
APEX™ II
Full
Other device families
No support
Introduction
The Altera DDR SDRAM Controller MegaCore function provides a
simplified interface to industry-standard DDR SDRAM memory.
New in Version
1.2.0
■
Support for column address strobe (CAS) latency of 3.0 clock cycles
Features
■
■
■
■
■
Burst lengths of 2, 4, or 8 data words
CAS latency of 2.0, 2.5, or 3.0 clock cycles
16-bit programmable refresh counter for automatic refresh
1, 2, 4, or 8 chip-select signals
Support for the NOP, READ, WRITE, AUTO_REFRESH,
PRECHARGE, ACTIVATE, and BURST_TERMINATE SDRAM
commands
Data mask lines supported for partial write operations
Bank management architecture, which minimizes latency
Access cascading architecture, which maximizes throughput
Memory data path widths of 8 to 80 bits
Each dqs signal supports 8 dq bits and samples read data
Multiple DIMM support
OpenCore feature allows designers to instantiate and simulate
designs in the Quartus® II software prior to purchasing a license
Hardware tested at 167 MHz with DDR333 (PC2700) memory devices
in Stratix devices
Hardware tested at 133 MHz with DDR266 (PC2100) memory devices
in APEX II devices
■
■
■
■
■
■
■
■
■
General
Description
10
The DDR SDRAM Controller handles the complex aspects of using DDR
SDRAM—initializing the memory devices, managing SDRAM banks, and
keeping the devices refreshed at appropriate intervals. The DDR SDRAM
Controller translates read and write requests from the local interface into
all the necessary SDRAM command signals.
Altera Corporation
GettingAbout this Core
DDR SDRAM Controller MegaCore Function User Guide
Figure 1 shows a system-level diagram of the DDR SDRAM Controller
(see Tables 13 and 14 on page 46 for signal descriptions).
Figure 1. DDR SDRAM Controller System-Level Diagram
clk
a
clk_shifted
ba
reset_n
cs_n
raddr
cke
b_size
ras_n
r_req
w_req
rw_ack
d_req
w_valid
r_valid
DDR SDRAM
Controller
MegaCore
Function
cas_n
we_n
DDR SDRAM
dm
dq
dqs
datain
dm_in
dataout
Altera Corporation
11
1
About this Core
The DDR SDRAM Controller is optimized for Altera Cyclone, Stratix,
Stratix GX, and APEX II devices. The advanced features available in these
devices allow you to interface directly to DDR SDRAM devices and to use
the data strobe signal (dqs) in the read and write direction.
About this Core
Performance
DDR SDRAM Controller MegaCore Function User Guide
Table 6 shows typical performance results for the DDR SDRAM
Controller.
Table 6. Typical Performance
Device
DDR SDRAM System fMAX (MHz)
Cyclone (EP1C20F400C6)
Pending Device Characteristics
Stratix (EP1S25F780C6)
Pending Device Characteristics
APEX II (EP2A15F672C9)
133
Table 7 shows typical sizes for the DDR SDRAM Controller.
Table 7. Typical Sizes
Data Width
(bits)
12
LEs
Cyclone Device
Stratix Device
APEX II Device
8
700
660
630
16
800
710
700
32
1,000
830
850
48
1,200
950
1,000
64
–
1,020
1,130
72
–
1,050
1,200
80
–
1,100
1,250
Altera Corporation
Getting Started
Software
Requirements
This section requires the following software:
■
Quartus® II version 2.2 SP1
Design Flow
2
This section assumes you are using a PC with the Windows
operating system. However, the core also works with UNIX
platforms. If you are using UNIX, you must install the Java
Runtime Environment version 1.3. Refer to the core’s readme file
for more information on UNIX support.
The DDR SDRAM Controller has the following design flows:
■
User top-level flow—Create a custom variation and instantiate it into
your existing functional top-level design. However, follow the
guidelines on setting up the PLLs and system timing analysis.
1
■
If you do not have a functional top-level design, use the
following method for evaluating the DDR SDRAM
Controller. Do not use a DDR SDRAM Controller instance
as a top-level design to compile in the Quartus II software.
Dummy top-level flow—Create a custom variation and use the wizardgenerated dummy top-level design to compile it in the Quartus II
software. The dummy top-level design instantiates your custom
variation, PLLs for the appropriate family, and dummy logic that
connects the local-side interface signals to pins via registers. This flow
allows you to perform area and timing analysis. You can use this flow
for any custom variation, but you cannot simulate, because the
dummy top-level is non-functional. To simulate your instance, Altera
provides a separate example testbench and script.
In addition, Altera provides a VHDL reference design for each of the
supported families in the \reference_design directory. You can compile
each reference design in the Quartus II software, perform post-route
simulation, and run in real hardware. The reference designs use read and
write command sequences to drive the controller. A script is provided,
which allows you to change the exact sequence of these commands.
f
Altera Corporation
For more information on the reference designs, see “Using the Reference
Design” on page 34 and doc\readme_test_stim.txt.
13
Getting Started
1
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Table 8 shows the steps for the three possible design flows of the DDR
SDRAM Controller.
Table 8. Design Flow
Steps
User Top-Level
Dummy Top-Level
Reference Design
HDL.
VHDL, Verilog, or AHDL.
VHDL or Verilog.
VHDL only.
Quartus II project
location.
Any directory.
Any directory.
The
reference_design
directory structure
must be maintained,
but can be moved.
Perform walkthrough. Yes.
Yes.
No.
Choose parameters.
Any combination.
Any combination.
Fixed.
32-bit memory for
Stratix and APEX II
devices; 16-bit for
Cyclone devices.
Configure PLL.
Follow PLL configuration section Fixed at 133 MHz (see
in UG
Note (1)).
Behavioral
simulation.
Yes, you can simulate using your
user top-level in VHDL or Verilog.
Altera also provides a VHDL
testbench that you can use to
simulate your core (see
“Simulate with the ModelSim
VHDL Model” on page 37).
No; you cannot simulate the
No.
dummy logic. However, Altera
provides a VHDL testbench
that you can use to simulate
your core (see “Simulate with
the ModelSim VHDL Model”
on page 37).
Run constraints
scripts.
See “Appendix A—The Quartus
II Constraint Settings” on
page 67.
Only supported for one
configuration and device for
each family.
Yes.
Quartus II compile
and place and route.
Yes.
Yes.
Yes.
Area estimates.
Yes.
Yes, but you must subtract the Yes.
dummy logic LEs.
Timing analysis.
See “Appendix A—The Quartus
II Constraint Settings” on
page 67.
Yes.
No.
No; you cannot simulate the
dummy logic.
Yes (VHDL only).
Post place-and-route No.
simulation with
ModelSim script.
Restrictions
14
–
Ensure that the Quartus II toplevel design entity is the same
name as your dummy toplevel.
Fixed at 133 MHz
(see Note (1)).
–
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingGetting Started
Note to Table 8:
(1)
To edit this frequency, see “Configure the PLL” on page 36.
This getting started covers the following topics:
Download and install the DDR SDRAM Controller MegaCore
function.
2.
Set up licensing.
3.
DDR SDRAM Controller MegaCore function walkthrough.
4.
Simulate your design to confirm the operation of your system.
5.
Compile and place-and-route.
6.
Timing analysis
7.
Post-route simulation.
8.
License the DDR SDRAM Controller MegaCore function and
configure the devices.
2
Getting Started
Download &
Install the
Function
1.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining the DDR SDRAM Controller MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at www.altera.com. Follow the instructions below to
obtain the DDR SDRAM Controller via the Internet. If you do not have
Internet access, you can obtain the DDR SDRAM Controller from your
local Altera representative.
Altera Corporation
1.
Point your web browser to www.altera.com/ipmegastore.
2.
Type DDR SDRAM in the Keyword Search box.
3.
Click Go.
4.
Choose your MegaCore function.
5.
Click the Free Evaluation link.
6.
Follow the on-line instructions to download the function and save it
to your hard disk.
15
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Installing the DDR SDRAM Controller Files
To install the DDR SDRAM Controller files, perform the following steps:
f
16
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>, where <path name> is the location of
the downloaded MegaCore function and <filename> is the file name
of the core. Click OK.
3.
Follow the on-line instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the DDR SDRAM Controller’s library directory
(<path>\ddr_sdram-<version>\lib) as a user library in the Quartus II
software. Search for “User Libraries” in Quartus II Help for
instructions on how to add a library.
For additional installation instructions, refer to the readme file.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingGetting Started
Directory Structure
Figures 2 and 3 show the directory structure for the DDR SDRAM
Controller.
Figure 2. Directory Structure (Part 1 of 2)
MegaCore
ddr_sdram-<version>
Contains the DDR SDRAM Controller MegaCore function files and documentation.
2
ahdl_for_cyclone
Contains modified Quartus II AHDL files for Cyclone devices.
dat
Contains a data file for each Cyclone device combination that is used
by the Tcl script to generate the instance-specific Tcl script.
doc
Contains the documentation for the core.
lib
Contains encrypted lower-level design files and some open-source example files that
are used in the design flow. After installing the MegaCore function, you should set a
user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
sim_lib
Contains the simulation models provided with the core.
modelsim
Contains the precompiled libraries for the ModelSim simulation tool.
vhdl
Contains the VHDL precompiled simulation libraries.
visualip
Contains the PC or UNIX precompiled models for the Visual IP software.
Altera Corporation
17
Getting Started
constraints
Contains a Tcl script that generates an instance-specific Tcl script for each instance of
the DDR-SDRAM Controller in a Cyclone device.
Examples of how to run the script are included.
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Figure 3. Directory Structure (Part 2 of 2)
MegaCore
ddr_sdram-<version>
Contains the DDR SDRAM Controller MegaCore function files and documentation.
reference_design
Contains the reference design source files.
apexii_example
Contains an example Quartus II project for APEX II devices containing
a 32-bit, 133-MHz DDR SDRAM Controller.
cyclone_example
Contains an example Quartus II project for Cyclone devices containing
a 16-bit, 133-MHz DDR SDRAM Controller.
stratix_example
Contains an example Quartus II project for Stratix devices containing
a 32-bit, 167-MHz DDR SDRAM Controller.
test_stimulus
Contains the clear text read and write command sequences and a Tcl script to
convert the command sequences into ROM contents for the reference designs.
user_simulation
Contains example ModelSim simulation scripts.
project_for_your-instance
Contains a Quartus II project that you must run from the the MegaWizard
Plug-In, before you run the user_simulation scripts.
vhdl
Contains the VHDL reference design source files.
testbench
Contains the testbench directories.
vhdl
Contains the sample VHDL testbench, which illustrates the functionality
of the core.
18
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
Set Up
Licensing
GettingGetting Started
You can use the Altera OpenCore® feature to compile and simulate the
DDR SDRAM Controller MegaCore function, allowing you to evaluate it
before purchasing a license. However, you must purchase and install a
license from Altera before you can generate programming files or EDIF,
VHDL, or Verilog HDL gate-level netlist files for simulation in third-party
EDA tools.
You can request a license file for your purchased DDR SDRAM Controller
from the Altera web site at http://www.altera.com/licensing and install
it on your PC. When you request a license file, Altera e-mails you a
license.dat file. If you do not have Internet access, contact your local
Altera representative.
1
Before you set up licensing for the DDR SDRAM Controller, you
must already have the Quartus II software installed on your PC
with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the DDR SDRAM Controller license file in a text editor. The
file should contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the DDR SDRAM Controller license file
and paste it into the Quartus II license file.
1
Altera Corporation
Do not delete any FEATURE lines from the Quartus II license
file.
19
Getting Started
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
2
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
5.
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
20
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
DDR SDRAM
Controller
Walkthrough
GettingGetting Started
This walkthrough describes the design flow using the Altera DDR
SDRAM Controller MegaCore function and the Quartus II development
system. Altera provides a MegaWizard® Plug-In with the DDR SDRAM
Controller. The MegaWizard Plug-In Manager, which you can use within
the Quartus II software, lets you create or modify design files to meet the
needs of your application.
This walkthrough consists of the following steps:
Create a New Quartus II Project
Launch the MegaWizard Plug-In Manager
Choose the Parameters
Complete the Custom Core
2
Create a New Quartus II Project
Before you create a core, you must create a new Quartus II project. With
the New Project wizard, you specify the working directory for the project,
assign the project name, and designate the name of the top-level design
entity. You also specify the DDR SDRAM Controller user library. To
create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction does not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
1
Altera Corporation
For the dummy top-level flow only, enter <variation
name>_dummy_top as the top-level design entity name, where
<variation name> is the name that you will chose for your custom
function.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\ddr_sdram-<version>\lib\ into the Library name
box, where <path> is the directory in which you installed the DDR
SDRAM Controller. The default installation directory is
c:\megacore.
21
Getting Started
■
■
■
■
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Next.
13. Choose the device family you wish to target from the Device dropdown box. Select Yes, you want to assign a specific device.
14. Choose an available device from the Device list.
1
-
The DDR SDRAM Controller wizard-generated constraint
script is suitable only for the following devices:
Cyclone EP1C20F400C6 device
Stratix EP1S25F1020C6 device
APEX II EP2A15F672C7 device
15. Click Next.
16. Click Finish.
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the DDR SDRAM Controller. To launch the
wizard, perform the following steps:
1.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
2.
Specify that you want to create a new custom megafunction and
click Next.
3.
Expand the Interfaces and Memory Controllers directories. Choose
DDR SDRAM-<version> in the Memory Controllers directory.
4.
Choose the output file type for your design; the wizard supports ,
VHDL, Verilog HDL, and AHDL (except for dummy top-level flow).
1
22
Refer to the Quartus II Help for more information on how to
use the MegaWizard Plug-In Manager.
The MegaWizard Plug-In also generates symbol files (.bsf).
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
5.
GettingGetting Started
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 4 shows the wizard after you have made
these settings.
Figure 4. Selecting the Megafunction
2
Getting Started
6.
Click Next.
Choose the Parameters
To specify your custom core parameters, perform the following steps:
1.
Choose the size parameters (see Figure 5).
1
Altera Corporation
To use the wizard-generated constraint script choose data
width bits = 32 bits for Stratix and APEX II devices; 16 bits
for Cyclone devices.
23
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Figure 5. Choose the Size
Table 9 describes the available size parameters.
Table 9. Size Parameters
Parameter
Range
Description
Data width bits
8, 16, 24, 32, 40,
48, 64, 72, or 80
The memory interface width. The local bus interface width is
twice the memory interface width, because the DDR SDRAM
interface is clocked on both edges of the clock. The maximum
memory width possible with the DDR SDRAM Controller on a
Cyclone device is 48 bits, and this is reduced even further if
more than one IO bank is not set to 2.5V.
Row address bits
11 to 14
The number of row address bits in the memory device.
Column address bits
8 to 13
The number of column address bits in the memory device.
Number of banks
2 or 4
The number of banks in the memory device.
Number of chip selects
1, 2, 4, or 8
The number of chip-select signals.
24
Altera Corporation
GettingGetting Started
DDR SDRAM Controller MegaCore Function User Guide
Table 10 describes the options.
Table 10. Options
Parameter
Description
Overwrite
Overwrite indicates whether or not the MegaWizard Plug-In overwrites the existing
dummy top-level design. Choose not to overwrite if you have edited the dummy toplevel design file and added your own code.
Target device family
The DDR SDRAM Controller supports the Stratix, Stratix GX, APEX II, and Cyclone
device families. The device family is the same as the family that you chose in the
Quartus II software, unless you chose an unsupported device family, whereby it
defaults to Stratix.
Non 2.5 V on left-hand
side
For Cyclone devices only. To use DDR-SDRAM byte groups on the left-hand side
(LHS) of the device, the left-hand power bank must be set to 2.5 V, where LHS refers
to the die orientation. Checking this option prevents you from making byte group
assignments on the LHS of the device. This option also limits the maximum possible
memory interface width to 24-bits for the smaller devices. For more information, refer
to the Cyclone data sheet.
2.
Click Next.
3.
Enter a value for the System Clock (see Figure 6). The System Clock
text box accepts values from 77.0 to 200.0 MHz. To set default timer
settings for the chosen frequency, click Set Defaults.
1
4.
Altera Corporation
For frequencies other than 133.333 MHz, see “Configure the
PLL” on page 36.
Enter the timer settings and choose the timing parameters (see
Figure 6).
25
2
Getting Started
Dummy top-level design The dummy top-level design name, which is created with the custom variation. The
dummy top-level design is a minimal design that allows you to compile the DDR
SDRAM Controller into a device. It instantiates the DDR SDRAM Controller custom
variation, some dummy logic (a set of registers) between the local-side interface and
the FPGA pins, and the necessary PLLs. You can use the dummy top-level design to
compile the DDR SDRAM Controller in the Quartus II software and perform a simple
timing analysis. This dummy top-level design also illustrates how to create a working
system with the DDR SDRAM Controller. You can edit this file, and replace the
dummy-logic with a real local-side interface.
The default name is <variation name>_dummy_top where <variation name> is the
name you chose for your DDR SDRAM Controller.
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
1
The default initialization time is 50 cycles, which is
appropriate for simulation. If you click Set Defaults, the
initialization time sets the correct number of cycles to give a
200 µs delay. If you intend to simulate you should change
the initialization time back to a small number (eg. 50 cycles)
to avoid lengthy simulation times.
Figure 6. Choose Timing Parameters & Timer Settings
26
Altera Corporation
GettingGetting Started
DDR SDRAM Controller MegaCore Function User Guide
Table 11 describes the available memory timing parameters.
Table 11. Memory Timing Parameters (Part 1 of 2)
Parameter
Range
Description
2, 4, or 8
The maximum number of data words in each DDR SDRAM data
burst. The burst length on the local bus interface is half the burst
length on the DDR SDRAM interface, because the DDR SDRAM
interface is clocked on both edges of the clock.
CAS latency (CL)
2.0, 2.5, or 3.0
After you assert cas_n, the memory presents the data CL clock
cycles later. Generally the higher the clock speed, the higher the
CAS latency. DDR SDRAM typically uses a setting of 2.0, 2.5, or 3.0
cycles. Consult your chosen DDR SDRAM memory device data
sheet for appropriate settings.
CL= 2.0 can typically be used for frequencies up to 133 MHz.
CL= 2.5 can typically be used for frequencies up to 167 MHz.
CL= 3.0 is typically required for frequencies of 200 MHz and above.
The read resynchronization phase setting (see “Resynchronization
of Captured Read Data from the DQS to the System Clock Domain”
on page 78) may delay the read data a further clock cycle.
Precharge command
period (RP)
2, 3, or 4
The time that must elapse between a precharge command and
banks becoming available for row access. RP is derived from tRP
and the clock speed and is specified in clock cycles.
RP = (tRP /clock period), rounded up to the next integer value,
where tRP is the value from the SDRAM data sheet,
clock period is the clock period of the SDRAM clock.
Active A to active B
(RRD)
2, 3, or 4
After an active command to one bank, there must be at least a
minimum time interval before the DDR SDRAM Controller issues a
subsequent active command to a different bank. RRD is derived
from tRRD and the clock speed and is specified in clock cycles.
RRD = (tRRD /clock period), rounded up to the next integer value,
where tRRD is the value from the SDRAM data sheet,
clock period is the clock period of the SDRAM clock.
Altera Corporation
27
2
Getting Started
Burst length
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Table 11. Memory Timing Parameters (Part 2 of 2)
Parameter
Active to read/write
(RCD)
Range
3, 4, or 5
Description
The active command opens a row in a particular bank. After an
active command, the DDR SDRAM controller does not issue a read
or write command until the minimum time interval has expired. RCD
is derived from tRCD and the clock speed and is specified in clock
cycles.
RCD = (tRCD/clock period), rounded up to the next integer value,
where tRCD is the value from the SDRAM data sheet,
clock period is the clock period of the SDRAM clock.
Auto-refresh command
period (RFC)
7 to 14
The auto-refresh command period is the amount of time that must
pass between successive auto-refresh commands. RFC is derived
from tRFC and the clock speed and is specified in clock cycles.
RFC = (tRFC/clock period), rounded up to the next integer value,
where tRFC is the value from the SDRAM data sheet
clock period is the clock period of the SDRAM clock.
Write recovery time
(WR)
28
2 or 3
Set the write recovery time to 3 for operation at higher frequencies
(consult memory device data sheet).
Altera Corporation
GettingGetting Started
DDR SDRAM Controller MegaCore Function User Guide
Table 12 describes the available timer settings.
Table 12. Timer Settings
Parameter
Description
Refresh command interval The refresh command interval is the number of clock cycles that elapse between
timer
each refresh command and is given by:
refresh period /clock period, rounded up to the next integer value.
Initialization time
The initialization time specifies the settling time after power up, and after the clocks
have settled, that the SDRAM device requires before any command activity from the
DDR-SDRAM Controller. This time is typically 200 µs and is given by:
200 µs/clock period, rounded up to the next integer value.
For simulation a small value such as 50 cycles is sufficient.
The DDR SDRAM Controller starts this initialization count when it is released from
reset. If the reset is a known delay after power-on (and PLL settling), the initialization
period can be reduced if advantageous. The mode registers are written after this
delay.
There is also a DLL lock timer delay built into the DDR SDRAM Controller. This is a
fixed period of 200 cycles of clk (independent of frequency) during which the core
waits while the DLLs within the memory device lock. This period starts after the
mode registers have been written (thus enabling the memory devices DLLs) and
when the delay is over, the core can accept user commands.
5.
Altera Corporation
Click Next.
29
2
Getting Started
If an SDRAM device connected to the controller has a 64-ms, 4,096-cycle refresh
requirement, the controller must issue a refresh command to the device at least
every 64 ms/4,096 = 15.625 µs. If the SDRAM and controller are clocked by a
100-MHz clock, the maximum value is 15.625 µs/0.01µs = 1,562 clock cycles.
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
6.
Select positive or negative clock edge (see Figure 7).
This option allows you to control which edge of the system clock
(clk) to use for the SDRAM address and command outputs. Which
edge you choose depends on how your hardware is setup and how
you have setup the clocks. For this walkthrough the following
recommendations apply:
–
–
For Stratix and Cyclone devices, select the negative edge.
For APEX II devices, you can also select the negative edge. Use
the positive edge if you are using the slower sidebanks for the
address and command outputs and the sidebanks are
sufficiently slow to guarantee hold time at the SDRAM.
Figure 7. Select Output Edge & Resynchronization Phase
7.
Select the Resynchronization Phase.
This option allows you to control the resynchronization of data from
the dqs clock domain into the system clock domain. You should
understand your hardware before you decide which phase to select.
f
30
For more information, see “Resynchronization of Captured Read Data
from the DQS to the System Clock Domain” on page 78.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingGetting Started
8.
Click Next.
9.
For Cyclone devices only, select the positions on the device for each
of the DDR SDRAM byte groups (see Figure 8).
This flow only allows you to implement a 16-bit interface on the LHS
of an EP1C20F400 device.
f
For more information on the floorplan, see the doc/readme.txt file.
2
To place an un-placed byte group, select the unplaced byte
group in the drop-down box at your chosen position. Placed
byte-groups are no longer available in the drop-down boxes.
b.
To move a placed byte group, un-place the byte group from the
current location (select ’--’ in the drop-down box). The byte
group now appears in all of the other empty byte group
locations, so you can now place the byte group as described
previously.
The floorplan matches the orientation of the Quartus II floorplanner. The
layout represents the die as viewed from above. A byte group consists of
eight dq pins, a dm pin and a dqs pin. The larger Cyclone devices have
eight possible regions where you can place a byte group—two on each
side of the device. The smaller devices only have a total of four groups—
one on each side of the device. On all devices, if the LHS power bank is
configured for anything other than 2.5V (e.g., if you are using
configuration devices), that side of the device is no longer available for use
as DDR SDRAM pins. The EP1C3T100 cannot use the LHS or RHS of the
device for 2.5V DDR, so is always limited to a maximum of three byte
groups. The JTAG and configuration output pins are on the RHS and must
be configured for 2.5 V operation, to use that side of the device for DDR.
1
Altera Corporation
The wizard does not make assignments for the address and
control pins; you must make these pin assignments.
31
Getting Started
a.
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Figure 8. Select Byte Group Position
Complete the Custom Core
To complete your custom core, perform the following steps:
1.
The final screen lists the design files that the wizard creates (see
Figure 9). Click Finish.
The wizard generates the following files:
–
–
–
–
–
–
–
32
One of the following files (depending on your selection), which
are used to used to instantiate an instance of the function in your
design:
AHDL text design file (<variation name>.tdf)
VHDL design file (<variation name>.vhd)
Verilog HDL design file (<variation name>.v)
A symbol file (<variation name>.bsf) used to instantiate the
function into a schematic design
An include file <variation name>.inc (Verilog HDL and AHDL
only)
An example of the instantiation of the core <variation name> _inst
A blackbox Verilog HDL model, <variation name>_bb (Verilog
HDL only)
A component declaration file <variation name>.cmp (VHDL only)
<variation name>_quartus_script.tcl, which can be used to apply
the necessary constraints to your custom core (not applicable for
Cyclone devices)
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
–
–
GettingGetting Started
<dummy top-level wrapper>, which instantiates your synthesized
instance of the DDR SDRAM Controller, some dummy logic, and
the necessary PLLs
A plain-text configuration file user_assignments.txt that is read
in by the Cyclone constraint generation script. This file defines
the byte group locations, which you chose using the floorplanner
on page 4 of the wizard, with other assignments. Cyclone devices
only.
<variation name> is the variation name that you chose in the
MegaWizard Plug-In.
1
<dummy top-level wrapper> is the dummy top-level design
name, which you chose on page 1 of the wizard. The default
name is <variation name>_dummy_top.
Figure 9. Design Files
2.
Altera Corporation
Before performing any other actions, read and click OK on the
message window (Figure 10).
33
2
Getting Started
1
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Figure 10. Message
When you have created your custom megafunction, you can integrate it
into your system design and compile.
Using the
Reference
Design
The reference design is the same for all device families with different
parameters: 32-bits for Stratix and APEX II devices; 16-bits for Cyclone
devices.
1
–
–
–
f
Altera recommends that you copy the following directories to a
new directory <working directory> before use:
/reference_design
/testbench
/user_simulation
For more information on the reference design for Cyclone devices, read
the doc/readme_test_stim.txt file.
Set Up the Reference Design
To set up the reference design, perform the following steps:
34
1.
Choose Open Project (File menu).
2.
Browse to the \<working directory>\reference_design\<family>
directory. Click Open. Choose example_top.quartus and click Open.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingGetting Started
3.
You must specify the DDR SDRAM Controller’s library directory
(<path>\ddr_sdram-<version>\lib) as a user library in the Quartus II
software. Search for “User Libraries” in Quartus II Help for
instructions on how to add a library.
4.
Choose MegaWizard Plug-In Manager (Tools menu).
5.
Select Edit an existing Custom Megafunction and click Next.
6.
Choose mw_wrapper.vhd file and Click Next.
7.
Click Finish.
8.
Getting Started
1
2
Do not change any of the MegaWizard Plug-In settings.
Click OK on any warning messages.
Compile the Reference Design
For Cyclone devices, perform the following steps:
1.
Open a Command Prompt.
2.
Type the following command:
cd <working directory>/reference_design/cyclone_example
3.
Type the following command:
generate_quartus_tcl_script_for_ref_design
1
4.
Do not run the generate_quartus_tcl_script.bat file.
In the Quartus II Tcl console type the following command:
source add_constraints.tcl
5.
Choose Start Compilation (Processing menu).
For Stratix and APEX II devices, perform the following steps:
1.
In the Quartus II Tcl console type the following command:
source mw_wrapper_quartus_script.tcl
2.
Altera Corporation
Choose Start Compilation (Processing menu).
35
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
Post-route Simulation
To simulate in the ModelSim simulator, perform the following steps:
f
Configure the
PLL
1.
Open the ModelSim simulator. Select Change Directory (File menu)
and change to the \<working directory>\user_simulation directory.
2.
Choose Execute Macro (Macro menu).
3.
For ModelSim PE choose simulate_<family>_ref_design_gate.do;
for ModelSim-Altera simulate_ae_<family>_ref_design_gate.do
and click Open.
For more information on the reference design test stimulus, see the
/reference_design/test_stimulus/readme_test_stim.txt file
If you have specified a frequency other than 133.333 MHz, you must edit
the following PLL instances:
■
■
/lib directory for the dummy top-level flow
/reference_design directory for the reference design
To edit the PLL instances for the dummy top-level flow, perform the
following steps:
1.
Open the Quartus II software.
2.
Choose Open Project (File menu).
3.
Browse to your relevant project. Click Open.
4.
Choose MegaWizard Plug-In Manager (Tools menu).
5.
Select Edit an existing Custom Megafunction and click Next.
6.
Choose the \ddr_sdram-v<version>\lib directory in the Look-In
box.
7.
Choose the appropriate example_<family>.vhd file and Click Next.
8.
Edit the PLL instance and click Finish.
To edit the PLL instances in the reference design, perform the following
steps:
1.
36
Open the Quartus II software.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
2.
Choose Open Project (File menu).
3.
Browse to the \ddr_sdram-v<version>\reference_design\<family>
directory. Click Open. Choose example_top.quartus and click Open.
4.
Choose MegaWizard Plug-In Manager (Tools menu).
5.
Select Edit an existing Custom Megafunction and click Next.
6.
Choose example_pll_<family>.vhd file and Click Next.
7.
Edit the PLL instance and click Finish.
2
Altera provides a ModelSim VHDL model that you can use to simulate the
DDR SDRAM Controller in your system. Altera also provides a Visual IP
model in the sim_lib\visualip directory, which you can use with the
Visual IP software and is supported by other Verilog HDL and VHDL
simulators. The VHDL model is supplied as pre-compiled libraries for the
ModelSim simulation tool and is installed in the
sim_lib\modelsim\vhdl\ directory. You can use these models to
simulate the core in your system, or you can use them with the testbench
provided with the core.
Simulate with the ModelSim VHDL Model
Before you simulate the VHDL model of your instance using the testbench
in the ModelSim software, perform the following steps:
Altera Corporation
1.
Download the Micron MT46V16M8 128-MB memory model (or
equivalent) to the \ddr_sdram-v<version>\testbench\vhdl
directory from the Micron web site,
http://www.micron.com/products/simmodel.jsp?path=/DRAM/
DDR+SDRAM.
2.
Open the Quartus II software.
3.
Choose Open Project (File menu).
4.
Browse to the \ddr_sdramv<version>\user_simulation\proj_for_your_instance directory.
5.
Choose example.quartus and click Open.
6.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
37
Getting Started
Behavioral
Simulation
GettingGetting Started
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
7.
Specify that you want to edit a custom megafunction and click Next.
8.
Choose example.vhd (see Figure 11).
Figure 11. Choose Example.vhd
9.
Choose your parameters (see “Choose the Parameters” on page 23).
1
Set small value (e.g., 50) for memory initialization time, to keep
the simulation time short.
10. Click Finish.
11. Click OK on the constraint script warning message.
1
You need not run the constraints scripts in this Quartus II project
unless you want to compile this project.
To simulate the VHDL model of your instance in the ModelSim
simulation tool, perform the following steps:
38
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingGetting Started
1.
Open the ModelSim simulator. Select Change Directory (File menu)
and change to the \ddr_sdram-v<version>\user_simulation
directory.
2.
Choose Execute Macro (Tools menu).
3.
Choose simulate_your_instance_rtl.do (see Figure 12) and click
Open.
2
Figure 12. Select simulate_your_instance_rtl.do
Getting Started
The simulate_your_instance_rtl.do script performs the following
functions:
■
■
■
■
■
■
Maps the provided library
Refreshes the library
Creates a working library work
Compiles your instance and the provided testbench into work
Executes vsim and opens a wave window with the testbench signals
Passes in parameters
Simulate with the Visual IP Model
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
1.
Altera Corporation
Point your web browser at
https://www.altera.com/support/software/download
/eda_software/visualip/dnl-visualip.jsp.
39
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
2.
Follow the on-line instructions to download the Innoveda Visual IP
software and save it to your hard disk.
To use the Visual IP model, perform the following steps:
1.
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Compile the wrapper for the core model.
The Verilog HDL version of the wrapper is in the
sim_lib\visualip\auk_ddr_sdram\interface\pli directory;
the corresponding VHDL version is in the
sim_lib\visualip\auk_ddr_sdram\interface\mti directory.
3.
Compile the memory model that you want to use.
4.
Compile the wizard-generated wrapper <variation name>.vhd,
<variation name>.v.
The Visual IP model is now ready for use in your simulator.
Compile &
Place-&-Route
After you have verified that your design is functionally correct, you are
ready to compile and place-and-route your design. The Quartus II
software works seamlessly with tools from many EDA vendors, including
Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and
Viewlogic.
Cyclone Devices
For Cyclone devices, before you compile and place-and-route your
project, perform the following steps:
1.
Open a Command Prompt.
2.
Type the following command:
cd <your project>
3.
Type the following command:
generate_quartus_tcl_script
40
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
4.
GettingGetting Started
In the Quartus II Tcl console type the following command:
source add_constraints.tcl
5.
Choose Start Compilation (Processing menu).
Stratix & APEX II Devices
If you selected an APEX II device in the MegaWizard Plug-In, the Quartus
II constraint script performs the following actions on your Quartus II
project:
■
■
■
■
Selects an APEX II device (EP2A15C672)
Applies the necessary Quartus II constraints for your chosen
frequency
Creates LogicLock™ regions that place the controller in the bottom
right of the APEX II device
Applies a sample pin configuration to match the controller
If you selected a Stratix device in the MegaWizard Plug-In, the Quartus II
constraint script performs the following actions on your Quartus II
project:
■
■
■
■
f
Copies the reference design files into your project directory
Selects a Stratix device (EP1S25F1020)
Applies the necessary Quartus II constraints for your chosen
frequency
Applies a sample pin configuration to match the controller
For more information on LogicLock incremental design capability, refer to
AN 161: Using the LogicLock Methodology in the Quartus II Design Software.
To apply the Quartus II constraint script, perform the following steps:
1.
Choose Auxiliary Windows > Tcl Console (View menu).
2.
In the Tcl console window type the following command:
source <variation name>_quartus_script.tcl
Altera Corporation
41
2
Getting Started
Before you compile and place-and-route your project, you should run the
MegaWizard Plug-In generated Quartus II constraint script (<variation
name>__quartus_script.tcl), or follow the manual procedure in
“Appendix A—The Quartus II Constraint Settings” on page 67.
Getting Started
DDR SDRAM Controller MegaCore Function User Guide
You can now compile your design. The Quartus II Compiler synthesizes,
performs place-and-route, and applies the necessary timings to your
design.
1
Timing
Analysis
Refer to the Quartus II Help for further instructions on
performing compilation.
After you have compiled your design in Quartus II, to check that the
timing requirements have been met, perform the following step:
v Check the compiler messages in the Processing tab in the Messages
window.
If the timing requirements were met, the following message appears
during compilation:
All timing requirements were met. See Report window for
more details.
If timing requirements were not met, open the Timing Analysis folder in
the Compilation Report window. Open the Clock Requirements section
for each clock to check that all requirements were met. Paths that failed to
meet timing requirements are marked in red.
1
Perform PostRoute
Simulation
42
You can use the MegaWizard-generated system to check timing
in the Quartus II software. However, if you want to perform
hardware testing or gate-level simulation, use the reference
design.
If you have licensed the core, you can generate EDIF, VHDL,
Verilog HDL, and standard delay output files from the Quartus II
software and use them with your existing EDA tools to perform functional
modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, see “Compile &
Place-&-Route” on page 40. The Quartus II software generates
output and programing files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for
postroute, device-level, and system-level simulation.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
1
License for
Configuration
GettingGetting Started
Alternatively, you can use the reference design for post-route
simulation, see “Post-route Simulation” on page 36.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FPGA. If you are evaluating the DDR
SDRAM Controller with the OpenCore feature, you must license the
function before you can generate programming files. To obtain licenses
contact your local Altera sales representative.
2
Getting Started
Altera Corporation
43
Notes:
Specifications
1
The DDR SDRAM Controller instantiates a control logic module and one
or more data path modules. Figure 13 shows a block diagram of the DDR
SDRAM Controller.
Specifications
DII Interface
Functional
Description
Figure 13. DDR SDRAM Controller Block Diagram
raddr
r_req
w_req
b_size
Control
Logic
rw_ack
r_valid
d_req
w_valid
a
ba
cs_n
ras_n
cas_n
we_n
cke
3
Specifications
clk
Local Bus
Interface
SDRAM
Interface
clk_shifted
dq
Data Path
Modules
datain
dqs
dataout
dm_in
dm
Signals
Table 13 shows the DDR SDRAM Controller local interface signals; Table
14 shows the DDR SDRAM Controller SDRAM interface signals. The local
interface signals operate on the positive edge of clk with the following
exception:
■
Altera Corporation
dataout[] is generated on either the positive or negative edge of
clk depending on the read resynchronization phase setting (see
45
Specifications
DDR SDRAM Controller MegaCore Function User Guide
“Resynchronization of Captured Read Data from the DQS to the
System Clock Domain” on page 78). For a resynchronization phase of
0 or 2, the output is generated on the positive edge; for 1 or 3, the
output is generated on the negative edge.
The assumption is that dataout[] is always sampled on the positive
edge of clk by the user's logic that is connected to the local-side interface.
For this reason, r_valid is always generated on the positive edge of clk,
regardless of whether dataout[] is generated on the positive or negative
edge of clk. The core adjusts the timing of r_valid according to the read
resynchronization phase.
Table 13. Local Interface Signals (Part 1 of 2)
Signal
I/O
Description
clk
Input
System clock.
clk_shifted
Input
clk_shifted is a shifted version of clk that is used only for SDRAM
write data.
clk_shifted must lead clk by 90° (lag by 270°).
reset_n
Input
System reset.
raddr[asize-1:0]
Input
Memory address for read/write requests. Width is set by asize. (1)
The raddr input corresponds to the chip, row, bank, and column
address in the SDRAM as follows:
raddr = (ch, rw, bn, co)
where:
ch = 1 bit (2 chip selects)
rw = number of row bits, e.g., 12
bn = number of bank bits, e.g., 2
co = number of column bits minus 1 (the LSB is unnecessary as local
address is twice the width of the SDRAM data width).
b_size[2:0]
Input
Burst size. Specifies the local-side burst size (1, 2, or 4) of the requested
access, which correspond to SDRAM burst sizes of 2, 4, and 8
respectively.
r_req
Input
Read request.
w_req
Input
Write request.
rw_ack
Output Read/write acknowledge. Acknowledgement of the present read or write
request.
46
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
Table 13. Local Interface Signals (Part 2 of 2)
Signal
I/O
Description
d_req
Output Data request. Indicates to the local bus interface that it should present
data on the next clock edge.
r_valid
Output Read data valid. When r_valid is sampled high on the positive edge of
clk, you can sample valid read data at the same time.
The timing of this signal adjusts according to different user-selected read
sample phases (see “Resynchronization of Captured Read Data from the
DQS to the System Clock Domain” on page 78).
For sample phases 0 and 1, r_valid goes high as early as is possible.
For sample phases 2 and 3, r_valid goes high one cycle later to
account for the extra cycle delay in sampling the read data from the
SDRAM.
The r_valid signal is always generated on the positive edge of clk.
w_valid
Output Write data valid. Indicates when data has been accepted by the DDR
SDRAM Controller.
datain[dsize-1:0]
Input
dataout[dsize-1:0]
Output Read data bus; width is set by dsize.
dm_in[(dsize/8)-1:0]
Input
Write data bus; width is set by dsize. (2)
3
Notes to Table 13:
(1)
(2)
asize is ch + rw + bn + co.
dsize is twice the width of the SDRAM data bus.
Altera Corporation
47
Specifications
Data mask. Masks individual bytes during data write. There is one dm_in
bit per byte.
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Table 14. SDRAM Interface Signals
Signal
I/O
Description
a[n:0]
Output
Address bus. The a bits are sampled during the ACT command to latch
Note (1) the row address and are sampled during the RD/WR command to latch
the column address. n depends on the size of SDRAM.
ba[n:0]
Output
Bank address. These signals determine to which bank the ACT, RD, WR,
Note (1) or PCH command is applied. n depends on the number of banks in the
SDRAM.
cs_n[n:0]
Output
SDRAM chip selects. n depends on the number of chip selects in the
Note (1) SDRAM.
cke
Output
SDRAM clock enable signal.
Note (1)
ras_n
Output
Row address strobe SDRAM command input.
Note (1)
cas_n
Output
Column address strobe SDRAM command input.
Note (1)
we_n
Output
Write enable, SDRAM command input.
Note (1)
dq[dsize/2-1:0]
I/O
SDRAM data bus (half the width of local bus).
dm[(dsize/16)-1:0]
Output
SDRAM data masks, which masks individual bytes during data write.
There is one dm bit per byte of dq.
dqs[(dsize/16)-1:0] I/O
SDRAM data strobe, which strobes data into the DDR devices during a
write operation and samples data into the Altera device in a read
operation. There is one dqs bit per byte of dq.
Note to Table 14:
(1)
48
The DDR SDRAM Controller can generate this output on either the positive or the negative clk edge.
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
Control Logic Module
Bus commands control SDRAM devices using combinations of the ras_n,
cas_n, and we_n signals. For instance, on a clock cycle where all three
signals are high, the associated command is a no operation (NOP). A NOP
command is also indicated when the chip select signal is not asserted.
Table 15 shows the standard SDRAM bus commands.
Table 15. Bus Commands
Command
Acronym
ras_n
cas_n
we_n
No operation
NOP
H
H
H
Active
ACT
L
H
H
Read
RD
H
L
H
Write
WR
H
L
L
Burst terminate
BT
H
H
L
PCH
L
H
L
Auto refresh
ARF
L
L
H
Load mode register
LMR
L
L
L
Precharge
3
The primary commands used to access SDRAM are read (RD) and write
(WR). When the WR command is issued, the initial column address and
data word is registered. When a RD command is issued, the initial address
is registered. The initial data appears on the data bus 1.5 to 3 clock cycles
later. This delay is the CAS latency and is due to the time required to read
the internal DRAM core and register the data on the bus. The CAS latency
depends on the speed of the SDRAM and the frequency of the memory
clock. In general, the faster the clock, the more cycles of CAS latency are
required. After the initial RD or WR command, sequential reads and
writes continue until the burst length is reached or a burst terminate (BT)
command is issued. DDR SDRAM memory devices support burst lengths
of 2, 4, or 8 data cycles. The auto refresh command (ARF) is issued
periodically to ensure data retention. This function is performed by the
DDR SDRAM Controller.
The load mode register command (LMR) configures the SDRAM mode
register. This register stores the CAS latency, burst length, burst type, and
write burst mode. Refer to the specification of the SDRAM you are using
for more details.
Altera Corporation
49
Specifications
The DDR SDRAM Controller must open SDRAM banks before it accesses
a range of addresses. The row and bank to be opened are registered at the
same time as the active (ACT) command. The DDR SDRAM Controller
closes the bank and opens it again, if it wants to access a different row. The
precharge (PCH) command closes a bank.
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Data Path Module
The data path module provides the SDRAM data interface to the local bus.
Local data is accepted on datain for write commands and data is
provided to the local interface on dataout during read commands.
Figures 14 to 17 show block diagrams of the data path module. The data
path width in and out of the controller is twice the data path width to the
DDR SDRAM devices—the DDR SDRAM data interface is clocked on
both edges.
Figure 14. APEX II Data Path Module Block Diagram (Read)
FPGA LEs
I/O elements
dq_oe
dq[7:0]
dq_out
Q
D
Q
D
Q
D
Q
D
dataout[15:0]
Q
D
FastRow Interconnect
Programmable Delay
clk
dqs_oe
dqs
dqs_out
Optional inversion (see Note 1)
Note:
(1)
50
You specify the optional inversion in the MegaWizard Plug-In.
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
Figure 15. Stratix Data Path Module Block Diagram (Read)
FPGA LEs
I/O elements
dq_oe
dq[7:0]
dq_out
Q
D
Q
Q
D
Q
D
dataout[15:0]
D
Q
D
ena
clk
latch
dqs_oe
dqs
dqs_out
Optional inversion (see Note 1)
dqs
Local Bus
90˚ Compensated
Delay Shift
3
Note:
(1)
In the read direction, the double-rate data from the dq pins are fed into a
positive and a negative-edge triggered register to sample data on both
edges of the data strobe signal (dqs). This signal is then passed through
another set of configurable registers to return it to the system clock
domain. You can configure the clock edge that these two registers are
clocked off in the MegaWizard Plug-In, to achieve good setup and hold
times in the transition from the dqs clock domain to the system clock
domain.
In APEX II devices, the DDR SDRAM Controller uses I/O element (IOE)
registers in the write direction to clock output signals, but uses logic
element (LE) registers in the read direction to clock input signals. Using
LE registers allows inputs to be clocked in with the dqs signals (via the
FastRow™ interconnect) without using any global clock resources. This
configuration has been successfully tested in hardware at speeds of up to
133 MHz.
In Stratix devices, the DDR SDRAM Controller uses IOE registers in the
write and the read direction. In the read direction, it uses the Stratix phase
shifting reference circuit, which provides a compensated delay of 90° on
each dqs signal that is used to sample the dq read data.
Altera Corporation
51
Specifications
You specify the optional inversion by selecting the appropriate read synchronization phase in the MegaWizard
Plug-In.
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Figure 16. APEX II & Stratix Data Path Module Block Diagram (Write)
FPGA LEs
dq_oe
I/O elements
D
Q
D
datain[15:0]
D
Q
[15:8]
D
Q
Q
dq[7:0]
clk
D
Q
[7:0]
D
Q
clk_shifted
dq_in
The data path module’s datain and dataout are fixed at 16 bits and dq
is fixed at 8 bits. To build data paths larger than 16 bits, the MegaWizard
Plug-In cascades data path modules to increase the data bus width in
increments of 16 bits (8 bits for SDRAM side).
In the write direction, the datain signal is registered and the passed into
the registers in the IOE where it is multiplexed onto the dq pins. This
signal is clocked by a phase-shifted clock so that the dqs signal, also
generated by the data path module, appears in the center of the data on
the dq pins.
52
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
Figure 17. Cyclone Data Path Module Block Diagram (Read and Write) Note (1), (2), (3)
FPGA LEs
dq_oe
I/O elements
Q
D
Q
clk
8
datain
D
Q
D
Q
0
16
S_Ao
8
D
D
Q
AOE
MUX
dq
Ao
1
Q
S_Bo
Bo
clk_shifted
8
Q
D
Q
D
Q
D
Ai
S_Ai
Ci
8
dataout
Q
D
Q
D
16
Bi
S_Bi
Programmable Delay
3
Delay
AND
BOE
Note 2
Specifications
AOE
dqs_oe
(Note 3)
D
Q
dqs_control
D
Q
D
Q
0
MUX
dqs
1
2
1
dm_in
D
Q
D
0
Q
MUX
Ao
1
D
Q
D
dm
1
Q
Bo
altddio Megafunctions
Notes:
(1)
(2)
(3)
This figure shows the logic for one dq output only. A complete byte group consists of eight times the dq logic with
the dqs and dm logic.
Each dqs requires a global clock resource. Invert combout of the altddio_bidir megafunction for the dqs pin before
feeding in to in_clock of the altddio_bidir megafunction for the dq pin.
dqs_oe is active high.
Altera Corporation
53
Specifications
Controller
Access
Operation
DDR SDRAM Controller MegaCore Function User Guide
The DDR SDRAM Controller provides a synchronous command interface
to the SDRAM. The following sections describe the controller access
operation.
Write Operation
When the local bus requests a memory write, the DDR SDRAM Controller
writes to the SDRAM using the following memory command sequence:
■
■
ACT
WR
Figure 18 on page 55 shows a typical sequence of DDR SDRAM Controller
writes—three writes, two writes of four cycles, and one of two cycles. (For
the SDRAM, there are two writes of eight cycles followed by a one write
of four cycles). This typical sequence is described below:
54
1.
The write request (w_req) signal is asserted with the address
(raddr) and the burst size (b_size). The local bus requests to write
four cycles’ worth of data to the SDRAM.
2.
If writing to a row that is not already open, the DDR SDRAM
Controller asserts the row address (a), bank address (ba), and
chip-select (cs_n) signals, and the ACT command. In this case, the
write targets a row that has previously been accessed so this is not
necessary.
3.
The DDR SDRAM Controller acknowledges the write request
(rw_ack) and requests data from local interface (d_req).
4.
Two clock cycles later, the DDR SDRAM Controller begins writing
the data with the WR command. The controller asserts the w_valid
signal to indicate that it has accepted the data during the write
sequence. Four data cycles are processed.
5.
The local interface write-request (w_req) remains asserted after the
DDR SDRAM controller asserts an acknowledge (rw_ack),
indicating it wishes to initiate another burst. After acknowledging
the first write request, the local interface changes the local address.
6.
As soon as the four write cycles from the first request are processed,
the next WR command is issued and the four data cycles begin.
7.
After acknowledging the second write request, the local interface
changes the address and the burst size to two.
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
8.
After acknowledging the third write request, the local bus deasserts
write requests and the DDR SDRAM Controller finishes writing data
to the DDR SDRAM.
1
If a write to a different bank or row is requested, a PCH and
ACT command sequence is automatically inserted between
the data cycles.
Figure 18. DDR SDRAM Controller Write Access Note (1)
[1]
[3] [5]
[4] [7]
[6]
sys_clk
0000
dm
b_size
4
4
2
raddr
addr A
addr B
addr C
r_req
Local Bus
Interface
w_req
3
rw_ack
Specifications
r_valid
dataout
d_req
w_valid
A1
datain
col 1
a
A2
A3
A4
B1
B2
B3
col 2
B4
C1
C2
col 3
ba
0
0
0
cs_n
2
2
2
cke
DDR
SDRAM
Interface
ras_n
cas_n
we_n
dq
dm_in
FF
00
FF
dqs
Note:
(1)
The numbers in brackets refer to the step numbers in the preceding text.
Altera Corporation
55
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Read Operation
When the local bus requests a memory read, the DDR SDRAM Controller
reads the SDRAM using the following memory command sequence:
■
■
ACT
RD
Figure 19 on page 57 shows a typical DDR SDRAM Controller read
sequence—three reads, two reads of four cycles followed by a read of two
cycles (for the SDRAM, there are two reads of eight cycles followed by a
read of four). This typical sequence is described below:
56
1.
The read request (r_req) signal is asserted with the address
(raddr) and the burst size (b_size). The local interface requests
four cycles worth of data from the SDRAM.
2.
If the current row is not open, the DDR SDRAM Controller asserts
the row address (a), bank address (ba), chip select (cs_n) signals,
and the ACT command.
3.
The DDR SDRAM Controller acknowledges the read request
(rw_ack) and issues the RD command. The data appears on the
local interface (dataout) a fixed number of clock cycles after the RD
command is issued, depending on the CAS latency (2.5 in this case).
The r_valid signal indicates valid data on the local interface.
4.
After the controller asserts the acknowledge signal (rw_ack), the
read request (r_req) signal remains asserted, indicating that
another read command should be issued. After acknowledging the
first read request, the local bus changes the local address.
5.
As soon as the four read cycles from the first read request are
processed, the second read command is issued and the second read
cycle begins.
6.
After an acknowledge of the second read sequence, the local
interface changes the local address and burst size to two.
7.
As soon as the four read cycles from the second request are
processed, the next RD command is issued and the two data cycles
begin.
8.
Because the current read burst length (2) is shorter than the memory
burst length (4), the controller issues a burst terminate (BT) signal to
the SDRAM to indicate that it should abort the burst.
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
1
If one of the reads goes to a different bank or row, a PCH and
ACT command sequence is automatically inserted between
the data cycles.
Figure 19. DDR SDRAM Controller Read Access Note (1)
[1]
[3] [4]
[6]
[5]
[7]
[8]
sys_clk
dm
0000
b_size
4
4
2
raddr
addr A
addr B
addr C
r_req
Local Bus
Interface
w_req
rw_ack
r_valid
A1
dataout
A2
A3
A4
B1
B2
B3
B4
C1 C2
3
d_req
Specifications
w_valid
datain
a
col 1
col 2
col 3
ba
0
0
0
0
cs_n
2
2
2
2
cke
DDR
SDRAM
Interface
ras_n
cas_n
we_n
dq
dm_in
FF
dqs
Note:
(1)
The numbers in brackets refer to the step numbers in the preceding text.
Altera Corporation
57
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Refresh Timing
The refresh timer causes the DDR SDRAM Controller to refresh the
SDRAM periodically, which maintains the contents. Refreshing is
performed by using the following memory command sequence:
■
■
PCH
ARF
The auto-refresh command period (see “Choose the Parameters” on
page 23) specifies the time that must elapse following a refresh command.
The time is specified in clock cycles because of variability caused by
different clock speeds.
Figures 20 shows the DDR SDRAM Controller auto-refresh sequence. This
sequence is described below:
1.
A PCH command is sent to all banks by setting address bit a[10]
high.
2.
An ARF command.
3.
After the auto-refresh command period (RFC) expires, the DDR
SDRAM Controller issues the next command.
Figure 20. Refresh Timing Note (1)
[1]
[2]
[3]
clk
cke
sa
0x400
ba
0
cs_n
0
ras_n
cas_n
we_n
Note:
(1)
58
The numbers in brackets refer to the step numbers in the preceding text.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingSpecifications
Initialization Timing
The DDR SDRAM Controller initializes the SDRAM memory devices by
issuing the following memory command sequence:
■
■
■
■
■
■
■
■
■
NOP (for 200 µs, programmable)
PCH
extended LMR (ELMR)
LMR
PCH
ARF
ARF
LMR
NOP (for 200 cycles of clk, fixed)
Figure 21 on page 60 shows a typical initialization timing sequence, which
is described below. The length of time between the reset and the first PCH
command should be 200 µs. This time can be reduced for simulation
testing by setting the start-up timer parameter in the MegaWizard PlugIn.
A PCH command is sent to all banks by setting address bit a[10]
high.
2.
An ELMR command enables the internal DLL in the memory
devices. An ELMR command is an LMR command with the bank
address bits set to address the extended mode register.
3.
An LMR command sets the operating parameters of the memory
such as CAS latency (CL) and burst length (BL). This LMR command
is also used to reset the internal DLL. The DDR SDRAM Controller
allows 200 clock cycles to elapse after a DLL reset and before it issues
a read command to the memory.
4.
A further PCH command places all the banks in their idle state.
5.
Two ARF commands must follow the PCH command.
6.
The final LMR command programs the operating parameters
without resetting the DLL.
The DDR SDRAM Controller does not send any read or write commands
to the memory until the 200 cycles of clk required after a DLL reset have
expired.
Altera Corporation
3
Specifications
1.
59
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Figure 21. DDR SDRAM Device Initialization Timing Note (1)
[1]
[2]
[3]
[4]
[5]
[5]
[6]
sys_clk
cke
sa
0
ba
cs_n
0
0
0
1
0
0
0
0
0
0
0
0
ras_n
cas_n
we_n
Note:
(1)
The numbers in brackets refer to the step numbers in the preceding text.
Miscellaneous SDRAM Settings
The DDR SDRAM Controller implements the following mode register and
extended-mode register settings that are not programmable:
■
■
60
The burst type is sequential (interleaved cannot be selected)
The drive strength is normal (reduced cannot be selected)
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
PLL
Configuration
GettingSpecifications
The PLL configuration differs for APEX II, Stratix, and Cyclone devices.
1
For Stratix GX devices, see “Cyclone & Stratix Devices” on
page 62.
APEX II Devices
The DDR SDRAM Controller requires two or three PLLs, depending on
whether or not a full-rate clock is available on the board as an input to the
APEX II device. Figure 22 shows the case where only a slower-rate clock
(e.g., 33.33 MHz) is available and one of the PLLs is used to multiply the
clock up to the full SDRAM clock rate.
Although the output of PLL2 is nominally the 0° output, in a real
hardware system you must apply a phase shift to the PLL2 clock. At the
DDR SDRAM inputs, the dqs signal and the clock should be in phase. The
differential clock signal comes directly from the clock buffer, but the dqs
signal is generated by the APEX II. You must compensate for the time-tooutput of the dqs signal and the PCB propagation delay of the dqs signal
to the DDR SDRAM, by advancing the phase of the PLL. To measure the
exact phase shift required, set the PLL shift to 0° and measure the
difference in phase between the dqs and clock signals. On the APEX II
memory interface board, which we used for hardware testing of the DDR
SDRAM Controller, an advance of 3ns is required. Because the PLL can
really only delay a clock, at 133MHz, the necessary delay is 4.5ns (7.5 - 3.0
= 4.5), see “Resynchronization of Captured Read Data from the DQS to the
System Clock Domain” on page 78.
f
Altera Corporation
For more information on the APEX II memory interface board, see “Core
Verification” on page 64.
61
3
Specifications
In this clocking scheme, PLL 1 multiplies the slower board-level clock up
to the memory system speed. If the clock is 33.33 MHz, a ×3 or ×4 multiply
produces a 100-MHz or 133-MHz clock, respectively. The resulting clock
from the APEX II device drives the differential clock buffer (e.g., Cypress
W256). The output of the clock buffer is sent back to the input of PLL 4
from where it can be internally routed to PLL 2 and PLL 4. PLL 2 creates
the main system clock, synchronous to the clocks to the SDRAM, while
PLL 4 creates the phase-shifted clock, which generates the write data
phase difference.
Specifications
DDR SDRAM Controller MegaCore Function User Guide
In Figure 22, register A represents the command and address outputs of
the controller, which are clocked off the output of PLL 2. Register B is
clocked with the read data strobe (dqs) to sample the read data into the
controller. Register C represents the data being brought back into the
system clock domain. You can clock register C off either edge of PLL 2’s
output, depending on your choice of rising or falling clock edge in the
MegaWizard Plug-In. Register D generates the outgoing write data and is
clocked off the output of PLL 4.
1
If a full-rate clock is available, you only need PLL 2 and PLL 4.
Connect the full-rate clock directly to the input of the external
clock buffer and connect the feedback output of the buffer to the
input of PLL 4.
Figure 22. APEX II PLL Configuration
FPGA
33.33 MHz
clock_source
133.33 MHz
PLL 1
(x3 or x4
if used)
PLL 2
(normal)
clk_to_buf
DDR SDRAM
Controller
clk
C
A
Write dqs and control
DDR SDRAM
B
PLL 3
(unused)
Read dqs
D
clock_from_buf
PLL 4
(phase
shift)
Write dq
clk_shifted
The APEX II memory interface board used this PLL configuration (see
“Board Design Package” on page 65).
Cyclone & Stratix Devices
The recommended configuration for implementing the DDR SDRAM
Controller in a Cyclone or a Stratix (including Stratix GX) device is to use
a single enhanced PLL to produce all the required clock signals. No
external clock buffer is required as the differential clock buffer can
generate clk and clk# signals for DDR SDRAM memory devices.
62
Altera Corporation
GettingSpecifications
DDR SDRAM Controller MegaCore Function User Guide
The main difference between clock configuration for Stratix and Cyclone
devices is that Cyclone devices do not have the DQS phase shift reference
circuit. Thus Cyclone devices do not need the additional dqs_ref_clk
clock input, which drives this circuit.
Figure 23 shows the recommended configuration for Stratix devices for
use with any PLL multiply or divide ratio including a ratio of one.
Figure 24 shows an optional Stratix configuration for use only when the
PLL input clock frequency (clock_source) equals the required SDRAM
clock (clk_to_sdram). A separate reference clock input is not required
in this instance. Figure 25 shows the Cyclone configuration for use with
any PLL multiply or divide ratios including a ratio of one.
1
f
The dqs_ref_clk input for Stratix devices can be either fedback from the clock output driving the SDRAM or a separate
clock output from the PLL. The phase of dqs_ref_clk relative
to the other clocks in the system is unimportant.
For more detail on the relationships between the different clocks, see
“Appendix B—DDR SDRAM Timing Analysis” on page 75.
3
Specifications
Figure 23. Stratix PLL Configuration
dqs_ref_clk
Stratix Device
DQS Phase
Reference
Circuit
clock_source
Enhanced
PLL
(xN/M)
clk
clk_ext
clk_to_sdram
clk_shifted
DDR SDRAM
DDR SDRAM
Controller
Altera Corporation
63
Specifications
DDR SDRAM Controller MegaCore Function User Guide
Figure 24. Stratix PLL Configuration (Clock Input Frequency equal to SDRAM
Clock)
Stratix Device
DQS Phase
Reference
Circuit
Enhanced
PLL
(x1 only)
clock_source
clk_ext
clk
clk_to_sdram
clk_shifted
DDR SDRAM
DDR SDRAM
Controller
Figure 25. Cyclone PLL Configuration
Cyclone Device
clk_ext
PLL
(xN /M)
clock_source
clk
clk_to_sdram
clk_shifted
DDR SDRAM
DDR SDRAM
Controller
Core
Verification
64
Core verification involves hardware testing and simulation testing.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingSpecifications
Simulation Testing
Altera has carried out extensive gate-level tests of the DDR SDRAM
Controller with industry-standard Denali memory models to ensure that
it meets the necessary timing parameters. A full timing simulation for
APEX II and Stratix devices of a typical PCB, including propagation
delays, was used to test the performance of the DDR SDRAM Controller
in an APEX II device. This was tested against Denali models of Micron
MT46V16M8TG_75 devices.
Hardware Testing
Altera has carried out hardware testing of the DDR SDRAM Controller
v1.1.0 using the APEX II memory interface board. The testing was carried
out at 133 MHz with an Altera EP2A15C672C7 device and PC2100 DDR
DIMMs (e.g., Micron MT8VDDT1664AG-265A1).
f
For more information on the APEX II memory interface board, contact
your Altera representative.
3
The following tests were carried out:
■
■
■
■
■
■
■
Walking ones on data lines
Worst-case data patterns (e.g., all 64 data bits switching from zero to
one at the same time)
Varying burst sizes (2, 4, 8 cycles)
Wrapping bursts
Column, bank and row changes
Partial writes (data mask tests)
Back-to-back writes and reads
Chip selects
Soak tests—repetitive combinations of the above at room
temperature for 24 hours at a time
Board Design Package
The following deliverables for board design are available for DDR
SDRAM customers from an Altera representative:
■
■
■
■
■
■
■
Altera Corporation
Schematic capture in ORCAD and PDF format
Timing analysis in Microsoft PowerPoint and PDF format
Power analysis in Microsoft Word, Excel, and PDF format
PCB design files in PADS and PDF format for each layer
PCB Gerber files
Block diagrams of board design in Visio, Word, and PDF format
IBIS models for the main memories and Altera devices in text and
PDF format
65
Specifications
■
■
Notes:
Appendix A—The Quartus II
Constraint Settings
This appendix describes how to manually apply the necessary constraints
to the Quartus II software for the DDR SDRAM Controller for Stratix or
APEX II devices. You must manually apply the constraints if your
requirements are different from those applied by the wizard-generated
Quartus II constraint script. For example, you may require a different
pinout or fMAX requirement to the standard constraints.
The procedure differs for APEX II or Stratix devices.
1
To perform the actions manually, perform the following steps:
3
1.
Appendix A
APEX II Devices
For information on Cyclone device constraint settings, refer to
docs/readme.txt.
Create a project called <variation name>_top, where <variation_name>
is your DDR SDRAM Controller instance name and create a custom
megafunction, see “DDR SDRAM Controller Walkthrough” on
page 21.
1
The PLL files are configured for 133-MHz operation. To change
the frequency of operation, use the MegaWizard Plug-In to edit
the \lib\example_pll.vhd file.
Choose Device (Assignments menu).
3.
In the Family drop-down box, choose APEX II. Under Target
Device, choose Specific device selected in the ’Available devices’
list.
1
Altera Corporation
To specify the devices in the selected family from which you
want to select a specific device, under Show in ’Available
devices’ list, choose the desired settings in the Package, Pin
count, Speed grade, and Voltage lists.
4.
Choose the target device in the Available devices list.
5.
Click Assign Pins.
67
Appendix A
2.
4
Appendix A—The Quartus II Constraint Settings DDR SDRAM Controller MegaCore Function User Guide
6.
f
In the Available pins & existing assignments list, choose the pin
number for the pin to which you want to assign, change, or delete a
node name assignment. Use the following recommendations:
For more information on voltage reference pins, refer to AN 117: Using
Selectable IO Standards in APEX 20KE/20KC & MAX 7000B Devices.
a.
Use either the top or the bottom banks for the dq and the dqs
pins, because these banks have the necessary programmable
delay feature to delay the dqs to clock the read data registers.
b.
Only place 16 dq and 2 dqs bits in each column so as not to
exceed the amount of current which each bank can sink.
c.
Set all the pins that interface with DDR SDRAM memory
devices to SSTL-2 CLASS II I/O standard.
d.
Set clocks to 2.5 V, to avoid conflict with the SSTL-2 assignment.
e.
Place the dqs pin with four dq pins immediately either side of
it, as each dqs pin has 8 associated dq bits.
f.
Do not break groups of 8 dq bits across column boundaries.
g.
Define all necessary voltage reference pins. Each VREF pin can
support 16 input or bidirectional pins, 8 on either side. Figure 26
shows an example of one column (or half a bank).
Figure 26. One Column
Half bank = One column
VREF dq
dq dq
dq dqs dq
7.
68
dq dq
dq
VREF
dq
dq dq
dq dqs dq
dq dq
dq VREF
Create a LogicLock region for the top-level of the DDR SDRAM
Controller, <variation_name>, which is 16 lab structures wide and 7
rows high.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix A—The Quartus II Constraint
8.
Create LogicLock regions for the data path modules. The APEX II
device supports two data path modules in each column. For the best
results, create a LogicLock region for each pair of modules, which is
1 MegaLAB™ structure wide and 1 row high. For example if you
have a 16-bit controller, create two LogicLock regions and place the
first (auk_ddr_sdram_component_ddr_gen_0_datapath) and
second (auk_ddr_sdram_component_ddr_gen_1_datapath) data
path modules in one of the regions. Place the third and fourth
datapath modules in the other region that you created. See the
example Quartus II project for examples of these regions.
9.
Inform the Quartus II software that the dqs signals are acting as
clocks.
b.
Click New. Enter a suitable name, e.g. dqs_is_a_clock, select
Based On, select example_pll in the drop-down box, click
Derived Clock Requirements, and enter 1.75 ns in the Offset
from base absolute clock fMAX box. Click OK. Click OK.
c.
Turn off the Cut Paths Between Unrelated Clock Domains
check box. Click OK.
d.
Choose Assignment Organizer (Assignments menu), click the
By Node tab, select Edit specific entity & node settings for,
type dqs in the Name box and press TAB. Expand Timing in the
Assignment Categories window. Choose Click here to add a
new assignment. Add a Clock Settings = dqs_is_a_clock
assignment to the dqs pins. Click OK.
10. Choose Assignment Organizer (Assignments menu), choose the By
Node tab, select Edit specific entity & node for, type the relevant
signal name in the Name box and press TAB. Expand Options for
Individual Nodes Only in the Assignment Categories window.
Apply the following assignments:
Altera Corporation
a.
Decrease Input Delay to Internal Cells = On, to each dq bit.
b.
FastRow Interconnect = On, to each dqs bit.
69
3
4
Appendix A
Choose Timing Settings (Assignments menu). Choose Clock in
the category box. Select Settings for individual clock signals
and click New. Enter a suitable name, e.g. example_pll, enter
a required fMAX, and click OK.
Board Design
Appendix A
Guidelines
a.
Appendix A—The Quartus II Constraint Settings DDR SDRAM Controller MegaCore Function User Guide
c.
Apply the following setting to each dqs bit:
For 100-MHz operation, set FastRow Interconnect Delay =
2130 ps.
For 133-MHz operation, set FastRow Interconnect Delay =
1875 ps.
d.
Fast Output Register = On, to all the control and address
signals.
11. Choose Start (Processing menu) and click Start Analysis &
Elaboration.
12. Choose Assignment Organizer (Assignments menu), choose the By
Node tab, click the 3 dots icon next to the Name box. In the Node
Finder window, enter *dq_oe* in the Named box. Choose
Registers: pre-synthesis in the Filter drop-down box. Click Start.
Move the nodes from the Nodes Found box to the Selected Nodes
box. In the Node Finder window, enter *dqs_oe* in the Named
box. Choose Registers: pre-synthesis in the Filter drop-down box.
Click Start. Move the nodes from the Nodes Found box to the
Selected Nodes box. Click OK. Expand Options for Individual
Nodes & Entities in the Assignment Categories window. Choose
Click here to add a new assignment. Choose Remove Duplicate
Registers in the Assignment Name drop-down box and choose Off
in the Setting drop-down box. Expand Options for Individual
Nodes Only in the Assignment Categories window. Choose Click
here to add a new assignment. Choose Global Signals in the
Assignment Name drop-down box and choose Off in the Setting
drop-down box. Click OK.
Stratix Devices
70
To perform the actions manually, perform the following steps:
1.
Create a project called <variation name>_top, where <variation_name>
is your DDR SDRAM Controller instance name and create a custom
megafunction, see “DDR SDRAM Controller Walkthrough” on
page 21.
2.
Choose Device (Assignments menu).
3.
In the Family drop-down box, choose Stratix. Under Target Device,
select Specific device selected in the ’Available devices’ list.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
1
To specify the devices in the selected family from which you
want to select a specific device, under Show in ’Available
devices’ list, choose the desired settings in the Package, Pin
count, Speed grade, and Voltage lists.
4.
Choose your target device in the Available devices list.
5.
Click Assign Pins.
6.
In the Available Pins & Existing Assignments list, choose the pin
number for the pin to which you want to assign, change, or delete a
node name assignment. Use the following recommendations:
7.
a.
Set all the pins that interface with DDR SDRAM memory
devices to SSTL-2 Class II I/O standard.
b.
Set clocks to 2.5 V, to avoid conflict with the SSTL-2 assignment.
c.
Set clk-to-sdram to differential SSTL-2 I/O standard.
3
Inform the Quartus II software that the dqs signals are acting as
clocks.
Choose Timing Settings (Assignments menu). Choose Clock in
the category box. Select Settings for individual clock signals
and click New. Enter a suitable name, e.g. example_pll, enter
a required fMAX, and click OK.
b.
Click New. Enter a suitable name, e.g. dqs_is_a_clock, select
Based On, select example_pll in the drop-down box, click
Derived Clock Requirements, and enter 1.75 ns in the Offset
from base absolute clock fMAX box. Click OK. Click OK.
c.
Turn off the Cut Paths Between Unrelated Clock Domains
check box. Click OK.
d.
Choose Assignment Organizer (Assignments menu), click the
By Node tab, select Edit specific entity & node settings for,
type dqs in the Name box and press TAB. Expand Timing in the
Assignment Categories window. Choose Click here to add a
new assignment. Add a Clock Settings = dqs_is_a_clock
assignment to the dqs pins. Click OK.
71
4
Appendix A
a.
Board Design
Appendix A
Guidelines
Altera Corporation
GettingAppendix A—The Quartus II Constraint
Appendix A—The Quartus II Constraint Settings DDR SDRAM Controller MegaCore Function User Guide
8.
9.
Choose Assignment Organizer (Assignments menu), choose the By
Node tab, select Edit specific entity & node for, type dqs in the
Name box and press TAB. Expand Options for Individual Nodes
Only in the Assignment Categories window. Choose Click here to
add a new assignment.
a.
Choose Click here to add a new assignment. Choose DQS
Frequency in the Assignment Name drop-down box, type 7.5
ns in the Setting box. Click Add.
b.
Choose Click here to add a new assignment. Choose DQS
Phase Shift in the Assignment Name drop-down box, type 90
in the Setting box. Click Add.
c.
Choose Click here to add a new assignment. Choose DQS
Input Reference Clock in the Assignment Name drop-down
box, type dqs_ref_clock in the Setting box. Click Add. Click
OK.
Choose Assignment Organizer (Tools menu), choose the By Node
tab, select Edit specific entity & node for. For all control signals,
expand Options for Individual Nodes Only in the Assignment
Categories window. Choose Fast Output Register in the Assignment
menu drop-down box, choose On in the Setting box. Click OK.
10. Choose Start (Processing menu) and click Start Analysis &
Elaboration.
11. Choose Assignment Organizer (Assignments menu), choose the By
Node tab, click the 3 dots icon next to the Name box. In the Node
Finder window, enter *inclock_enable* in the Named box.
Choose Registers: pre-synthesis in the Filter drop-down box. Click
Start. Move the nodes from the Nodes Found box to the Selected
Nodes box. Click OK. Expand Timing in the Assignment Categories
window. Choose Click here to add a new assignment. Choose Cut
Timing Path in the Assignment Name drop-down box and choose
On in the Setting drop-down box. Click OK.
72
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix A—The Quartus II Constraint
12. Choose Assignment Organizer (Assignments menu), choose the By
Node tab, click the 3 dots icon next to the Name box. In the Node
Finder window, enter *dq_oe* in the Named box. Choose
Registers: pre-synthesis in the Filter drop-down box. Click Start.
Move the nodes from the Nodes Found box to the Selected Nodes
box. In the Node Finder window, enter *dqs_oe* in the Named
box. Choose Registers: pre-synthesis in the Filter drop-down box.
Click Start. Move the nodes from the Nodes Found box to the
Selected Nodes box. Click OK. Expand Options for Individual
Nodes & Entities in the Assignment Categories window. Choose
Click here to add a new assignment. Choose Remove Duplicate
Registers in the Assignment Name drop-down box and choose Off
in the Setting drop-down box. Click OK.
3
Board Design
Appendix A
Guidelines
4
Appendix A
Altera Corporation
73
Notes:
Appendix B—DDR SDRAM
Timing Analysis
Successful hardware implementation of a DDR SDRAM Controller is
critically dependent upon board layout, FPGA placement, and set up of
the clocks in the system. Furthermore, while it is relatively
straightforward to get a single prototype working in hardware, you must
fully understand the potential variations in timing that must be accounted
for when designing for volume production. All of these issues become
increasingly difficult at higher clock frequencies. This section describes
the timing analysis that you must do, to verify your particular
implementation of the DDR SDRAM Controller. Little of this analysis is
individual to the Altera DDR SDRAM Controller, you can apply the
following guidelines generally to the implementation of DDR SDRAM
controllers using Altera FPGAs.
FPGA-SDRAM
Interface
The FPGA-SDRAM interface timing analysis covers the following four
areas:
■
■
■
■
Write data timing
Address and command timing
Read data capture using dqs
Resynchronization of captured read data from the dqs to the system
clock domain
1
3
Board Design
Guidelines
Introduction
Before you read this section, ensure that you have read “DDR
SDRAM Controller Walkthrough” on page 21 and you are
familiar with the DDR SDRAM Controller’s parameters and
options.
Write Data Timing
This section describes the following two DDR SDRAM input pin
requirements that must be met:
5
Data relative to dqs
dqs relative to clock
The dqs, dq and dm trace lengths should be tightly matched, so these
requirements are met at the FPGA output pins and thus the DDR SDRAM
input pins.
Altera Corporation
75
Appendix B
■
■
Appendix B—DDR SDRAM Timing Analysis
1
DDR SDRAM Controller MegaCore Function User Guide
The timing requirements of dm at the input to the DDR SDRAM
are identical to those for dq data. You must treat the dm bit
exactly the same as the dq bits within the same byte group.
Setup and hold times for the write dq and dm data are relative to the edges
of DQS write (tDS and tDH). These are symmetrical and typically 0.5 ns for
a 133 MHz device. The dqs signal is normally generated on the positive
edge of clk (because of the tDQSS requirement described shortly). Thus dq
and dm data out is clocked using clk_shifted, which leads clk by 90°
(–90°). The edges of dqs are centred on the dq/dm data when they arrive
at the DDR SDRAM. Table 13 on page 46 describes clk and
clk_shifted.
The DDR SDRAM has a write requirement tDQSS, i.e., the positive edge of
dqs on writes must be within 25% (90°) of the positive edge of the DDR
SDRAM clock input. At low frequencies you might meet this requirement
without taking any special precautions. However, at 167 MHz the error is
only ±1.5 ns. If the same clock phase on the FPGA is used to clock dqs and
drive out to the FPGA clock pin via a buffer, the skew between them at the
FPGA pins may be close to or greater than the tDQSS margin.
A dedicated PLL output, with a small phase delay for the external clock,
is used to align the edges of the clock and dqs at the FPGA pins.
Figure 27 shows the phase adjustment of the external clock.
The clock exits via a differential IO buffer (tPD clk_ext to pin), but the
tCO for DQS write (tPD clk to pin) is made up of the IO register's tCQ and
the IO DDR multiplex delay plus an output buffer delay so is typically
longer. Therefore, the external clock (clk_ext) phase at the PLL (e0)
must be about 1 ns later than the clk phase at the PLL (c0), for clk and
dqs to align at the pins. The effective path tPD (clk to pin) is now equal
to tCQ DQS write
76
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix B—DDR SDRAM Timing
Figure 27. Phase Adjustment of External Clock and Address and Command Timing
clk
clk_ext
FPGA CLK Pin
tDQSS
SDRAM Write Requirement
DQS Write (at FPGA Pin)
Phase delay setting of PLL
output e0 relative to c0
tPD (clk_ext to Pin)
tPD (clk to Pin)
tCQ (DQS Write)
tSU
tH
SDRAM Address/Command
Input Timing
tCO
Address/Command Pins
(positive edge)
3
Board Design
Guidelines
Address/Command Pins
(negative edge)
tCO
Address & Command Timing
The DDR SDRAM address and command inputs typically require
symmetrical 1 ns setup and hold times with respect to the DDR SDRAM
clock. The address and command FPGA pins nominally change at the
same time as DQS write—they are both generated on clk. The positive
edge of the DDR SDRAM clock is aligned with DQS write to satisfy tDQSS,
therefore address and command outputs cannot reliably be generated on
the positive edge of clk; the negative edge should normally be used. You
can set the system clock edge (see Figure 27) upon which these outputs are
generated in the MegaWizard Plug-In; it is negative by default.
1
77
5
Appendix B
Altera Corporation
You can use the positive edge of the clock for APEX II devices, if
you can guarantee the hold time for the DDR SDRAM. The hold
time can be guaranteed, if you use the slower sidebanks for DDR
SDRAM address and command signals.
Appendix B—DDR SDRAM Timing Analysis
DDR SDRAM Controller MegaCore Function User Guide
Read Data Capture using DQS
During read operations, DDR SDRAM devices output DQ and DQS such
that they have simultaneous edges. To use dqs as a strobe (clock) to
capture dq, the dqs signal must be delayed by 90° with respect to dq
within the FPGA.
APEX II, Stratix, Stratix GX and Cyclone devices include special delay
element chains on the dqs input path, which generate a 90° phase shift of
dqs relative to the dq data (as seen at the input of the first dq capture
register). For APEX II and Cyclone devices, set these delays to a nominal
time delay that represents a 90° phase shift at the chosen DDR SDRAM
clock frequency. The delay is subject to process, voltage, and temperature
(PVT) variations.
Stratix and Stratix GX devices incorporate a DQS phase-shift reference
circuit that continuously and automatically adjusts the phase shift to keep
it at 90°, independent of PVT variations. The circuit requires a reference
clock equal in frequency to the DDR SDRAM clock; the duty cycle, phase,
and source of this clock are unimportant. The phase-shift error for Stratix
devices is not subject to PVT variations.
If you ensure that the dq, dm, and dqs trace lengths are tightly matched
within each byte group, typically within 0.1 inches, the edges of dq data
and dqs nominally arrive at the FPGA aligned. No further steps need be
taken for the timing of dq sampling.
On APEX II and Cyclone devices, the maximum phase delay is 2.1 or
2.8 ns, respectively. Therefore, the phase delay only provides the 90°
phase shift for frequencies above 120 MHz or 90 MHz, respectively. For
lower frequencies, this delay is nevertheless sufficient to ensure reliable
capture of dq with the delayed dqs.
Resynchronization of Captured Read Data from the DQS to the
System Clock Domain
Read data is captured into the DDR registers using dqs signals as a clock.
Therefore, data must be transferred from the dqs clock domain to the
system clock (clk) domain (resynchronization), to present data_out
synchronously at the local-side interface.
Figure 28 shows the timing analysis, which is required to reliably transfer
data from register A to register B.
78
Altera Corporation
GettingAppendix B—DDR SDRAM Timing
DDR SDRAM Controller MegaCore Function User Guide
Figure 28. Timing Analysis, Note (1),
dqs_ref_clk
FPGA
DQS Phase
Shift
Reference
Circuit
DDR
SDRAM
Note 2
tPD (Clock Trace)
tPD (clk_ext to pin)
e1
clock_
source
(2)
clk_ext
e0
PLL
FPGA CLK
clk_shifted (Note 3)
c1
CLK
tPD (clk to pin)
clk (Note 4)
c0
(3)
clk_to _sdram
tDQSS
(Write)
DDR SDRAM
Controller
DQS Write (Note 5)
(1)
D
3
Q
D
Q
D
Q
Board Design
Guidelines
tDQSCK
(Read)
tCQ (DQS Write)
Address/
Command Pins
Note 6
tPD (Capture)
Note 7
data_out
(9)
Q
D
DQ Read
(8)
Q
DQ
D
A
B
90 o
tPD (Routing)
tSU (Resynchronization)
tH (Resynchronization)
tCQ (Capture)
(7)
(6)
DQS Read
(5)
(4)
tPD (DQS Trace)
Note 8
Notes:
(1)
(2)
(4)
(5)
(6)
(7)
(8)
Altera Corporation
79
5
Appendix B
(3)
The text refers to the numbers in parenthesis.
The dqs_ref_clk input for Stratix devices can be either fed-back from the clock output driving the DDR SDRAM
or a separate clock output from the PLL. The phase of this reference clock relative to the other clocks in the system
is unimportant.
The clk_shifted signal is shown for completenes, but it is not needed in the timing analysis for round-trip delay
or address/command timing.
clk is the system clock, and there is no skew to be taken into account across the FPGA.
The dqs signal is bidirectional. DQS Write and DQS Read are shown as two separate pins for this timing analysis.
This signal path depends on the edge of address/command outputs selected on page 3 of the MegaWizard Plug-In.
Register B’s clock input is inverted, if you select an odd phase number in the MegaWizard Plug-In.
The DQS phase-shift reference circuit controls the 90° phase shift dynamically. The control path is not shown and
its operation is user transparent.
Appendix B—DDR SDRAM Timing Analysis
DDR SDRAM Controller MegaCore Function User Guide
At the output of register A, the data is already at single data rate, but is
still in the dqs clock domain.
1
Register A in Figure 28 represents the DDR capture logic. The Q
output of register A represents the point at which the read data
has been converted from DDR to SDR. dqH (dq data during dqs
high) is sampled on the positive edge of the 90° phase-shifted
dqs pulse, but re-sampled on the negative edge of the 90° phaseshifted dqs pulse, to align it with dqL (dq data during dqs low).
Once sampled by the negative edge of the 90° phase-shifted dqs
pulse, dqL and dqH are available for resynchronization.
To sample the Q output of register A into register B, you need the time
relationship between the clock input and the D input of register B,which
depends on the phase relationship between dqs and clk and involves the
following steps:
■
■
■
Calculate the round-trip delay (RTD) for your system.
Select a resynchronization phase of the system clock that reliably
samples the Q output of register A, based on the calculated safe
resynchronization window (see Figure 30).
Select the resynchronization phase on page 3 of the MegaWizard
Plug-In.
Round-Trip Delay
The register B clock input is clk. To determine the timing of data at the D
input of register B relative to clk, consider the following timing-path
dependencies, which are in reverse order:
■
■
■
■
Data arrives at the D input of register B
Data arrives at the Q output of register A
DQS strobe from the DDR SDRAM arrives at the clock input of
register A
The DDR SDRAM clock input arrives (a delayed version of clk).
There are therefore three main parts to this path:
■
■
■
80
Clock Delays—between the FPGA global clock net and the DDR
SDRAM clock input.
DQS Strobe Delays—between the DDR SDRAM clock input and dqs’s
arrival at the FPGA capture registers
Read Data Delays—between the output of register A and the input of
register B.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix B—DDR SDRAM Timing
Figure 28 shows the individual delays between points (1) and (9). The sum
of all these delays is the RTD—from the FPGA clock to the DDR SDRAM
and back to the FPGA (input to register B). Figure 29 shows the timing
relationship of the signals for the delays between points (1) to (9) for a CAS
latency of 2.5.
3
Board Design
Guidelines
5
Appendix B
Altera Corporation
81
Appendix B—DDR SDRAM Timing Analysis
DDR SDRAM Controller MegaCore Function User Guide
Figure 29. RTD Calcuation Note (1)
Round-Trip Delay
Resynchronization
Phase
0
1
2
clk (1)
tPD (clk to pin)
Clock
FPGA CLK Pin (2)
tPD (Clock Trace)
SDRAM CLK Pin (3)
tDQSCK
SDRAM DQS Pin (4)
(during Read
CL = 2.5)
tPD (DQS Trace)
FPGA DQS Pin (5)
DQS
Strobe
90 o
90o DQS
phase shift (6)
tPD (Capture)
Clock input
at Register A (7)
tCQ (Capture)
Q Output
of Register A (8)
tPD (Routing)
Captured
DQ Data
D Input
of Register B (9)
Notes:
(1)
(2)
(3)
(4)
(5)
82
The numbers in parenthesis refer to the numbers on Figure 28.
The calculation of RTD requires the timing from the system clock (clk) to the FPGA clock pin. However, the clock
pin is not driven by clk but clk_ext, which has different timing at the PLL.
The DQS Strobe edge can be anywhere within +/- tDQSCK of the DDR SDRAM clock pin edge. For calculating the
maximum RTD the diagram assumes the strobe occurs tDQSCK after the clock. For calculating the mnimum it has
to be assumed it ocurs tDQSCK before.
The delays in the DQS path from FPGA pin to capture register are matched to those for the DQ path with the
exception of the DQS delay chain.
Although data is initially sampled at a capture register on the positive edge of DQS, it is only on the negative edge
that both DQH and DQL are available at the Q outputs of the DDR capture logic. At this point they are then single
data rate.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix B—DDR SDRAM Timing
To determine the point at which the data can be reliably resynchronized,
calculate the minimum and maximum RTD.
1
Remember to take into account PVT variations.
Delay (1) to (2) does not have a corresponding signal path. To meet the
tDQSS DDR SDRAM write requirement (see “Write Data Timing” on
page 75), the clock edge at (2) is nominally aligned with the edge of DQS
write at the FPGA pin,
tPD (clk to pin) = tCQ (DQS Write)
So you can use tCQ (DQS Write) for the delay (1) to (2).
Delay (2) to (3) is the trace delay for the clock. If there are multiple DIMMs
or devices in the system, the one furthest away from the FPGA should be
used for the maximum calculation; the closest for the minimum.
Delay (4) to (5) is the trace delay for dqs, which is typically tightly
matched to the trace delay for the dq signals in the same byte group. To
calculate the maximum RTD, use the byte group with the longest trace
lengths; for the minimum use the shortest. Similarly, if there are multiple
DIMMs or devices in the system, the one furthest away from the FPGA
should be used for the maximum calculation; the closest for the minimum.
Trace lengths between different byte groups do not have to be tightly
matched, but a significant difference between the longest and shortest
increases the variation in the RTD. This increase reduces the window size
within which the data can be reliably resynchronized.
3
Board Design
Guidelines
Delay (3) to (4) is the relationship between the clock and the timing of the
DQS strobe during reads. This is tDQSCK in DDR-SDRAM specifications,
nominally 0, but typically varies by ± 0.75 ns depending on the DDR
SDRAM device-speed grade. The DQS output strobe is only guaranteed
to be within ±tDQSCK of the clock input. So use tDQSCK (max), typically
+0.75 ns, for calculating the maximum RTD; tDQSCK (min), typically –0.75
ns, for calculating the minimum delay.
5
Appendix B
Altera Corporation
83
Appendix B—DDR SDRAM Timing Analysis
DDR SDRAM Controller MegaCore Function User Guide
PLL jitter and clock duty cycle also affect the RTD. Add each of these
delays to the maximum value and subtract from the minimum. PLL jitter
and clock duty cycle are not shown in Figure 28, but are included in Table
16, which shows example RTD calcuations.
Table 16. Example RTD Calculations
Delay
Numbers in
Figures 28
and 29
Example Maximum
Values (ns)
Example Minimum
Values (ns)
Notes
tPD (clk to pin)
(1) to (2)
3.00
2.00
Equal to tCQ (DQS Write)
tPD (clock trace)
(2) to (3)
0.50
0.33
2 to 3 inches @166 ps/inch
tDQSCK
(3) to (4)
+ 0.75
– 0.75
tPD (dqs trace)
(4) to (5)
0.50
0.33
2 to 3 inches @166ps/ inch
90° phase-shift
(5) to (6)
2.00
1.75
Ensure that you account
for the phase error in
Cyclone and APEX II
devices.
tPD (capture)
(6) to (7)
1.50
1.00
tCQ (capture)
(7) to (8)
0.05
0
tPD (routing)
(8) to (9)
1.50
1.00
PLL jitter
–
+ 0.10
– 0.10
Clock duty cycle
–
+ 0.40
– 0.40
Round-Trip Total
(1) to (9)
10.30
5.16
See SDRAM
specifications.
45/55% duty at 133 MHz
Resynchronization Phase Selection
When you have calculated the maximum and minimum RTD, convert
them to the equivalent number of system clock cycles at your operating
frequency, to find the point at which the data becomes valid relative to
clk. The example maximum delay in Table 16 represents 1.4 cycles at 133
MHz; the minimum represents 0.7 cycles.
The resynchronization phase options are four consecutive clock edges
numbered 0 to 3 starting at the first positive edge following the theoretical
time at which the Q outputs of register A change. The resynchronization
phases are therefore different for CAS latencies of 2.0 and 3.0 compared to
2.5. Figure 30 shows the effect of the RTD on the the time that the data is
available for resynchronization against the theoretical time, which has
zero implementation-specific delays and is just 90°. Figure 30 shows the
example maximum delay from Table 16 and the minimum delay.
84
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
GettingAppendix B—DDR SDRAM Timing
The overlap of the minimum and maximum data valid windows defines
the data valid window, which comprises the safe resynchronization
window and tSU and tH of register B. You must choose your
resynchronization phase to be within the safe resynchronization window.
In the Figure 30 examples, choose phase 2 for CL = 2.0 or 3.0; and phase 1
for CL = 2.5.
3
Board Design
Guidelines
5
Appendix B
Altera Corporation
85
Appendix B—DDR SDRAM Timing Analysis
DDR SDRAM Controller MegaCore Function User Guide
Figure 30. Effect of Read RTD on the Choice of Resynchronization Phase for RTL Example
clk (PLL c0)
dq (see Note 1)
H
L
o
dqs (90 shifted)
(see Note 1)
Theoretical Q Output
of Register A at (8)
(see Note 1 & 2)
H/L
Theoretical RTD
Minimum RTD
CL = 2.0
or 3.0
H/L
Actual Data Valid at
D Input of Register B
at (9) (see Note 2)
Maximum RTD
H/L
tSU (Register B)
tH (Register B)
Safe Resynchronization Window
Resynchronization
Phase
dq (see Note 1)
0
H
1
2
3
L
dqs (90o shifted)
(see Note 1)
Theoretical Q Output
of Register A at (8)
(see Note 1 & 2)
H/L
Theoretical RTD
Minimum RTD
H/L
CL = 2.5
Actual Data Valid at
D Input of Register B
at (9) (see Note 2)
Maximum RTD
H/L
tSU (Register B)
tH (Register B)
Safe Resynchronization Window
Resynchronization
Phase
0
1
2
3
Note:
(1)
(2)
86
These are the timings, if all of the implementation-specific system delays are zero.
The numbers in parenthesis refer to the numbers on Figure 28.
Altera Corporation
Appendix C—Board Design
Guidelines
6
Appendix C
This appendix provides general guidelines for board design when using
the DDR SDRAM Controller and information about decoupling
capacitance.
General
Guidelines
The following general guidelines apply.
Keep the DIMM and the Altera device close together. The routing
length between the Altera device and the DIMM should be within
4.5 inches.
2.
Altera device target impedance is 50 Ω ± 10%. Locations of the series
impedance-balancing resistors RS are important. For address and
control signals, place these series-terminating resistors as close as
possible to the Altera device. For data, data strobe, and data mask
signals, place the series-terminating resistors as close as possible to
the DIMM socket, to achieve the best signal integrity results. Pull-up
resistors RT to VTT (1.25 V) are required for data, data strobe, data
mask, address, and control signals and should be located after the
end of the DIMM structure. Routing length to the pull-ups is less
critical but most designs require 0.5 to 1 inch to route. Figure 31
shows this prescribed termination scheme.
1
Altera Corporation
These instructions are guidelines only. The best way to
predict that the termination arrangement meet your
requirements is to simulate your design, including the PCB
and device packages. For more information, see the Micron
Technical Note on Termination, TN-00-13.
87
3
Board Design
Guidelines
1.
Appendix C—Board Design Guidelines
DDR SDRAM Controller MegaCore Function User Guide
Figure 31. Termination Scheme
VTT
RT = 56 Ω
Address
and Control
Signals
RS = 10 Ω
50 Ω
VTT
DIMM Pin
RT = 56 Ω
Data Strobe,
Data Mask,
and Data Signals
88
50 Ω
RS = 10 Ω
3.
Data byte-groups must be matched as closely as possible when
routing on the PCB. Data group dq0 to dq7, dm0, dqs0, for example,
should have timing skews matched as closely as possible, i.e., 17 ps
(0.1 inch). Data byte-group to data byte-group matching, of 17 ps
(0.1 inch) is also recommended. To achieve this take the longest trace
and match the rest of the signals (dq, dqm, dqs) with the longest
trace. Also, vias have electrical length and should be accounted for in
all trace balancing configurations. Proper routing topology is best
achieved when all point-to-point connections match not only in
physical length but also in electrical length.
4.
Because unbuffered address and control signals are generally much
noisier (they create crosstalk), route them on different layers or with
greater spacing than data, data mask and data strobes, when
escaping the Altera device BGA and on the memory channel. Do not
route differential clocks and clock enables close to address signals.
5.
Route differential clock pairs in parallel with lengths matched within
10 ps (0.0588 inch). The spacing ratio between the clock and
clock_n should be 1:1. Keep the ratio between the differential pairs
to a minimum of 3:1.
6.
Avoid routing signals across split planes. Controlling returns at high
frequencies is very desirable. Also, avoid routing memory signals
any closer than 0.025 inch from AGP, GTL, PCI or system clocks. In
addition, avoid routing memory signals in close proximity to system
reset signals.
Altera Corporation
DDR SDRAM Controller MegaCore Function User Guide
7.
When using resistor networks, Altera recommends that the address
and control signals be confined to separate physical packages from
data signals.The address/control lines and data (dq, dqm, dqs)
should not share R-pack series resistors, to eliminate crosstalk within
R-pack. Keep series and pull-up resistor network tolerances within
1 to 2%.
In a worst-case scenario, as many as 81 drivers (64 data, 8 ECC, 9 strobe)
may be switching from one state to the other on a memory module. The
controller may have an additional 28 signals transitioning at the same time
in a pipelined access. Traditional methods for providing decoupling
involve placing capacitors in locations that are convenient, based on the
routing of the board and applying some predetermined ratio of capacitors
to driver pins. Unfortunately, the higher switching speeds of DDR may
render such typical ratios less useful. Perform careful planning and
analysis to ensure that sufficient decoupling is provided.
89
3
Board Design
Guidelines
The critical limiting factor in designing a decoupling system is usually not
the amount of capacitance, but the amount of inductance in the capacitor
leads and the vias attaching the caps to the power and ground planes.
Using 0.1-µF caps in an 0603 package should provide sufficient
capacitance. VTT voltage decoupling should be made on the motherboard
very close to the parallel pull-ups. The decoupling capacitors should be
connected between VTT and ground. The APEX II memory interface board
has a 0.1-µF capacitor for every other VTT pin. The APEX II memory
interface board also has 0.1-µF and 0.01-µF capacitors for every VDD and
VDDQ pin.
Altera Corporation
6
Appendix C
Decoupling
Capacitance
GettingAppendix C—Board Design Guidelines
Notes: