T3 Framer MegaCore Function
T3FRM
August 2001
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
A-UG-IPT3FRM-1.02
T3 Framer MegaCore Function (T3FRM) User Guide
Copyright © 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device
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About this User Guide
User Guide
This user guide provides comprehensive information about the Altera® T3
Framer MegaCore® Function (T3FRM).
Table 1 shows the user guide revision history.
B
Refer to the T3FRM readme file for late-breaking information that is not
available in this user guide
Table 1. Revision History
Date
Description
December 2000 First release
How to Find
Information
May 2001
First revision. Added “Core Verification Summary” section.
August 2001
Second revision. Added Midbus signals identifying the DS3
overhead bits required for framing, and supporting timing
diagrams. Revised the “Getting Started” chapter.
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About this User Guide
T3 Framer MegaCore Function (T3FRM) User Guide
How to Contact
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T3 Framer MegaCore Function (T3FRM) User Guide
Typographic
Conventions
About this User Guide
The T3 Framer MegaCore Function (T3FRM) User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
Bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Quartus II and MAX+PLUS II
Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX
8000 Device with the BitBlaster™ Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
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H
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Altera Corporation
Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
The angled arrow indicates you should press the Enter key.
The feet direct you to more information on a particular topic.
v
About this User Guide
Abbreviations
& Acronyms
vi
T3 Framer MegaCore Function (T3FRM) User Guide
AHDL
AIC
AIRbus
AIS
AMI
B3ZS
CRC
DS2
DS3
ESB
EDA
EXZ
FEAC
FEBE
FIFO
HDLC
LAPD
LCV
LE
LIU
LOS
M23
Mbps
NRZ
OOF
PC
PMON
PRBS
RDI
RTL
RX
SONET
SPE
STS-1
TX
VHDL
VHSIC
Altera Hardware Description Language
Application Identification Channel
Access to Internal Registers Interface
Alarm Indication Signal
Alternate Mark Inversion
Bipolar Three Zero Substitution
Cyclic Redundancy Check
Digital Signal Level 2
Digital Signal Level 3
Embedded System Block
Electronic Design Automation
Excessive Zeros
Far End Alarm and Control
Far End Block Errors
First In First Out
High-Level Data Link Control
Link Access Protocol D
Line Code Violation
Logic Element
Line Interface Unit
Loss Of Signal
Multiplex 23
Megabits per second
Non-Return-to-Zero
Out Of Frame
Personal Computer
Performance Monitor
Pseudo Random Bit Sequence
Remote Defect Indication
Register Transfer Level
Receive
Synchronous Optical Network
Synchronous Payload Envelope
Synchronous Transport Signal level 1
Transmit
VHSIC Hardware Description Language
Very High Speed Integrated Circuit
Altera Corporation
Contents
User Guide
About this User Guide
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Abbreviations & Acronyms .......................................................................................................... vi
Specifications
General Description .......................................................................................................................11
Functional Description ..................................................................................................................12
RXFRMR ..........................................................................................................................................13
B3ZS Decoding for Dual Rail & Single Rail Signals ..........................................................13
PMON ......................................................................................................................................13
Frame Searching and OOF Detection .................................................................................14
Parity Check ............................................................................................................................14
AIS and Idle Signal ................................................................................................................14
C-bit Parity Functions ...........................................................................................................14
RDI Detection .........................................................................................................................15
M23 Application .....................................................................................................................15
Receive FEAC .........................................................................................................................15
Receive HDLC ........................................................................................................................16
External LOS Insertion ..........................................................................................................16
TXFRMR ..........................................................................................................................................17
B3ZS Encoding for Dual Rail & Single Rail Signals ..........................................................17
Frame Bit Insertion ................................................................................................................17
RDI ...........................................................................................................................................18
AIS and Idle Signal ................................................................................................................18
C-bit Parity Functions ...........................................................................................................18
M23 Application .....................................................................................................................18
Diagnostic Insertion ...............................................................................................................18
Software Insertion of C-bits ..................................................................................................18
Transmit FEAC Generator ....................................................................................................18
Transmit HDLC ......................................................................................................................19
Generation & Detection of Pseudo- Random Bit Streams (PRBS) ..........................................19
Receive .....................................................................................................................................19
Transmit ..................................................................................................................................19
Maintenance ....................................................................................................................................20
System Reset ...........................................................................................................................20
Interfaces & Protocols ....................................................................................................................20
T3 Line Interface .....................................................................................................................20
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Contents
T3 Framer MegaCore Function (T3FRM) User Guide
Midbus Interface ....................................................................................................................20
Receive Direction ...........................................................................................................21
Transmit Direction .........................................................................................................22
AIRbus Interface .....................................................................................................................22
T3 Mapper Interface ..............................................................................................................23
Receive .............................................................................................................................23
Transmit ..........................................................................................................................23
T3 Overhead Interface ...........................................................................................................24
Performance ....................................................................................................................................25
I/O Signals ......................................................................................................................................25
Software Interface ..........................................................................................................................27
Memory Map ..........................................................................................................................27
Registers ..................................................................................................................................28
Master Register Description .........................................................................................29
MSTR_INT - Master Interrupt Status - 'h0 ......................................................... 29
MSTR_INT_EN - Master Interrupt Enable - 'h2 ................................................ 29
RESERVED - Reserved - 'h2 ................................................................................. 29
PRBS_CTRL - PRBS control - 'h6 ......................................................................... 29
PRBS_INT - PRBS Interrupt Status - 'h8 ............................................................. 29
PRBS_INT_EN - PRBS Interrupt Enable - 'hA ................................................... 30
PRBS_THRES - PRBS Threshold - 'hC ................................................................ 30
PRBS_ERR - PRBS Bit Error Counter - 'hE ......................................................... 30
TXFRMR Register Description .....................................................................................30
TXFRMR_CTRL - Transmit Framer control - 'h10 ............................................ 30
TXFRMR_DIAG - Transmit Framer Diagnostic - 'h12...................................... 30
TFEAC Register Descriptions .......................................................................................31
TFEAC_CTRL - Transmit FEAC control - 'h14 .................................................. 31
TFEAC_CODE - Transmit FEAC Code - 'h16 .................................................... 31
CINST1 - C-Bit Insertion 1 - 'h18.......................................................................... 31
CINST2 - C-Bit Insertion 2 - 'h1A......................................................................... 32
THDLC Register Descriptions ......................................................................................32
THDLC_CTRL - Transmit HDLC Control - 'h20............................................... 32
THDLC_STAT - Transmit HDLC Status - 'h22.................................................. 32
THDLC_INT - Transmit HDLC Interrupt Status - 'h24.................................... 32
THDLC_INTR_EN - Transmit HDLC Interrupt Enable - 'h26 ........................ 33
THDLC_FIFO_DATA - Transmit HDLC FIFO Data Write - 'h28................... 33
RXFRMR Register Description .....................................................................................33
RXFRMR_CTRL - Receive Framer Control - 'h30 ............................................. 33
RXFRMR_STAT - Receive Framer Status - 'h32................................................. 33
RXFRMR_INT - Receive Framer Interrupt Status - 'h34 .................................. 34
RXFRMR_INT_EN - Receive Framer Interrupt Enable - 'h36 ......................... 34
RFEAC Register Descriptions ......................................................................................34
RFEAC_CTRL - Receive FEAC control - 'h38 .................................................... 34
RFEAC_STAT - Receive FEAC Status - 'h3A ..................................................... 35
RFEAC_INT - Receive FEAC Interrupt Status - 'h3C ....................................... 35
RFEAC_INT_EN - Receive FEAC Interrupt Enable - 'h3E............................... 35
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Contents
T3 Framer MegaCore Function (T3FRM) User Guide
RFEAC_CODE - Receive FEAC Code - 'h40 ...................................................... 35
Counter Register Descriptions .....................................................................................35
LCVCTR - LCV Counter - 'h42............................................................................. 35
OOFCTR - OOF Counter - 'h44 ............................................................................ 35
LOSCTR - LOS Counter - 'h46.............................................................................. 35
EXZCTR - EXZ Counter - 'h48.............................................................................. 36
PERRCTR - PERR Counter - 'h4A........................................................................ 36
CPERRCTR - CPERR Counter - 'h4C .................................................................. 36
FEBECTR - FEBE Counter - 'h4E.......................................................................... 36
AISCTR - AIS Counter - 'h50 ................................................................................ 36
RHDLC Register Descriptions .....................................................................................36
RHDLC_CTRL - Receive HDLC control - 'h60 .................................................. 36
RHDLC_STAT - Receive HDLC Status - 'h62 .................................................... 37
RHDLC_INT - Receive HDLC Interrupt Status - 'h64...................................... 37
RHDLC_INT_EN - Receive HDLC Interrupt Enable - 'h66 .............................37
RHDLC_FIFO_DATA - Receive HDLC FIFO Data Read - 'h68 ...................... 38
RHDLC_ADDR - RHDLC Address- 'h6A .......................................................... 38
Core Verification Summary ..........................................................................................................39
Simulation Environment .......................................................................................................39
Compatibility Testing Environment ...................................................................................39
Getting Started
Design Walkthrough .....................................................................................................................41
Obtaining & Installing the T3FRM ..............................................................................................42
Downloading the MegaCore Function ...............................................................................42
Installing the MegaCore Files ...............................................................................................42
Generating a Custom T3FRM .......................................................................................................43
Implementing the System .............................................................................................................44
Simulating Your Design ................................................................................................................44
Using the Verilog Demo Testbench .....................................................................................44
Using the Visual IP Software ...............................................................................................45
Synthesis, Compilation & Place & Route ...................................................................................45
Using Third-Party EDA Tools for Synthesis ......................................................................45
Using the Quartus II development tool for compilation and place-and-route .............45
Licensing for Configuration .........................................................................................................46
Performing Post-Routing Simulation ..........................................................................................46
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Altera Corporation
Notes:
Specifications
User Guide
General
Description
Operating at the standard T3 data rate of 44.736 Mbps, the Altera® T3
Framer MegaCore® Function (T3FRM) supports unchannelized DS3
applications with C-bit parity functions, and specialized M23
applications.
1
Performance monitoring (RXFRMR) is achieved using interval counters to
accumulate: LCVs, FEBE events, AIS, LOS, EXZ, P-bit parity errors, C-bit
parity errors, OOF errors. RXFRMR also synchronizes frames for the
unchannelized C-bit parity functions and specialized M23 applications,
while the TXFRMR generates frames for these applications.
Five interfaces support T3FRM functions. See “Interfaces & Protocols” on
page 20
Table 1 shows T3FRM optional features.
Table 1. Optional Features
Note (1)
Options
Basic Configuration
HDLC Controller—Transmit and receive HDLC controllers with
data FIFO buffer to process overhead bit HDLC channel.
Parameters Choices
LEs
ESBs
–
–
1,301
0
HDLC
Y/N
571
2
Note:
(1)
The numbers for LEs and ESBs are approximate as of August, 2001. Users are strongly advised to run the
MegaWizard Plug-In, and the Quartus II software to see exact numbers for the T3FRM.
The optional HDLC terminates the path maintenance data link and
accumulates data in a FIFO buffer inside the RXFRMR and inserts data to
the path maintenance data link channel with a data FIFO buffer inside the
TXFRMR. RXFRMR and TXFRMR provide HDLC/LAPD frame
generation and processing.
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Specifications
Two sub-blocks, the receive framer (RXFRMR) and the transmit framer
(TXFRMR) perform multiple functions, including: generation and
detection of PRBS, FEAC detection and insertion, B3ZS decoding and
encoding, generation and detection of control and alarm codes.
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
The T3FRM complies with all applicable standards, including: Telcordia,
Transport Systems Generic Requirements (TSGR): Common Requirements
GR-499-CORE, Issue 2, December 1998; and American National Standards
Institute, Digital Hierarchy-Formats Specifications T1.107-1995
Functional
Description
This section provides a detailed description of the T3FRM divided into
RXFRMR and TXFRMR functions. Figure 1 is a complete block diagram of
the T3FRM, detailing the sub-blocks, RXFRMR and TXFRMR; and its five
interfaces.
Figure 1. Block Diagram
rxreset_n
rxsclk
RXFRMR
rxbit
T3 Mapper
Interface
rclk
T3 Line
Interface
rohclk
rpdata
rohfp
rndata (2)
roh
T3 Overhead
Interface
lcv (2)
mrxclk
mrxena
mrxffp
mrxefp
mrxfoh
mrxval
mrxdat[7:0]
alos
Midbus Interface
RCLK DOMAIN
CLK44 DOMAIN
read
sel
txreset_n
clk44
wdata[15:0]
addr[6:1]
rdata[15:0]
AIRbus
Interface (1)
dtack
irq
tclk
T3 Line
Interface
tpdata
tndata (3)
tfp (3)
TXFRMR
mtxclk
mtxena
mtxffp
mtxefp
mtxfoh
mtxval
mtxdat[7:0]
Midbus Interface
tohclk
tohfp
toh
T3 Overhead
Interface
tohins
txsclk
txbit
T3 Mapper
Interface
Notes:
(1)
(2)
(3)
12
The AIRbus interface provides access to internal registers for the entire block.
lcv and rndata are one pin.
tfp and tndata are one pin.
T3 Framer MegaCore Function (T3FRM) User Guide
RXFRMR
Specifications
The RXFRMR extracts overhead bits from the incoming DS3 bit stream;
this function is compatible with the C-bit parity DS3 format. The DS3
frame is dissected into distinct blocks of information bits; and each is
processed by different functional blocks.
B3ZS Decoding for Dual Rail & Single Rail Signals
For a dual rail, B3ZS input signal, the decoder decodes data, and provides
indications of LCVs. For a single rail, NRZ input signal, a separate LCV
input signal is used to indicate line code violations, which are detected by
an upstream B3ZS decoder.
Specifications
Figures 2 and 3 illustrate the dual rail and single rail decoding scheme.
Figure 2. Receive Dual Rail Decoding Scheme
rclk
rpdata
B
0
V
0
0
rndata
data
1
1
0
0
0
1
0
1
0
1
1
0
Figure 3. Receive Single Rail Decoding Scheme
rclk
rpdata
X1
I1
I2
...
F1
I1
I2
...
C1
I1
lcv
PMON
PMON provides internal interval counters in the RXFRMR register block
to measure persistent errors. PMON counters interface with RXFRMR to
accumulate erroneous events including: LCV, LOS, EXZ, P-bit parity
error, C-bit parity error, FEAC, OOF error, and AIS, in interval counters.
PMON continues to accumulate these events in the counters until the
software is programmed to read a particular counter value. After a read
operation, the counter is cleared.
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Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Frame Searching and OOF Detection
The RXFRMR searches for valid frames from the incoming DS3 signal
using F-bits and M-bits. The framing status is reported in the internal
status register. The RXFRMR also detects OOF defects for incoming DS3
signals.
Parity Check
The RXFRMR compares the P-bits against the parity results of the
previous M-frame, calculates the parity of the incoming frame, and stores
the result for comparison with the next frame.
AIS and Idle Signal
The incoming DS3 signal is monitored for an AIS, or an idle signal. An AIS
defect is detected when a signal consisting of the AIS pattern, described
below, is received:
–
–
–
–
–
–
The AIS signal has a valid M-frame alignment channel,
M-subframe alignment channel, and valid P-bits.
The information bits are set to a ‘b10 sequence. The C-bits are set
to zero.
The X-bits are set to 1.
The idle signal has a valid M-frame alignment channel,
M-subframe alignment channel, and valid P-bits.
The information bits are set to a ‘b1100 sequence. The C-bits are
set to zero in M-subframe 3.
The remaining C-bits can take on any values.
C-bit Parity Functions
The C-bit parity application is software programmable. RXFRMR extracts
C-bits with their respective functions. C-bits that constitute the FEAC
channel are sent to the RFEAC block for further processing. See “Receive
FEAC” on page 15. Similarly, C-bits that make up the path maintenance
data link are sent to the RHDLC block. See “Receive HDLC” on page 16.
RXFRMR also checks C-bit parity and FEBEs. These errors, together with
LCVs and EXZs indications, are accumulated in the PMON. See “Receive
Dual Rail Decoding Scheme” on page 13. C-bit parity functions can be
disabled by software. If disabled, all C-bits are set to 1.
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T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
Table 2 lists the various C-bit channel functions.
Table 2. C-bit Channel Functions
M-Subframe
C-bit
Description
C1
AIC signal. Set to 1 to indicate C-bit parity function.
1
C2
Reserved for future use. Set to 0.
1
C3
Used for FEAC signal.
2
C1C2C3
Unused. Set to 1.
3
C1C2C3
Combined with P-bits to form five CP-bits for parity. They should have the same
value as P-bits.
4
C1C2C3
Used for FEBE functions.
5
C1C2C3
Used for HDLC/LAPD data link at a rate of 28.2 Kbps.
6
C1C2C3
Unused. Set to 1.
7
C1C2C3
Unused. Set to 1.
1
Specifications
1
RDI Detection
If both extracted X-bits are 0, an RDI is detected and reported in the
internal status register. The defect is removed if both extracted X-bits are
1. If the X-bits are not equal, the RDI status remains in its previous state.
M23 Application
While the T3FRM provides transparent transmission of M23 frames, it
does not handle DS2 multiplexing, or bit stuffing.The M23 application is
selected by software. RXFRMR monitors the AIC signal which toggles
every M-frame for M23 frames and reports the result in the internal status
register. Other C-bits are ignored and sent to a serial hardware overhead
extraction and insertion interface. See “T3 Overhead Interface” on
page 24.
Receive FEAC
The RFEAC detects the bit-oriented codes contained in the DS3 C-bit
parity FEAC channel received from the RXFRMR. The FEAC codes are
received as 16-bit sequences, each consisting of eight 1’s, a 0, six code bits,
and a trailing 0. If a valid code is detected, the RFEAC block asserts the
corresponding bit in the FEAC interrupt status register. The RFEAC block
receives idle code if no valid code is detected. A software programmable
feature allows an interrupt to be generated when a detected code has been
validated, and when the code is removed.
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15
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Receive HDLC
The RHDLC receives HDLC/LAPD frame bits from the RXFRMR. It also
provides a data link for the AIRbus to receive maintenance information.
The RXFRMR handles framing, frame synchronization and optional
address matching. Processing of the address, control, and information
fields is software programmable.
The RHDLC detects the change from flag characters to the first byte of
data. It then:
■
■
■
Removes the stuffed zeros on the incoming data stream;
Converts serial bits into bytes;
Calculates the CRC.
If any errors exist, it records the error in the HDLC status register.
The received data is placed into a 128x10 bit FIFO buffer. All of this data
is processed by software. An interrupt is generated when a complete
message is stored in the FIFO buffer. The FIFO buffer can be reset and
cleared by software. The RHDLC generates interrupts from several
sources which are: transmission abort, FIFO buffer half empty, FIFO
buffer empty, CRC error, end of message, and FIFO buffer overrun. All
these events are recorded in the interrupt status registers.
The FIFO buffer is divided as follows: bits 7:0 are data bits, bit 8
is an end of packet (EOP), and bit 9 is a start of packet (SOP).
External LOS Insertion
The alos pin can inject LOS errors into incoming data. When alos is held
high continuously for 175 or more cycles, the RXFRMR should be able to
detect LOS, assert the LOS bit in the RXFRMR register, generate an
interrupt, and assert the LOSI bit in the RXFRMR interrupt status register.
The LOS counter will increment.
16
T3 Framer MegaCore Function (T3FRM) User Guide
TXFRMR
Specifications
The TXFRMR inserts overhead bits into the incoming DS3 payload bit
stream, which is compatible with C-bit parity DS3 format. The TXFRMR
performs the following functions.
B3ZS Encoding for Dual Rail & Single Rail Signals
A software programmable feature allows the DS3 signal to be output as
single rail, NRZ signal, or dual rail, B3ZS signal. For dual rail interface,
data is encoded with a B3ZS coding scheme. The signal is encoded in
compliance with the AMI coding scheme.
Figure 4. Transmit Dual Rail Encoding Scheme
tclk
tpdata
tndata
Data
1
1
0
0
0
1
0
1
0
0
0
1
1
0
Figure 5. Transmit Single Rail Encoding Scheme
tclk
tpdata
X1
I1
I2
F1
I1
I2
C1
I1
tfp
Start of M-frame
Frame Bit Insertion
TXFRMR receives payload data from the Midbus interface. The M-bits
and F-bits are inserted into the M-frame. The parity of the payload data is
calculated and stored for the next M-frame. Previous results of parity
calculations of the M-frames are inserted in the P-bit position.
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1
Specifications
Figures 4 and 5 illustrate the B3ZS dual rail and single rail encoding
scheme.
17
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
RDI
The RXFRMR detects LOS, OOF or AIS. The TXFRMR sets both X-bits to
‘00’ if any errors are detected. Otherwise, both are set to ‘11’. They are
software programmable via the internal register.
AIS and Idle Signal
AIS and the idle signal can be inserted according to the status signals of
the internal register set by software.
C-bit Parity Functions
The C-bit parity application is software programmable. TXFRMR inserts
C-bits with their respective functions. CP-bits are equivalent to P-bits. The
FEBE indications are detected by RXFRMR and the status is stored in the
internal register.
M23 Application
While the T3FRM provides transparent transmission of M23 frames, it
does not handle DS2 multiplexing, or bit stuffing. The M23 application is
software programmable. TXFRMR toggles the AIC signal every M-frame.
All other C-bits are forced to 0 unless they are overridden by hardware
insertion—See “T3 Overhead Interface” on page 24.
Diagnostic Insertion
TXFRMR can be programmed to insert erroneous events for diagnostic
purpose. These events are: FEBE, P-bit parity error, CP-bit parity error,
M-bit error, LCV, and LOS. The insertion occurs when there is a bit
transition from 0 to 1 in the diagnostic control register.
Software Insertion of C-bits
TXFRMR can be programmed to insert C-bits by setting the control
register. Values of the C-bits to be inserted are programmed via the
internal registers.
Transmit FEAC Generator
The TFEAC Generator transmits codes to the C-bit parity FEAC channel
via the TXFRMR. The idle code is used to disable the transmission of other
codes. If the FEAC channel is disabled by software, the TFEAC block
sends all 1s to the channel.
18
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
Transmit HDLC
The THDLC provides a serial data link for the C-bit parity HDLC/LAPD
path maintenance data link. It is used by the microprocessor to transmit
HDLC data frames via TXFRMR.
The FIFO buffer is divided as follows: bits 7:0 are data bits, bit 8
is and End Of Packet (eop), and bit 9 is a Start Of Packet (sop).
The THDLC stuffs a 0 into the serial data output if there are more than five
consecutive 1s in the raw transmit data or in the CRC data. This prevents
the unintentional transmission of flag or abort sequences.
Transmission can be aborted by software setting a control bit to send an
abort sequence, ‘b01111111.
THDLC generates an interrupt when FIFO buffer is full, half full, or an
underflow has occurred.
Generation &
Detection of
PseudoRandom Bit
Streams
(PRBS)
Receive
On the receive side, PRBS detection is software programmable. Software
searches for the PRBS pattern from the in-coming unframed bit stream.
When the number of error-free bits from the input reaches the
programmable threshold value, a synchronization register bit is set. Once
synchronized, an error in the incoming bit stream causes the bit error
counter to increment. Following an error, the shift register is re-filled
during a time in which no errors are reported. Error reporting resumes
when the error has been purged and the shift register contains new data.
Transmit
On the transmit side, PRBS generation is software programmable.
Software generates an unframed pseudo-random bit pattern with a length
of 216-to-1. The result is fed back to the input of the first stage.
Altera Corporation
19
1
Specifications
THDLC can be disabled by software, but keeps sending 1s while disabled.
When enabled, it continuously transmits flags (‘b01111110) until data is
ready to be sent. THDLC automatically begins transmission of data once
at least one complete message moves into the FIFO buffer. THDLC
calculates the CRC-16 values and transmits these values after the last byte
of data has been sent. The data is then serialized and the flags are inserted
until the next complete message is available. The FIFO buffer can be reset
and cleared by software.
Specifications
Maintenance
T3 Framer MegaCore Function (T3FRM) User Guide
System Reset
T3FRM provides active low reset pins for both the transmit, txreset_n,
and receive, rxreset_n. These pins can be asserted asynchronously, and
de-asserted synchronously.
Interfaces &
Protocols
Five interfaces—illustrated in Figure 1—support the T3FRM: the T3 Line
interface, the Midbus interface, the Access to Internal Registers (AIRbus)
interface, the T3 Mapper interface, and the T3 Overhead interface.
The T3 Line interface accepts and transmits data on both a single data rail
or an encoded dual data rail. The Midbus allows for connection to a
SONET framer. A 16-bit synchronous microprocessor interface (AIRbus)
provides control, maintenance, and status monitoring capabilities. A
serial interface provides a connection to a T3 mapper for receiving and
transmitting payload data. A T3 Overhead interface executes overhead bit
extraction and insertion. Each interface function is detailed further in this
section.
For all timing diagrams in this section, it is implied that the data
busses are changing state on the rising edge of every clock. Only
when the nature of the data carried on the data busses changes is
there a transition shown on the data bus.
T3 Line Interface
The T3FRM features both single rail and dual rail interfaces that connect
to standalone line interface units, which allow for transmission of T3 data
from the LIU to the T3FRM. The T3FRM can act as a T3 Line interface
slave. An LIU is a transceiver used to interface between the T3FRM and a
wiring device. In the TX direction the LIU converts encoded digital signals
into appropriate pulses for transmission over cable. In the RX direction
the opposite action occurs.
Midbus Interface
The Midbus interface is a simple synchronous full-duplex data path bus.
A T3FRM Midbus runs at 44.736MHz over a single byte lane in each
direction. In the RX direction, data is transferred from the Midbus master,
RXFRMR, to the slave. In the TX direction, data is transferred from the
slave to the Midbus master, TXFRMR. In each direction the Midbus can
carry eight bits per clock cycle. It includes Midbus receive data
(mrxdat[7:0]) and Midbus receive enable (mrxena) lines to indicate
valid data transfers in the receive direction, and a Midbus transmit data
(mtxdat[7:0]) and Midbus transmit enable (mtxena) lines to indicate
valid data requests in the transmit direction.
20
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
Figures 6 and 7 show example Midbus interface data receive and transmit
transactions.
Figure 6. Receive Midbus Clock & Data Timing Diagram
rxclk
rxval
rxdat
D1
D2
D3
1
Specifications
Figure 7. Transmit Midbus Clock & Data Timing Diagram
txclk
txval
D1
txdat
D2
D3
Receive Direction
Figure 8 shows the Midbus signals in the receive direction. The T3FRM
presents data on mrxdat, on the rising edge of mrxclk. The following
position indicators are also presented along with the data.
■
mrxval indicates that the following strobes are valid:
–
mrxena indicates valid user payload on the mrxdat bus
–
mrxffp indicates a multi-frame pulse
–
mrxefp indicates a sub-frame pulse
–
mrxfoh indicates an overhead pulse
Figure 8. Midbus Receive Timing Diagram
mrxffp
...
mrxefp
...
mrxfoh
mrxdat
D1
mrxval
mrxena
Altera Corporation
D2
...
...
...
...
...
...
...
...
...
D3
D4
...
...
...
...
...
...
...
...
...
D5
21
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Transmit Direction
Figure 9 shows the Midbus signals in the transmit direction. The T3FRM
provides position commands (listed below) that indicate the type of byte
being processed on the next clock pulse. mxtdat is ignored when mtxena
is low in the preceding clock cycle.
■
mtxval indicates that the following strobes are valid:
–
mtxena indicates user payload on the mtxdat bus
–
mtxffp indicates a multi-frame pulse
–
mtxefp indicates a sub-frame pulse
–
mtxfoh indicates an overhead pulse
Figure 9. Midbus Transmit Timing Diagram
mtxffp
...
mtxefp
...
mtxval
...
...
...
...
...
mtxena
...
...
mtxfoh
mtxdat
D1
D2
D3
...
...
...
...
...
...
...
D4
D5
AIRbus Interface
The AIRbus interface provides access to internal registers using a simple
synchronous internal processor bus protocol. This protocol consists of
separate read (rdata) and write (wdata) data buses, a data transfer
acknowledge (dtack) signal, and a select (sel) signal. An address bus
(addr[6:1]) and read (read) signal indicate the location and type of
access within the block. The rdata buses and dtack signals can be
merged from multiple blocks using a simple OR function. The dtack
signal is sustained until the block sel is removed (four-way
handshaking) meaning the AIRbus can cross clock domain boundaries.
T3FRM is an AIRbus slave with a data width of 16 bits.
B
22
More detailed Midbus and AIRbus interface information is available from
the Altera web site at http://www.altera.com.
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
T3 Mapper Interface
T3FRM provides a serial bit stream that interfaces with a T3 mapper. The
DS3 bit stream, including the overhead bits, is mapped into the SONET
STS-1 SPE asynchronously via the T3 Mapper interface. The T3 mapper is
responsible for providing a mechanism to compensate for frequency
differences.
Receive
Transmit
A T3 mapper transmits DS3 bits to T3FRM. A new DS3 bit is expected to
be present on the txbit signal at the rising edge of txsclk. This bit is
retrieved by the T3FRM on the next rising edge of txsclk.
Figures 10 and 11 show example T3 Mapper interface, receive and
transmit, transactions.
Figure 10. Receive T3 Mapper Timing Diagram
rxsclk
rxbit
X1
I1
I2
I84
F1
I1
I2
I84
F1
I1
I2
I84
Figure 11. Transmit T3 Mapper Timing Diagram
txsclk
txbit
Altera Corporation
X1
I1
I2
I84
23
1
Specifications
T3FRM sends DS3 bits to a T3 mapper. Data is presented on the rxbit
signal by T3FRM on the rising edge of rxsclk. The data is then retrieved
on the next rising edge of rxsclk by the T3 mapper.
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
T3 Overhead Interface
The T3FRM provides a serial hardware interface for the insertion and
extraction of overhead bits. This interface runs at a rate of 522 kHz.
Overhead bits can be serially inserted to the DS3 frame using the T3
Overhead interface. TXFRMR receives overhead bits from the interface
and overrides internally generated bits. Hardware insertion can be
disabled by software. This interface provides the proper clocking and
framing for the serial interface.
Figure 12 shows the insertion of overhead bits.
Figure 12. T3 Overhead Insertion Timing Diagram
tohclk
tohfp
toh
X1
F1
C1
F2
C2
F3
C3
F4
X2
F1
tohins
Overhead bits are extracted and input from the RXFRMR. RXFRMR
extracts all overhead bits and sends them to the T3 Overhead interface,
which shifts out the overhead bits. The interface provides the proper
clocking and framing of the output overhead bit stream.
Figure 13 shows the extraction of overhead bits.
Figure 13. T3 Overhead Extraction Timing Diagram
rohclk
rohfp
roh
24
X1
F1
C1
F2
C2
F3
C3
F4
X2
F1
T3 Framer MegaCore Function (T3FRM) User Guide
Performance
Specifications
Table 3 shows the required speed and estimated gate count of the T3FRM
in an APEX 20KE device.
Table 3. Performance
Note (1)
LEs
ESBs
fMAX (MHz)
1,301 - 1,872
0-2
44.736 is required
Note:
(1)
Table 4 lists the input/output signals for the T3FRM.
Table 4. I/O Signals (Part 1 of 2)
Port
Direction
Description
Receive T3 Line Interface Signals
rclk
Input
Line receive clock at nominal rate of 44.736 MHz
rpdata
Input
Line receive positive data for dual rail interface—NRZ output for single
rail interface.
rndata
Input
Line receive negative data for dual rail interface
lcv
Input
Line code violation for single rail signal
Receive T3 Mapper Interface Signals
rxsclk
Output
Receive clock—serial bit stream
rxbit
Output
Receive data—serial bit stream
rohclk
Output
Receive overhead clock at nominal rate of 44.736 MHz
rohfp
Output
Receive overhead frame pulse
roh
Output
Receive overhead data
mrxclk
Output
Receive clock
mrxena
Output
Receive enable
mrxffp
Output
Receive multi-frame pulse
mrxefp
Output
Receive sub-frame pulse
mrxfoh
Output
Receive overhead pulse
mrxval
Output
Frame (payload + overhead) byte enables for mrxdat
mrxdat[7:0]
Output
Receive data
Receive Midbus Signals
clk44 Domain Signals
clk44
Altera Corporation
Input
1
Specifications
I/O Signals
All LE and ESB numbers are approximate as of August 2001. They reflect the range
from the basic to full-feature variant.
External reference clock at nominal rate 44.736 MHz
25
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Table 4. I/O Signals (Part 2 of 2)
Transmit T3 Line Interface Signals
tclk
Output
Line transmit clock at nominal rate 44.736 MHz
tpdata
Output
Line transmit positive data for dual rail interface. NRZ output for single
rail interface.
tndata
Output
Line transmit negative data for dual rail interface.
tfp
Output
Start of M-frame pulse for single rail interface.
Transmit T3 Mapper Interface Signals
txsclk
txbit
Output
Transmit clock—serial bit stream
Input
Transmit data—serial bit stream
tohclk
Output
Transmit overhead clock at 522 kHz
tohfp
Output
Transmit overhead frame pulse
toh
Input
Transmit overhead data
tohins
Input
Transmit overhead insertion enable
Transmit Midbus Signals
mtxclk
Output
Transmit clock
mtxena
Output
Transmit data enable
mtxffp
Output
Transmit multi-frame pulse
mtxefp
Output
Transmit sub-frame pulse
mtxfoh
Output
Transmit overhead pulse
mtxval
Output
Frame (payload + overhead) byte enables for mtxdat
Input
Transmit data
read
Input
Read
sel
Input
Select
wdata[15:0]
Input
Write data
addr[6:1]
Input
Address
mtxdat[7:0]
AIRbus Signals
rdata [15:0]
Output
Read data
dtack
Output
Data transfer acknowledge
irq
Output
Interrupt request
Maintenance Signals
rxreset_n
Input
Active low receive reset
txreset_n
Input
Active low transmit reset
Input
Hardware LOS insertion
Test Signal
alos
26
T3 Framer MegaCore Function (T3FRM) User Guide
Software
Interface
Specifications
Memory Map
All addresses are 16-bit accesses and are shown as hex values. The access
addresses for each register increment by units of 2, since the accesses are
16-bits wide.
Table 5. Memory Map (Part 1 of 2)
Address
Description
'h0
'h2
MSTR_INT
Master Interrupt Status
MSTR_INT_EN
Master Interrupt Enable
'h4
RESERVED
Reserved
'h6
PRBS_CTRL
PRBS control
'h8
PRBS_INT
PRBS Interrupt Status
'hA
PRBS_INT_EN
PRBS Interrupt Enable
'hC
PRBS_THRES
PRBS Threshold
'hE
PRBS_ERR
PRBS Bit Error Counter
'h10
'h12
TXFRMR_CTRL
Transmit Framer control
TXFRMR_DIAG
Transmit Framer Diagnostic
'h14
TFEAC_CTRL
Transmit FEAC control
'h16
TFEAC_CODE
Transmit FEAC Code
'h18
CINST1
C-Bit Insertion 1
'h1A
CINST2
C-Bit Insertion 2
'h20
'h22
THDLC_CTRL
Transmit HDLC control
THDLC_STAT
Transmit HDLC Status
'h24
THDLC_INT
Transmit HDLC Interrupt Status
'h26
THDLC_INTR_EN
Transmit HDLC Interrupt Enable
'h28
THDLC_FIFO_DATA
Transmit HDLC FIFO Data Write
'h30
'h32
RXFRMR_CTRL
Receive Framer control
RXFRMR_STAT
Receive Framer Status
'h34
RXFRMR_INT
Receive Framer Interrupt Status
'h36
RXFRMR_INT_EN
Receive Framer Interrupt Enable
'h38
RFEAC_CTRL
Receive FEAC control
'h3A
RFEAC_STAT
Receive FEAC Status
'h3C
RFEAC_INT
Receive FEAC Interrupt Status
'h3E
RFEAC_INT_EN
Receive FEAC Interrupt Enable
'h40
RFEAC_CODE
Receive FEAC Code
'h42
LCVCTR
LCV counter
'h44
OOFCTR
OOF counter
'h46
LOSCTR
LOS counter
'h48
EXZCTR
EXZ counter
1
Specifications
Altera Corporation
Register
27
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Table 5. Memory Map (Part 2 of 2)
Address
Register
Description
'h4A
PERRCTR
PERR counter
'h4C
CPERRCTR
CPERR counter
'h4E
FEBECTR
FEBE Counter
'h50
AISCTR
AIS Counter
'h60
'h62
RHDLC_CTRL
Receive HDLC control
RHDLC_STAT
Receive HDLC Status
'h64
RHDLC_INT
Receive HDLC Interrupt Status
'h66
RHDLC_INT_EN
Receive HDLC Interrupt Enable
'h68
RHDLC_FIFO_DATA
Receive HDLC FIFO Data Read
'h6A
RHDLC_ADDR
RHDLC Address
Registers
Table 6 lists the access codes used to describe the type of register bits.
Table 6. Register Bit Description
Code
28
Description
RW
RO
Read/Write
RW1C
Read/Write 1 to Clear
RW0S
Read/Write 0 to Set
RTC
Read to Clear
RTS
Read to Set
RTCW
Read to Clear/Write
RTSW
Read to Set/Write
RWTC
Read/Write any value to Clear
RWTS
Read/Write any value to Set
RWSC
Read/Write Self-Clearing
RWSS
Read/Write Self-Setting
UR0
Unused bits/Read as 0
UR1
Unused bits/Read as 1
Read-Only
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
Master Register Description
MSTR_INT - Master Interrupt Status - 'h0
Field
Bits
Access
Function
Default
PRBS
RFEAC
4
RO
When 1, the PRBS block has generated an interrupt.
0
3
RO
When 1, RFEAC has generated an interrupt.
0
RHDLC
2
RO
When 1, RHDLC has generated an interrupt.
0
THDLC
1
RO
When 1, the THDLC has generated an interrupt.
0
RXFRMR
0
RO
When 1, the RXFRMR has generated an interrupt.
0
1
Field
Bits
Access
Function
Default
PRBS
RFEAC
4
RW
This is a PRBS interrupt enable.
0
3
RW
This is an RFEAC interrupt enable.
0
RHDLC
2
RW
This is an RHDLC interrupt enable.
0
THDLC
1
RW
This is a THDLC interrupt enable.
0
RXFRMR
0
RW
This is an RXFRMR interrupt enable.
0
RESERVED - Reserved - 'h2
Field
RXFRMR
Bits
0
Access
RW
Function
This field is reserved for future use.
Default
0
PRBS_CTRL - PRBS control - 'h6
Field
RXPRBS
TXPRBS
Bits
Access
Function
Default
1
RW
This is a PRBS detection enable.
0
0
RW
This is a PRBS generation enable.
0
PRBS_INT - PRBS Interrupt Status - 'h8
Field
SYNC
Altera Corporation
Bits
0
Access
RW1C
Function
When 1, synchronization is achieved. When 0,
synchronization is lost.
Default
0
29
Specifications
MSTR_INT_EN - Master Interrupt Enable - 'h2
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
PRBS_INT_EN - PRBS Interrupt Enable - 'hA
Field
SYNC
Bits
0
Access
RW
Function
This is a synchronization interrupt enable.
Default
0
PRBS_THRES - PRBS Threshold - 'hC
Field
THRES
Bits
7:0
Access
RW
Function
This is an upper threshold PRBS synchronization.
Default
8'h40
PRBS_ERR - PRBS Bit Error Counter - 'hE
Field
CNT
Bits
15:0
Access
RTC
Function
This is a PRBS bit error counter.
Default
0
TXFRMR Register Description
TXFRMR_CTRL - Transmit Framer control - 'h10
Field
Bits
Access
Function
Default
UNI
7
RW
When 1, the single rail is enabled. When 0, the dual rail is
enabled.
0
CINST
6
RW
When 1, the C-bits are inserted by software. When 0, the
C-bits are generated internally.
0
SONET
5
RW
When 1, use data input from T3 Mapper Interface. When 0, 0
use data input from Midbus interface.
CBIT
4
RW
When 1, the C-bit parity application is enabled. When 0, the 0
M23 application is enabled.
RDI
3
RW
When 1, set X1X2='b00. When 0, set X1X2-'b11.
0
AIS
2
RW
This is an AIS indication enable.
0
IDLE
1
RW
This is an idle signal enable.
0
TOHDIS
0
RW
When 1, the overhead bit insertion is disabled. When 0, the 0
overhead bit insertion is enabled.
TXFRMR_DIAG - Transmit Framer Diagnostic - 'h12 (Part 1 of 2)
Field
DEXZ
30
Bits
7
Access
RW
Function
When in transition from 0 to 1, insert EXZ by forcing three
consecutive zeros into the data stream.
Default
0
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
TXFRMR_DIAG - Transmit Framer Diagnostic - 'h12 (Part 2 of 2)
Field
Bits
Access
Function
Default
DFEBE
6
RW
When in transition form 0 to 1, insert FEBE by setting the
three C-bits in M-subframe 4 to zero.
DPARERR
5
RW
When in transition from 0 to 1, the P-bits are inverted before 0
insertion into the DS3 stream.
DCPARERR
4
RW
When in transition from 0 to 1, the three C-bits in
M-subframe 3 are inverted before insertion into the DS3
stream.
DMBERR
3
RW
When in transition from 0 to 1, the M-bits are inverted before 0
insertion into the DS3 stream.
DFBERR
2
RW
When in transition from 0 to 1, the MF-bits are inverted
before insertion into the DS3 stream.
0
DLCV
1
RW
When in transition from 0 to 1, a line code violation is
inserted by generating an incorrect polarity of violation.
0
DLOS
0
RW
When in transition from 0 to 1, the data output is forced to a 0
continuous zero.
0
0
1
Specifications
TFEAC Register Descriptions
TFEAC_CTRL - Transmit FEAC control - 'h14
Field
ENA
Bits
0
Access
RW
Function
Default
This is TFEAC enable. When disabled, the TFEAC sends all 0
1s to the FEAC channel.
TFEAC_CODE - Transmit FEAC Code - 'h16
Field
TCODE
Bits
5:0
Access
RW
Function
A 6-bit FEAC code is to be transferred.
Default
0
CINST1 - C-Bit Insertion 1 - 'h18
Field
Bits
Access
Function
Default
M1
M2
14:12
RW
11:9
RW
These are C1C2C3 bits for M-subframe 2.
0
M3
8:6
RW
These are C1C2C3 bits for M-subframe 3.
0
M4
5:3
RW
These are C1C2C3 bits for M-subframe 4.
0
M5
2:0
RW
These are C1C2C3 bits for M-subframe 5.
0
Altera Corporation
0
31
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
CINST2 - C-Bit Insertion 2 - 'h1A
Field
M6
M7
Bits
Access
Function
Default
5:3
RW
These are C1C2C3 bits for M-subframe 6.
0
2:0
RW
These are C1C2C3 bits for M-subframe 7.
0
THDLC Register Descriptions
THDLC_CTRL - Transmit HDLC Control - 'h20
Field
Bits
Access
Function
Default
CRC_MODE
4
RW
When 1, select CRC-CCITT. When 0, select CRC-16.
FF_RST
3
RW
When there is a transition from 0 to 1, the FIFO buffer is
reset and cleared.
EOM
2
RW
When 1, the last byte of the message has been written to the 0
message FIFO buffer. This bit is automatically cleared in the
next clock cycle.
ABORT
1
RW
When 1, this register: aborts the current transmission, sends 0
an abort code with pattern until this bit is reset to 0, and
resets the FIFO buffer.
ENA
0
RW
This is the THDLC enable. When disabled, the FIFO buffer 0
is reset.
0
THDLC_STAT - Transmit HDLC Status - 'h22
Field
Bits
Access
Function
Default
UNDERFLOW
2
RO
When 1, the message FIFO buffer is in an underflow
condition.
0
FF_FULL
1
RO
When 1, the message FIFO buffer is full.
0
FF_HFULL
0
RO
When 1, the message FIFO buffer is half full.
0
THDLC_INT - Transmit HDLC Interrupt Status - 'h24
Field
Bits
Access
Function
Default
UNDER
FF_FULL
2
RW1C
A message FIFO buffer underflow has occurred.
0
1
RW1C
This is a change of message (FIFO buffer full status
interrupt).
0
FF_HFULL
0
RW1C
This is a change of message (FIFO buffer half full status
interrupt).
0
32
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
THDLC_INTR_EN - Transmit HDLC Interrupt Enable - 'h26
Field
Bits
Access
Function
Default
UNDER
FF_FULL
2
RW
This is a message FIFO buffer underflow interrupt enable.
0
1
RW
This is a message FIFO buffer full interrupt enable.
0
FF_HFULL
0
RW
This is a message FIFO buffer half full interrupt enable.
0
THDLC_FIFO_DATA - Transmit HDLC FIFO Data Write - 'h28
Field
9:0
Access
RW
Function
Default
This is a transmit FIFO buffer data write. Data is written into 0
the FIFO buffer via this register.
RXFRMR Register Description
RXFRMR_CTRL - Receive Framer Control - 'h30
Field
Bits
Access
Function
Default
CBEN
2
RW
When 1, the C-bit parity application is enabled. When 0, the 0
M23 application is enabled.
REFR
1
RW
Reframing is triggered by a 0 to 1 transition of the REFR bit. 0
UNI
0
RW
When 1, the single rail is enabled. When 0, the dual rail is
enabled.
0
RXFRMR_STAT - Receive Framer Status - 'h32 (Part 1 of 2)
Field
Bits
Access
Function
Default
LCV
EXZ
7
RO
When 1, a line code violation has occurred.
0
6
RO
When 1, excessive zeros have occurred.
0
LOS
5
RO
When 1, a loss of signal has occurred.
0
OOF
4
RO
When 1, the frame alignment is lost. When 0, the frame
alignment is found.
0
AIS
3
RO
When 1, an AIS pattern has been received.
0
IDLE
2
RO
When 1, an idle pattern has been received.
0
RDI
1
RO
When 1, RDI has been detected, i.e. X1X2='b00. When 0, 0
the RDI has been removed, i.e. X1X2='b11. If X1 differs from
X2, this bit remains unchanged.
Altera Corporation
1
Specifications
TFDATA
Bits
33
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
RXFRMR_STAT - Receive Framer Status - 'h32 (Part 2 of 2)
Field
AIC
Bits
0
Access
RO
Function
Default
This is the current status of the AIC signal, i.e. the first C-bit 0
of M-subframe. When 1, the AIC has been logic one for 63
consecutive occasions, thus indicating the presence of a
C-bit parity application. When 0, the AIC signal has been
logic zero for two or more times within 15 consecutive
occasions, thus indicating the M23 application.
RXFRMR_INT - Receive Framer Interrupt Status - 'h34
Field
Bits
Access
Function
Default
LCVI
EXZI
7
RW1C
This is a change of state of the LCV status interrupt.
0
6
RW1C
This is a change of state of the EXZ status interrupt.
0
LOSI
5
RW1C
This is a change of state of the LOS status interrupt.
0
OOFI
4
RW1C
This is a change of state of the OOF status interrupt.
0
AISI
3
RW1C
This is a change of state of the AIS status interrupt.
0
IDLEI
2
RW1C
This is a change of state of the IDLE status interrupt.
0
RDII
1
RW1C
This is a change of state of the RDI status interrupt.
0
CBITI
0
RW1C
This is a change of state of the CBIT status interrupt.
0
RXFRMR_INT_EN - Receive Framer Interrupt Enable - 'h36
Field
Bits
Access
Function
Default
LCV
EXZ
7
RW
This is a change of state of the LCV status interrupt enable.
0
6
RW
This is a change of state of the EXZ status interrupt enable.
0
LOS
5
RW
This is a change of state of the LOS status interrupt enable. 0
OOF
4
RW
This is a change of state of the OOF status interrupt enable.
AIS
3
RW
This is a change of state of the AIS status interrupt enable. 0
IDLE
2
RW
This is a change of state of the IDLE status interrupt enable.
RDI
1
RW
This is a change of state of the RDI status interrupt enable. 0
CBIT
0
RW
This is a change of state of the CBIT status interrupt enable. 0
0
0
RFEAC Register Descriptions
RFEAC_CTRL - Receive FEAC control - 'h38
Field
ENA
34
Bits
0
Access
RW
Function
This is the RFEAC enable.
Default
0
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
RFEAC_STAT - Receive FEAC Status - 'h3A
Field
IDLE
Bits
Access
0
RO
Function
The FEAC is idle.
Default
0
RFEAC_INT - Receive FEAC Interrupt Status - 'h3C
Field
VALID
Bits
Access
0
RW1C
Function
When 1, a valid FEAC code has been received.
Default
1
0
Field
VALID
Bits
Access
0
RW
Function
This is a valid code interrupt enable.
Default
0
RFEAC_CODE - Receive FEAC Code - 'h40
Field
RCODE
Bits
Access
5:0
RO
Function
A 6-bit FEAC is received.
Default
6'h3f
Counter Register Descriptions
LCVCTR - LCV Counter - 'h42
Field
LCVCNT
Bits
15:0
Access
RTC
Function
This is the line code violation counter.
Default
0
OOFCTR - OOF Counter - 'h44
Field
OOFCNT
Bits
15:0
Access
RTC
Function
This is the out of frame counter.
Default
0
LOSCTR - LOS Counter - 'h46
Field
LOSCNT
Altera Corporation
Bits
15:0
Access
RTC
Function
This is the loss of signal counter.
Default
0
35
Specifications
RFEAC_INT_EN - Receive FEAC Interrupt Enable - 'h3E
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
EXZCTR - EXZ Counter - 'h48
Field
EXZCNT
Bits
Access
15:0
RTC
Function
This is the excessive zeros counter.
Default
0
PERRCTR - PERR Counter - 'h4A
Field
PERRCNT
Bits
Access
15:0
RTC
Function
This is the P-bit error counter.
Default
0
CPERRCTR - CPERR Counter - 'h4C
Field
CPERRCNT
Bits
Access
15:0
RTC
Function
This is the CP-bit error counter.
Default
0
FEBECTR - FEBE Counter - 'h4E
Field
FEBECNT
Bits
Access
15:0
RTC
Function
This is the far end block error counter.
Default
0
AISCTR - AIS Counter - 'h50
Field
AISCNT
Bits
15:0
Access
RTC
Function
This is the alarm indication signal counter.
Default
0
RHDLC Register Descriptions
RHDLC_CTRL - Receive HDLC control - 'h60
Field
Bits
Access
Function
Default
CRC_MODE
4
RW
When 1, select CRC-CCITT. When 0, select CRC-16.
ADDM
2
RW
When 1, the RHDLC detects the address of the incoming
0
packet, and only stores data in the FIFO buffer if the address
matches the contents of the address register. When 0, all
data is stored in the FIFO buffer.
FF_RST
1
RW
When there is a transition from 0 to 1, the FIFO buffer is
reset and cleared.
0
ENA
0
RW
When 1, RHDLC is enabled. When 0, RHDLC is disabled.
When disabled, the FIFO buffer and related interrupts are
cleared.
0
36
0
T3 Framer MegaCore Function (T3FRM) User Guide
Specifications
RHDLC_STAT - Receive HDLC Status - 'h62
Field
Bits
Access
Function
Default
FF_EMTY
FF_HEMTY
3
RO
When 1, the message FIFO buffer is empty.
0
2
RO
When 1, the message FIFO buffer is half empty.
0
RSVD
1
RW
This field is reserved
0
IDLE
0
RO
When 1, RHDLC is in idle status.
0
1
RHDLC_INT - Receive HDLC Interrupt Status - 'h64
Bits
Access
Function
Default
FRM_ERR
CRC_ERR
6
RW1C
When 1, a frame error was detected.
0
5
RW1C
When 1, a CRC error was detected in the last LAPD frame. 0
EOM
4
RW1C
When 1, a complete message has been stored in the FIFO 0
buffer.
FF_EMTY
3
RW1C
This is a change of message (FIFO buffer empty status).
FF_HEMTY
2
RW1C
This is a change of message (FIFO buffer half empty status). 0
ABORT
1
RW1C
An abort sequence is detected in this field.
0
OVR
0
RW1C
When 1, the data is written over unread data in the FIFO
buffer.
0
0
RHDLC_INT_EN - Receive HDLC Interrupt Enable - 'h66
Field
Bits
Access
Function
Default
FRM_ERR
CRC_ERR
6
RW
This is a frame error interrupt enable.
0
5
RW
This is a CRC error interrupt enable.
0
EOM
4
RW
This is an end of message interrupt enable.
0
FF_EMTY
3
RW
This is a message FIFO buffer empty interrupt enable.
0
FF_HEMTY
2
RW
This is a message FIFO buffer half empty interrupt enable.
0
ABORT
1
RW
This is an abort sequence interrupt enable.
0
OVR
0
RW
This is a message FIFO buffer overrun enable.
0
Altera Corporation
37
Specifications
Field
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
RHDLC_FIFO_DATA - Receive HDLC FIFO Data Read - 'h68
Field
Bits
Access
Function
Default
PADDR
15:8
RW
In address matching mode, the first byte received after a flag 8'h01
character is compared against the contents of this register.
If a match occurs, the data, including the matching first byte,
is written into the FIFO buffer. Only the most significant six
bits are compared to the incoming address.
RFDATA
7:0
RW
In address matching mode, the second byte received after a 8'h3c
flag character is compared against the contents of this
register. If a match occurs, the packet data, including the
matching second byte, is written to the FIFO buffer. Only the
most significant seven bits are compared to the incoming
address.
RHDLC_ADDR - RHDLC Address- 'h6A
Field
Bits
Access
Function
Default
PADDR
15:8
RW
In address matching mode, the first byte received after a flag 8'h01
character is compared against the contents of this register.
If a match occurs, the data, including the matching first byte,
is written into the FIFO buffer. Only the most significant six
bits are compared to the incoming address.
SADDR
7:0
RW
In address matching mode, the second byte received after a 8'h3c
flag character is compared against the contents of this
register. If a match occurs, the packet data, including the
matching second byte, is written into the FIFO buffer. Only
the most significant seven bits are compared to the
incoming address.
38
T3 Framer MegaCore Function (T3FRM) User Guide
Core
Verification
Summary
Specifications
The full-feature variant of the T3FRM was thoroughly tested for
compliance with industry standards. Testing was done by simulation, and
in-circuit for third-party compatibility. Both test environments are
described briefly, including the number of test programs, and their
results.
Simulation Environment
A test suite using the utilities and the RTL model of the T3FRM was used
to verify the proper operation of all the features described in the RXFRMR
and TXFRMR sections. The RXFRM and TXFRM were tested at full speed:
44.736 MHz. Table 7 lists the results of the simulation for the full-feature
variant of the T3FRM
Table 7. Results
Number of test programs (1)
24
Number of test programs passing
24
Number of test programs failing
0
Number of test cases (1)
42
Number of test cases passing
42
Number of test cases failing
0
Note:
(1)
Each test program contains at least one test case.
Compatibility Testing Environment
The full-feature variant of the T3FRM was evaluated—within an APEX
EP20K400EFC672 device—against a commercial third-party DS3 framer
with similar features, as required by industry standards. The Altera PCI
MegaCore function was used to interface to the AIRbus, and to the
third-party framer. Figure 14 shows the test board used.
Software from a host PC was used to set registers on the T3FRM, and the
third-party framer. The effects of setting these registers, and any
corresponding registers, were observed to determine functionality.
Altera Corporation
39
1
Specifications
The T3FRM was simulated using behavioral utilities with multiple
simulators, including but not limited to ModelSim SE. The behavioral
utilities consist of T3 bit stream generators and monitors, payload
generators and monitors, an AIRbus master model, and clock generators.
Specifications
T3 Framer MegaCore Function (T3FRM) User Guide
Figure 14. Test Board
Third-Party ASSP
APEX EP20K400EFC672
Tests were run for extended periods of time, thereby testing millions of T3
frames. Table 8 lists the results of the hardware verification for the
full-feature variant of the T3FRM.
Table 8. Results
Number of test programs (1)
40
Number of test programs passing
40
Number of test programs failing
0
Number of test cases (1)
51
Number of test cases passing
51
Number of test cases failing
0
Note:
(1)
40
Each test program contains at least one test case.
Getting Started
User Guide
2
You can test-drive a T3FRM using the Altera® OpenCore® feature—within
the Quartus® II software—to instantiate it, to perform place-and-route, to
perform static timing analysis, and to simulate it using a third-party
simulator, within your custom logic. You only need licenses when you are
ready to generate programming files.
Getting
GettingStarted
Started
Design
Walkthrough
This section describes how to obtain a variant from the T3 Framer
MegaCore® Function (T3FRM). It explains how to install the T3FRM on
your PC, and walks you through the process of implementing the variant
in a design.
This design walkthrough involves the following steps:
1.
Obtaining and installing the T3FRM MegaCore Function.
2.
Generating a custom T3FRM for your system using the
MegaWizard® Plug-In.
3.
Implementing the rest of your system using AHDL, VHDL, or
Verilog HDL.
4.
Simulating the T3FRM within your design.
5.
Synthesis, compilation, and place-and-route.
6.
Licensing the T3FRM to configure the device.
7.
Performing post-routing simulation.
The instructions assume that:
■
■
■
■
Altera Corporation
You are using a PC
You are familiar with the Quartus II software.
The Quartus II software (the newest version) is installed in the default
location.
You are using the OpenCore feature to test-drive a T3FRM, or you
have licensed it.
41
Getting Started
Obtaining &
Installing the
T3FRM
T3 Framer MegaCore Function (T3FRM) User Guide
To start using the T3FRM, you need to obtain the MegaCore package,
which includes the following:
■
■
■
■
■
■
Data sheet
User guide
AIRbus and Midbus interface functional specifications
MegaWizard Plug-In
–
Encrypted gate level netlist
–
Place-and-route constraints (where necessary)
–
Secure RTL simulation model
Demo testbench
Access to problem reporting system
Downloading the MegaCore Function
If you have Internet access, you can download the T3 Framer MegaCore
function from the Altera web site. Follow the instructions below to obtain
the core via the Internet. If you do not have Internet access, you can obtain
the core from your local Altera representative.
1.
Point your web browser at http://www.altera.com/IPmegastore.
2.
In the IP MegaSearch keyword field type T3.
3.
Click the link for the T3 Framer MegaCore function.
4.
On the product page, click the Free Test-Drive icon.
5.
Follow the on-line instructions to download the function and save it
to your hard disk.
Installing the MegaCore Files
Use the MegaWizard Plug-In to generate the files and install them on your
PC. The following instructions describe this process.
For UNIX systems, you must have Java runtime environment version 1.3
before you can use the MegaWizard Plug-In. You can download this file
from the Java web site at http://www.java.sun.com.
For Windows, follow the instructions below:
1.
42
Click Run (Start menu).
Altera Corporation
T3 Framer MegaCore Function (T3FRM) User Guide
2.
Type <path name>\<filename>.exe, where <path name> is the location
of the downloaded T3FRM and <filename> is the filename of the
T3FRM. Click OK.
3.
The MegaCore Installer dialog box appears. Follow the
MegaWizard Plug-In instructions to finish the installation.
4.
Disregard this step if you are using Quartus II version 1.1 or higher.
Otherwise, after you have finished installing the files, you must
specify the directory in which you installed them as a user library in
the Quartus II software. Search for “User Libraries” in Quartus II
Help for instructions on how to add these libraries.
This section describes the design flow using the T3 Framer MegaCore
function and the Quartus II development system. A MegaWizard Plug-In
is provided with the T3FRM. The MegaWizard Plug-In Manager—used
within the Quartus II software—allows you to create or modify design
files to meet the needs of your application. You can then instantiate the
T3FRM in your design file.
To create a custom T3FRM using the MegaWizard Plug-In, follow these
steps:
1.
Altera Corporation
Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In
Manager command (Tools menu) in the Quartus II software. The
MegaWizard Plug-In Manager dialog box is displayed.
Refer to Quartus II Help for detailed instructions on how to use
the MegaWizard Plug-In Manager.
2.
Specify that you want to create a new custom variant and click Next.
3.
On the second page of the MegaWizard Plug-In, open the
Communications folder, and select the T3FRM from the T3 folder.
4.
Choose the type of output files (language), specify the folder and
name for the files the MegaWizard Plug-In creates, and click Next.
5.
Select the optional parameters and choices that you require.
6.
The final screen lists the design files created by the MegaWizard
Plug-In, and indicates the location of the simulation models for the
selected variant. Click Finish.
43
2
Getting Started
Generating a
Custom T3FRM
GettingGetting Started
Getting Started
Implementing
the System
T3 Framer MegaCore Function (T3FRM) User Guide
Once you have created/obtained your custom T3FRM, you are ready to
implement it. You can use the files generated by the MegaWizard Plug-In,
and use the Quartus II software or other EDA tools to create your design.
Table 1 lists the generated files.
Table 1. MegaWizard Plug-In Files
Description
Design File Wrapper
Sample Instantiation
Black Box Module
Symbol files for the Quartus II software used to instantiate the
T3FRM into a schematic design
An encrypted HDL netlist file
Verilog HDL
VHDL
.v
.vhd
_inst.v
_inst.vhd
_bb.v
–
.bsf
.bsf
.e.vqm.v
.e.vqm.v
Note:
(1) AHDL output file creation is not supported in the T3FRM v1.2.0 MegaWizard Plug-In. If AHDL output files
are required, please contact [email protected] request them.
Simulating
Your Design
Altera provides three models to be used for functional verification of the
T3FRM within your design. A Verilog demo testbench, including scripts
to run it, is also provided. This demo testbench used with the ModelSim
AE 5.5a simulator demonstrates how to instantiate a model in a design.
To find the simulation models for your selected variant, refer to the last
page of the MegaWizard Plug-In Manager. These models and the demo
testbench are located on your hard drive, the paths are:
■
■
■
■
sim_lib/<variant>/modelsim_verilog/
sim_lib/<variant>/modelsim_vhdl/
sim_lib/<variant>/visual_ip/
sim_lib/<variant>/test/
<variant> is a unique code (aotXXXX_#_t3frm) assigned to the
specific configuration requested through the MegaWizard PlugIn.
Using the Verilog Demo Testbench
The demo testbench includes some simple stimulus to control the user
interfaces of the T3FRM. Each T3FRM variant includes scripts to compile
and run the demo testbench using a variety of simulators and models.
44
Altera Corporation
T3 Framer MegaCore Function (T3FRM) User Guide
GettingGetting Started
Using the Visual IP Software
The Visual IP software facilitates the use of Visual IP simulation models
with third-party simulation tools. To view a simulation model, you must
have the Visual IP software installed on your system. To download the
software, or for instructions on how to use the software, refer to the Altera
web site at http://www.altera.com, and search for Visual IP. For
examples of how to use the provided Visual IP model, refer to the sample
scripts included with the demo testbench.
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
1.
Create your custom design instantiating a T3FRM.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the T3FRM instantiation as a black box by either
setting attributes or ignoring the instantiation.
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II development tool for compilation and placeand-route
To use the Quartus II software to compile and place-and-route your
design, follow these steps:
Altera Corporation
1.
Select Compile mode (Processing menu).
2.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Disregard this step if you are using Quartus II version 1.1 or higher.
Otherwise, specify the user libraries for the project and the order in
which the Compiler searches the libraries.
45
2
Getting Started
Synthesis,
Compilation &
Place & Route
Getting Started
T3 Framer MegaCore Function (T3FRM) User Guide
4.
Specify the input settings for the project. Choose EDA Tool Settings
(Project menu). Select Custom EDIF in the Design entry/synthesis
tool list. Click Settings. In the EDA Tool Input Settings dialog box,
make sure that the relevant tool name or option is selected in the
Design Entry/Synthesis Tool list.
5.
Add your third-party EDA tool-generated netlist file to your project.
6.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
7.
Add the pre-synthesized and encrypted .e.vqm.v file from your
working directory, created by the MegaWizard Plug-In Manager.
8.
Constrain your design as needed.
9.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design.
Refer to Quartus II Help for further instructions on performing
compilation.
Licensing for
Configuration
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera semiconductor device. If you are
evaluating the T3FRM with the OpenCore feature, you must license the
function before you can generate programming files. To obtain licenses
contact your local Altera sales representative.
Performing
Post-Routing
Simulation
46
All current T3FRM variants use a single license, with ordering
code: PLSM-T3FRM.
After you have licensed the T3FRM, you can generate EDIF, VHDL,
Verilog HDL, and Standard Delay Output Files from the Quartus II
software and use them with your existing EDA tools to perform functional
modeling and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, refer to the
“Using the Quartus II development tool for compilation and placeand-route”section. The Quartus II software generates output and
programing files.
Altera Corporation
T3 Framer MegaCore Function (T3FRM) User Guide
4.
GettingGetting Started
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation.
2
Getting Started
Altera Corporation
47
Notes: