Reed-Solomon Compiler
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
Document Version:
Document Date:
3.3.3
3.3.3 rev 1
January 2003
Reed-Solomon Compiler MegaCore Function User Guide
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
UG-RSCOMPILER-3.6
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
Reed-Solomon (RS) Compiler comprising the RS encoder and RS decoder
MegaCore® functions.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the core features,
including new features in this release
Refer to the readme file for late-breaking information that is not
available in this user guide
Table 1. Revision History
Date
How to Find
Information
January 2003
No changes.
October 2002
Device support table added.
July 2002
DSP Builder support information added.
OpenCore® Plus hardware evaluation information added.
March 2002
Stratix™ family information added.
Many additions to various sections to clarify the information.
August 2001
Additions to performance tables.
April 2001
Version number change.
March 2001
Changes to performance tables. Product code changes.
February 2001
Revised screen shots. Parameter name changes.
December 2000
Changes to the performance tables.
■
■
■
■
Altera Corporation
Description
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
Reed-Solomon Compiler MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The Reed-Solomon Compiler User Guide uses the typographic conventions
shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Device Family Support ....................................................................................................................9
Introduction ....................................................................................................................................10
New in Version 3.3.3 ......................................................................................................................10
Features ...........................................................................................................................................10
General Description .......................................................................................................................11
DSP Builder Support .............................................................................................................13
OpenCore & OpenCore Plus Hardware Evaluation .........................................................14
Product Options .............................................................................................................................15
MegaWizard Plug-In .....................................................................................................................15
Getting Started ............................................................................................................................................17
Software Requirements .................................................................................................................17
Design Flow ....................................................................................................................................17
Download & Install the RS Compiler MegaCore Function .....................................................18
Obtaining the RS Compiler ...................................................................................................18
Install the MegaCore Files ....................................................................................................18
Directory Structure ................................................................................................................20
Set Up Licensing .............................................................................................................................21
Append the License to Your license.dat File ......................................................................21
Specify the Core’s License File in the Quartus II Software ..............................................22
Generate a Custom RS Function ..................................................................................................23
Create a New Quartus II Project ..........................................................................................23
Launch the MegaWizard Plug-In Manager .......................................................................24
Select the Parameters .............................................................................................................25
Simulate with Models ...................................................................................................................30
Setting Up Your System ........................................................................................................31
Using the VHDL Model ........................................................................................................33
Simulate using the Visual IP Model ....................................................................................34
Compile & Simulate in the Quartus II Software ........................................................................35
Synthesis, Compilation & Post-Routing Simulation .................................................................36
License for Configuration .............................................................................................................37
Perform Post-Routing Simulation ...............................................................................................37
Altera Corporation
7
Contents
Specifications ..............................................................................................................................................39
Functional Description ..................................................................................................................39
DSP Builder Feature & Simulation Support .......................................................................40
OpenCore Plus Time-Out Behavior ....................................................................................40
RS Encoder ..............................................................................................................................41
RS Decoder ..............................................................................................................................46
Shortened Codewords ...........................................................................................................52
Performance ....................................................................................................................................53
8
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the RS Compiler.
Table 4. RS Compiler Release Information
Item
Version
Release Date
Ordering Code (Product ID)
Vendor ID(s)
Device Family
Support
3.3.3
January 2003
IP-RSENC (0039 0041)
IP-RSDEC (0080 0041)
6AF7 and 6AF8 (Standard)
6AF9 and 6AFA (Time-Limited)
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
About this Core
Reed-Solomon Compiler MegaCore Function User Guide
Table 5 shows the level of support offered by the Reed-Solomon
MegaCore function to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Stratix GX
Cyclone
™
Stratix™
Full
Full
Full
Mercury™
Excalibur
Support
™
HardCopy™
®
Full
Full
Full
ACEX 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera® RS Compiler comprises two types of encoders and three types
of decoders.
New in Version
3.3.3
■
■
Fixed issue with DSP Builder integration
Fixed issue with example testbench files
Features
■
■
■
■
Has the DSP Builder Ready certification
Support for the DSP Builder software v2.1.0
Support for MATLAB version 6.5 and Simulink version 5.0
High-performance encoder/decoder for error detection and
correction
Fully parameterized RS function, including:
–
Number of bits per symbol
–
Number of symbols per codeword
–
Number of check symbols per codeword
–
Field polynomial
–
First root of generator polynomial
–
Space between roots in generator polynomial
Decoder features:
–
Discrete, streaming, or continuous architectures
–
Variable option (not with continuous)
–
Erasure-supporting option
Encoder features continuous and variable architectures
Support for shortened codewords
■
■
■
■
10
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
■
■
General
Description
Conforms to Consultative Committee for Space Data Systems (CCSDS)
Recommendations for Telemetry Channel Coding, May 1999
Easy-to-use MegaWizard Plug-In
–
Generates parameterized encoders or decoders
–
Generates example test vectors
Efficient RTL models for use in VHDL and Verilog HDL simulators
RS codes are widely used for error detection and correction. To use RS
codes, a data stream is first broken into a series of codewords. Each
codeword consists of several information symbols followed by several
check symbols (also known as parity symbols). Symbols can contain an
arbitrary number of bits. The Altera RS Compiler supports four to ten bits
per symbol. In an error correction system, the encoder adds check symbols
to the data stream prior to its transmission over a communications
channel. Once the data is received, the decoder checks for and corrects any
errors (see Figure 1).
Figure 1. RS Codeword Example
Codeword
Symbol
4 to 10 bits
per symbol.
0010
0110
1010
Information symbols, which
contain the original data.
0011
0111
1011
Check symbols, added by
the RS encoder before
transmission over a
communications channel.
RS codes are described as (N,K) where N is the total number of symbols
per codeword, K is the number of information symbols, and R is the
number of check (also known as redundant) symbols (N – K). Errors are
defined on a symbol basis (i.e., any number of bit errors within a symbol
is considered as only one error).
Altera Corporation
11
1
About this Core
■
About this Core
About this Core
Reed-Solomon Compiler MegaCore Function User Guide
The RS decoder always tries to detect and correct errors in the codeword.
However, as the number of errors increases the decoder gets to a stage
where it can no longer correct but only detect errors, at which point the
decoder asserts the decfail signal. As the number of errors increases
still further the results become unpredictable. Table 6 shows how the
decoder corrects and detects errors depending on R.
Table 6. Decoder Detection and Correction
Number of Errors
≤ R/2
≤ R,
≥ R/2
>R
Decoder Behavior
Decoder detects and corrects errors.
Decoder asserts decfail and can only detect errors.
Unpredictable results.
The erasure supporting option allows the RS decoder to correct up to R
symbol errors, if you give the location of the errors to the decoder.
RS codes are based on finite-field (i.e., Galois field) arithmetic. Any
arithmetic operation (i.e., addition, subtraction, multiplication, and
division) on a field element gives a result that is an element of the field.
The size of the Galois field is determined by the number of bits per
symbol; specifically, the field has 2m elements, where m is the number of
bits per symbol. A specific Galois field is defined by a polynomial, which
is user-defined for the RS Compiler. The MegaWizard® Plug-In only lets
the user select valid field polynomials.
The maximum number of symbols in a codeword is limited by the size of
the finite field to 2m – 1. For example, a code based on 10-bit symbols can
have up to 1,023 symbols per codeword. The RS Compiler supports
shortened codewords.
The variable option allows you to vary N and R, from their minimum
allowable values up to their selected values, when you are encoding or
decoding. This option is not available for the continuous decoder.
12
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
About this Core
DSP Builder Support
1
DSP Builder allows system developers, algorithm implementers, and
hardware engineers to share a common development platform. The DSP
Builder shortens DSP design cycles by helping you create the hardware
representation of a DSP design in an algorithm-friendly development
environment. You can combine existing MATLAB functions and Simulink
blocks with Altera DSP Builder blocks to link system-level design and
implementation with DSP algorithm development. The DSP Builder
consists of libraries of blocks as shown in Figure 2.
Altera Corporation
13
About this Core
DSP system design in Altera programmable logic devices requires both
high-level algorithms and HDL development tools. The Altera DSP
Builder, which you can purchase as a separate product, integrates the
algorithm development, simulation, and verification capabilities of The
MathWorks MATLAB and Simulink system-level design tools with
VHDL synthesis and simulation of Altera development tools.
About this Core
Reed-Solomon Compiler MegaCore Function User Guide
Figure 2. DSP Builder Blocks in Simulink Library Browser
DSP Builder version 2.0.0 and higher provides modular support for Altera
DSP cores, including the RS Compiler. The MATLAB software
automatically detects cores that support DSP Builder, and the cores
appear in the Simulink library browser.
f
For more information on using DSP Builder with the RS Compiler, see
“DSP Builder Feature & Simulation Support” on page 40.
OpenCore & OpenCore Plus Hardware Evaluation
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus® II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed before making a purchase decision. However, you cannot generate
device programming files.
14
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
About this Core
1
f
Product
Options
If you are simulating a time-limited MegaCore function using
the DSP Builder and Simulink, i.e., in software, the core
operation does not time out and the done pin stays low.
For more information on OpenCore Plus hardware evaluation using the
RS Compiler, see “OpenCore Plus Time-Out Behavior” on page 40 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
The RS Compiler comprises two types of encoders and three types of
decoders. In addition, you can select up to two optional features for each
decoder type. Table 7 shows the combinations that are currently available.
Table 7. Available Products & Options
Type of Function
Options
Variable
Erasure-Supporting
v
v
N/A
Streaming decoder
v
v
Continuous decoder
N/A
v
Standard encoder
Discrete decoder
v
MegaWizard
Plug-In
The RS Compiler has an interactive wizard-driven interface that allows
you to create custom encoders or decoders easily. You can launch the
MegaWizard Plug-In Manager from within the Quartus® II software, or
you can run it from the command line. The wizard allows you to input
your choice of parameters and generates a custom MegaCore function in
AHDL, VHDL, or Verilog HDL, which you can integrate into your system
design.. You can also select parameters that have been preset for either the
DVB or CCSDS standards.
Altera Corporation
15
1
About this Core
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that includes Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
Notes:
Getting Started
Software
Requirements
The instructions in this section require the following minimum hardware
and software:
1
Design Flow
This section assumes you are using a PC with the Windows
operating system. However, the core also works with UNIX
platforms. If you are using UNIX, you must install the Java
Runtime Environment version 1.3. Refer to the core’s readme file
for more information on UNIX support.
Once you have purchased a license for the RS Compiler, the design flow
involves the following steps:
1
Altera Corporation
2
Microsoft Windows 98 or higher operating system
Quartus® II, version 2.1 (or higher)
DSP Builder version 2.0.0 or higher (optional)
If you have not purchased a license, you can test-drive the core
for free using the OpenCore or OpenCore Plus feature. For more
information on the OpenCore Plus feature, refer to AN 176:
OpenCore Plus Hardware Evaluation of MegaCore Functions.
1.
Download and install the RS Compiler MegaCore function.
2.
Set up licensing. This step is not required if you are test-driving the
core using the OpenCore feature, however, you do need to obtain
and install an OpenCore Plus license to test-drive the core using this
feature.
3.
Generate a custom MegaCore function.
4.
Implement your system using AHDL, VHDL, or Verilog HDL.
5.
Compile your design.
6.
Simulate your design to confirm the operation of your system.
7.
License the RS Compiler MegaCore function and configure the
devices.
17
Getting Started
■
■
■
Getting Started
Download &
Install the RS
Compiler
MegaCore
Function
Reed-Solomon Compiler MegaCore Function User Guide
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining the RS Compiler
If you have Internet access, you can download MegaCore functions from
Altera’s web site at http://www.altera.com. Follow the instructions
below to obtain the RS Compiler via the Internet. If you do not have
Internet access, you can obtain the RS Compiler from your local Altera
representative.
1.
Point your web browser to http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Signal Processing (DSP) from the Technology drop-down
list box.
4.
Type RS Compiler in the Keyword Search box.
5.
Click Go.
6.
Click the link for the Altera RS Compiler in the search results table.
The product description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
the I Agree button at the bottom of the page.
9.
Follow the instructions on the RS Compiler download and
installation page to download the function and save it to your hard
disk.
Install the MegaCore Files
For Windows, follow the instructions below:
18
1.
Click Run (Start menu).
2.
Type <path name>\<filename>, where <path name> is the location of
the downloaded MegaCore function and <filename> is the filename
of the function. Click OK.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
GettingGetting Started
3.
The MegaCore Installer dialog box appears. Follow the online
instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the MegaCore function’s library folder
(\rs_compiler-<version>\lib) as a user library in the Quartus II
software. Search for “User Libraries” in Quartus II Help for
instructions on how to add a library.
2
Getting Started
Altera Corporation
19
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Directory Structure
Figure 3 shows the directory structure for the RS Compiler.
Figure 3. Directory Structure
MegaCore
rs-compiler-<version>
Contains the RS Compiler MegaCore function files and documentation.
doc
Contains the documentation for the core.
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
dspbuilder
Contains the files for DSP Builder functionality.
lib_time_limited
Contains encrypted lower-level design files for OpenCore Plus hardware evaluation.
After installing the MegaCore function, you should set a user library in the
Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
dspbuilder
Contains the files for DSP Builder functionality.
sim_lib
Contains the simulation models provided with the core.
modelsim
Contains the ModelSim simulation models.
vhdl
Contains the VHDL simulation models.
reeds
Contains the precompiled simulation library.
testbench
Contains the VHDL testbench.
visualip
Contains the Visual IP simulation models.
20
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Set Up
Licensing
GettingGetting Started
You can use the Altera OpenCore feature to compile and simulate the RS
Compiler MegaCore function, allowing you to evaluate it before
purchasing a license. You can simulate your RS Compiler design in the
Quartus II software using the OpenCore feature. However, you must
obtain a license from Altera before you can generate programming files or
EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in
third-party EDA tools.
1
If you want to use the OpenCore Plus feature, you must request
a license file from the licensing page of the Altera web site
(http://www.altera.com/licensing) to enable it. Your license file
is sent to you via e-mail; follow the instructions below to install
the license file.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the RS Compiler, you must
already have the Quartus II software installed on your PC with
licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Altera Corporation
Quartus II
MAX+PLUS II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the RS Compiler license file in a text editor. The file should
contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the RS Compiler license file and paste it
into the Quartus II license file.
21
2
Getting Started
After you purchase a license for RS Compiler, you can request a license file
from the Altera web site at http://www.altera.com/licensing and install
it on your PC. When you request a license file, Altera e-mails you a
license.dat file. If you do not have Internet access, contact your local
Altera representative.
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
1
5.
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
22
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
Do not include any spaces either around the semicolon or in
the path/filename.
1
Click OK to save your changes.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Generate a
Custom RS
Function
GettingGetting Started
This section describes the design flow using the RS Compiler and the
Quartus II development system. Altera provides a MegaWizard® Plug-In
with the RS Compiler. The MegaWizard Plug-In Manager, which you can
use within the Quartus II software, lets you create or modify design files
to meet the needs of your application. You can then instantiate the custom
megafunction in your design file.
Create a New Quartus II Project
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software if you prefer.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\rs-compiler-<version>\lib\ into the Library name
box, where <path> is the directory in which you installed the RS
Compiler. The default installation directory is c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
Altera Corporation
23
2
Getting Started
Before you begin creating a core, you must create a new Quartus II project.
With the New Project wizard, you specify the working directory for the
project, assign the project name, and designate the name of the top-level
design entity. You will also specify the RS Compiler user library. To create
a new project, perform the following steps:
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the RS Compiler. To launch the wizard,
perform the following steps:
1.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
2.
Specify that you want to create a new custom megafunction and
click Next.
3.
Select RS Compiler-<version> in the DSP > Error
Detection/Correction directory.
4.
Choose the output file type for your design; the wizard supports
AHDL, VHDL, and Verilog HDL.
5.
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 4 shows the wizard after you have made
these settings.
1
24
Refer to the Quartus II Help for more information on how to use
the MegaWizard Plug-In Manager.
<variation name> and <directory name> must be the same name
and the same directory that your Quartus II project use.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
GettingGetting Started
Figure 4. Select the Megafunction
2
Getting Started
Select the Parameters
To select your parameters, perform the following steps:
Altera Corporation
1.
Choose the device family.
2.
Select RS encoder or decoder.
3.
Select the erasure-supporting (decoder only) or variable options.
4.
For a decoder, you must select the implementation parameters:
whether the decoder is discrete, streaming, or continuous and
whether to use full or half keysize (see Figures 5 and 6). Click
Next.
25
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Figure 5. Select the Decoder
Figure 6. Select the Encoder
26
Altera Corporation
GettingGetting Started
Reed-Solomon Compiler MegaCore Function User Guide
Table 8 shows the implementation parameters.
Table 8. Implementation Parameters
Parameter
Range
Description
Encoder or a decoder.
Specifies an encoder or a decoder.
Available options
Erasure-supporting option, and/or
variable option.
Specifies the erasure-supporting option and/or
the variable option. Erasure-supporting
substantially increases the logic resources
used.
Architecture (1)
Discrete, streaming, or continuous.
Specifies a discrete, streaming, or continuous
decoder architecture.
Keysize (1), (2)
Half or full.
There is a trade-off between the amount of logic
and the number of cycles used to determine the
location and number of errors. Full creates a
function that uses more logic, but less clock
cycles to process the codeword. Half creates a
function that uses less logic, but requires more
cycles to process the codeword. When
N+R>10R the trade-off does not exist; half
creates a function that uses less logic with the
same throughput.
Note:
(1)
(2)
This parameter applies to the decoder only.
This parameter was called speed in earlier versions.
5.
Choose the parameters that define the specific RS codeword that you
wish to implement (see Figure 7). You can enter the parameters one
by one, click DVB Standard to use digital video broadcast (DVB)
standard values, or click CCSDS Standard to use the CCSDS
standard values. Click Next.
1
Altera Corporation
The MegaWizard Plug-In only allows you to select legal
combinations of parameters.
27
2
Getting Started
Type of Device
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Figure 7. Choose the Parameters
Table 9 shows the RS codeword parameters.
Table 9. RS Codeword Parameters
Parameter
Value
Discrete or
Streaming
Architecture
Continuous
(Full)
Architecture
Description
Continuous
(Half)
Architecture
Number of bits per symbol (m) 4 to 10
6 to 10
6 to 10
Specifies the number of bits
per symbol.
Number of symbols per
codeword (N)
check + 1
to 2m – 1
7(check + 1)
to 2m – 1
10check + 4
to 2m – 1
Specifies the total number of
symbols per codeword.
Number of check symbols
per codeword (check)
4 to N – 1
(1)
4 to N/7 – 1
(1)
4 to (N – 4)/10
(1)
Specifies the number of
check symbols per
codeword.
Field polynomial (irrpol)
First root of polynomial
generator (genstart)
Root spacing in generator
polynomial (rootspace)
Any valid polynomial (2)
Specifies the polynomial
defining the Galois field.
0 to (2m – 2)
Indicates the first root of the
generator polynomial.
Any valid root space (2)
Specifies the space between
roots in the generator
polynomial.
Notes:
(1)
(2)
28
Maximum value is 50.
The MegaWizard Plug-In only allows the selection of legal values.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
6.
GettingGetting Started
For a throughput calculation, enter the frequency in MHz, select the
desired units, and click Calculate (see Figure 8). Click Next.
Figure 8. Throughput Calculator
2
The MegaWizard Plug-In lists the product order codes for your
custom megafunction (see Figure 9), which you need to license the
core. Click Next.
Figure 9. Product Order Codes
8.
Altera Corporation
The final screen lists the design files that the wizard creates (see
Figure 10). Click Finish.
29
Getting Started
7.
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Figure 10. Design Files
When you finish going through the wizard, it generates a VHDL
component declaration file (.cmp), an AHDL include file (.inc), and the
following:
■
■
■
■
AHDL Design File (.tdf), VHDL Design File (.vhd), or Verilog Design
File (.v) depending on your selection, used to instantiate an instance
of the RS encoder/decoder in your design
Vector File (.vec) used for simulation within the Quartus II
environment
Symbol Files (.bsf) used to instantiate the RS encoder/decoder into a
schematic design
Hexadecimal (Intel-Format) File (.hex) with the contents of the ROM
blocks used in the function
Once you have created a custom megafunction, you can integrate it into
your system design and compile.
Simulate with
Models
Altera provides register transfer level (RTL) VHDL models that you can
use to simulate the functionality of the RS function in your system. The
VHDL models are supplied as pre-compiled libraries for the Model
Technology ModelSim simulation tool and support both encoding and
decoding functions. You can integrate these RTL models into your system,
speeding simulation. Altera also provides Visual IP models, which you
can use with the Visual IP software and are supported by other
simulators. Additionally, you can synthesize the MegaCore function in
the Quartus II software and then generate VHDL Output Files (.vho) or
Verilog Output Files (.vo) for simulation in third-party simulators (the
MegaCore function must be licensed to use this feature).
The following instructions describe how to set up your system and how to
simulate the VDHL models using the ModelSim simulation tool.
30
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
GettingGetting Started
Setting Up Your System
The pre-compiled VHDL model is provided with the RS Compiler, and is
installed in the directory sim_lib\ModelSim\vhdl\ReedS. Follow the
steps below to set up your system to use the model.
1.
Run the ModelSim simulation tool and create a logical map called
ReedS to the directory containing the compiled library by typing the
following command in the ModelSim simulation tool:
2
vmap ReedS <Drive:>/<RS MegaCore Path>
/sim_lib/ModelSim/vhdl/ReedS
2.
Altera Corporation
Altera provides sample testbenches and configuration files with the
models in the sim_lib\ModelSim\vhdl\testbench directory. You
should compile these files and save them into the ReedS library,
before simulating in the ModelSim simulation tool, by performing
the following steps:
a.
Choose Compile (Design menu).
b.
In the Compile HDL Source Files dialog box, click Default
Options (see Figure 11). The Compiler Options dialog box
appears (see Figure 12).
31
Getting Started
You can also use the ModelSim graphical user interface to create the
logical map. Refer to the ModelSim online help for details.
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
Figure 11. Compile HDL Source Files Dialog Box
Figure 12. Compiler Options
32
c.
In the Compiler Options dialog box, turn on the Use 1993
Language Syntax option in the VHDL tab. Click OK.
d.
In the Compile HDL Source Files dialog box, select ReedS in
the Library drop-down list.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
GettingGetting Started
e.
Select the file you wish to compile and click Compile. For
example, for an erasure-supporting discrete decoder, select and
compile Bench_eras_dsc.vhd, followed by Rs_eras_dsc_tb.vhd.
f.
Once compilation finishes, click Done.
Using the VHDL Model
To use the model, you must first instantiate it in your system. To
instantiate the VHDL model in your system, you can instantiate the
parameterized models by using the generic testbenches as templates.
Alternatively, you can instantiate the VHDL entity created by the
MegaWizard Plug-In, which acts as a wrapper to the parameterized
model.
2
■
■
■
■
■
■
■
■
■
■
Rs_eras_dsc_tb.vhd for the erasure-supporting discrete decoder
Rs_eras_str_tb.vhd for the erasure-supporting streaming decoder
Rs_eras_cont_tb.vhd for the erasure-supporting continuous decoder
Rs_std_cont_tb.vhd for the standard continuous decoder
Rs_std_dsc_tb.vhd for the standard discrete decoder
Rs_std_str_tb.vhd for the standard streaming decoder
Rs_var_dsc_tb.vhd for the variable discrete decoder
Rs_var_str_tb.vhd for the variable streaming decoder
Rs_vera_dsc_tb.vhd for the variable, erasure-supporting, discrete
decoder
Rs_vera_str_tb.vhd for the variable, erasure-supporting, streaming
decoder
All files include the encoder and a testbench with a generic stimulus and
a generic channel introducing some errors. These configurations must be
loaded specifying the parameter values (for non-default values). Six of the
parameters (n, check, m, irrpol, genstart and rootspace) can be
obtained from page 4 of the MegaWizard Plug-In. Refer to Figure 7 on
page 28 and Table 10 on page 39.
The keysize parameter can be set to full or half; the clock_period
parameter can be any valid time period (for example, 30 ns).
You can quickly load the configuration from the command line in the
ModelSim simulation tool. For example:
Altera Corporation
33
Getting Started
Altera provides generic testbenches and configurations to demonstrate
how to use the models. The configurations are included in the following
files, the VHDL configuration is defined with the prefix cfg_. The files
provided are:
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
vsim -Girrpol=37 -Ggenstart=1 -Grootspace=1 -Gm=5
-Gkeysize=\"full\" -Gn=31 -Gcheck=6
{-Gclock_period=30 ns} ReedS.cfg_rs_eras_dsc_tb
You can also use the ModelSim graphical user interface to load the
configuration. Refer to the ModelSim online help for details.
Simulate using the Visual IP Model
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
1.
Point your web browser at
http://www.altera.com/products/ip/altera/visual_ip.html.
2.
Follow the online instructions to download the software and save it
to your hard disk.
To use the Visual IP model, perform the following steps:
1.
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Ensure the appropriate ModelSim and Visual IP bin directories are in
the path, e.g.,:
c:\modeltech\win32pe;c:\progra~1\visualIP\bin;
3.
Set the VIP_MODELS_DIR environment variable to point to the
directory containing the Visual IP models, e.g.:
set VIP_MODELS_DIR =
C:\Megacore\rs_compiler-<version>\sim_lib\visualip\r
34
4.
Start the ModelSim simulation tool, select Change Directory (File
menu), and change the directory to your working directory for the
simulator.
5.
Create a new working library in this directory by selecting Create a
New Library (Design menu). Select a new library and a logical
mapping to it and type work in the Library field. Click OK.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
6.
GettingGetting Started
The ModelSim simulation tool creates a settings file, modelsim.ini,
in the working directory. Open this file in a text editor and search for
the string veriuser. You should find the following line:
; Veriuser = veriuser.sl
Remove the semi-colon (otherwise the line is treated as a comment
and ignored) and change the directory name to where you Visual IP
is installed, e.g.,:
2
Veriuser = c:\progra~1\visualIP\bin\libplimtivip
7.
Compile the wrapper for the model. The Verilog version of the
wrapper is found in the
$VIP_MODELS_DIR\<model_name>\interface\pli directory; the
corresponding VHDL version is in the $VIP_MODELS_DIR
\<model_name>\interface\mti directory. For example, to compile
the Verilog wrapper from the ModelSim command line, enter the
following command:
vlog
{$VIP_MODELS_DIR/<model_name>/interface/pli/<model_na
me>.v}
where <model_name> is your chosen model name.
The Visual IP model is now ready for use in your simulator.
Compile &
Simulate in the
Quartus II
Software
Altera Corporation
The following steps explain how to compile and simulate your design in
the Quartus II software.
1
For the best results, you should uncheck the Auto Carry Chains
option in the Option & Parameter Settings dialog box (Project
Menu). You should also check the Auto Packed Registers to
reduce the size by 10 to 15%. However, this setting may reduce
the speed (in some cases drastically), so uncheck the Auto
Packed Registers if speed is a premium.
1.
Click Start Compilation (Project Menu) to compile your design.
2.
Click Simulation Mode (Project Menu). Choose Simulator Settings
(Project Menu) and select the Time/Vectors tab. In the Source of
Vector Stimuli box, select the relevant vector file .vec .
35
Getting Started
Save the modelsim.ini file and return to the ModelSim simulation
tool.
Getting Started
Reed-Solomon Compiler MegaCore Function User Guide
3.
Synthesis,
Compilation &
Post-Routing
Simulation
Click Start Simulation (Project Menu) to begin simulation.
The Quartus II software work seamlessly with tools from all EDA
vendors, including Cadence, Exemplar Logic, Mentor Graphics,
Synopsys, Synplicity, and Viewlogic. After you have licensed the
MegaCore function, you can generate EDIF, VHDL, Verilog HDL, and
Standard Delay Output Files from the Quartus II software and use them
with your existing EDA tools to perform functional modeling and postroute simulation of your design.
The following sections describe the design flow to compile and simulate
your custom MegaCore design with a third-party EDA tool. To synthesize
your design in a third-party EDA tool and perform post-route simulation,
perform the following steps:
36
1.
Create your custom design instantiating a RS Compiler MegaCore
function.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the MegaCore instantiation as a black box by either
setting attributes or ignoring the instantiation.
3.
After compilation, generate a hierarchical netlist file in your thirdparty EDA tool.
4.
Open your netlist file in the Quartus II software.
5.
Select Compile mode (Processing Menu).
6.
Specify the compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
7.
Specify the user libraries for the project and the order in which the
compiler searches the libraries.
8.
Specify the input settings for the project. Choose EDA Tool Settings
(Project menu). Select Custom EDIF in the Design entry/synthesis
tool list. Click Settings. In the EDA Tool Input Settings dialog box,
make sure that the relevant tool name or option is selected in the
Design Entry/Synthesis Tool list.
9.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project Menu). Use the 1993 VHDL language option.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
GettingGetting Started
10. Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design, and generates output and
programming files.
11. Import your Quartus II-generated output files (.edo, .vho, .vo, or
.sdo) into your third-party EDA tool for post-route, device-level, and
system-level simulation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera PLD. If you are evaluating the RS Compiler
with the OpenCore feature, you must license the function before you can
generate programming files. To obtain licenses contact your local Altera
sales representative.
Perform PostRouting
Simulation
After you have licensed the core, you can generate EDIF, VHDL, Verilog
HDL, and Standard Delay Output Files from the Quartus II software and
use them with your existing EDA tools to perform functional modeling
and post-routing simulation of your design.
Altera Corporation
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, see “Compile &
Simulate in the Quartus II Software” on page 35. The Quartus II
software generates output and programing files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for
postroute, device-level, and system-level simulation.
37
2
Getting Started
License for
Configuration
Notes:
Specifications
Functional
Description
The RS Compiler’s parameters, which define the specific RS code for the
encoder or decoder, are described in detail in “Generate a Custom RS
Function” on page 23. You can only specify the parameters using the
MegaWizard Plug-In.
Table 10 shows the RS codeword parameters.
Table 10. RS Codeword Parameters
Parameter
Description
Specifies the number of bits per symbol.
N
Specifies the total number of symbols per codeword.
check
Specifies the number of check symbols per codeword.
irrpol
Specifies the polynomial defining the Galois field.
genstart
Indicates the first root of the generator polynomial.
rootspace
Specifies the space between roots in the generator polynomial.
3
Specifications
m
The generator polynomial of the code is represented by the following
equation:
check – 1 + i
g(x) =
∏ (x – αa.i)
0
i = i0
where:
i0 = genstart; a = rootspace; check is the number of check symbols,
and
α is a root of the polynomial.
Altera Corporation
39
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
DSP Builder Feature & Simulation Support
You can create Simulink Model Files (.mdl) using the RS Compiler and
DSP Builder blocks. DSP Builder supports the following RS Compiler
options:
■
■
■
Standard encoder architecture
Continuous decoder architecture
Erasure-supporting option for the continuous decoder architecture
DSP Builder does not support the following RS Compiler options:
■
■
■
Variable option for the encoder or decoder
Streaming decoder architecture
Discrete decoder architecture
1
The MegaWizard Plug-In allows you to select supported options
only.
After you create your model, you can perform simulation. DSP Builder
supports the simulation files shown in Table 11 for the RS Compiler.
Table 11. RS Compiler Simulation File Support in DSP Builder
Simulation Type
Simulation Flow
Precompiled ModelSim model
for RTL functional simulation
The DSP Builder SignalCompiler block generates a ModelSIm Tcl script and a
VHDL testbench on-the-fly.
VHDL Output File (.vho) models You can generate a .vho after you have purchased a license for your
for timing simulation
MegaCore function. Refer to the “VHDL Output File (.vho)” topic in Quartus II
Help for more information.
Visual IP Models
Not Supported
Quartus II simulation
The DSP Builder SignalCompiler block generates a Quartus II simulation
vector file on-the-fly.
For more information on DSP Builder, see “DSP Builder Support” on
page 13.
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
40
The rsout signal remains low
The timed_out signal is driven from low to high
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
A time-limited the RS Compiler runs for approximately 30 minutes for a
150-MHz clock (exactly 2.7 × 1011 clock cycles).
f
For more information on OpenCore Plus hardware evaluation, see
“OpenCore & OpenCore Plus Hardware Evaluation” on page 14 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
RS Encoder
Table 12 shows the RS encoder signals.
Table 12. Encoder Signals
Name
Type
Description
sysclk
Input
System clock.
reset
Input
Resets the encoder asynchronously. Active high.
start
Input
Indicates the first symbol in a new input codeword. The
start signal must be pulsed for one clock cycle Active
high.
Input
Active high, clock enable, which enables data into the
encoder and on the output data bus. When enable is
low the encoder’s operation is suspended.
rsin[]
Input
m-bit wide input data bus.
rsout[]
Output
m-bit wide output data bus.
numn[] (1)
Input
Variable value of N. Can be any value from the minimum
allowable value of N up to the selected value of N.
numcheck (1) Input
Specifications
enable
Variable number of check symbols. Can be any value
from the minimum allowable value of check up to the
selected value of check.
Note:
(1)
Altera Corporation
3
Used only when the variable option is selected.
41
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Table 13 shows the DSP Builder RS encoder signals.
Table 13. Encoder Signals—DSP Builder
Name
Type
Description
start
Input
Indicates the first symbol in a new input codeword. The
start signal must be pulsed for one clock cycle Active
high.
ena
Input
Active high, clock enable, which enables data into the
encoder and on the output data bus. When enable is
low the encoder’s operation is suspended.
rsin[]
Input
m-bit wide input data bus.
rsout[]
Output
m-bit wide output data bus.
Timing
The RS encoder is fully synchronous and operates on the rising edge of
sysclk. The function’s internal registers are cleared asynchronously by
setting reset high. To begin the encoding process, assert enable and
pulse start high for at least one clock cycle with the initial codeword’s
symbol at the rising edge of the sysclk. Data on rsin is sampled at the
rising edge of sysclk and made available immediately on rsout. The
remaining information symbols appear in subsequent cycles as long as
enable is asserted. The check symbols are output after all of the
information symbols. You must leave space for the check symbols before
you encode the next set of information symbols.
42
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Figure 13 shows the timing diagram for continuous encoding for 15
information symbols and 9 check symbols.
Figure 13. Continuous Encoding
sysclk
reset
enable
start
15
numn[4..1]
6
numcheck[3..1]
rsin[4..1]
0
rsout[4..1]
8 7
0
6
8 7
5 4
6
5 4
3
2
3
1
2
0
1
0
2 13 14 0 10 3
8 7
6
8 7
5 4
6
3
5 4
2
3
1
2
1
3
Altera Corporation
Specifications
First information symbol in codeword
43
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Figure 14 shows the use of the enable signal to temporarily halt operation
of the encoder.
Figure 14. Use of the Enable Signal
sysclk
reset
enable
start
15
numn[4..1]
6
numcheck[3..1]
rsin[4..1]
rsout[4..1]
0
8
0
7
8
6
7
5
6
4
5
3
4
First information symbol in codeword
44
2
3
1
2
0
1
0
2 13 14
0
10
3
0
Check symbols
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Variable Encoder
You can change the number of symbols in a codeword at run-time without
resetting the encoder. You must make the changes between complete
codewords; you cannot change numcheck during encoding.
Figure 15. Variable Encoding
sysclk
reset
enable
start
numn[4..1]
15
12
6
4
numcheck[3..1]
rsin[4..1]
0
0
6
8 7
5 4
6
5 4
3
2
3
1
2
0
1
0
2 13 14 0 10 3
7 6
5
7 6
4 3
5
2
4 3
1
2
3
0
1
0
Specifications
rsout[4..1]
8 7
First information symbol in codeword
Altera Corporation
45
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
RS Decoder
Table 14 shows the RS decoder signals.
Table 14. RS Decoder Signals
Name
Type
Description
sysclk
Input
System clock.
reset
Input
Decoder reset. The discrete decoder must be reset between each codeword.
rsin[]
Input
m-bit wide input data bus.
bypass
Input
When asserted, the decoder outputs the uncorrected input data instead of the
corrected data. All other operations are unaffected and the decoder’s latency
remains the same.
rsout[]
Output
m-bit wide output data bus.
decfail
Output
Asserted at the beginning of a data output when the decoder has detected errors
and cannot correct them.
numerr[]
Output
Number of symbol errors found. Displays up to the maximum number of
correctable errors.
dsin (1)
Input
Data input control. Data input only takes place in clock cycles when dsin is
asserted. In the discrete and streaming decoders, dsin must remain
de-asserted for at least one clock cycle after reset is de-asserted.
dsout (1)
Input
Data output control. Data can be output when dsout is asserted. If dsout is not
asserted, data is not output. There is a three-cycle latency between a change in
dsout and the time when the output starts and stops.
rdyin (1)
Output
Indicates the decoder is ready to accept a new codeword.
outvalid (1)
Output
Asserted when the decoder outputs a codeword.
sync (2)
Output
Asserted when the first symbol of a new codeword is required (not applicable for
the initial codeword).
ce (2)
Input
Chip enable. When de-asserted, the decoder’s operation is suspended.
numn[] (3)
Input
Variable value of N. Can be any value from the minimum allowable value of N up
to the selected value of N.
numcheck (3)
Input
Variable number of check symbols.Can be any value from the minimum
allowable value of check up to the selected value of check.
eras_ind (4)
Input
When asserted, the symbol in rsin[] is marked as an erasure.
Notes:
(1)
(2)
(3)
(4)
46
Discrete and streaming decoder only.
Continuous decoder only.
Used only when the variable option is selected.
Used only when the erasure-supporting option is selected.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Table 15 shows the DSP Builder RS decoder signals.
Table 15. RS Decoder Signals—DSP Builder
Name
Type
Description
rsin[]
Input
m-bit wide input data bus.
bypass
Input
When asserted, the decoder outputs the uncorrected input data instead of the
corrected data. All other operations are unaffected and the decoder’s latency
remains the same.
rsout[]
Output
m-bit wide output data bus.
decfail
Output
Asserted at the beginning of a data output when the decoder has detected errors
and cannot correct them.
numerr[]
Output
Number of symbol errors found. Displays up to the maximum number of
correctable errors.
sync
Output
Asserted when the first symbol of a new codeword is required (not applicable for
the initial codeword).
ena
Input
Chip enable. When de-asserted, the decoder’s operation is suspended.
eras_in (1)
Input
When asserted, the symbol in rsin[] is marked as an erasure.
3
(1)
Used only when the erasure-supporting option is selected.
The RS decoder MegaCore function can be specified with a discrete,
streaming or continuous architecture. The discrete architecture processes
one entire codeword before starting the next codeword. The streaming
architecture creates a pipelined decoder with a depth of three codewords,
but requires some clock cycles between each input codeword for
processing. The continuous decoder accepts a new codeword
immediately following the end of the previous codeword. Figure 16
illustrates the decoder architectures.
Figure 16. Decoder Architectures
Discrete
Decoding
1
Streaming
Decoding
3
1
4
5
1
Continuous
Decoding
Altera Corporation
2
3
4
2
5
1
6
6
2
3
7
3
4
5
6
47
Specifications
Notes:
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Discrete Decoder
A discrete decoder processes one codeword at a time and must be reset
between each codeword. The decoder receives the codeword’s first
symbol on the rising edge of sysclk after reset is de-asserted,
depending on the value of dsin (data is only input when dsin is high).
The dsin signal must remain de-asserted for at least one clock cycle after
reset is de-asserted. The rdyin signal is asserted during reset and
remains asserted until the decoder receives the last codeword symbol.
The outvalid signal is asserted when the decoder outputs valid data on
rsout[]. When dsout is asserted, the discrete decoder outputs one
symbol on each rising clock edge until all data is transferred. The
outvalid signal is de-asserted when all data is transferred. If the discrete
decoder detects more errors than it can correct, it asserts decfail and
presents the uncorrected data on rsout[].
Streaming Decoder
The streaming decoder has a pipeline depth of three codewords.
Therefore, the decoder must receive three codewords before it places the
first corrected codeword at rsout[]. The outvalid signal is not
asserted until the first valid codeword is available at rsout[]. When
outvalid is asserted, corrected symbols are presented at rsout[] on
every clock cycle, depending on the value of dsout. If the streaming
decoder detects more errors than it can correct, it asserts decfail and
presents the uncorrected codeword on rsout[].
The streaming decoder interface is similar to the discrete decoder, except
the streaming decoder is only reset once. If reset is asserted while
codewords are being decoded, the codewords are lost. The rdyin signal
indicates when the streaming decoder can accept a new codeword; once
rdyin goes high, the decoder expects a new symbol at each rising clock
edge, depending on the value of dsin (data is only input when dsin is
high). At startup, dsin must remain de-asserted for at least one clock
cycle after reset is de-asserted.
48
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Continuous Decoder
The continuous decoder, similar to the streaming decoder, also has a
pipeline depth of three codewords. Therefore, the decoder must receive
three codewords before it places the first corrected codeword at rsout[].
However, the continuous decoder does not have idle gaps between
codewords; the codewords enter and are placed at the output
continuously. When sync is asserted, a new codeword’s first symbol can
be accepted by the decoder (not applicable for the initial codeword). The
first output symbol follows sync four symbols later. The continuous
decoder is suspended by de-asserting ce. The decoder is reset by deasserting ce, and applying reset for at least one clock cycle. When ce is
re-asserted the first symbol can be accepted by the decoder.
If the continuous decoder detects more errors than it can correct, it asserts
decfail and presents the uncorrected codeword on rsout[].
1
There is no variable option available for the continuous decoder.
3
Timing Diagrams
Altera Corporation
49
Specifications
Figures 17 and 18 show timing diagrams for discrete and streaming
decoder operation. At least one clock cycle separation is required between
reset de-assertion and dsin assertion. Figures 19 and 20 show timing
diagrams for continuous decoder operation.
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Figure 17. Using dsin to Control Input of Data to Decoder
sysclk
reset
rdyin
dsin
rsin
22
19
21 20
18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 31 10
Figure 18. Using dsout to Control Output of Data from the Decoder
sysclk
dsout
rsout
17
0 22 21 20 19 18 17
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 31 10
outvalid
Figure 19. Continuous Decoder
sysclk
ce
reset
sync
rsin[6..1]
rsout[6..1]
numerr[4..1]
6
5
20 17 31 46 24 56 37 55
4
3
2
1
0
9
3
60 54 48 42 36 30 24 18 12 6
41 10 59 32 59 56 55 59
3
1
2
3
4
5
6
7
8
9
0
57 51
45
10 11 12 13 14
2
bypass
decfail
Input codeword's first symbol
Output codeword's first symbol
Note:
(1)
50
One codeword’s first input symbol is 9, the first output symbol of a previous codeword is the following 1.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Figure 20. Use of the Chip Enable Signal with the Continuous Decoder
sysclk
ce
reset
sync
rsin[6..1]
31 46 24 56 37 55
rsout[6..1]
1
9
3
60
41 10 59 32 59 56 55 59 1
numerr[4..1]
54
48 42 36 30 24 18 12
2
3
4
3
5
6
7
8
6
9
0 57 51 45 39
10 11 12 13 14 15
2
bypass
decfail
Input codeword's first symbol
3
Output codeword's first symbol
Specifications
Note:
(1)
One codeword’s first input symbol is 9, the first output symbol of a previous codeword is the following 1.
Decoding Time
The continuous decode requires a fixed length of time t to decode, where
t is the number of clock cycles.
For the discrete and streaming decoders the time to decode is variable and
depends on the number of errors in the codeword. This applies to
standard, erasure-supporting, and variable options.
Erasure-supporting Option
In normal operation the RS decoder detects and corrects symbol errors.
The number of symbol errors that can be corrected, C, depends on the
number of check symbols, R. and is given by C ≤ R/2
If the location of the symbol errors is marked as an erasure, the RS decoder
can correct twice as many errors, i.e., C ≤ R.
1
Altera Corporation
Erasures are symbol errors with a known location.
51
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
External circuitry identifies which symbols have errors and passes this
information to the decoder using the eras_ind signal. The eras_ind
input indicates an erasure (when the erasure-supporting decoder option
is selected).
The RS decoder can work with a mixture of erasures and errors.
A codeword is correctly decoded if (2e + E) ≤ R
where:
e = errors with unknown locations
E = erasures
R = number of check symbols.
For example, with ten check symbols the decoder can correct ten erasures,
or five symbol errors, or four erasures and three symbol errors.
Interleaving
Interleaving is a tool that matches the error correcting capabilities of a
code to the error characteristics of the channel. Interleaving is useful for
RS codes in a burst-noise environment. Interleaving uses the RS code’s
strength of correcting random errors by spreading the burst across many
codewords, which makes the errors look as if they were random and not
grouped in a burst.
f
For more details on interleaving, refer to the Altera Interleaver/DeInterleaver MegaCore Function User Guide and the reference design
provided with the RS Compiler.
Keysize
The keysize parameter allows you to trade-off the amount of logic
resources against the supported throughput. Full has twice as many
Galois field multipliers as half. A full decoder uses more logic and is
probably slightly slower in frequency, but supports a higher throughput.
If full and half give you the required throughput for your parameters,
always select half.
Shortened Codewords
A shortened codeword contains fewer symbols than the maximum value
of N, which is 2m –1. A shortened codeword is mathematically equivalent
to a maximum-length code with the extra data symbols at the start of the
codeword set to 0.
52
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
For example, (204,188) is a shortened codeword of (255,239). Both of these
codewords use the same number of check symbols, i.e., 16.
To use shortened codewords with the Altera RS encoder and decoder, you
use the MegaWizard Plug-In to set the codeword length to the correct
value, in the example, 204. If you want to process codewords of differing
lengths, use the variable encoder and/or decoder.
Performance
You can calculate the decoder performance using the formulae in
Table 16, which define the maximum number of clock cycles required to
process each codeword.
Table 16. Performance Calculations—Standard Decoder
Keysize
Discrete (1)
Streaming
Continuous
half
3N + 11check + 4 max [(N + check),(10check + 4)]
N
full
3N + 8check + 5
N
max [(N + check),(7check + 5)]
3
Note:
(1)
First symbol in to last symbol out.
Keysize
Discrete (1)
Streaming
half
3N + 11check + 6 max [(N + check),(10check + 6)] N
full
3N + 9check + 6
Continuous
max [(N + check),(8check + 6)] N
Note:
(1)
Altera Corporation
First symbol in to last symbol out.
53
Specifications
Table 17. Performance Calculations—Erasure-Supporting Decoder
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Tables 19 to 22 show the function’s performance and area utilization for
various devices using the Quartus II software version 2.0. The
performance in megabits per second is derived from the formulae in
Table 16 and maximum frequency at which the design can operate.
Table 18. Performance & Area Utilization for ACEX Devices—Standard Note (1)
Architecture
Keysize
m
N
check
LEs
ESBs
Performance
fMAX
(MHz)
Mbps (2) Mbps (3)
discrete
half
8
204
16
2,052
3
76
157
144
streaming
half
8
204
16
2,463
6
81
603
555
continuous
half
8
204
16
1,947
6
80
640
589
Note:
(1)
(2)
(3)
EP1K100QC208-1 device
Megabits per second, including check symbols.
Megabits per second, data only.
Table 19. Performance & Area Utilization for APEX II Devices—Standard Note (1)
Architecture
Keysize
m
N
check
LEs
ESBs
Performance
fMAX
(MHz)
Mbps (2) Mbps (3)
streaming
full
6
63
8
1,062
3
138
739
645
discrete
half
8
204
16
1,963
2
105
218
201
streaming
half
8
204
16
2,332
3
99
739
681
continuous
half
8
204
16
1,851
2
113
908
837
streaming
half
8
207
20
2,832
3
104
764
691
continuous
full
8
255
32
4,093
5
98
789
690
streaming (4)
half
8
255
32
5,167
3
102
642
562
Note:
(1)
(2)
(3)
(4)
54
EP2A15F672C7 device
Megabits per second, including check symbols.
Megabits per second, data only.
With variable option.
Altera Corporation
Reed-Solomon Compiler MegaCore Function User Guide
Specifications
Table 20. Performance & Area Utilization for Stratix Devices—Standard Note (1)
Architecture
Keysize
m
N
check
LEs
RAM
Blocks
Performance
fMAX
(MHz)
Mbps (4) Mbps (5)
streaming
full
6
63
8
973
6 (2)
173
921
804
discrete
half
8
204
16
1,731
3 (3)
137
283
261
streaming
half
8
204
16
2,213
6 (3)
133
987
910
continuous
half
8
204
16
1,617
6 (3)
138
1,110
1,023
streaming
half
8
207
20
2,666
6 (3)
137
1,003
906
continuous
full
8
255
32
3,548
6 (3)
125
1,000
875
streaming (6)
half
8
255
32
4,625
6 (3)
114
721
630
Note:
EP1S10F780C6 device
M512 blocks
M4K blocks.
Megabits per second, including check symbols.
Megabits per second, data only.
With variable option.
3
Specifications
(1)
(2)
(3)
(4)
(5)
(6)
Table 21. Performance & Area Utilization for APEX II Devices—Erasure-Supporting Note (1)
Architecture
Keysize
m
N
check
LEs
ESBs
Performance
fMAX
(MHz)
Mbps (2) Mbps (3)
streaming
half
8
204
16
4,595
3
106
787
725
continuous
half
8
204
16
3,629
5
109
875
807
streaming (4)
half
8
255
32
9,508
4
91
570
499
Note:
(1)
(2)
(3)
(4)
EP2A15F672C7 device
Megabits per second, including check symbols.
Megabits per second, data only.
With variable option.
Altera Corporation
55
Specifications
Reed-Solomon Compiler MegaCore Function User Guide
Table 22. Performance & Area Utilization for Stratix Devices—Erasure-Supporting Note (1)
Architecture
Keysize
m
N
check
LEs
RAM
Blocks
(2)
Performance
fMAX
(MHz)
Mbps (3) Mbps (4)
streaming
half
8
204
16
4,305
6
131
976
899
continuous
half
8
204
16
3,288
6
136
1,092
1006
streaming (5)
half
8
255
32
8,555
7
110
691
604
Note:
(1)
(2)
(3)
(4)
(5)
EP1S10F780C6 device
M4K blocks.
Megabits per second, including check symbols.
Megabits per second, data only.
With variable option.
Overall resource requirements vary widely depending on the parameter
values used. The number of logic elements required to implement the
function is linearly dependent on both the field size and the number of
check symbols. The number of ESBs/EABs used depends on whether the
decoder is discrete (3 ESBs/EABs up to 8 bits per symbol), streaming (6
ESBs/EABs up to 8 bits per symbol), or continuous (7 ESBs/EABs up to 8
bits per symbol). More ESBs/EABs are required for 9 or 10 bits per
symbol. Specifying the erasure-supporting and the variable option also
increases the number of ESBs/EABs required.
56
Altera Corporation