FFT
MegaCore Function
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
Document Version:
Document Date:
1.3.2
1.3.2 rev1
October 2002
FFT MegaCore Function User Guide
Copyright  2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
A-UG-FFT-1.3
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
FFT MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 10 for a complete list of the features, including
new features in this release
Refer to the FFT MegaCore function readme file for late-breaking
information that is not available in this user guide
Table 1. User Guide Revision History
Date
How to Find
Information
October 2002
Cyclone device information added.
July 2002
DSP Builder and OpenCore® Plus information added.
April 2002
Stratix™ support information added.
March 2001
JRE Runtime Environment information removed.
January 2001
MegaWizard screen shots updated.
January 2001
First release.
■
■
■
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Altera Corporation
Description
™
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
FFT MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
FFT MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The FFT MegaCore Function User Guide uses the typographic conventions
shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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v
Notes:
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 1.3.2 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
DSP Builder Support .............................................................................................................11
OpenCore & OpenCore Plus Hardware Evaluation .........................................................12
Getting Started ............................................................................................................................................15
Software Requirements .................................................................................................................15
Design Flow ....................................................................................................................................15
Download & Install the Function ................................................................................................15
Obtaining the FFT MegaCore Function ..............................................................................15
Installing the FFT Files ..........................................................................................................16
FFT Directory Structure ........................................................................................................16
Set Up Licensing .............................................................................................................................18
Append the License to Your license.dat File ......................................................................18
Specify the Core’s License File in the Quartus II Software ..............................................19
FFT Walkthrough ...........................................................................................................................20
Create a New Quartus II Project ..........................................................................................21
Launch the MegaWizard Plug-In Manager .......................................................................21
Generate a Custom FFT Core ...............................................................................................23
Using the Reference Designs ........................................................................................................26
Using the MATLAB Utilities ........................................................................................................27
FFTVECA Utility ....................................................................................................................27
FFTTBLA Utility .....................................................................................................................29
Using the Command Line Utilities ..............................................................................................29
FFTVECA Utility ....................................................................................................................29
FFTTBLA Utility .....................................................................................................................31
Simulate your Design ....................................................................................................................31
Synthesis, Compilation & Place & Route ...................................................................................31
Using Third-Party EDA Tools for Synthesis ......................................................................32
Using the Quartus II Development Tool for Compilation & Place & Route .................32
Altera Corporation
vii
Contents
Configure a Device ........................................................................................................................32
Perform Post-Routing Simulation ...............................................................................................33
Specifications ..............................................................................................................................................35
Functional Description ..................................................................................................................35
Block Floating Point Architecture ........................................................................................35
Precision ..................................................................................................................................37
External Memory ...................................................................................................................38
Using the FFT as an IFFT ......................................................................................................38
DSP Builder Feature & Simulation Support .......................................................................40
OpenCore Plus Time-Out Behavior ....................................................................................41
Signals ..............................................................................................................................................41
Timing Diagrams ...........................................................................................................................43
Reference Designs ..........................................................................................................................44
Reference Design A ................................................................................................................45
Reference Design B ................................................................................................................45
Reference Design C ................................................................................................................47
Reading the Results from the Reference Designs ..............................................................47
Performance ....................................................................................................................................49
Appendix A—Relating the Time Domain to the Frequency Domain ........................................53
Example 1 ........................................................................................................................................53
Example 2 ........................................................................................................................................54
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the FFT MegaCore
function.
Table 4. FFT Release Information
Item
Version
Device Family
Support
1.3.2
Release Date
October 2002
Ordering Code
IP-FFT
Product ID(s)
0034
Vendor ID(s)
6AF7 and 6AF8 (Standard)
6AF9 and 6AFA (Time-Limited)
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
■
■
■
Altera Corporation
Description
Full—The core meets all functional and timing requirements for the
device family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
9
About this Core
FFT MegaCore Function User Guide
Table 5 shows the level of support offered by the FFT MegaCore function
to each of the Altera device families.
Table 5. Device Family Support
Device Family
™
Support
Stratix GX
Full
Cyclone™
Full
™
Stratix
Full
Mercury™
™
Full
Excalibur
Full
HardCopy™
Full
®
ACEX 1K
Full
APEX™ II
Full
APEX 20KE & APEX 20KC
Full
APEX 20K
Full
FLEX
Full
Other device families
No support
Introduction
The Altera FFT MegaCore function is a parameterizeable core that
implements complex fast Fourier transforms (FFT) and inverse FFT (IFFT)
for high performance applications.
New in Version
1.3.2
■
■
■
Support for StratixGX devices
Support for Cyclone devices
Support for MATLAB version 6.5 and Simulink version 5.0
Features
■
■
■
■
■
Has the DSP Builder Ready certification
Support for the DSP Builder software v2.0.0
FFT and IFFT implementations
Radix 4 and mixed radix 4 and 2 implementations
Block floating-point techniques—maintain the maximum dynamic
range of the data during processing.
Interfaces to on-chip or off-chip memory
System clock frequency > 200 MHz
Easy-to-use MegaWizard Plug-In
MATLAB and command line simulation utilities
Three reference designs
Optimized to use the Stratix DSP blocks and the TriMatrix™ memory
architecture
Support for OpenCore and OpenCore Plus hardware evaluation
OpenCore feature allows designers to instantiate and simulate
designs in the Quartus II software prior to purchasing a license
■
■
■
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10
Altera Corporation
FFT MegaCore Function User Guide
The FFT MegaCore function implements a block floating point system for
maximum accuracy. The core uses an in-place mixed radix 4 and 2
decimation in frequency architecture, and implements any transform
length that is a power of 2. Partitioning between radix 4 and radix 2 passes
is implemented automatically by the core. When the desired FFT length is
not a power of 4, the processor automatically switches between radix 4
and radix 2 processing to achieve the required transform length.
The core can use a combination of on-chip (internal) or off-chip (external)
memories. When using off-chip memory, the core requires two banks of
data RAM to store the input data, output data, and intermediate
processing values. Three reference designs are provided as examples of
how to implement various types of memory interfaces, including memory
for data, intermediate storage, twiddle ROM, or any interfaces required to
load and unload data memory. The core takes advantage of the dual-port
memory in Cyclone, Stratix, APEX 20K, APEX II, ACEX 1K, and
FLEX 10KE devices, when internal memory is selected. Other devices can
be used (e.g., FLEX 10K, and FLEX 6000), but you must implement the
core’s memory requirements externally.
The core automatically generates all addresses for the data RAM and
twiddle ROM accesses.
The core reads data in normal sequence. After processing, the final result
is in digit-reversed format for a pure radix 4 FFT, or both digit- and
bit-reversed format for a mixed radix 4 and radix 2 FFT. The reference
designs include code to return data in normal order.
You can specify the core’s block floating point exponent width, the
transform length, the data width, and the twiddle width independently.
Altera Corporation
11
1
About this Core
General
Description
About this Core
About this Core
FFT MegaCore Function User Guide
DSP Builder Support
DSP system design in Altera programmable logic devices requires both
high-level algorithms and HDL development tools. The Altera DSP
Builder, which you can purchase as a separate product, integrates the
algorithm development, simulation, and verification capabilities of The
MathWorks MATLAB and Simulink system-level design tools with
VHDL synthesis and simulation of Altera development tools.
DSP Builder allows system developers, algorithm implementers, and
hardware engineers to share a common development platform. The DSP
Builder shortens DSP design cycles by helping you create the hardware
representation of a DSP design in an algorithm-friendly development
environment. You can combine existing MATLAB functions and Simulink
blocks with Altera DSP Builder blocks to link system-level design and
implementation with DSP algorithm development. The DSP Builder
consists of libraries of blocks as shown in Figure 1.
12
Altera Corporation
FFT MegaCore Function User Guide
About this Core
Figure 1. DSP Builder Blocks in Simulink Library Browser
1
About this Core
DSP Builder version 2.0.0 and higher provides modular support for Altera
DSP cores, including the FFT. The MATLAB software automatically
detects cores that support DSP Builder, and the cores appear in the
Simulink library browser.
f
For more information on using DSP Builder with the FFT, see “DSP
Builder Feature & Simulation Support” on page 40.
OpenCore & OpenCore Plus Hardware Evaluation
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus® II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed before making a purchase decision. However, you cannot generate
device programming files.
Altera Corporation
13
About this Core
FFT MegaCore Function User Guide
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that includes Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
1
f
14
If you are simulating a time-limited MegaCore function using
the DSP Builder and Simulink, i.e., in software, the core
operation does not time out and the done pin stays low.
For more information on OpenCore Plus hardware evaluation using the
FFT, see “OpenCore Plus Time-Out Behavior” on page 41 and AN 176:
OpenCore Plus Hardware Evaluation of MegaCore Functions.
Altera Corporation
Getting Started
Software
Requirements
This section requires the following software:
■
■
A PC running the Windows operating system
Quartus® II version 2.0 SP2 or higher
Design Flow
Download &
Install the
Function
This document assumes that you are using a PC with the
Windows operating system. However, you can also use the FFT
MegaCore function on UNIX platforms.
This walkthrough involves the following steps:
1.
Download and install the FFT MegaCore function.
2.
Generate a custom MegaCore function.
3.
Implement your system using AHDL, VHDL, or Verilog HDL.
4.
Compile your design.
5.
Use the reference designs.
6.
Use the MATLAB utilities.
7.
Use the command line utilities.
8.
Simulate your design to confirm the operation of your system.
9.
License the FFT MegaCore function and configure the devices.
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining the FFT MegaCore Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at http://www.altera.com. Follow the instructions
below to obtain the FFT via the Internet. If you do not have Internet access,
you can obtain the FFT from your local Altera representative.
Altera Corporation
15
Getting Started
1
2
Getting Started
FFT MegaCore Function User Guide
1.
Point your web browser to http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Signal Processing (DSP) from the Technology drop-down
list box.
4.
Type FFT in the Keyword Search box.
5.
Click Go.
6.
Click the link for the Altera FFT MegaCore function in the search
results table. The product description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
the I Agree button at the bottom of the page.
9.
Follow the instructions on the FFT download and installation page
to download the function and save it to your hard disk.
Installing the FFT Files
For Windows, perform the following steps:
1.
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The FFT Installation dialog box appears. Follow the online instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the directory in which you installed them
(e.g., <path>/fft-iff-<version>\lib) as a user library in the Quartus II
software. Search for “User Libraries” in Quartus II Help for
instructions on how to add these libraries.
FFT Directory Structure
Figure 2 shows the directory structure for the FFT.
16
Altera Corporation
GettingGetting Started
FFT MegaCore Function User Guide
Figure 2. FFT Directory Structure
megacore
fft-ifft-<version>
Contains the FFT MegaCore function files and documentation.
bin
Contains the command line utilities for the core.
doc
Contains the documentation for the core.
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
2
lib_time_limited
Contains encrypted lower-level design files for OpenCore Plus hardware evaluation.
After installing the MegaCore function, you should set a user library in the
Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
dspbuilder
Contains the files for DSP Builder functionality.
matlab
Contains the MATLAB utilities for the core.
reference_design
Contains the reference design source files.
Altera Corporation
17
Getting Started
dspbuilder
Contains the files for DSP Builder functionality.
Getting Started
Set Up
Licensing
FFT MegaCore Function User Guide
You can use Altera’s OpenCore feature to compile and simulate the FFT
MegaCore function, allowing you to evaluate it before purchasing a
license. You can simulate your design in the Quartus II software using the
OpenCore feature. However, you must obtain a license from Altera before
you can generate programming files or EDIF, VHDL, or Verilog HDL
gate-level netlist files for simulation in third-party EDA tools.
After you purchase a license for the FFT core, you can request a license file
from the Altera web site at http://www.altera.com/licensing and install
it on your PC. When you request a license file, Altera e-mails you a
license.dat file. If you do not have Internet access, contact your local
Altera representative.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the FFT core, you must already
have the Quartus II software installed on your PC with licensing
set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS® II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the FFT core license file in a text editor. The file should contain
one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the FFT core license file and paste it
into the Quartus II license file.
1
18
Do not delete any FEATURE lines from the Quartus II license
file.
Altera Corporation
GettingGetting Started
FFT MegaCore Function User Guide
5.
Save the Quartus II license file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or at a command prompt.
Specify the Core’s License File in the Quartus II Software
To specify the core’s license file, perform the following steps:
1
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Altera Corporation
2
Create a text file with the FEATURE line and save it to your hard disk.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
19
Getting Started
1.
Getting Started
FFT
Walkthrough
FFT MegaCore Function User Guide
This walkthrough explains how to create a custom core using the Altera
FFT MegaWizard Plug-In and the Quartus II software. As you go through
the wizard, each page is described in detail. When you are finished
generating a custom core, you can incorporate it into your overall project.
You can use Altera’s OpenCore evaluation feature to compile and
simulate the MegaCore functions, allowing you to evaluate the FFT before
deciding to purchase a license. However, you must purchase a license
before you can generate programming files or EDIF, VHDL, or
Verilog HDL gate-level netlist files for simulation in third-party EDA
tools.
This walkthrough consists of the following steps:
■
■
■
20
“Create a New Quartus II Project” on page 21
“Launch the MegaWizard Plug-In Manager” on page 21
“Generate a Custom FFT Core” on page 23
Altera Corporation
FFT MegaCore Function User Guide
GettingGetting Started
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the FFT user library. To create a new project, perform
the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction does not display if
you turned it off previously).
4.
Specify the working directory for your project. This walkthrough
uses the directory d:\temp\example
5.
Specify the name of the project. This walkthrough uses fft.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\fft-ifft-<version>\lib\ into the Library name
box, where <path> is the directory in which you installed the FFT.
The default installation directory is c:\megacore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the FFT. To launch the wizard, perform the
following steps:
Altera Corporation
21
Getting Started
2.
2
Getting Started
FFT MegaCore Function User Guide
1.
Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1
2.
Specify that you want to create a new custom megafunction and
click Next.
3.
Select FFT-ifft-<version> in the DSP > Transforms directory.
4.
Choose the output file type for your design; the wizard supports
AHDL, VHDL, and Verilog HDL.
5.
Specify a directory, <directory name> and name for the output file,
<variation name>. Figure 3 shows the wizard after you have made
these settings.
1
22
Refer to the Quartus II Help for more information on how to use
the MegaWizard Plug-In Manager.
<variation name> and <directory name> must be the same name
and the same directory that your Quartus II project uses.
Altera Corporation
GettingGetting Started
FFT MegaCore Function User Guide
Figure 3. Select the Megafunction
2
Getting Started
Generate a Custom FFT Core
To generate a custom core, perform the following steps:
1.
Select the parameter values that you require. For a description of the
parameters, see Table 5 on page 24.
1
Altera Corporation
The MegaWizard Plug-In only allows you to select legal
combinations of parameters, and warns you of any invalid
configurations.
2.
Select Internal Memory, External Memory, or Hybrid Memory.
3.
Select FFT or IFFT (see Figure 4).
23
Getting Started
FFT MegaCore Function User Guide
Table 5. Parameters
Parameter
Values
Description
FFT or IFFT
–
Device family
Stratix or other
When you select Stratix, the core uses the Stratix DSP block,
which reduces the logic usage and allows higher performance.
Data width (datawidth)
8 to 24 bits
The width of the input data and output data. It is also the precision
of the intermediate values during processing of the FFT.
Twiddle width
(twiddlewidth)
8 to 24 bits
The precision of the twiddle factors.
Float width (floatwidth) 3 to 8
Points (points)
Internal memory, external
memory, or hybrid memory
Select an FFT or an IFFT core.
The block floating point. When floatwidth = 3, the core uses
fixed point architecture; for floatwidth ≥ 4, the core uses block
floating point architecture.
24 to 220
–
The transform length.
When you select internal memory the core is set up to use internal
memory for the data RAM banks and the twiddle ROM.
When you select external memory, the core is set up to use
external memory for the data RAM banks and the twiddle ROM.
The external memory setting inserts additional pipelining stages
on its interfaces, which can be placed in the I/O cells of the device,
allowing higher device performance.
Hybrid memory allows you to connect to external dual-port data
RAM and internal twiddle ROM.
Version 1.1 or earlier
compatible timing
24
Yes or no
Select the core timing to be compatible with version 1.1 or earlier
of the core. The core gives better fMAX performance with the latest
compatible timing.
Altera Corporation
FFT MegaCore Function User Guide
GettingGetting Started
Figure 4. Selecting the Parameters
2
Getting Started
4.
The MegaWizard Plug-In calculates the number of clock cycles to
perform a transform, based on your selections. Click Next.
5.
The final screen lists the main design files that the wizard creates
(see Figure 5). Click Finish.
Figure 5. Summary of Files Generated
Altera Corporation
25
Getting Started
FFT MegaCore Function User Guide
The wizard generates the following files:
■
■
■
■
■
One of the following files (depending on your selection), which you
use to instantiate an instance of the function in your design:
–
An AHDL Text Design File (<variation name>.tdf)
–
A VHDL Design File (<variation name>.vhd)
–
Verilog Design File (<variation name>.v)
A symbol file (.bsf), which you use to instantiate the function into a
schematic design
Two memory initialization files (.hex), which contain the twiddle
ROM values
Two files <variation name>_inst and <variation name>_bb
A reference design file (<variation name>aukfft_fftchipa.tdf,
<variation name>aukfft_fftchipb.tdf, or <variation
name>aukfft_fftchipc.tdf), depending on your selection.
When you have created your custom megafunction, you should connect it
to memory and provide an interface for reading and writing data. The
reference designs show you how to achieve this, for memories that are
either internal or external.
Using the
Reference
Designs
The MegaWizard Plug-In generates one of the following three reference
designs:
■
■
■
Reference design A (<variation name>aukfft_fftchipa.tdf), which
shows you how to connect to internal dual-ported RAM and internal
twiddle ROM
Reference design B (<variation name>aukfft_fftchipb.tdf), which
shows you how to connect to external data RAM and external twiddle
ROM.
Reference design C (<variation name>aukfft_fftchipc.tdf), which
shows you how to connect to a combination of external dual-ported
RAM and internal twiddle ROM
You can use the reference designs to simulate the functionality of the core
in your system. The reference designs:
■
■
■
■
■
■
■
f
26
Are generated as AHDL source code
Are synthesizable
Form a basis for your design.
Determine the final destination data bank at compile time
Attach the reference design’s read interface automatically
Contain logic to correct bit reversal
Work with all HDL instances of the core
For more information on the reference designs, see “Reference Designs”
on page 44.
Altera Corporation
GettingGetting Started
FFT MegaCore Function User Guide
Using the
MATLAB
Utilities
f
Altera provides two MATLAB utilities to test the FFT MegaCore function.
These utilities (FFTVECA.m and FFTTBLA.m) work with reference
design A.
For more information on MATLAB, refer to the Math Works website at
http://www.mathworks.com.
Before you use the MATLAB utilities, you must generate twiddle ROM
data for the reference design, by generating a custom core (see “Generate
a Custom FFT Core” on page 23).
Getting Started
1
Altera recommends you create a working directory <project>
into which you copy the reference design A from the
reference_design directory (aukfft_fftchipa.tdf,
example_ffta.bsf,
example_ffta.cmp,
example_ffta.inc,
example_ffta.tdf,
example_ffta_twidsin.hex,
example_ffta_twidcos.hex,
aukfft_twidrom.tdf, and
aukfft_ram_dp.tdf).
You are now ready to use the MATLAB utilities.
FFTVECA Utility
FFTVECA.m creates a vector simulation file (.vec) from a MATLAB input
vector. To create the .vec file perform the following steps:
1.
Altera Corporation
2
Open the MATLAB software. At the command prompt change the
directory to \FFT-iff-<version>\matlab.
27
Getting Started
FFT MegaCore Function User Guide
2.
Create an input vector <vec> in MATLAB, with completely random
data, by typing the following command:
>> maxvalue = (2^datawidth) - 1;r
>> rr = rand(1,points);r % create a random vector
>> rr = rr - .5;r% make positive and negative
% vector components
>> ss = rand(1,points);r
>> ss = ss - .5;r
>> vec = floor (rr*maxvalue + i*ss*maxvalue);r
% vector has real and imaginary components,
% scale to maximum value.
where points and datawidth are the default values of reference
design A (points = 512, datawidth = 8, floatwidth = 5).
3.
Call the utility, which creates a file aukfft_fftchipa.vec in the matlab
directory, by typing the parameters and values as shown:
FFTVECA (<vec>, points, datawidth, floatwidth)r
e.g.
FFTVECA (vec, 512, 8, 5)r
28
4.
Open the Quartus II software and set up a new project with the copy
of reference design A as the design.
5.
Click Start Compilation (Processing Menu) to compile your design.
6.
Click Simulation Mode (Processing menu). Choose Simulator
Settings (Processing menu) and select the Time/Vectors tab. In the
Source of Vector Stimuli box, select aukfft_fftchipa.vec. Click OK.
7.
Click Run Simulation (Processing menu) to begin simulation.
8.
Close the Report window. Click Open (File menu). In the Files of
Type box select waveform vector files, and open
aukfft_fftchipa-sim.vwf (this is in the <project>\db directory).
Change all signals to hexadecimal and save this file as a vector table
output file, aukfft_fftchipa.tbl, in the matlab directory.
Altera Corporation
GettingGetting Started
FFT MegaCore Function User Guide
FFTTBLA Utility
The FFTTBLA utility is used to extract the result of the FFT into a
MATLAB vector. Call the FFTTBLA.m utility as shown:
Y = FFTTBLA (points, datawidth); r
You can now use MATLAB to analyze the results. For example, type in the
following command:
2
plot(abs(y)))
Using the
Command Line
Utilities
For a direct comparison with the MATLAB floating point FFT,
scale the data by the exponent, see “Block Floating Point
Architecture” on page 35.
If you do not have MATLAB, Altera provides command line utilities (for
Windows only) (fftveca.exe and fftbla.exe) that work with reference
design A. The command line utilities have the same functionality as the
MATLAB utilities of the same name, and you can use them to generate
waveforms for test cases.
Reference design A has the following default parameters, which you can
change and are defined as constants at the start of the file:
points = 512,
datawidth = 8,
floatwidth = 5,
twiddlewidth = 8,
backward_compatible = 0,
stratix = 1,
rom_in_4k_mem_blocks = 1
1
Altera recommends you create a working directory <project>
into which copy the reference design A from the
reference_design directory.
You are now ready to use the command line utilities.
FFTVECA Utility
FFTVECA.exe creates a vector simulation file (.vec). To create the .vec file
perform the following steps:
1.
Altera Corporation
Open a command prompt window. Change the directory to
\FFT-iff-<version>\bin.
29
Getting Started
1
Getting Started
FFT MegaCore Function User Guide
2.
Call the utility, which creates a file aukfft_fftchipa.vec in the bin
directory, by typing the parameters and values as shown:
fftveca points datawidth floatwidth waveform
amplitude frequency phase
The first three parameters are the same as the core parameters and
waveform = cosine, cisoid, rand, or impulse
amplitude is given by 0 < amplitude < 2 (datawidth – 1), as a float
frequency is given by – points/2 ≤ frequency ≤ points/2, as a float
phase can be – 0.5 ≤ phase ≤ 0.5, as a float
Cosine is generated from
round (amplitude × cos(2π(n × frequency/points + phase))),
where n = 0,..., points – 1.
Cisoid is generated from
round (amplitude × cos(2π(n × frequency/points + phase))
+ √(–1) × sin(2π(n × frequency/points + phase))),
where n = 0,..., points – 1.
Impulse is generated from
amplitude × (cos(2π × phase) + √(–1) × sin(2π × phase)) in array location
zero. All other locations are set to zero.
Rand is generated from
amplitude × uniform(n),
where n = 0,..., points – 1, and uniform(n) is a uniform random number
in the range {–1,..., +1}
30
3.
Open the Quartus II software and set-up a new project with the copy
of reference design A as the design.
4.
Click Start Compilation (Processing Menu) to compile your design.
5.
Click Simulation Mode (Processing menu). Choose Simulator
Settings (Processing menu) and select the Time/Vectors tab. In the
Source of Vector Stimuli box, select aukfft_fftchipa.vec. Click OK.
Altera Corporation
FFT MegaCore Function User Guide
GettingGetting Started
6.
Click Run Simulation (Processing menu) to begin simulation.
7.
Close the Report window. Click Open (File menu). In the Files of
Type box select waveform vector files, and open
aukfft_fftchipa-sim.vwf (this is in the <project>\db directory).
Change all signals to hexadecimal and save this file as a vector table
output file, aukfft_fftchipa.tbl, in the bin directory.
FFTTBLA Utility
FFTTBLA (points, datawidth); r
The file aukfft_fftout.txt contains the real and imaginary outputs of the
FFT in the following format:
real[0] imag[0]
real[1] imag[1]
..
real[points – 1] imag[points – 1]
The exponent is not extracted. This file can be read by the application of
your choice for further analysis or visualization, e.g., Microsoft Excel to
compute and chart the magnitude and phase.
Simulate your
Design
Synthesis,
Compilation &
Place & Route
Altera Corporation
The following steps explain how to simulate your design in the Quartus II
software.
1.
Click Start Compilation (Processing Menu) to compile your design.
2.
Click Simulation Mode (Processing menu). Choose Simulator
Settings (Processing menu) and select the Time/Vectors tab. In the
Source of Vector Stimuli box, select <variation name>.vec, where
<variation name> is the name you specified in the MegaWizard PlugIn.
3.
Click Run Simulation (Processing menu) to begin simulation.
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus II development tool, or by a third-party
synthesis tool. The Quartus II software works seamlessly with tools from
many EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic.
31
2
Getting Started
The FFTTBLA utility is used to extract the FFT results from the file
aukfft_fftchipa.tbl into the file aukfft_fftout.txt. Call the FFTTBLA.exe
utility as shown:
Getting Started
FFT MegaCore Function User Guide
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, perform the
following steps:
1.
Create your custom design instantiating a FFT MegaCore function.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the FFT MegaCore function instantiation as a black
box by either setting attributes or ignoring the instantiation.
3.
After compilation, generate a netlist file in your third-party EDA
tool.
Using the Quartus II Development Tool for Compilation & Place &
Route
To use the Quartus II software to compile and place-and-route your
design, perform the following steps:
1.
Select Compile mode (Processing menu).
2.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Specify the input settings for the project (not necessary for AHDL
cores). Choose EDA Tool Settings (Project menu). Select Custom
EDIF in the Design entry/synthesis tool list. Click Settings. In the
EDA Tool Input Settings dialog box, make sure that the relevant
tool name or option is selected in the Design Entry/Synthesis Tool
list.
4.
Add your third-party EDA tool-generated netlist file to your project.
5.
Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
6.
Compile your design. The Quartus II compiler synthesizes and
performs place-and-route on your design.
1
Configure a
Device
32
Refer to Quartus II Help for further instructions on performing
compilation.
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must license the function before
you can generate configuration files.
Altera Corporation
FFT MegaCore Function User Guide
Perform
Post-Routing
Simulation
After you have licensed the core, you can generate EDIF, VHDL, Verilog
HDL, and Standard Delay Output Files from the Quartus II software and
use them with your existing EDA tools to perform functional modeling
and post-routing simulation of your design.
1.
Open your existing Quartus II project.
2.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu).
3.
Compile your design with the Quartus II software, see “Synthesis,
Compilation & Place & Route” on page 31. The Quartus II software
generates output and programing files.
4.
You can now import your Quartus II software-generated output files
(.edo, .vho, .vo, or .sdo) into your third-party EDA tool for
post-route, device-level, and system-level simulation.
33
2
Getting Started
Altera Corporation
GettingGetting Started
Notes:
Specifications
Functional
Description
The FFT MegaCore function’s parameters, which define your custom FFT
function, are described in “FFT Walkthrough” on page 20. You can only
specify the parameters using the MegaWizard Plug-In.
The core computes the forward transform as given in equation 1, and
inverse transforms as given in equation 2.
points – 1
F(k) =
Σf(n)e–j2πnk/points
(1)
n=0
3
where k = 0, ..., points – 1
Specifications
points – 1
f(n) = (1/points)
ΣF(k)ej2πnk/points
(2)
k=0
where n = 0, ..., points – 1
Block Floating Point Architecture
The FFT MegaCore function uses a block floating point architecture (see
Figure 6), which is a combination of fixed and floating point architectures
that maintains precision and speed. With block floating point all of the
values have an independent mantissa, but share a common exponent in
each data block.
Altera Corporation
35
Specifications
FFT MegaCore Function User Guide
Figure 6. Block Floating Point Architecture
Mantissa
Exponent
Points
Data Width
Float Width
With a fixed point architecture the data width needs to be sufficient to
represent all values. In an FFT with word growth this makes either the
data width excessive or leads to a loss of precision. With a floating point
architecture each number is represented as a mantissa with an individual
exponent. This leads to improved precision, but floating point operations
are slow and demand lots of logic.
The FFT core’s block floating point architecture represents each number
with an independent mantissa, but shares a common exponent in each
data block. Inputs to the core are as fixed point numbers (i.e. the exponent
is effectively 0, you do not enter an exponent).
The block floating point architecture makes full use of the data width
through the core. After every pass the data width may grow by up to 3
bits. The block floating point architecture shifts the new result back to data
width after each pass, keeping the most significant bits (MSBs) but losing
the LSBs. The number of shifts is added to the exponent, i.e., to
compensate for word growth the core divides the mantissa and
increments the exponent. In effect, the block floating point acts as a digital
automatic gain control. If you select more than the minimum float width,
the precision of the FFT increases, particularly if the input signal is not
using the full dynamic range. However noise can also increase.
The FFT core’s output is block floating point. The scaling accumulates
every pass over the full transform and is output as the exponent. The
mantissa is stored in the memory; the exponent is output by the
exponent signal. The exponent is signed and an additional bit is added
to allow for the signed bit. You must scale the FFT output by the final
exponent. The scaling factor is given by 2(–exponent).
36
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Precision
The data width, twiddle width, and float width determine the FFT’s
resolution.
Data Width
The data width determines the width of the data that is stored between
passes and counts towards the data width through the core. Increasing the
data width increases the precision. When you increase the precision, any
additional bits should be made the least significant bits (LSBs) and tied to
0.
Twiddle Width
The twiddle factors are sampled sine and cosine waves, which the core
uses as multiplicands. There is no value in having a twiddle width value
that exceeds the data width value, because the extra precision does not
produce greater accuracy from the transform. The greatest precision is
achieved when twiddle width = data width.
On each pass of a radix 4 FFT, the word length increases by up to 3 bits.
The float width must be sufficient to represent the largest possible data
growth, i.e., 3 bits × number of passes.
For example, for a 64-point FFT:
number of passes = ceiling(log4 points) = 3 passes
data growth = number of passes × number of bits growth per pass
= 3 × (up to 3 bits per pass)
= 9 bits potential growth.
The recommended float width = ceiling(log2 data growth)
= ceiling(log2 9)
= 4.
The minimum float width value is 3 for up to 1024 points, and 4 for 2048
points or more.
1
Altera Corporation
For float width = 3, the FFT core has a fixed point architecture.
37
Specifications
Float Width
3
Specifications
FFT MegaCore Function User Guide
External Memory
When using external memory, the bank that the result ends up in depends
upon the number of points.
If ceiling (log4points) is odd the result always starts on the right memory
and ends up on the left memory.
If ceiling (log4points) is even, the result starts on the right memory and
ends on the right memory (so the next transform must start on the left),
and vice versa.
The direction signal indicates what is happening to the data.
Using the FFT as an IFFT
The MegaWizard Plug-In allows you to select either an FFT or IFFT core.
In many systems, it is advantageous to perform the FFT and the IFFT in
the same core, to reduce the logic. You can use the FFT to produce an IFFT
by loading the real memory with imaginary data and vice versa.
You must adjust the results for the IFFT by dividing the result by the
number of points. You can do this by adding the number of passes to the
exponent.
The float width must be increased for an IFFT, to accomodate the division
by points (in the IFFT the normalization is performed in the exponent,
which avoids loss of numerical precision in the fixed point output).
Figure 7 shows how to use an FFT for IFFT.
38
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Figure 7. Using an FFT for IFFT
FFT
Real
Memory
realdatain
realdataout
FFT Core
Imaginary
Memory
imagdatain
imagdataout
exponent
IFFT
Real
Memory
realdataout
realdatain
3
FFT Core
imagdatain
imagdataout
Specifications
Imaginary
Memory
exponent
number of passes
Altera Corporation
39
Specifications
FFT MegaCore Function User Guide
DSP Builder Feature & Simulation Support
You can create Simulink Model Files (.mdl) using the FFT and DSP
Builder blocks. DSP Builder supports the following FFT options:
■
■
Internal memory
FFT and IFFT cores
DSP Builder does not support the following FFT options:
■
■
External memory
Hybrid memory
1
The MegaWizard Plug-In allows you to select supported options
only.
After you create your model, you can perform simulation. DSP Builder
supports the simulation files shown in Table 6 for the FFT.
Table 6. FFT Simulation File Support in DSP Builder
Simulation Type
Simulation Flow
Precompiled ModelSim model
for RTL functional simulation
Not supported.
VHDL Output File (.vho) models You can generate a .vho after you have purchased a license for your
for timing simulation
MegaCore function. Refer to the “VHDL Output File (.vho)“ topic in Quartus II
Help for more information.
Visual IP Models
Not supported
Quartus II simulation
The DSP Builder SignalCompiler block generates a Quartus II simulation
vector file on-the-fly.
A DSP Builder FFT core differs from a non-DSP Builder core in the
following ways:
■
■
f
40
A DSP Builder FFT core handles all addressing, therefore you only
have to provide either a write signal or a read signal. The FFT core
outputs data two clock cycles after a read signal
A DSP Builder FFT core has three additional signals ip_ready,
op_ready, and op_valid (see Tables 7 and 8)
For more information on DSP Builder, see “DSP Builder Support” on
page 12.
Altera Corporation
FFT MegaCore Function User Guide
Specifications
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
The timed_out signal is driven from low to high
realdataout and imagdataout set to zero
A time-limited the FFT runs for approximately 30 minutes for a 150 MHz
clock (exactly 2.7 × 1011 clock cycles).
f
Signals
For more information on OpenCore Plus hardware evaluation, see
“OpenCore & OpenCore Plus Hardware Evaluation” on page 13 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
Table 7 shows the FFT core input signals. Table 8 shows the FFT core
output signals.
Table 7. Input Signals
3
Description
sysclk
The system clock. All memory accesses and core processing are at the
system clock rate.
reset
reset is an asynchronous, active-high signal and must be asserted
before the first FFT operation.
go
When high, go starts the FFT processing a new block of data. go must
be kept high until done goes high, otherwise the current FFT operation
is aborted and must be reset before the following transform.
realdatain[datawidth..1]
imagdatain[datawidth..1]
These buses are for the real and imaginary components of the data
and intermediate values stored in the memory bank.
realtwid[twiddlewidth..1]
imagtwid[twiddlewidth..1]
These buses are for the real and imaginary components of the twiddle
factors.
Altera Corporation
41
Specifications
Signal Name
Specifications
FFT MegaCore Function User Guide
Table 8. Output Signals
Signal Name
Description
realdataout[datawidth..1]
imagdataout[datawidth..1]
These buses are the real and imaginary components of the butterfly
results that are written to the data memory.
readaddress[addresswidth..1]
readaddress[] contains the read address for the data memory.
writeaddress[addresswidth..1] writeaddress[] contains the write address for the data memory.
twidaddress[addresswidth..1]
twidaddress[] contains the read address for the twiddle memories.
exponent[(floatwidth+1)..1]
exponent[] gives the final scaling factor of the FFT data in twos
complement form.
done
When high, the core has completed processing the last FFT. You can
now read out of the data memory.
writeenable
The writeenable signal is for designs where data is stored in dualported memory. The writeenable signal is high when the FFT core
has valid outputs. writeenable can be connected to the write enable
of the memory. Reference design A shows writeenable in use.
direction
The direction signal is for designs where two physical memories are
implemented. In this case, the left bank is enabled when direction
is high, and the right bank is enabled when direction is low. The
core does not stop at anytime during processing, so the direction
signal is the only write enable control for the left and right memory
banks, until done is asserted when you must stop writing to the
memories. Reference design B shows direction in use.
Table 9 shows the DSP Builder FFT core input signals. Table 10 shows the
DSP Builder FFT core output signals.
Table 9. Input Signals—DSP Builder FFT Core
Signal Name
Description
realin[datawidth..1]
imagin[datawidth..1]
These buses are for the real and imaginary components of the data
and intermediate values stored in the memory bank.
read
When the read signal is high and op_rdy is high, the FFT core
outputs data two clock cycles later.
write
When the write signal is high and ip_rdy is high, the FFT core
accepts data on realin and imagin inputs.
42
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Table 10. Output Signals—DSP Builder FFT Core
Signal Name
Description
realout[datawidth..1]
imagout[datawidth..1]
These buses are the real and imaginary components of the transform
results that are output.
exp[(floatwidth+1)..1]
exp[] gives the final scaling factor of the FFT data in twos
complement form.
ip_rdy
When high, ip_rdy indicates that the FFT requires more data.
op_rdy
When high, the core has completed processing the last FFT. You can
now read out of the data memory. The op_rdy signal remains high
until all data is read.
valid
When high, valid indicates that the output data is valid.
Timing
Diagrams
Figure 8 shows the FFT MegaCore function signals. The resolution of the
diagram is such that the inclusion of sysclk is not practical. This is also
true of the address and data buses where activity is shown rather than
explicit edges. For reference design B, it is assumed that the incoming data
has been written to the left memory bank.
You must write the real and imaginary values to the reference designs
simultaneously.
Figure 8. FFT Core Signals
reset
go
done
writeenable
readaddress
writeaddress
realdatain, imagdatain
realdataout, imagdataout
realtwid, imagtwid
twidaddress
exponent
Altera Corporation
43
3
Specifications
The exponent signal varies as data is being processed, because the core is
trying to maintain maximum dynamic range using block floating-point
techniques. The exponent signal is valid after done goes high.
Specifications
FFT MegaCore Function User Guide
The twiddle ROM is read from continuously while processing and the
core is designed to work with synchronous memories.
The read address/control is registered as it enters the synchronous
memory and the data is registered on its way out, which results in a two
clock cycle delay (see Figure 9).
Figure 9. Read Data Delay (Internal Memory)
sysclk
readaddress[10:0]
addr 2
addr 3
addr 4
addr 5
addr 6
addr 7
realdatain[7:0]
addr 0
addr 1
data 0
data 1
data 2
data 3
data 4
data 5
imagdatain[7:0]
data 0
data 1
data 2
data 3
data 4
data 5
When using external memory, you have to register the read
address/control on its way out and the returning data on its way in. This
is in addition to the synchronous external memory (see Figure 10).
Figure 10. Read Data Delay (External Memory)
sysclk
readaddress[10:0]
addr 4
addr 5
addr 6
addr 7
realdatain[7:0]
data 0
data 1
data 2
data 3
imagdatain[7:0]
data 0
data 1
data 2
data 3
Reference
Designs
addr 0
addr 2
addr 3
The core is provided with three reference designs, A, B, and C, which
show you how the variations produced by the MegaWizard Plug-In are
connected in a design. Reference design A shows you how to connect the
core to internal dual-ported RAM and internal twiddle ROM. Reference
design B shows you how to connect to external single-port data RAM and
external twiddle ROM. Reference design C shows you how to connect to
internal dual-port data RAM and external twiddle ROM. Reference
design C shows you how to use the external memory timing, which
allows you to register the memory addresses and data.
1
44
addr 1
The reference designs contain logic that implements bit reversed
and digit reversed addressing.
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Reference Design A
Reference design A (aukfft_fftchipa) shows you how to connect the
example variation, example_ffta, which uses internal memory. Figure 11
shows reference design A. Most of the connection glue logic is
implemented in subcomponents. The aukfft_twidrom subcomponent
instantiates reduced ROMs that contain only a quarter wave of data, and
logic to recover the full data set. The Stratix device optimized version,
aukfft_twidrom_4k, uses the Stratix M4K memory blocks in dual-port
ROM mode to halve the required twiddle memory; this approach is also
applicable to other technologies, such as APEX II devices, that support
dual-port ROM.
Figure 11. Reference Design A
aukfft_twidrom
address
example_ffta
aukfft_ram_dp
writeenable
fftwriteenable
read
twreal
realtwid
readaddress
fftreadaddress
write
twimag
imagtwid
writeaddress
twidaddress
writeaddress
fftrealdataout
readaddress
imagdataout
fftimagdataout
realdatain
fftrealdatain
imagdatain
fftimagdatain
writereal
User
Interface
writeimag
readreal
readimag
go
exponent
User
Interface
done
Reference Design B
Reference design B (aukfft_fftchipb) shows you how to connect the
example variation, example_fftb, which uses external memory. Figure 12
shows reference design B. Most of the connection glue logic is
implemented in subcomponents. aukfft_xlrbufferif, implements the
control logic that decodes the RAM bank that the core is reading from and
writing to. Also, the glue logic that is required to arbitrate between the
user interface and the core is implemented in this subcomponent. All of
the memories are in the top level and have been labeled as external (even
though they are on-chip), which allows the external design to be
simulated. When you compile for use with external memory, the required
input and output signals must be added to the design interface, and the
memory instance removed from the design.
Altera Corporation
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3
Specifications
fftwriteaddress
realdataout
Specifications
FFT MegaCore Function User Guide
If you want to use a mixture of internal and external memory, e.g.,
external data RAM and internal twiddle ROM, use reference design B as
a basis for your design and take the interface signals for the required
external memory to the top-level interface. If reference design B is
compiled without any modifications, all the memories are implemented
as internal memories, but this is less efficient than using reference design
A.
Figure 12. Reference Design B
User
Interface
aukfft_fftchipb
Left External
RAM Data Bank
aukfft_xlrbufferif
Right External
RAM Data Bank
example_fftb
aukfft_xtwidromif
External
Twiddle ROM
46
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Reference Design C
Reference design C (aukfft_fftchipc) shows you how to connect the
external configuration of the core to a combination of internal and external
memory. Reference design C has additional pipelining between the core
and the memory, which allows for registering of the signals while
retaining synchronization for on-chip memory. Figure 12 shows reference
design C.
Figure 13. Reference Design C
aukfft_twidrom
address
aukfft_ram_dp
example_fftc
writeenable
fftwriteenable
read
twreal
realtwid
readaddress
fftreadaddress
write
twimag
imagtwid
writeaddress
twidaddress
fftwriteaddress
writeaddress
realdataout
fftrealdataout
readaddress
imagdataout
fftimagdataout
realdatain
fftrealdatain
imagdatain
fftimagdatain
writereal
User
Interface
writeimag
readreal
3
readimag
direction
Specifications
Registers
go
exponent
User
Interface
done
Reading the Results from the Reference Designs
Each reference design includes logic that allows you to read the results
directly in natural order.
1
Read the results only when done goes high.
Figures 14, 15, and 16 show how to interpret the data as it is read out from
address 0 to points. There is an offset between the read address being
applied and the data results returned, e.g., two clock cycles for reference
design A.
Altera Corporation
47
Specifications
FFT MegaCore Function User Guide
Figure 14. Input Data versus Write Address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
10
11
12
13
14
15
Write Address
Figure 15. Output Data versus Read Address
Data
4
3
2
1
1
0
2
3
4
5
6
7
9
8
16
Read Address
Figure 16. Output Data versus Read Address—Symmetrical about Zero
Data
4
3
2
1
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
Read Address
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Altera Corporation
FFT MegaCore Function User Guide
Performance
Specifications
The datawidth and twiddlewidth parameters have the biggest impact
on size and performance, because the logic and memory resources
required by the core are essentially linear to these parameters. All other
parameters have little effect on the required logic resources, however
points has a linear effect on the required memory resources.
For Stratix devices, the core uses the Stratix DSP blocks. If both
datawidth and twiddlewidth are less than 17, the core requires 1 DSP
block; otherwise 4 DSP blocks are required.
The amount of RAM (in bits) required is given by:
2 × datawidth × points
The amount of twiddle ROM (in bits) required is given by:
twiddlewidth × points/4, for Stratix devices
twiddlewidth × points/2, for all other devices.
3
The performance of the core is dependent on:
the clock rate of the system
the number of clocks cycles required to calculate the FFT
The number of clock cycles is determined by the number of passes and the
number of clock cycles per pass,
where:
number of passes = ceiling((log2(points))/2)
number of clock cycles per pass (for internal memory)=
points + ceiling(log2(twiddlewidth)) + 15
number of clock cycles per pass (for external memory)=
points + ceiling(log2(twiddlewidth)) + 19
The total number of clock cycles per transform is given by:
total number of clock cycles per transform =
(number of passes × number of clock cycles per pass) + 6
Altera Corporation
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Specifications
■
■
Specifications
FFT MegaCore Function User Guide
Tables 11 and 12 shows examples of the performance and size of the core,
for the reference design A, with different devices using the Quartus II
software version 2.1.
Table 11. Performance and Size for APEX 20KE Devices
Device
Float
Width
Data Twiddle
Width Width
Points
Size
Memory
(LEs) (1) (ESBs)
(2)
fMAX
(MHz)
Transform
Time (µs)
EP20K60EBC356-1
5
8
8
64
1,331
2
118
2.12
EP20K60EBC356-1
5
8
8
256
1,386
3
136
8.10
EP20K60EBC356-1
5
8
8
1,024
1,424
10
124
41.75
EP20K400EBC652-1
5
8
8
8,192
1,523
80
111
513.08
EP20K100EBC356-1
5
16
16
64
3,266
4
115
2.22
EP20K100EBC356-1
5
16
16
256
3,337
6
119
9.27
EP20K100EBC356-1
5
16
16
1,024
3,375
20
106
48.89
EP20K1500EBC652-1
5
16
16
8,192
3,506
160
67
852.99
EP20K160EBC356-1
5
24
24
64
5,433
6
83
3.07
EP20K160EBC356-1
5
24
24
256
5,520
9
84
13.20
EP20K160EBC356-1
5
24
24
1,024
5,558
30
78
66.85
Notes:
(1)
(2)
50
LEs: logic elements
ESBs: embedded system blocks
Altera Corporation
FFT MegaCore Function User Guide
Specifications
Table 12. Performance and Size for Stratix Devices
Device
Float Data Twiddle Points
Width Width Width
EP1S10F780C5
5
8
8
EP1S10F780C5
5
8
EP1S10F780C5
5
8
EP1S20F780C5
5
EP1S10F780C5
EP1S10F780C5
Size
(LEs)
(1)
Memory
M4K Blocks M-RAMs
fMAX
(MHz)
Transform
Time (µs)
64
674
2
0
249
1.01
8
256
734
2
0
238
4.62
8
1,024
776
5
0
247
21.08
8
8
8,192
876
4
1
179
319.40
5
16
16
64
1,167
2
0
222
1.15
5
16
16
256
1,243
3
0
227
4.86
EP1S10F780C5
5
16
16
1,024
1,285
9
0
229
22.76
EP1S20F780C5
5
16
16
8,192
1,419
8
1
211
271.21
EP1S10F780C5
5
24
24
64
2,040
4
0
187
1.38
EP1S10F780C5
5
24
24
256
2,132
5
0
192
5.77
EP1S10F780C5
5
24
24
1,024
2,174
14
0
198
26.27
EP1S20F780C5
5
24
24
8,192
2,336
12
1
161
356.66
Specifications
Notes:
(1)
LEs: logic elements.
Altera Corporation
3
51
Specifications
52
FFT MegaCore Function User Guide
Altera Corporation
Appendix A—Relating the
Time Domain to the
Frequency Domain
Parseval’s Theorem (equation 1) states that the power in the time domain
must be equivalent to the power in the frequency domain, which does not
necessarily mean the amplitudes in each domain are the same.
i = K–1
∑
i = K–1
s( i)
1
= ---K
2
i=0
∑
S(i )
2
(1)
i=0
where:
K = the number of points
s is the sample amplitude in the time domain
S is the sample amplitude in the frequency domain.
Example 1
Example 1 is an impulse of amplitude 64 (see Figure 18) input to the real
memory only (no imaginary component) to a 16 point FFT. Equation 2
shows the power in the time domain. Equation 3 shows the power in the
frequency domain.
4
Figure 17. Example 1
Time Domain
s
S
64
16
t
i = K–1
∑
Appendix A
Frequency Domain
(exponent = -2)
s( i)
2
·2
= 64 = 4, 096
f
(2)
i=0
i = K–1
1
---K
∑
S( i)
2
1
–( – 2 ) 2
= ------ ( 16 ( 16 × 2
) ) = 4, 096
16
(3)
i=0
Altera Corporation
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Appendix A
FFT MegaCore Function User Guide
Therefore the power in the time domain must be equivalent to the power
in the frequency domain.
The error, which indicates the loss of precision because of the fixed data
width is given by equation 4:
i = K–1
∑
E =
i = K–1
1
S ( i ) – ---K
2
i=0
Example 2
∑
S(i )
2
= 4, 096 – 4, 096 = 0
(4)
i=0
Example 2 is a sine wave input (see Figure 18) to the real memory only (no
imaginary component) to a 16 point FFT. The sine wave is a special
instance; in the time domain the power is given by equation 5. Equation
6 shows the power in the frequency domain.
Figure 18. Example 2
Frequency Domain
(exponent = -4)
Time Domain
S
s
50
100
t
f
1
-100
2
2
Ks
4
16 × 100
--------- = ----------------------- = 8 × 10 = 80000
2
2
(5)
i = K–1
1
---K
∑
S(K)
2
1
–( –4 ) 2
–( – 4 ) 2
= ------ ( ( 50 × 2
) + ( 50 × 2
) ) = 80000
16
(6)
i=0
Therefore the power in the time domain must be equivalent to the power
in the frequency domain.
54
Altera Corporation
GettingAppendix A
FFT MegaCore Function User Guide
The error, which indicates the loss of precision because of the fixed data
width is given by equation 7:
i = K–1
E =
∑
i=0
i = K–1
1
S ( i ) – ---K
2
∑
S(i )
2
= 80000 – 80000 = 0
(7)
i=0
4
Appendix A
Altera Corporation
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Notes: