DSP Builder
Quartus II & MATLAB/Simulink Interface
User Guide
September 2001, v0.02
Pre-Release
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
A-UG-DSPBUILDER-0.02
Copyright
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Copyright  2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
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Altera Corporation
About this User Guide
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This user guide provides comprehensive information about the Altera®
DSP builder.
Table 1 shows the user guide revision history.
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See “Features” on page 11 for a complete list of the core features,
including new features in this release.
Refer to the DSP builder readme file for late-breaking information
that is not available in this user guide.
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Description
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Table 1. User Guide Revision History
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September 2001,
v0.2
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August 2001
How to Find
Information
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Altera Corporation
Updated block screen shots, added the Bus Concatenation
and n-to-1 Multiplexer blocks, removed the 2Mux1 block,
added additional parameter descriptions to the IF Statement,
LUT, and Gain blocks. Made minot grammatical and
formatting changes throughout.
First version of the preliminary user guide for the pre-release
version of the DSP builder.
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
How to Contact
Altera
About this User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Information Type
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Table 2. How to Contact Altera
Access
USA & Canada
All Other Locations
Electronic mail
[email protected] (1)
[email protected] (1)
Non-technical
customer service
Telephone hotline
(800) SOS-EPLD
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
or
Altera Literature
Services
(408) 544-7606
(408) 544-6401
(408) 544-6401 (1)
Electronic mail (DSP
questions)
[email protected]
[email protected]
World-wide web site (general
technical questions)
http://mysupport.altera.com http://mysupport.altera.com
(1)
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ftp.altera.com
ftp.altera.com
Telephone
(408) 544-7104
(408) 544-7104 (1)
World-wide web site
http://www.altera.com
http://www.altera.com
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FTP site
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Fax
General product
information
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
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Telephone hotline
(408) 544-7606
(800) 800-EPLD
(6:00 a.m. to 6:00 p.m.
Pacific Time)
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Fax
Technical support
You can also contact your local Altera sales office or sales representative.
Altera Corporation
About this User Guide
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Typographic
Conventions
The DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
uses the typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Quartus II Help topics are
shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device
with the BitBlaster™ Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
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Bold Type with Initial
Capital Letters
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Digital Signal Processing
Fast Fourier Transform
Finite Impulse Response
Infinite Impulse Response
Intellectual Property
Least Significant Bit
Model File (.mdl)
Most Significant Bit
Numerically Controlled Oscillator
Register Transfer Level
Signed Binary Fractional
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DSP
FFT
FIR
IIR
IP
LSB
MDL
MSB
NCO
RTL
SBF
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Abbreviations
& Acronyms
About this User Guide
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Altera Corporation
Contents
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About this User Guide ............................................................................. iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Abbreviations & Acronyms .......................................................................................................... vi
About DSP Builder .................................................................................11
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General Description .......................................................................................................................11
Features ...........................................................................................................................................11
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Getting Started ......................................................................................13
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DSP Builder Software Requirements ..........................................................................................13
Design Flow ....................................................................................................................................13
Install the DSP Builder ..................................................................................................................14
Obtain the DSP Builder .........................................................................................................14
Install the DSP Builder ..........................................................................................................15
DSP Builder Directory Structure .........................................................................................16
Set Up Licensing .............................................................................................................................16
DSP Builder Tutorial .....................................................................................................................18
1. Create the Sine Generator Model ....................................................................................18
1.1 Create a New Model ................................................................................................20
1.2 Add the Sine Wave Block .......................................................................................21
1.3 Add the SinIn Block .................................................................................................21
1.4 Add the Delay Block ................................................................................................23
1.5 Add the SinDelay Block ..........................................................................................24
1.6 Add the Mux Block ..................................................................................................25
1.7 Add the Random Number Block ...........................................................................26
1.8 Add the Noise Block ................................................................................................27
1.9 Add the BusBuild Block ..........................................................................................28
1.10 Add the gnd Block .................................................................................................29
1.11 Add the Product Block ..........................................................................................30
1.14 Add the SreamMod Block .....................................................................................31
1.13 Add the Scope Block ..............................................................................................32
1.14 Add the SignalCompiler Block ............................................................................33
1.15 Simulate Your Model in Simulink .......................................................................35
2. Synthesize & Compile the Design Automatically .........................................................36
3. Synthesize the Design Manually .....................................................................................37
4. Compile the Design Manually in the Quartus II Software ..........................................39
Altera Corporation
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Contents
5. Perform RTL Simulation with the ModelSim Software ...............................................40
Instantiating IP in Your Model ....................................................................................................42
Specifications .......................................................................................45
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About the DSP Builder Blocks .....................................................................................................45
Block Number Formats .................................................................................................................46
Signed Binary Fractional Representation ...................................................................................47
Hierarchical Design .......................................................................................................................48
Altlab Blocks ........................................................................................51
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AltBus Block ....................................................................................................................................51
Input Port & Output Port Modes .........................................................................................52
Internal Node Mode ..............................................................................................................53
Black Box Input Output Mode .............................................................................................54
Constant Mode .......................................................................................................................54
BusBuild Block ...............................................................................................................................55
Bus Concatenation Block ..............................................................................................................57
BusConversion Block .....................................................................................................................57
ExtractBit Block ..............................................................................................................................59
SignalCompiler Block ....................................................................................................................60
Data Width Propagation .......................................................................................................61
Tapped Delay Line .........................................................................................................63
Arithmetic Operation ....................................................................................................64
Clock Assignment ..................................................................................................................67
SubSystem Block ............................................................................................................................69
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Arithmetic Blocks ...................................................................................71
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Comparator Block ..........................................................................................................................71
Gain Block .......................................................................................................................................72
Increment Decrement Block .........................................................................................................74
Magnitude Block ............................................................................................................................75
Parallel Adder Subtractor Block ..................................................................................................76
Product Block ..................................................................................................................................77
APEX DSP Board EP20K200EBC652-1X Blocks ................................................79
APEX DSP Board EP20K1500EBC652-1X Blocks ...............................................83
Gates Blocks ........................................................................................87
n-to-1 Multiplexer Block ...............................................................................................................87
Case Statement Block .....................................................................................................................88
If Statement Block ..........................................................................................................................89
Logical Bit Operator Block ............................................................................................................90
Logical Bus Operator Block ..........................................................................................................91
LUT Block ........................................................................................................................................92
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Contents
MegaCore IP Blocks ...............................................................................93
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FFT Compiler Block .......................................................................................................................94
FIR Block .........................................................................................................................................94
IIR Block ..........................................................................................................................................97
NCO Block ......................................................................................................................................98
Reed Solomon Block ......................................................................................................................98
Interleaver Deinterleaver Block ...................................................................................................99
Storage Blocks .................................................................................... 101
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Delay Block ...................................................................................................................................101
Down Sampling Block .................................................................................................................102
Dual-Port RAM Block ..................................................................................................................103
Pattern Block .................................................................................................................................105
ROM EAB Block ...........................................................................................................................106
Up Sampling Block ......................................................................................................................108
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Appendix ........................................................................................... 111
Altera Corporation
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About DSP Builder
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Digital signal processing (DSP) development in Altera® programmable
logic devices requires both high-level algorithm development tools and
hardware description language (HDL) tools. Altera’s DSP builder
integrates these tools by combining the algorithm development,
simulation, and verification capabilities of the MathWorks system-level
design tools with Altera HDL development tools.
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The DSP builder is a set of building blocks that shortens DSP design cycles
by helping you create the hardware representation of a DSP design in an
algorithm-friendly development environment. You can use existing
MATLAB functions and Simulink blocks as part of the design and test
process. DSP builder links system-level design and DSP algorithm
development; therefore, algorithm and system designers can share a
common development platform.
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You can use the blocks in the DSP builder to create a hardware
implementation of a Simulink system modeled in sampled time. The DSP
builder contains bit- and cycle-accurate Simulink blocks, which cover
basic operations such as arithmetic or storage functions as well as complex
functions such as forward error correction or filtering. The OpenCore®
feature lets you test-drive Altera MegaCore® functions for free using the
Quartus® II or MAX+PLUS® II software, as well as other EDA tools such
as the LeonardoSpectrum and Synplify software. The DSP builder
SignalCompiler block reads Simulink Model Files (.mdl) and writes out
VHDL files and Tcl scripts for hardware implementation and simulation.
Features
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Altera Corporation
Links The Mathworks MATLAB and Simulink environment with the
Altera Quartus II environment
Supports a single representation of a DSP design
Automatically generates a VHDL testbench, which imports MATLAB
and Simulink test vectors for co-verification
Automatically performs VHDL synthesis and compilation
Enables cycle-accurate design simulation of real-time data
Enables rapid prototyping using the Altera APEX™ DSP
development board
Interfaces with the MATLAB Signal Processing ToolBox and Filter
Design Toolbox
Provides a variety of fixed-point arithmetic and logic operators for
use with the Simulink software
11
About DSP Builder
General
Description
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Includes a library of Altera intellectual property (IP) functions—
which can be evaluated for free using the OpenCore feature—for
optimized implementation of complex DSP functions:
–
FFT compiler
–
FIR compiler
–
IIR compiler
–
NCO compiler
–
Reed-Solomon compiler
–
Interleaver/deinterleaver
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About DSP Builder
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Altera Corporation
Getting Started
DSP Builder
Software
Requirements
2
MATLAB version 6.0
Simulink version 4.0
Java Virtual Machine version 1.3 or higher
Synplify version 6.1 or LeonardoSpectrum version 2000.01b
Quartus II version 1.1 or MAX+PLUS II version 10.0
ModelSim version 5.5
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Getting Started
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The following software is required to create HDL designs that use blocks
from the DSP builder:
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You are using a PC running Windows.
You install the DSP builder in the default location,
c:\MegaCore\DSPBuilder.
You are familiar with the MATLAB, Simulink, LeonardoSpectrum,
Quartus II, and ModelSim software and the software is installed on
your PC in the default location.
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The instructions provided in this document assume that:
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Design Flow
Altera Corporation
For more information on any of the software products used in
this design example, refer to the documentation provided with
the software.
When using the DSP builder to build a design, you start out by creating a
model in the MATLAB and Simulink software. After you have created
your model, you can output HDL files for synthesis and compilation or
generate files for simulation in the ModelSim software. The design flow
involves the following steps:
1.
Create a model using the MATLAB and Simulink software using a
combination of Simulink and DSP builder blocks.
2.
Use the output files generated by the DSP builder SignalCompiler
block to perform RTL synthesis in the Synplify or
LeonardoSpectrum software.
3.
Compile your design in the Quartus II or MAX+PLUS II software.
4.
Perform RTL simulation using the ModelSim software and output
files generated by the DSP builder SignalCompiler block.
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
Figure 1 shows the system-level design flow using the DSP builder.
Figure 1. System-Level Design Flow
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System-Level Design
MATLAB Simulink Software
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SignalCompiler (1)
RTL Simulation
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RTL Synthesis
Compilation
Quartus II Software
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Install the DSP
Builder
(1)
SignalCompiler generates VHDL files and Tcl scripts for synthesis in the
LeonardoSpectrum or Synplify software, compilation in the Quartus II software,
and simulation in the ModelSim software. The Tcl scripts let you perform synthesis
and compilation automatically from within the MATLAB and Simulink
environment.
Before you can start using the DSP builder, you must obtain the library
and install it on your PC. The following instructions describe this process.
Obtain the DSP Builder
You can obtain the DSP builder files from your local Altera sales
representative.
14
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Install the DSP Builder
To install the DSP builder on a PC running Windows 98/NT/2000,
perform the following steps:
2.
Type <path name>\DSPBuilder.exe, where <path name> is the
location of the downloaded file.
3.
Click OK. The DSPBuilder Installer dialog box appears. Follow the
on-line instructions to finish installation.
4.
Start the MATLAB software.
5.
At the MATLAB prompt, change the directory to the
<path>\DSPbuilder\Altlib directory by typing the following
command in the MATLAB Command Window:
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Choose Run (Windows Start menu).
Type Setup_DSPBuilder r in the Command Window.
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<path>\DSPBuider\Altlib r
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Expand the Simulink icon in the Launch Pad window.
Double-click on the Library Browser icon. The Altera Library folder
appears in the Simulink Library Browser window.
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Altera Corporation
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2
Getting Started
1.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
DSP Builder Directory Structure
The DSP Builder installation program copies files into the directories
shown in Figure 2.
Figure 2. DSP Builder Directory Structure
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Anaconda
AltLib
Contains the DSP builder files, including the files needed to execute the MegaCore wizards from within
the Simulink environment.
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DesignExamples
Contains example design files and screen shots for the blocks in the DSP builder. The GettingStarted
subdirectory contains the example design files described in the Getting Started section of the DSP Builder
Quartus II & MATLAB/Simulink Interface User Guide.
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doc
Contains DSP builder documentation, including the DSP Builder Quartus II & MATLAB/Simulink Interface
User Guide and the on-line help files for each DSP builder block, which are displayed in the MATLAB software.
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MegaCoreLib
Contains the MegaCore function files used bu the DSP builder.
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MegaCoreSimLib
Contains simulation files used by the MegaCore and library of parameterized modules (LPM) functions
provided with the DSP builder.
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Lpm
Contains simulation files for the LPM functions.
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ReedS
Contains files for the Reed-Solomon compiler MegaCore function.
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wfir
Contains files for the FIR compiler MegaCore function.
Set Up
Licensing
You can freely simulate models using DSP builder blocks in the Simulink
software before deciding to license the product. Once you have purchased
a license, you can generate HDL output files and Tcl scripts using the
SignalCompiler block.
1
You only need to set up licensing if you have purchased a license
for the DSP builder.
When you purchase a license, Altera sends you a license.dat file that
enables HDL file and Tcl script generation. To install the license, perform
the following steps.
1
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Before you set up licensing for the DSP builder, you must
already have the Quartus II or MAX+PLUS II software installed
on your PC with licensing set up.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1.
Close the following software if it is running on your PC:
Quartus II
MAX+PLUS II
MATLAB or Simulink
LeonardoSpectrum
Synplify
ModelSim
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2.
Open the DSP builder license file in a text editor. The file should
contain one FEATURE line in the file, spanning 2 lines.
3.
Open your Quartus II or MAX+PLUS II license.dat file in a text
editor.
4.
Copy the FEATURE line from the DSP builder license file and paste it
into the Quartus II or MAX+PLUS II license file.
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Do not delete any FEATURE lines from the Quartus II or
MAX+PLUS II license file.
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Save the Quartus II or MAX+PLUS II license file.
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename in a DOS box or command prompt.
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Figure 3 shows a sample updated license.dat file that includes the DSP
builder FEATURE line (highlighted in blue).
Figure 3. Example license.dat File
Altera Corporation
17
Getting Started
1
5.
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
DSP Builder
Tutorial
Getting Started
This tutorial uses a sample design, SinGen.mdl, to demonstrate the DSP
builder design flow. The SinGen.mdl model generates a sine wave. Each
block in the model is parameterizable. You set the parameters in the block
parameter dialog boxes in the Simulink user interface. The dialog boxes
display when you double-click on a block in your model. Click the Help
button in the block parameter dialog boxes to view the block’s on-line
help.
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To create the sine generator model, follow the steps in “1. Create the Sine
Generator Model” below.
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If you did not use the default installation directory,
c:\MegaCore\DSPBuilder, you must update the working
directory in the SignalCompiler block by performing these steps
after you open the Altera-provided model file:
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To use the Altera-provided model file, open the file
<path>\DSPBuilder\DesignExamples\GettingStarted\SinMdl\SinG
en.mdl and skip to “2. Synthesize & Compile the Design Automatically”
on page 36.
Double-click the SignalCompiler block.
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1.
Change the Working Directory to reflect the directory in
which you installed the DSP builder.
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2.
Paths in the MATLAB and Simulink software are case
sensitive. Therefore, you MUST type the path in the
Working Directory box exactly as it appears in your
system, including case.
3.
Choose Update diagram (Edit menu).
4.
Choose Save (File menu).
5.
Continue with “2. Synthesize & Compile the Design
Automatically” on page 36.
1. Create the Sine Generator Model
To implement the design SinGen.mdl, perform the following steps. If you
do not want to create the design, Altera provides it in the
<path>\DSPBuilder\DesignExamples\GettingStarted\SinMdl
directory. Figure 4 shows the finished design.
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Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1
The instructions for this tutorial assume that you have basic
knowledge of the Simulink software. Refer to Simulink Help for
information on using the software.
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Figure 4. Sine Generator Design Example
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Getting Started
You must specify the bit width at the source and destination of the
data path logic function. The SignalCompiler block propagates this
bit width from the source to the destination through all intermediate
blocks. You can optionally specify the bit width of intermediate
blocks such as the Delay block.
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As you build your model, you should follow these design rules:
In the sine generator sample design, the SinIn and SinDelay blocks
have a bit width of 16. Therefore, SignalCompiler automatically
assigns a bit width of 16 to the intermediate Delay block. Each DSP
builder block has specific design rules. The bit width growth rule is
described in the documentation for each block.
■
The DSP builder uses synchronous design rules to convert a Simulink
design into hardware. The SignalCompiler block identifies
synchronous DSP builder blocks, such as Delay blocks, and assigns
the required input signals accordingly.
Most DSP systems operate with a normalized frequency with respect
to the Nyquist rate. The DSP builder version 1.0 works with a Nyquist
rate of 1.0, which means that the manimum normalized frequency is
1/2. All discrete sampling blocks operate at this normalized sampling
frequency (1.0). For example, to create a 500 kHz sine wave using a 40
MHz sample rate where:
Altera Corporation
19
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
Normalized sample frequency = 1.0
Actual sample rate = 40 MSPS
Using the Simulink Sine Wave block from the Sources library,
specify:
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( Desired Actual Frequency in Hz ) × 2π
Frequency (radians/second) = ----------------------------------------------------------------------------------------------( Actual Sampling Rate in Hz )
3
10 × 2π= 500
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40 10
Makre sure the block operates with a sample time of 1.
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The DSP builder supports multi-rate usage by the implicit use of the
block’s clock enable pin. “SignalCompiler Block” on page 60
describes the details of the feature.
Start the MATLAB software.
2.
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1.1 Create a New Model
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Choose the New > Model command (File menu) to create a new
model file.
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3.
Choose Save (File menu) in the new model window.
Browse to the directory in which you want to save the file. This
directory will be your working directory. This example uses the
working directory c:\MegaCore\DSPBuilder\DesignExamples\
GettingStarted\SinMdl.
5.
Type the filename into the File name box. This example uses the
name singen.mdl.
6.
Click Save.
7.
Expand the Simulink icon in the MATLAB Launch Pad window by
clicking the + symbol next to the icon.
8.
Double-click on the Library Browser icon.
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4.
The following steps describe how to add the blocks used in the
singen.mdl example to your model and simulate your model.
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Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1.2 Add the Sine Wave Block
Perform the following steps to add the Sine Wave block.
In the Simulink Library Browser, click on the Simulink Sources
library to view the blocks in the library.
2.
Drag and drop a Sine Wave block into your model (the singen
window).
3.
Double-click on the Sine Wave block in your model.
4.
Set the Sine Wave block parameters as shown in Figure 5 and click
OK.
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Figure 5. Sine Wave Parameters
1.3 Add the SinIn Block
Perform the following steps to add the SinIn block.
1.
Altera Corporation
Expand the Altera Library by clicking the + symbol next it. The DSP
builder sublibraries are displayed. Leave the library expanded for
the rest of the tutorial. See Figure 6.
21
Getting Started
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 6. Altera Library in Simulink Library Browser
22
2.
Select the AltLab sublibrary.
3.
Drag and drop the AltBus block from the Simulink Library Browser
into your model. Position the block to the right of the Sine Wave
block.
4.
Click on the AltBus text under the block icon in your model.
5.
Delete the text AltBus and type in the text SinIn.
6.
Double-click on the SinIn block in your model. The block’s
parameter dialog box displays.
7.
Set the parameters as shown in Figure 7 and click OK.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 7. SinIn Parameters
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Getting Started
Draw a connection line from the right side of the Sine Wave block to
the left side of the SinIn block.
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1.4 Add the Delay Block
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Perform the following steps to add the Delay block.
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1.
Altera Corporation
Select the Storage sublibrary from the Altera Library in the Simulink
Library Browser.
2.
Drag and drop the Delay block into your model and position it to the
right of the SinIn block.
3.
Double-click on the Delay block in your model.
4.
Set the parameters as shown in Figure 8 and click OK.
23
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
or
Draw a connection line from the right side of the SinIn block to the
left side of the Delay block.
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Figure 8. Delay Parameters
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1.5 Add the SinDelay Block
Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
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Perform the following steps to add the SinDelay block.
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2.
Drag and drop an AltBus block into your model, positioning it to the
right of the Delay block.
3.
Click on the AltBus text under the block icon in your model.
4.
Delete the text AltBus and type in the text SinDelay.
5.
Double-click on the SinDelay block in your model.
6.
Choose Output Port from the Node Type drop-down list box.
7.
Click Apply.
1
24
The dialog box options change when you select a new node
type and click Apply.
8.
Choose 16 from the [number of bits].[] drop-down list box. Figure 9
shows the dialog box after you have made these settings.
9.
Click OK to save your changes.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 9. SinDelay Parameters
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10. Draw a connection line from the right side of the Delay block to the
left side of the SinDelay block.
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1.6 Add the Mux Block
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Perform the following steps to add the Mux block.
Altera Corporation
1.
Select the Simulink Signals & Systems library in the Simulink
Library Browser.
2.
Drag and drop a Mux block into your design, positioning it to the
right of the SinDelay block.
3.
Double-click on the Mux block in your model.
4.
Set the parameters as shown in Figure 10 and click OK.
25
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 10. Mux Parameters
Draw a connection line from the bottom left of the Mux block to the
right side of the SinDelay block.
6.
Draw a connection line from the top left of the Mux block to the line
in between the SinIn and Delay blocks.
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5.
1.7 Add the Random Number Block
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Select the Simulink Sources library in the Simulink Library
Browser.
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Perform the following steps to add the Random Number block.
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2.
26
Drag and drop a Random Number block into your model,
positioning it underneath the Sine Wave block.
3.
Double-click on the Random Number block in your model.
4.
Set the parameters as shown in Figure 11 and click OK.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 11. Random Number Parameters
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Getting Started
1.8 Add the Noise Block
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Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
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Perform the following steps to add the Noise block.
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2.
Drag and drop an AltBus block into your model, positioning it to the
right of the Random Number block.
3.
Click on the AltBus text under the block icon in your model.
4.
Delete the text AltBus and type in the text Noise.
5.
Double-click on the Noise block.
6.
Choose the Single Bit option from the Bus Type drop-down list box.
1
Altera Corporation
The dialog box options change when you select a new bus
type and click Apply.
7.
Click Apply. Figure 12 shows the dialog box after you have made
this setting.
8.
Click OK.
27
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
Draw a connection line from the right side of the Random Number
block to the left side of the Noise block.
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Figure 12. Noise Parameters
1.9 Add the BusBuild Block
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Perform the following steps to add the BusBuild block.
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Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
2.
Drag and drop the BusBuild block into your model, positioning it to
the right of the Noise block.
3.
Double-click on the BusBuild block in your model.
4.
Set the parameters as shown in Figure 13 and click OK.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 13. BusBuild Parameters
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Draw a connection line from the right side of the Noise block to the
top left side of the BusBuild block.
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1.10 Add the gnd Block
Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
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Perform the following steps to add the gnd block.
Drag and drop an AltBus block into your model, positioning it
underneath the Noise block.
3.
Click on the AltBus text under the block icon in your model.
4.
Delete the text AltBus and type in the text gnd.
5.
Double-click on the gnd block.
6.
Choose the Single Bit option from the Bus Type drop-down list box.
7.
Choose Constant from the Node Type drop-down list box.
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2.
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Altera Corporation
The dialog box options change when you select a new bus
and node type and click Apply.
8.
Click Apply. Figure 14 shows the dialog box after you have made
this setting.
9.
Click OK.
29
Getting Started
5.
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 14. gnd Parameters
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10. Draw a connection line from the right side of the gnd block to the
bottom left side of the BusBuild block.
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1.11 Add the Product Block
Perform the following steps to add the Product block.
Select the Arithmetic sublibrary from the Altera Library in the
Simulink Library Browser.
2.
Drag and drop a Product block into your model, positioning it to the
right of the BusBuild block and slightly above it. Leave enough space
that you can draw a connection line underneath the Product block.
3.
Double-click on the Product block.
4.
Set the parameters as shown in Figure 15 and click OK.
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1.
30
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
2
or
Draw a connection line from the top left of the Product block to the
line between the Delay and SinDelay blocks.
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1.14 Add the SreamMod Block
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Perform the following steps to add the StreamMod block.
Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
2.
Drag and drop an AltBus block into your model, positioning it to the
right of the Product block.
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1.
Click on the AltBus text under the block icon in your model.
4.
Delete the text AltBus and type in the text StreamMod.
5.
Double-click on the StreamMod block.
6.
Set the parameters as shown in Figure 16 and click OK.
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3.
Altera Corporation
31
Getting Started
5.
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Figure 15. Product Parameters
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Draw a connection line from the left side of the Product block to the
right side of the StreamMod block.
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Figure 16. StreamMod Parameters
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1.13 Add the Scope Block
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Perform the following steps to add the Scope block.
1.
Select the Simulink Sinks library in the Simulink Library Browser.
2.
Drag and drop a Scope block into your model and position it to the
right of the StreamMod block.
3.
Double-click on the Scope block.
4.
Click the Properties icon.
5.
Set the following parameters:
a.
Type 3 in the Number of axes box.
b.
Type 23.41356673960612 in the Time range box.
See Figure 17. Click OK.
6.
32
Close the scope window.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 17. Scope Properties
2
Getting Started
Draw a connection line from the right side of the Mux block to the
top left side of the Scope block.
8.
Draw a connection line from the right side of the StreamMod block
to the middle left side of the Scope block.
9.
Draw a connection line from the right side of the BusBuild block to
the bottom left of the Scope block.
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10. Draw a connection line from the bottom left of the Product block to
the line between the BusBuild block and the Scope block.
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1.14 Add the SignalCompiler Block
Altera Corporation
Perform the following steps to add the SignalCompiler block.
1.
Select the AltLab sublibrary from the Altera Library in the Simulink
Library Browser.
2.
Drag and drop a SignalCompiler block into your model.
3.
Double-click the SignalCompiler block in your model.
4.
Set the following parameters:
a.
Choose APEX 20KE from the Device Family drop-down list box.
b.
Choose Speed from the Optimization drop-down list box.
c.
Choose LeonardoSpectrum from the Synthesis Tool dropdown list box. This tutorial uses the LeonardoSpectrum
33
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
synthesis software. If you want to use the Synplify software,
choose Synplify from the Synthesis Tool drop-down list box.
d.
Type the following information into the Working Directory box:
c:\MegaCore\DSPBuilder\DesignExamples\GettingStarted\SinMdl
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Figure 18. SignalCompiler Parameters
5.
Click OK.
6.
Choose Save (File menu) to save the model.
You are now ready to simulate your model in the Simulink software.
34
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1.15 Simulate Your Model in Simulink
To simulate your model in the Simulink software, perform the following
steps.
2.
Type 200 in the Stop time box.
3.
Click OK.
4.
Start simulation by choosing Start (Simulation menu) or by pressing
the Ctrl+T keys.
5.
Double-click on the Scope Sin and Scope Rnd blocks to view the
simulation results.
6.
Click the binoculars icon to auto-scale the waveforms. Figure 19
shows the scaled waveforms.
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Choose Simulation parameters (Simulation menu).
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Figure 19. Scope Simulation Results
Altera Corporation
35
2
Getting Started
1.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
To perform VHDL synthesis and compilation automatically, go to
“2. Synthesize & Compile the Design Automatically” on page 36.
To perform VHDL synthesis and compilation manually, skip to
“3. Synthesize the Design Manually” on page 37.
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2. Synthesize & Compile the Design Automatically
SignalCompiler maps each Altera library block in the SinGen.mdl design
to the DSP builder VHDL library. In this step you use the SignalCompilerGenerate HDL, Perform VHDL Synthesis, and Compile option to
perform synthesis in the Synplify or LeonardoSpectrum software and
compilation in the Quartus II software.
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To synthesize and compile the design manually, go to
“3. Synthesize the Design Manually” on page 37.
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Perform the following steps for automatic synthesis and compilation:
Open the SignalCompiler block in your model.
2.
Turn on the Generate HDL, Perform VHDL Synthesis, and
Compile option.
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Click Apply. Synthesis begins automatically in synthesis tool you
specified in “1.14 Add the SignalCompiler Block” on page 33. Once
synthesis is complete, compilation in the Quartus II software begins.
Messages from the synthesis and compilation tools are displayed in
the MATLAB Command window.
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1
For the Quartus II software to compile automatically, you
must have Quartus II Tcl script support enabled. If you are
using a version of the Quartus II software that does not
support Tcl scripting (e.g., Quartus II Web Edition), you will
receive a message in the MATLAB Command Window
saying the the Tcl Script Support feature is not available.
If your version of the Quartus II software does not support
Tcl scripts, you must perform compilation manually.
Complete the remaining steps below and then go to
“4. Compile the Design Manually in the Quartus II
Software” on page 39.
36
4.
Once synthesis and compilation are complete, turn off the Generate
HDL, Perform VHDL Synthesis, and Compile option.
5.
Click OK.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
6.
Skip to “5. Perform RTL Simulation with the ModelSim Software” on
page 40
3. Synthesize the Design Manually
or
To synthesize and compile the design automatically, go to
“2. Synthesize & Compile the Design Automatically” on page 36.
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You can synthesize the design files manually by performing the following
steps:
Open the SignalCompiler block in your model.
2.
Turn on the Generate HDL option.
3.
Click Apply. SignalCompiler generates HDL file(s) and Tcl script(s).
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Turn off the Generate HDL option.
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Click OK.
6.
Open the generated HDL files in your synthesis software and
perform synthesis.
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5.
1
Refer to the documentation for your synthesis software for
instructions on how to synthesize the design.
Figure 20 shows the SinGen project in the LeonardoSpectrum software.
Altera Corporation
37
2
Getting Started
1
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SignalCompiler maps each Altera library block in the SinGen.mdl design
to the DSP builder VHDL library. In this step you use the SignalCompilercreated SinGen.vhd file and SinGen.tcl script for synthesis in the
Synplify or LeonardoSpectrum software. The VHDL file contains the RTL
design and the Tcl script sets up the environment and performs synthesis
in the designated synthesis software.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 20. SinGen LeonardoSpectrum View
The RTL view illustrates the result of the conversion process from
Simulink blocks to HDL. See Figure 21.
Figure 21. RTL View
38
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
4. Compile the Design Manually in the Quartus II Software
After you perform synthesis in the Synplify or LeonardoSpectrum
software, the software generates ATOM netlist files (EDIF or VQM) in
your working directory. You can then compile these files in the Quartus II
software to generate the Programmer Object File (.pof) used to program
an Altera device.
To synthesize and compile the design automatically, go to
“2. Synthesize & Compile the Design Automatically” on page 36.
To compile the design in the Quartus II software, perform the following
steps:
Start the Quartus II software.
2.
Create a new project using the files generated by the synthesis
software by choosing New Project Wizard (File menu).
3.
Click Next in the Introduction if you have not turned it off
previously.
4.
Browse to your working directory and select the SinGen.vqm file.
Click Open. The project and name top-level design entity boxes are
filled in automatically.
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6.
Altera Corporation
Choose Start Compilation (processing menu) to begin compilation.
Double-click Floorplan View in the SinGen Compilation Report
window to view the results of the compilation.
Figure 22 shows the Quartus II compilation results in the Floorplan view.
The shift register of depth 2 and width 16 (Delay block in Simulink) is
mapped to 32 APEX 20KE logic elements. 33 inputs/outputs are used to
bring data and clock signals into the device.
39
2
Getting Started
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 22. Quartus II Floorplan View
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5. Perform RTL Simulation with the ModelSim Software
SignalCompiler generates a a simulation script, Tb_SinGen.tcl, and a
VHDL testbench that imports the Simulink input stimuli, Tb_
SinGen.vhd. You can use these files in the ModelSim software to perform
RTL simulation. To perform RTL simulation with the ModelSim software,
perform the following steps:
1.
Start the ModelSim software.
2.
Choose Change Directory (File menu).
3.
Browse to your working directory and click Open.
4.
Choose Execute Macro (Macro menu).
5.
Browse for the Tb_SinGen.tcl script and click Open.
The simulation results are displayed in a waveform. The simulation
initializes all design registers with a positive pulse on the SRST input
signal.
40
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
The ModelSim waveform editor displays the signals in decimal
(STD_LOGIC_VECTOR(15 DOWNTO 0) notation. You can view the signals
as a digital or analog waveform. Figure 23 shows the simulation.
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Figure 23. VHDL Simulation
2
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Getting Started
Figure 24 shows the analog display.
Altera Corporation
41
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 24. Analog Display
Instantiating IP
in Your Model
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Drag and drop the SignalCompiler block into your design if you
have not already done so.
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For complex signal processing functions, you can use the Altera
MegaCore functions in the MegaCore IP library. To use a MegaCore
function in a new model, perform the following steps:
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2.
42
Double-click the SignalCompiler block and type your working path
into the Working Directory box.
1
You must include the SignalCompiler block in your
Simulink model file and set the working directory for the
MegaCore wizards to operate properly.
3.
Click OK.
4.
Choose Save (File menu).
5.
Drag and drop the MegaCore IP block that you want to use into your
model.
6.
Double-click on the block to launch the MegaCore wizard.
7.
Go through the wizard, setting the parameters that you want to use.
Refer to “MegaCore IP Blocks” on page 93 and to the user guide for
the MegaCore function for more information on how to use the
wizards.
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1
You can download the latest user guides for Altera
MegaCore functions from the Literature section on the
Altera web site.
8.
When the wizard completes, you are returned to the model file.
9.
Choose Save (File menu).
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Figure 25. Example MegaCore IP Design Using the NCO Compiler
Altera Corporation
2
Getting Started
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Figure 25 shows an example design using the NCO compiler MegaCore
function.
43
Specifications
About the DSP
Builder Blocks
or
Altlab
Arithmetic
DSP Board EP20K200EBC652-1X
DSP Board EP20K1500EBC652-1X
Gates
MegaCore IP
Storage
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■
■
■
■
■
■
■
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DSP builder blocks are arranged into sublibraries by functionality. The
following sublibraries are included in the DSP builder:
in
An overview of the block
Parameters
Simulink design example
Simulink scope
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■
■
■
■
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The documentation for each DSP builder block includes the following
information:
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For all blocks, the input buses must be scalar. The sample frequency is set
to 1. For combinatorial blocks such as gates, the output occurs at the same
clock cycle as the input. For registered blocks, the output occurs according
to the phase clock parameter setting.
5
Specifications
Altera Corporation
45
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Block Number
Formats
Getting Started
Table 1 describes the number formats used in the DSP builder. Refer to the
description of each block for the number formats it supports.
Table 1. Number Types
SBF
Description
Notation
Simulink-to-HDL Translation
[L].[R] => [L]—Number of bits
on the left side of the binary
point; the most significant bit
(MSB) is the sign bit.
Signed binary
fractional
representation; a
fractional number
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Signed binary; natural [L] => [L]—Number of bits of A Simulink signed binary signal A[L]
number
the signed bus; the sign bit is translates into VHDL signal sign
the MSB.
STD_LOGIC_VECTOR : signal A :
STD_LOGIC_VECTOR(L - 1 DOWNTO 0)
[L] => [L]—Number of bits of
the unsigned bus.
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Unsigned Unsigned binary;
binary
natural number
[1]
A Simulink unsigned binary signal A[L]
translates into VHDL signal sign
STD_LOGIC_VECTOR : signal A :
STD_LOGIC_VECTOR(L - 1 DOWNTO 0)
A Simulink single bit signal translates into a
VHDL STD_LOGIC signal.
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Single bit Integer that takes the
values 1 or 0.
in
Signed
binary
A Simulink SBF signal A[L].[R] translates into
the VHDL signal sign STD_LOGIC_VECTOR
: signal A : STD_LOGIC_VECTOR(L+R-1
DOWNTO 0)
or
[R]—Number of bits on the
right side of the binary point.
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Number
Type
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Figure 1 graphically compares the signed binary fractional, signed binary,
and unsigned binary number formats
Figure 1. Number Format Comparison
[4].[4] Signed Binary Fractional Notation
7
6
5
4
3
2
1
0
3
2
1
0
3
2
1
0
Sign Bit
8-Bit Signed Integer
7
6
5
4
Sign Bit
8-Bit Unsigned Integer
7
46
6
5
4
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Signed Binary
Fractional
Representation
For hardware implementation, Simulink signals must be formatted into
the desired hardware bus format. Therefore, floating-point values must be
converted to fixed-point values. This conversion is a critical step for
hardware implementation because the number of bits required to
represent a fixed-point value plus the location of the binary point affects
both the size of the hardware resource usage and the system performance.
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Choosing a large number of bits yields excellent performance—the fixedpoint result is almost identical to the floating-point result—but consumes
a large amount of hardware. The designer’s task consists of finding the
right size/performance trade-off. The DSP builder speeds-up the design
cycle by enabling simulation with fixed-point and floating-point signals
in the same environment.
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The AltBus block converts floating-point Simulink signals to fixed-point
signals. The fixed-point signals are represented in signed binary fractional
(SBF) format as shown below:
[number of bits].[]—Represents the number of bits on the left side of
the binary point including the sign bit.
■
[].[number of bits]—Represents the number of bits on the right side of
the binary point.
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In VHDL, the signals are shown as STD_LOGIC_VECTOR. For example,
the 4-bit binary number 1101 is represented as:
This signed integer is equal to –3
VHDL
This signed STD_LOGIC_VECTOR is interpreted as –3
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Simulink
If you change the location of the binary point to 11.01, i.e., 2 bits on the left
side of the binary point and two bits on the right side, the numbers are
represented as:
Simulink
This signed integer is equal to –0.75
VHDL
This signed STD_LOGIC_VECTOR is interpreted as –3
Altera Corporation
47
5
Specifications
From a system-level analysis standpoint, multiplying a number by –0.75
or –3 is obviously very different, especially when looking at the bit width
growth. In the one case the multiplier output bus grows on the MSB, in the
other case the multiplier output bus grows on the LSB.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
In both cases the binary numbers are identical. However, the location of
the binary point affects how a simulator formats the signal representation.
For complex systems, you can adjust the binary point location to define
the signal range and the area of interest.
Hierarchical
Design
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The DSP builder supports hierarchical design via the subsystem
mechanism available in the Simulink software. You can define the
boundaries of each hierarchical level by connecting the Altera AltBus
block to the Simulink Inport/Outport block. The SignalCompiler block
preserves the hierarchy structure in the VHDL design and each MATLAB
or Simulink Model File (.mdl) hierarchical level translates into one VHDL
file.
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Figure 2 illustrates a hierarchy for the sample design fir3tap.mdl, which
implements two FIR filters as described in “Data Width Propagation” on
page 61.
48
Altera Corporation
Getting Started
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 2. Hierarchical Design Example
Altera Corporation
49
5
Specifications
You can add your own VHDL code to the design and specify which
subsystem block(s) should be translated into VHDL by the
SignalCompiler. This process, called black boxing, uses the AltBus block
in Black Box Input Output mode. Set the AltBus Node Type parameter to
Black Box Input Output. When parsing this information, SignalCompiler
processes SubSystem 1 as a black box in the VHDL design. Figure 3
illustrates this concept.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Getting Started
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Figure 3. Using a Black Box
If you use a MegaCore IP block in your model, the IP block is
treated as a black box when SignalCompiler generates HDL
output files.
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Altera Corporation
Altlab Blocks
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AltBus Block
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The AltBus block converts a floating-point Simulink bus to a fixed-point
bus. You can use the AltBus block to connect Simulink blocks and specify
the signed binary fractional dimension. You can insert AltBus into a data
path or you can use it as an I/O delimiter for both inputs and outputs.
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Although the fixed conversion is performed by default by truncating the
LSB and MSB, rounding and saturation are possible and insert additional
RTL logic in the data path. The parameterized rounding and saturation
options are AltBus block parameters.
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Table 1 shows the AltBus parameters.
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Table 1. AltBus Parameters (Part 1 of 2)
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Name
Node Type
Value
Internal Node, Input Port, Output
Port, Constant, Black Box Input,
Black Box Output
Description
Indicate the type of node you wish to create.
Bus Type
Signed Integer, Signed Fractional, Choose the number format of the bus.
Unsigned Integer, or Single Bit
[number of bits].[]
1 - 51
Indicate the number of bits on the left side of the
binary point. including the sign bit. For example, 6.6
stands for a 12-bit sign bus (11 DOWNTO 0), where
the bit 11 is the sign bit. This parameter does not
apply to single bit buses.
[].[number of bits]
0 - 51
Indicate the number of bits on the right side of the
binary point. This parameter only applies to signed
fractional buses.
Altera Corporation
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Altlab Blocks
The blocks in the AltLab library are used to manipulate signals and buses.
For example, the AltBus block converts a floating-point Simulink bus to a
fixed-point bus and can be used to connect Simulink blocks to specify the
signed binary fractional dimension. The SignalCompiler block converts
the Simulink model to an RTL equivalent for synthesis and simulation.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
Table 1. AltBus Parameters (Part 2 of 2)
Name
Value
Description
On or Off
Indicate whether you wish to saturate the signal. With
saturation, if the filtered output is greater than the
maximum positive or negative value able to be
represented, the output is forced (or saturated) to the
maximum positive or negative value.
Round
On or Off
Indicate whether you wish to round the signal. The
output is rounded away from zero.
Bypass Bus Format
On or Off
Turn on this option if you wish to perform simulation in
Simulink using floating-point numbers.
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Input Port & Output Port Modes
Internal Node Mode
Black Box Input Output Mode
Constant Mode
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You can use the AltBus block in a Simulink design in any of the following
modes:
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Input Port & Output Port Modes
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These modes are used to define the boundaries of the hardware
implementation as well as to convert floating-point Simulink signals
(coming from generic Simulink blocks) to signed binary fractional format
(feeding Altera blocks). Figure 1 illustrates how a floating-point number
(4/3 = 1.3333) is converted into SBF format with 3 different binary point
locations:
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■
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[2].[2]—4/3 converts to 1.25
[4].[0]—4/3 converts to 1
[1].[3]—4/3 converts to –0.75 (truncation, the signal overflows to a
negative value)
[1].[3]—4/3 converts to 0.875 (with saturation and rounding turned
on)
Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 1. Floating-Point Conversion
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Altlab Blocks
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Internal Node Mode
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This mode is used to convert a Simulink signal from one SBF format to
another. This mode is used to assign the bus width of an internal node that
will be implemented in hardware. Figure 2 illustrates the usage of AltBus
in Internal Node mode (block InternalNode4.4) and Input Port mode
(block DataIn6.6). In this example a 12-bit bus with a ([6].[6]) SBF format
is converted to an 8-bit bus with a [4].[4] SBF format.
Altera Corporation
Figure 2. Internal Node
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
In VHDL, this operation results in truncating a 12-bit bus (DataIn(11
DOWNTO 0)) to an 8-bit bus (InternalNode(7 DOWNTO 0)) with the
assignment:
InternalNode(7 DOWNTO 0)) <= DataIn(9 DOWNTO 2))
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You can also perform additional internal bus manipulation with the
Altera BusConversion, ExtractBit, or BuildBus blocks.
Black Box Input Output Mode
The pin names of the HDL block must match the pin names of
the Simulink block.
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This AltBus mode is used for hierarchical designs. You should use this
node type if you do not want SignalCompiler to translate the sub-level
design to HDL (i.e., only the top-level symbol appears in the HDL). This
mode is useful when your model has a Simulink block that is associated
with a separate HDL block.
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Figure 3 illustrates the Black Box Input Output mode.
Simulink
Model File
Anaconda
Block
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Figure 3. Black Box Input Output Mode
AltBus
(Black Box
Input Output
Mode)
Non-Anaconda
Block
VHDL
Design File
Altera
Block
For the VHDL subdesign to
work in the VHDL design file,
the signal names in the
HDL design must be the
same as the signal names
in the Simulink model.
VHDL
Subdesign
Constant Mode
Use this mode when a bus or bit must be set to a static value.
SignalCompiler translates the static value to a constant STD_LOGIC or
STD_LOGIC_VECTOR in VHDL. During compilation, the compiler
typically reduces the gate count of any logic fed by this constant signal.
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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The BusBuild block is used to construct buses from single bit inputs. The
output bus is defined in signed binary fractional representation. You can
choose the bus type that you wish to use, and specify the number of bits
on either side of the binary point. The BusBuild and ExtractBit blocks are
typically used when mixing bit-level Boolean operation with arithmetic
operation. The Simulink signal representation of BusBuild is always
signed. The HDL mapping of BusBuild is a simple wire.
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The input MSB (which is the sign bit of the signed binary fractional bus) is
shown at the top left of the symbol and the input LSB is displayed at the
bottom left of the symbol.
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Tables 2 and 3 show the I/O formats and parameters, respectively.
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Table 2. BusBuild I/O Formats
N STD_LOGIC
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HDL
Outputs
Simulink
N = [L]+[R]
SBF ([L].[R])
HDL
STD_LOGIC_VECTOR : N (= L + R)
STD_LOGIC_VECTOR
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n single bit [1]
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Inputs
Simulink
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Table 3. BusBuild Parameters
Name
Bus Type
Value
Description
Signed Integer, Signed Choose the number format of the bus.
Fractional, or Unsigned
Integer
Output [number of bits].[]
1 - 51
Indicate the number of bits on the left side of the binary
point, including the sign bit.
Output [].[number of bits]
0 - 51
Indicate the number of bits on the right side of the binary
point. This parameter only applies to signed binary
fractional buses.
Figure 4 shows a design example using the BusBuild block.
Altera Corporation
55
Altlab Blocks
BusBuild Block
If you use the Simulink Constant block in your Altera design,
you can only use it for simulation.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
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Figure 4. BusBuild Example
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
This block concatenates two buses. The result is AB, where A is the most
significant bit (MSB) slice of the output bus and B is the least significant
bit (LSB) of the output bus. Tables 4 and 5 show the I/O formats and
parameters, respectively.
Table 4. Bus Concatenation I/O Formats
Outputs
Simulink
Bus A (n bits)
Bus B (m bits)
HDL
STD_LOGIC_VECTOR(n-1 DOWNTO 0) HDL
STD_LOGIC_VECTOR(m-1 DOWNTO 0)
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Inputs
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Table 5. Bus Concatenation Parameters
STD_LOGIC_VECTOR((m + n) -1
DOWNTO 0)
Description
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Value
Bus A Width
1 - 51
Bus B Width
1 - 51
Enter the width of the first bus to concatenate.
Output Is Signed
On or Off
Enter the width of the first bus to concatenate.
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Name
m + n bits
or
Simulink
in
Indicate whether the output bus is signed.
BusConversion
Block
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This block converts a bus from one node type to another. Tables 6 and 7
show the I/O formats and parameters, respectively.
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Table 6. BusConversion I/O Formats
Inputs
Outputs
Simulink
N = [L] + [R]
SBF ([L].[R])
Simulink
N = [L] + [R]
SBF ([L].[R])
HDL
STD_LOGIC_VECTOR : N (= L + R)
STD_LOGIC_VECTOR
HDL
STD_LOGIC_VECTOR : N (= L + R)
STD_LOGIC_VECTOR
Table 7. BusConversion Parameters
Name
Value
Description
Input Bus Type
Signed Integer,
Signed Fractional,
Unsigned Integer
Choose the input bus type for the simulation.
Input [number of bits].[]
1 - 51
Indicate the number of bits on the left side of the binary point
including the sign bit.
Altera Corporation
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6
Altlab Blocks
Bus
Concatenation
Block
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
Table 7. BusConversion Parameters
Name
Value
Description
1 - 51
Indicate the number of bits on the right side of the binary
point. This parameter only applies to signed binary fractional
buses.
Output Bus Type
Signed Integer,
Signed Fractional,
Unsigned Integer
Choose the output bus type for the simulation.
Output [number of bits].[]
1 - 51
Indicate the number of bits on the left side of the binary point
Output [].[number of bits]
1 - 51
Indicate the number of bit on the right side of the binary point.
This parameter only applies to signed binary fractional buses.
Input Bit Connected to
Output MSB
0 - 51
Input Bit Connected to
Output LSB
0 - 51
Round
On or Off
Saturate
On or Off
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Input [].[number of bits]
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Indicate whether rounding should be turned on or off.
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Indicate whether saturation should be turned on or off.
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Figure 5 shows a design example using the BusConversion block.
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Figure 5. BusConversion Example
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
ExtractBit Block
The ExtractBit block reads a Simulink bus in signed binary fractional
format and outputs the bit specified with the Extracted Bit parameter.
This block can be enhanced with multiple bit or bus slice extraction.
6
Altlab Blocks
Tables 8 and 9 show the I/O formats and parameters, respectively.
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Table 8. ExtractBit I/O Formats
Inputs
Outputs
N = [L] + [R]
SBF ([L].[R])
HDL
STD_LOGIC_VECTOR : N (= L + R)
STD_LOGIC_VECTOR
0 - 32
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0 - 51
Extracted Bit
Description
Indicate the number of bits on the left side of the binary point, including
the sign bit.
Indicate the number of bits on the right side of the binary point.
Indicate which bit to extract.
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Input [].[number of bits]
STD_LOGIC
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Value
1 - 51
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Single bit [1]
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Table 9. ExtractBit Parameters
Input [number of bits].[]
Simulink
or
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Figure 6 shows a design example using the ExtractBit block.
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Figure 6. ExtractBit Example
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
SignalCompiler
Block
Altlab Blocks
SignalCompiler is the Altera Simulink block that defines the parameters
for conversion of the Simulink model to RTL HDL files. You should add
the SignalCompiler block to your design if you wish to:
■
■
Generate HDL design files of your Simulink design and Tcl scripts
Use a MegaCore function in your Simulink design
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The SignalCompiler block contains parameters such as the target Altera
device family, optimization (speed or area), and synthesis tool
(LeonardoSpectrum or Synplify). You can simulate the design using any
simulator; however, Altera provides an automated flow using Tcl scripts
for the ModelSim PE, SE, and ModelSim-Altera simulators.
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When you turn on the Generate HDL, Perform VHDL Synthesis, and
Compile option and click Apply, SignalCompiler creates RTL HDL
design files and Tcl scripts in your working directory. Then,
SignalCompiler executes the Tcl scripts to perform synthesis with the
synthesis tool that you selected and to compile the design in the Quartus
II software. The results of synthesis and compilation are displayed in the
MATLAB Command Window.
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When you turn on the Generate HDL option and click Apply,
SignalCompiler generates the RTL HDL design files in your working
directory. You can use the files to perform synthesis and compile the
design.
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Table 10 shows the parameters for this block.
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
6
Table 10. SignalCompiler Parameters
Value
Altlab Blocks
Name
Description
APEX 20K, Mercury, Indicate which Altera device family you want to target in your
ACEX 1K,
design.
FLEX 10K
Optimization
Area or Speed
Indicate whether you want to optimize the design for area or
speed.
Synthesis Tool
LeonardoSpectrum
or Synplicity
Indicate which synthesis tool you want to use.
Generate HDL
On or Off
Turn on this option to generate VHDL design files and Tcl scripts
for your design. To regenerate the design files and scripts, you
must turn the option off, click Apply, turn it on, and click Apply.
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Device Family
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You must turn this option off before performing simulation in
Simulink.
To perform simulation in the ModelSim software, turn on the
Generate VHDL Stimuli Files option and then run your
simulation in Simulink. SignalCompiler outputs files for use with
the ModelSim software.
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Generate VHDL Stimuli On or Off
Files
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Generate HDL, Run
On or Off
VHDL Synthesis, Place
and Route
If this option is on, the Simulink simulation runs more slowly than
if it is off. Therefore, you should only turn on this option when you
wish to generate files for use with ModelSim.
Turn on this option to generate VHDL design files and Tcl scripts
for your design and then automatically run the design through
systhesis software and the Quartus II software. To regenerate
the design files and scripts and rerun synthesis and place and
route, you must turn the option off, click Apply, turn it on, and
click Apply.
You must turn this option off before performing simulation
Simulink.
Working Directory
User Specified
Indicate your current working directory; the HDL output files are
created in this directory.
Data Width Propagation
During the Simulink-to-VHDL conversion, SignalCompiler assigns a bit
width value to all of the Altera blocks in the design. You can specify the
bit width value of an Altera block in the Simulink design, for example by
using the AltBus block. However, you do not need to specify the bit width
value of each block; SignalCompiler propagates the bit width information
from the source of a data path to its destination.
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
The design fir3tapsub.mdl, which is provided in the
<path>\DSPBuilder\DesignExamples\GettingStarted\Fir3Tap
directory, illustrates the bit width propagation. The fir3tapsub.mdl
design is a 3-tap finite impulse response (FIR) filter. See Figure 7
Before simulating the model or generating HDL files, ensure that
the path to your working directory is set up properly. The
Working Directory field is case-sensitive. The default working
directory used in the model is:
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c:\MegaCore\DSPBuilder\DesignExamples\
GettingStarted\Fir3Tap
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The input data signal is an 8-bit bus (AltBus) in SBF format [4].[4].
The output data signal is also an 8-bit bus in SBF format [4].[4].
Three delay blocks are used to build the tapped delay line.
The coefficient values are {1, -5, 1}. A Gain block performs the
coefficient multiplication.
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■
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Figure 7. 3-Tap FIR Filter
Figure 8 shows the RTL representation (in the Synplify software) of
fir3tapsub.mdl created by SignalCompiler.
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 8. 3-Tap FIR Filter in RTL View (Synplify Software)
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Tapped Delay Line
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The bit width propagation mechanism starts at the source of the data path,
in this case at the AltBus block iAltBuss, which is an 8-bit input bus.
This bus feeds the register U2, which feeds U3, which feeds U4.
SignalCompiler propagates the 8-bit bus in this register chain and each
register is 8 bits wide. See Figure 9.
Figure 9. Tap Delay Line in RTL View (Synplify Software)
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
Arithmetic Operation
Figure 10 shows the arithmetic section of the filter, which uses the
equation:
ΣC X
i i
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Where Ci are the coefficients and Xi are the data.
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Figure 10. 3-Tap FIR Filter Arithmetic Operation in RTL View (Synplify
Software)
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
■
Multiplying a × b in SBF format is equal to:
[la].[ra] × [lb].[rb]
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The bus width of the resulting signal is:
[la]+[lb].[ra]+[rb]
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Adding a + b + c in SBF format is equal to:
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[la].[ra] + [lb].[rb] + [lc].[rc]
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The bus width of the resulting signal is:
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max([la], [lb], [lc])+2 . max([ra], [rb], [rc])
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The output bit width of the Gain blocks gain and gain2 – x1.875 is
14 bits, the output bit width of the Gain block gain1 - x5.5 is 16 bits. This
difference is explained by the fact that SignalCompiler uses the optimal
minimum number of bits necessary to code 1.875 and –5.5.
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The parallel adder has tree input buses of 14, 16, and 14 bits. To perform
this addition in binary, SignalCompiler automatically sign extends the
14 bit buses to 16 bits. The output bit width of the parallel adder is 18 bits,
which covers the full resolution.
There are several options that can change the internal bit width resolution
and therefore change the size of the hardware required to perform the
function described in Simulink:
■
■
■
The bit width of the input data can be changed.
The bit width of the output data can be changed and the VHDL
synthesis tool removes the unused logic.
Insert AltBus blocks (using the internal node setting) for specific
nodes.
Figure 13 shows how the AltBus blocks are used to control internal bit
widths. In this example, the output of the Gain block is reduced to 4 bits
(SBF format [2].[2]). The scope displays the functional effect of this
truncation on the coefficient values.
Altera Corporation
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6
Altlab Blocks
The design requires 3 multipliers (AltiMultZ1 and AltiMultZ0) and one
parallel adder (Padder). Arithmetic operation grows the bus width in the
following ways:
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
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Figure 11. 3-Tap Filter with AltBus to Control Bit Widths
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The RTL view displays the effect on the hardware of this truncation. The
parallel adder required has a smaller bit width (4 bits) and the synthesis
tool reduces the size of the multiplier based on a 4-bit output. See
Figure 12
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Figure 12. 3-Tap Filter with AltBus to Control Bit Widths in RTL View (Synplify
Software)
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Clock Assignment
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From a clock standpoint, DSP builder blocks fall into two categories:
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Combinatorial blocks—The output always changes at the same sample
time slot as the input.
Registered blocks—The output changes after a variable number of
sample time slots.
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Figure 13 illustrates DSP builder block combinatorial behaviour. The
Magnitude block translates in VHDL as a combinatorial signal.
SignalCompiler does not add clock pins to this function.
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Figure 13. Magnitude Block
Figure 14 illustrates the registered logic. In the VHDL netlist,
SignalCompiler adds clock pin inputs to this function. The Delay block,
with the depth parameter equal to 3, is converted into a VHDL shift
register with a depth of 3 and an initial value of zero.
Altera Corporation
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Altlab Blocks
As stated in “2. Synthesize & Compile the Design Automatically” on page
36, Simulink designs that use DSP builder blocks work with one clock
domain for synchronous DSP builder blocks. SignalCompiler identifies
synchronous DSP builder blocks such as the Delay block and implicitly
connects the clock, clock enable, and reset signals in the VHDL design for
synthesis. Although your design must use a single clock domain, you can
create a multi-rate design by driving the clock enable signal of the register.
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Altlab Blocks
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Figure 14. Delay Block
The fastest sample rate is an integer multiple of the slower sample
rates. The values are specified in the Clock Phase Selection box in the
Delay dialog box.
The Clock Phase Selection box accepts a binary pattern string to
describe the clock phase selection. Each digit or bit of this string is
processed sequentially on every cycle of the fastest clock. When the
bit is equal to one, the block is enabled; when the bit is equal to zero,
the block is disabled. For example:
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For multi-rate designs—which use blocks with different sample rates—
the DSP builder design rules on the registered Altera block are as follows:
–
1—The delay block is always enabled and captures all data
–
10—The delay block is enabled every other phase and every
passing through the block (sampled at the rate 1).
–
other data (sampled at the rate 1) passes through.
0100—The delay block is enabled on the second phase out of 4
and only the second data out of 4 (sampled at the rate 1) passes
through. In other words, the data on phases 1, 3, and 4 do not
pass through the Delay block.
Figures 15 and 16 show a Delay block operating at a one quarter rate on
the 1000 and 0100 phases, respectively.
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Altera Corporation
Altlab Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 15. 1000 Phase Delay
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Altlab Blocks
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Figure 16. 0100 Phase Delay
SubSystem
Block
Altera Corporation
You can use the SubSystem block to add a level of hierarchy to your
design. When SignalCompiler converts the model to HDL files, it
generates a separate file for each top-level file and subsystem. For
example, if you have a single top-level file with two subsystems,
SignalCompiler creates 3 output files, one for the top-level model and one
for each of the subsystems.
69
Arithmetic Blocks
7
The Comparator block compares 2 signed buses and returns a single bit.
The block implicitly reads the input data type (e.g., signed binary or
unsigned integer). Tables 1 and and 2 show the I/O formats and
parameters, respectively.
Arithmetic
Blocks
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This library contains two’s complement signed arithmetic blocks such as
multipliers and adders. The data bus format for all arithmetic blocks is
signed binary fractional. For unsigned buses, the bus width must be
extended by 1 bit.
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Comparator
Block
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Table 1. Comparator I/O Formats
Simulink SBF A[aL].[aR], B [bL].[bR]
STD_LOGIC_VECTOR
A(aL+aR-1 DOWNTO 0)
B(bL+bR-1 DOWNTO 0)
Outputs
Simulink Integer 1 or 0
HDL
STD_LOGIC
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Inputs
Name
Operator
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Table 2. Comparator Parameters
Value
a == b, a ~= b, a < b,
a <= b, a >= b, a > b
Description
Indicate which operation you wish to perform on the two buses.
Figure 1 shows an example using the Comparator block.
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Arithmetic Blocks
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Figure 1. Comparator Example
Gain Block
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The pipeline value is implicitly assigned based on the number of unit
delays connected to the output.
The output width is 2 times the input width.
Representation is signed.
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The Gain block generates its output by multiplying its input by a specified
gain factor. You must enter the gain as a numeric value in the Gain
parameter field. The input and gain must be a scalar. One input is
constant.
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The Simulink software also provides a Gain block. If you use the
Simulink Gain block in your model, you can only use it for
simulation; SignalCompiler cannot convert it to HDL.
Tables 3 and 4 show the I/O formats and parameters, respectively.
Table 3. Gain I/O Formats
Inputs
Simulink SBF A[aL].[aR], K [kL].[kR]
HDL
STD_LOGIC_VECTOR
A(aL+aR-1 DOWNTO 0)
K(kL+kR-1 DOWNTO 0)
72
Outputs
Simulink R[aL]+[kL].[kR]+[aR]
HDL
R(aL+aR-1+kL+kR-1 DOWNTO 0)
Altera Corporation
Arithmetic Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Table 4. Gain Parameters
Name
Value
Description
User Defined
Indicate the gain value you want to use as a decimal number. The
gain is masked to the number format (bus type) you select.
Map gain value to
bus type
Signed Integer, Signed Indicate the bus number format you want to use for the gain value.
This option is only available if the Pipeline setting is greater than 1.
Fractional, Unsigned
Integer
[Gain value
number of bits].[]
1 - 51
Select the number of bits on the left side of the binary point,
including the sign bit. This option is only available if the Pipeline
setting is greater than 1.
[].[Gain value
number of bits]
0 - 51
Select the number of bits on the right side of the binary point. This
option is only available if the Pipeline setting is greater than 1. This
option is only available when Signed Fractional is selected.
Pipeline
0-4
The Pipeline value is implicitly assigned based on the number of
unit delays connected to the output.
Use LPM
On or Off
This option is used if you plan to synthesize your design. When the
Use LPM option is turned on, the Gain block is mapped to the
LPM_MULT library of parameterized modules (LPM) function and
the VHDL synthesis tool uses the Altera LPM_MULT
implementation. If the option is turned off, the VHDL synthesis tool
uses the * operator to synthesize the product. If your design does
not need arithmetic boundary optimization—such as connecting a
multiplier to constant combinatorial logic or register balancing
optimization—the LPM_MULT implementation generally yields a
better result for both speed and area.
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Gain Value
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Figure 2 shows an example using the Gain block.
Figure 2. Gain Example
Altera Corporation
73
Arithmetic
Blocks
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7
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Increment
Decrement
Block
Arithmetic Blocks
The Increment Decrement block generates a counting sequence in time.
The output can be a signed integer, unsigned integer, or signed binary
fractional number. For all number formats, the counting sequence
increments/decrements the LSB bit by one. Tables 5 and 6 show the I/O
formats and parameters, respectively. The block has a clock phase
selection control that operates as described in Table 6.
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Table 5. Increment/Decrement I/O Formats
Inputs
Outputs
Clock enable
For unsigned integers:
Simulink
(Integer 1 or 0)
Simulink (UB [L])
HDL
(STD_LOGIC)
(STD_LOGIC_VECTOR(L-1 DOWNTO 0)
or
HDL
For signed integers and signed fractional:
Simulink
(Integer 1 or0)
Simulink (SBF [L].[R])
HDL
(STD_LOGIC)
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Reset
Value
Description
in
Name
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Table 6. Increment/Decrement Parameters
(STD_LOGIC_VECTOR(L+R-1 DOWNTO 0))
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HDL
Choose the number format you wish to use for the bus.
Signed Integer,
Signed Fractional,
Unsigned Integer
<number of bits>.[]
1 - 51
[].<number of bits>
disabled when Unsigned Integer is turned on.
Increment or
Decrement
Indicate whether you wish to count up or down.
Starting Value
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Direction
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Bus Type
User Defined
Enter the value with which to begin counting.
Use Control Inputs
On or Off
Indicate whether you would like to use additional control inputs (clock
enable and reset).
Clock Phase
Selection
User Defined
Phase selection. The delay block is enabled when the phase value is
equal to one of the following options:
1—The delay block is always enabled and captures all data passing
through the block (sampled at the rate 1).
10—The delay block is enabled every other phase and every other
data (sampled at the rate 1) passes through.
0100—The delay block is enabled on the second phase out of 4 and
only the second data out of 4 (sampled at the rate 1) passes
through. In other words, the data on phases 1, 3, and 4 do not pass
through the delay block.
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Altera Corporation
Arithmetic Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 3 shows an example using the Increment/Decrement block.
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Figure 3. Increment/Decrement Example
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Arithmetic
Blocks
Magnitude
Block
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Table 7. Magnitude I/O Formats
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The Magnitude block generates the output as the absolute value of the
input. Table 7 shows the I/O formats for this block.
Inputs
SBF A[aL].[aR]
HDL
STD_LOGIC_VECTOR A(aL+aR-1
DOWNTO 0)
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Simulink
Altera Corporation
Outputs
Simulink SBF A[aL].[aR]
HDL
STD_ULOGIC_VECTOR A(aL+aR
DOWNTO 0)
Figure 4 shows an example using the Magnitude block.
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Arithmetic Blocks
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Figure 4. Magnitude Example
Parallel Adder
Subtractor
Block
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The expected format for the Parallel Adder/Subtractor block is signed
binary fractional (SBF). If the input widths are not the same, the
SignalCompiler sign extends the buses so that they match the largest input
width. The VHDL file created has a optimized, balanced adder tree.
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If you need to add unsigned data, Altera recommends that you use the
BusBuild block to create a bus one bit bigger than the largest input width
with the MSB stuck to zero.
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Tables 8 and 9 show the I/O formats and parameters, respectively.
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Table 8. Parallel Adder/Subtractor I/O Formats
Inputs
Outputs
Simulink SBF A2[a2L].[a2R], A2[a2L].[a2R], AN[anL].[anR]
Simulink SBF Rmax([AiL])+ceil(log2(N)).max([AiR])
HDL
HDL
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
K(kL + kR - 1 DOWNTO 0)
STD_LOGIC_VECTOR
R(max([AiL]) + ceil(log2(N)).max([AiR])
- 1 DOWNTO 0)
Table 9. Parallel Adder/Subtractor Parameters
Name
Value
Description
Number of Inputs
2 - 16
Indicate the number of inputs you wish to use.
Add (+) Sub (-)
User Defined
Specify addtion or substraction operation of each port with the
characters (+) / (-). i.e., for 3 ports +-+ yields a - b + c.
Pipeline
On or Off
When checked the pipeline delay is equal to ceil(log2(number of
inputs)).
76
Altera Corporation
Arithmetic Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 5 shows an example using the Parallel Adder/Subtractor block.
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Figure 5. Parallel Adder/Subtractor Example
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Arithmetic
Blocks
Product Block
The Product block supports two inputs and scalars only (no multidimensional Simulink signals). The output width is 2 times the input
width. Representation is signed.
1
The Simulink software also provides a Product block. If you use
the Simulink Product block in your model, you can only use it for
simulation; SignalCompiler cannot convert it to HDL.
Tables 10 and 11 show the I/O formats and parameters, respectively.
Table 10. Product I/O Formats
Inputs
Outputs
Simulink
SBF A[aL].[aR], B [bL].[bR]
Simulink
R[aL]+[bL].[bR]+[aR]
HDL
SBF A[aL].[aR], B [bL].[bR]
HDL
R(aL+aR+bL+bR-1 DOWNTO 0)
Altera Corporation
77
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Arithmetic Blocks
Table 11. Product Parameters
Name
Value
Description
0-4
The Pipeline value is implicitly assigned based on the number of unit
delays connected to the output.
Use LPM
On or Off
This option is used if you plan to synthesize your design. When the
Use LPM option is turned on, the Product block is mapped to the
LPM_MULT library of parameterized modules (LPM) function and the
VHDL synthesis tool uses the Altera LPM_MULT implementation. If
the option is turned off, the VHDL synthesis tool uses the * native
operator to synthesize the product. If your design does not need
arithmetic boundary optimization—such as connecting a multiplier to
constant combinatorial logic or register balancing optimization—the
LPM_MULT implementation generally yields a better result for both
speed and area.
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Pipeline
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Figure 6 shows an example using the Product block.
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Figure 6. Product Example
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Altera Corporation
APEX DSP Board
EP20K200EBC652-1X
Blocks
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The DSP development board is a prototyping platform that provides
system designers with an economical solution for hardware and software
verification. This rapid prototyping board enables the user to debug and
verify both functionality and design timing. With two analog input and
output channels per board and the ability to combine boards easily with
right angle connectors, the board can be used to construct an extremely
powerful processing system. Combined with DSP IP from Altera and the
Altera Megafunction Partners Program (AMPP™) partners, the user can
solve design problems that formerly required custom hardware and
software solutions.
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A2D_0—Controls A/D converter 0 (J2)
A2D_1—Controls A/D converter 1 (J3)
D2A_0—Controls D/A converter 0 (J5)
D2A_1—Controls D/A converter 1 (J6)
LED0—Controls user LED 0 (D6)
LED1—Controls user LED 1 (D7)
LED2—Controls user LED 1 (D8)
SWITCH0—Controls push-button switch 0 (SW0)
SWITCH1—Controls push-button switch 1 (SW1)
SWITCH2—Controls push-button switch 2 (SW2)
SWITCH3—Controls slider switch 3 (SW3)
SWITCH4—Controls slider switch 4 (SW3)
SWITCH5—Controls slider switch 5 (SW3)
SWITCH6—Controls slider switch 6 (SW3)
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■
■
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
79
8
APEX DSP
Board Blocks
The blocks in this library provide a connection to analog-to-digital (A/D)
converters, digital-to-analog (D/A) converters, LEDs, and switches on the
APEX DSP development board (starter version). You can use these blocks
in your design to control actions on the board. This library contains the
following blocks (see Figure 1):
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
APEX DSP Board Blocks
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Figure 1. APEX DSP EP20K200EBC652-1X Blocks
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Figure 2 shows an example design using the NCO compiler MegaCore
function and board blocks.
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Altera Corporation
APEX DSP Board Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 2. NCO Compiler & Board Blocks
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APEX DSP
Board Blocks
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Altera Corporation
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APEX DSP Board
EP20K1500EBC652-1X
Blocks
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The DSP development board is a prototyping platform that provides
system designers with an economical solution for hardware and software
verification. This rapid prototyping board enables the user to debug and
verify both functionality and design timing. With two analog input and
output channels per board and the ability to combine boards easily with
right angle connectors, the board can be used to construct an extremely
powerful processing system. Combined with DSP IP from Altera and the
Altera Megafunction Partners Program (AMPP™) partners, the user can
solve design problems that formerly required custom hardware and
software solutions.
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A2D_0—Controls A/D converter 0 (J2)
A2D_1—Controls A/D converter 1 (J3)
D2A_0—Controls D/A converter 0 (J5)
D2A_1—Controls D/A converter 1 (J6)
LED0—Controls user LED 0 (D6)
LED1—Controls user LED 1 (D7)
LED2—Controls user LED 1 (D8)
SWITCH0—Controls push-button switch 0 (SW0)
SWITCH1—Controls push-button switch 1 (SW1)
SWITCH2—Controls push-button switch 2 (SW2)
SWITCH3—Controls slider switch 3 (SW3)
SWITCH4—Controls slider switch 4 (SW3)
SWITCH5—Controls slider switch 5 (SW3)
SWITCH6—Controls slider switch 6 (SW3)
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■
■
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
83
8
APEX DSP
Board Blocks
The blocks in this library provide a connection to analog-to-digital (A/D)
converters, digital-to-analog (D/A) converters, LEDs, and switches on the
APEX DSP development board (professional version). You can use these
blocks in your design to control actions on the board. This library contains
the following blocks (see Figure 1):
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
APEX DSP Board Blocks
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Figure 1. APEX DSP EP20K1500EBC652-1X Blocks
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Figure 2 shows an example design using the NCO compiler MegaCore
function and board blocks.
84
Altera Corporation
APEX DSP Board Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 2. NCO Compiler & Board Blocks
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APEX DSP
Board Blocks
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Altera Corporation
85
Gates Blocks
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This library contains boolean operators, which you can use for operations
such as control operations. The sign bit and data bit of the signal buses are
handled at the boolean level.
n-to-1
Multiplexer
Block
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Inputs
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Table 1. n-to-1 Multiplexer I/O Formats
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The n-to-1 Multiplexer block is a n-to-1 full binary bus multiplexer with
one select control. The output width of the multiplexer is equal to the
input width. The block works on any data type and sign extends the
inputs if there is a bit width mismatch. Tables 1 and 2 show the I/O
formats and parameters, respectively.
Outputs
SBF, A[aL].[aR], B [bL].[bR] (Operand A, B)
sel[1] (selector)
Simulink SBF, Rmax([aL],[bL]).max([aR],b[R])
HDL
STD_LOGIC_VECTOR
A(aL+aR-1 DOWNTODOWNTO 0),
B(bL+bR-1 DOWNTO 0) STD_LOGIC sel
HDL
STD_LOGIC_VECTOR
A(max([aL],[bL])+max([aR]
b[R])-1 DOWNTO 0)
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Simulink
Value
9
Description
Number of Inputs
2 to 10
Choose how many inputs you want the multiplexer to
have.
One Hot Select Bus
On or Off
Indicate whether you want to use one-hot selection for
the bus select signal.
Gates Blocks
Name
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Table 2. n-to-1 Multiplexer Parameters
Figure 1 shows an example using the n-to-1 Multiplexer block.
Altera Corporation
87
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Gates Blocks
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Figure 1. n-to-1 Multiplexer Example
Case Statement
Block
in
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The Case Statement block compares the input signal (which must be a
signed or unsigned integer) with a set of case values. The block returns a
boolean bit for each case. The maximum number of outputs is 10. You
must append a comma (,) after each case. For example, for four cases, you
would enter 1,2,3,4, in the Case Values field. Table 3 show the Case
Statement block parameters.
Case Values
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On or Off
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Default Case
Value
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Name
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Table 3. Case Statement Parameters
User
Specified
Description
Turn on this option if you want the default output signal to go high
when the other outputs are false.
Indicate the values with which you want to compare the input. Include
a comma after each value.
Altera Corporation
Gates Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
If Statement
Block
The If Statement block returns a boolean result based on the IF condition
equation. The input arguments—a, b, c, d, e, f, g, h, i, or j—must be signed
or unsigned integers. A single level of parenthesis is supported. The
operators are given in Table 4.
Table 4. Supported If Statement Operators
Operation
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Operator
+
OR
&
AND
$
XOR
=
Equal To
Not Equal To
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Greater Than
Less Than
Table 5. If Statement Parameters
Value
in
Name
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Table 5 shows the If Statement block parameters.
Description
2 - 10
IF
User Defined Indicate the if condition using any of the following operators: +, &, $, =,
~, >, or < and the variables a, b, c, d, e, f, g, h, i, or j.
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On or Off
Altera Corporation
On or Off
Indicate the number of inputs to the If Statement.
This option turns on the false output signal, which goes high if the
condition evaluated by the If Statement is false.
This option enables the n input signal, which you can use to cascade
multiple IF Statement blocks together.
89
9
Gates Blocks
Pr
ELSE Output
ELSE IF Input
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Number of Inputs
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Logical Bit
Operator Block
Gates Blocks
The input to this block is a single bit. If the integer is positive, it is
interpreted as a boolean 1, otherwise it is interpreted as 0. The number of
inputs is variable. Tables 6 and 7 show the I/O formats and parameters,
respectively.
Table 6. Logical Bit Operator I/O Formats
Outputs
Simulink
n single bit [1] (n operand)
Simulink
HDL‘
n STD_LOGIC
HDL
Name
Value
AND, OR, XOR, NAND, NOR, or
NOT
Number of Inputs
2 - 16
Description
Indicate which operator you wish to use.
Indicate the number of inputs.
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Logical Operator
Single bit [1]
STD_LOGIC
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Table 7. Logical Bit Operator Parameters
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Inputs
in
Figure 2 shows an example using the Logical Bit Operator block.
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Figure 2. Logical Bit Operator Example
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Altera Corporation
Gates Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Logical Bus
Operator Block
This block performs logical operations on a signed binary fractional bus.
You can perform masking (enter in decimal notation) or shifting (indicate
the number of bits). Tables 8 and 9 show the I/O formats and parameters,
respectively.
Table 8. Logical Bus Operator I/O Formats
Outputs
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Inputs
Simulink SBF, A[aL].[aR]
Simulink
SBF, A[aL].[aR]
HDL
HDL
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
Value
nf
Name
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Table 9. Logical Bus Operator Parameters
Description
1 - 51
Indicate the number of bits on the left side of the binary
point, including the sign bit.
[].[number of bits]
0 - 51
Logic Operation
AND, OR, XOR, Invert, Shift
Left, Shift Right, Rotate Left,
Rotate Right
Indicate the logical operation to perform.
Number of Bits to
Shift
User Defined
Indicate how many bits you wish to shift.
Indicate the number of bits on the right side of the binary
point.
Figure 3 shows an example using the Logical Bus Operator block.
9
Gates Blocks
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[numberof bits].[]
Figure 3. Logical Bus Operator Example
Altera Corporation
91
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Gates Blocks
The LUT block stores data as 2(address width) - 1) words of data width on the
left + data width on the right long. The values of the words are specified
in the data vector field:
■
■
-a, b, c, d, where a, b, c, and d are signed binary frational integers in the
address locations 0, 1, 2, 3.
-a, b, c, d, where a, b, c, and d are signed binary frational integers in the
address locations 0, 2, 3, 4. The address location 1 and any others
without a specified location have the value “File Empty
Location”.
1
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LUT Block
If you want to use a Hexadecimal File (.hex) to store data, use the
ROM EAB block not the LUT block.
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Tables 10 and 11 show the I/O formats and parameters, respectively.
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Table 10. LUT I/O Formats
Inputs
Outputs
Simulink SBF, D[dL].[dR] (data bus)
HDL
HDL
STD_LOGIC_VECTOR
A(dL + dR - 1 DOWNTO 0)
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STD_LOGIC_VECTOR
Addr(aL - 1 DOWNTO 0)
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Simulink Unsigned binary, Addr[aL] (Address bus)
Name
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Table 11. LUT Parameters
Value
Description
1 - 51
Indicate the number of data bits stored on the left side of the binary
point including the sign bit.
Data [].[number of bits]
0 - 51
Indicate the number of data bits stored on the right side of the binary
point.
Address Width
2 - 16
Indicate the address width.
Data Vectors
User Defined Specify the values of the words in the data vector values fields.
Pr
Data [number of bits].[]
File Empty Location with User Defined This parameter specifies the default value(s) of this memory location if
you do not specify values for all of the locations of the look-up table.
Use EAB/ESB
On or Off
Matlab Array
User Defined This field must be a one-dimensional MATLAB array with a length
smaller than 2 to the power of the address width. You can specify the
array in the MATLAB Command Window using a variable, or you can
specify it directly in the Matlab Array box.
92
Indicate whether you wish to use embedded array blocks (EABs) in
FLEX 10K devices or embedded system blocks (ESBs) in APEX
devices.
Altera Corporation
MegaCore IP Blocks
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Altera MegaCore functions are rigorously tested and optimized for the
highest performance and lowest cost in Altera programmable logic
devices (PLDs). All MegaCore functions are fully parameterizable
through Altera's unique MegaWizard® Plug-In and Compiler tools and
are delivered in encrypted netlist format.
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The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus II or MAX+PLUS II software and other EDA tools
such as the LeonardoSpectrum and Synplify software. You can verify the
functionality of a megafunction quickly and easily, as well as evaluate its
size and speed before making a purchase decision. You only need to
purchase a license when you are completely satisfied with a core’s
functionality and performance, and would like to generate device
programming files.
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The DSP builder contains evaluation versions of the following cores in the
MegaCore IP library:
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■
■
■
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FFT compiler
FIR compiler
IIR compiler
NCO compiler
Reed-Solomon compiler
Interleaver/deinterleaver
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Some of the IP cores provided in the DSP builder support a
subset of the features that are available in the standard version of
the core. The IP block documentation describes which features
are unavailable in the DSP builder version, and provides screen
shots of the affected core wizard pages. You can download the
standard version of the cores from the Altera web site at
http://www.altera.com/IPmegastore.
10
MegaCore IP
Blocks
Altera Corporation
93
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
FFT Compiler
Block
MegaCore IP Blocks
1
The FFT Compiler block in the DSP builder supports a subset of
the features available in the standard version of the core. The
DSP builder version does not support the external memory
wizard option.
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The Altera fast Fourier transform (FFT) MegaCore function is a
parameterizeable core for high-performance applications that implements
complex input and output transforms for FFT and IFFT. The core uses an
in-place mixed radix of 4 and 2 decimation in frequency architecture, and
implements any transform length that is a power of 2. Partitioning
between radix 4 and radix 2 passes is implemented automatically by the
core’s control unit. When the desired FFT length is a power of 2, the
processor automatically switches between radix 4 and radix 2 processing
to achieve the required transform length.
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For more information, refer to the FFT MegaCore Function User Guide.
FIR Block
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Many digital systems use signal filtering to remove unwanted noise,
provide spectral shaping, or to perform signal detection or analysis. Two
types of filters that provide these functions are FIR filters and infinite
impulse response (IIR) filters. FIR filters are used in systems that require
a linear phase and have inherently stable structure. IIR filters are used in
systems that can tolerate phase distortion. Typical filter applications
include signal preconditioning, band selection, and low-pass filtering. The
FIR compiler speeds up the design cycle by:
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■
■
■
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Finding the coefficients needed to design a particular type of FIR
filter with a particular set of characteristics.
Generating clock-cycle-accurate FIR filter models (also known as bittrue models).
Producing Verilog HDL and VHDL models.
Generating Model Files and M-Files for the MATLAB environment.
Automatically generating the code required for the MAX+PLUS II or
Quartus II software to synthesize high-speed, area-efficient FIR filters
of various architectures.
Creating standard test vectors (i.e., impulse, step, and random input)
to test the response of the FIR filter.
1
The FIR block in the DSP builder supports a subset of the
features that are available in the standard version of the FIR
compiler. For example, the FIR DSP builder block only supports
fixed coefficients and fixed-rate filters; multi-rate filters are not
supported.
The following flow describes the FIR compiler options that are available
with the DSP builder.
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Altera Corporation
MegaCore IP Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
1.
Create the coefficients. Unlike the standalone FIR compiler, you can
only generate new coefficients. See Figure 1.
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Figure 1. Generate the Coefficients
2.
Analyze the coefficients. You only have the option to recreate the
coefficient set or to reload it from a file. See Figure 2.
10
MegaCore IP
Blocks
Altera Corporation
95
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
MegaCore IP Blocks
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Figure 2. Analyze the Coefficients
3.
Make input and output specifications. You have the same options as
in the standard FIR compiler.
4.
Specify the architecture. You cannot specify the number of multiplyaccumulate (MAC) units. Additionally, you only have the option to
create the following architectures:
■
■
■
5.
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Fixed coefficient, fixed rate, fully serial
Fixed coefficient, fixed rate, multi-bit serial
Fixed coefficient, fixed rate, fully parallel
View the simulation display and specify the simulation files. You
have the same options as in the standard FIR compiler.
For more information, refer to the FIR Compiler MegaCore Function User
Guide.
Altera Corporation
MegaCore IP Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
IIR Block
The IIR block in the DSP builder supports a subset of the features
available in the standard version of the core. DSP builder version
does not support the maximum latency option. See Figure 3.
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Figure 3. IIR Simulation Wizard Options
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Digital filters provide an important function in DSP design, and are used
in a wide variety of applications such as signal separation, restoration, or
shaping. The two classes of digital filters are IIR and FIR. IIR filters are
primarily used for high data throughput applications that require a sharp
cut-off characteristic. IIR filters require less hardware than FIR filters and
have a faster response. The IIR structure is well suited to automatic gain
control circuits (AGC), Goertzel algorithm implementation, digital direct
synthesis, or cascaded integrated comb (CIC) filters. Due to poles in their
transfer function, IIR filters are known as feedback systems. The recursive
nature of the IIR filter introduces additional design steps such as the
analysis of phase distortion and finite word-length effects. The IIR
compiler MegaCore function speeds up IIR design cycles by combining
built-in system level analysis tools with a parameterizable IIR MegaCore
function.
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MegaCore IP
Blocks
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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MegaCore IP Blocks
For more information about the IIR compiler and complete instructions on
using the wizard, refer to the IIR Compiler MegaCore Function User
Guide.
NCO Block
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A digital numerically controlled oscillator (NCO) generates a digital
representation of sine and cosine waves. NCOs are typically used as
building blocks in digital signal processing systems such as modulators,
demodulators, digital phase locked loops (PLLs), and symbol recovery
circuits. NCOs can be used to generate a carrier or modulate a signal onto
a carrier.
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The Altera NCO compiler supports both ROM and CORDIC
implementations. In the ROM implementation, a ROM block—
implemented as either a discrete chip or in the ESBs/EABs of Altera
devices—stores the sine or cosine values, and data is output every clock
cycle. ROM implementations are best used for applications that require
higher frequency and lower precision.
For more information, refer to the NCO Compiler MegaCore Function
User Guide.
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For applications that require high precision and low frequency, a
CORDIC implementation, in which the sine and cosine values are created
by the CORDIC algorithm, is most effective. The function uses a very
small ROM and extra clock cycles to perform the calculation. The
CORDIC implementation uses one clock cycle for every bit of data. For
example, 8 data bits require 8 clock cycles to calculate the result.
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Reed Solomon
Block
Reed-Solomon (RS) codes are widely used for error detection and
correction. To use RS codes, a data stream is first broken into a series of
code words. Each code word consists of several information symbols
followed by several check symbols (also known as parity symbols).
Symbols can contain an arbitrary number of bits. The Altera RS compiler
MegaCore function supports four to ten bits per symbol. In an error
correction system, the encoder adds check symbols to the data stream
prior to its transmission over a communications channel. Once the data is
received, the decoder checks for and corrects any errors.
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The Reed Solomon block in the DSP builder supports a subset of
the features available in the standard version of the core. The
DSP builder version supports continuous Reed-Solomon
encoders and decoders. It does not support variable encoders or
decoders and does not support decoders in streaming or discrete
mode. These features are available in the standard version of the
Reed-Solomon compiler.
Altera Corporation
MegaCore IP Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 4 shows the supported/unsupported Reed-Solomon wizard
options.
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Figure 4. Reed-Solomon Wizard Options
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For more information, refer to the Reed-Solomon Compiler MegaCore
Function User Guide.
Interleaving is a standard digital signal processing function used in many
communications systems. Applications that store or transmit digital data
require error correction to reduce the effect of spurious noise that can
corrupt data. Digital communications systems designers can choose many
types of error-correction codes (ECCs) to reduce the effect of errors in
stored or transmitted data. For example, Reed-Solomon
encoders/decoders, which are block-encoding algorithms, are used
frequently to perform forward error correction (FEC).
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Interleaver
Deinterleaver
Block
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Symbol interleaver/deinterleavers can mitigate the effects of burst noise.
Typically, these functions are needed for transport channels that require a
bit error ratio (BER) on the order of 10-6. Interleaving improves the
efficiency of Reed-Solomon encoders/decoders by spreading burst errors
across several Reed-Solomon codewords.
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MegaCore IP
Blocks
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
MegaCore IP Blocks
The Altera symbol interleaver/deinterleaver function uses internal or
external single-port or dual-port RAM. You can implement single-port
RAM using FLEX 10K embedded array blocks (EABs) or an external RAM
device; you can implement dual-port RAM using the dual-port RAM
capability of APEX 20K embedded system blocks (ESBs) or FLEX 10KE
EABs, or an external RAM device. Dual-port RAM provides a faster and
smaller implementation than single-port RAM.
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The Interleaver Deinterleaver block in the DSP builder supports
a subset of the features available in the standard version of the
core. The DSP builder version supports internal memory usage
and block mode only. Convolutional mode is not supported.
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For more information, refer to the Symbol Interleaver/Deinterleaver
MegaCore Function User Guide.
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Altera Corporation
Storage Blocks
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Storage Blocks
Delay Block
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The Delay block works with signed or unsigned data. It delays the
incoming data by the amount specified by the Depth parameter.
Tables 1 and 2 show the I/O formats and parameters, respectively.
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Table 1. Delay I/O Formats
Inputs
SBF, A[aL].[aR]
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
Description
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Value
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Table 2. Delay Parameters
Name
Simulink
HDL
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STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
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Simulink
User Defined Indicate the delay length of the block.
Use Control Inputs
On or Off
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Depth
Indicate that you wish to use additional control inputs (clock enable and
reset).
User Defined Phase selection. The delay block is enabled when the phase value is equal
to one of the following options:
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Clock Phase
Selection
Outputs
1—The delay block is always enabled and captures all data passing
through the block (sampled at the rate 1).
10—The delay block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The delay block is enabled on the second phase out of 4 and only
the second data out of 4 (sampled at the rate 1) passes through. In other
words, the data on phases 1, 3, and 4 do not pass through the delay block.
Figure 1 shows an example using the Delay block.
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Storage Blocks
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Figure 1. Delay Example
Down Sampling
Block
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The Down Sampling block works with signed or unsigned data. The input
data changes at the Simulink sample rate value of the overall design,
which has the value 1.0. The data must appear at the correct sampling rate,
e.g., when down sampling by 4, the output data equals the input data
every fourth clock cycle.
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Tables 3 and 4 show the I/O formats and parameters, respectively.
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Table 3. Down Sampling I/O Formats
Inputs
HDL
SBF, A[aL].[aR]
Simulink
SBF, A[aL].[aR]
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
HDL
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
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Simulink
Outputs
Table 4. Down Sampling Parameters
Name
Down Sampling Rate
Value
1 - 20
Description
Indicate the down sampling rate.
Figure 2 shows an example using the Down Sampling block.
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Altera Corporation
Storage Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 2. Down Sampling Example
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Storage Blocks
Dual-Port RAM
Block
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The Dual-Port RAM block works with signed and unsigned data.
SignalCompiler maps data to the embedded RAM (EABs or ESBs) in
Altera devices. The initial condition of the RAM is zero. The clocking
mechanism works such that all input data (i.e., data, address, and write
enable) are registered; the output data is not.
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Tables 5 and 6 show the I/O formats and parameters, respectively.
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Table 5. Dual-Port RAM I/O Formats
Inputs
Outputs
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Simulink SBF, D[dL].[dR] (data bus)
Simulink Unsigned binary:
ReadAddr[aL], WriteAddr[aL] (Address bus)
SBF:
A[aL].[aR] (data bus)
HDL
Unsigned binary:)
STD_LOGIC_VECTOR
ReadAddr(aL - 1 DOWNTO 0)
WriteAddr(aL - 1 DOWNTO 0)
HDL
STD_LOGIC_VECTOR
A(dL + dR - 1 DOWNTO 0)
SBF:
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Storage Blocks
Table 6. Dual-Port RAM Parameters
Name
Value
Description
2 - 20
Indicate the address width.
Clock Phase
Selection
User Defined Phase selection. The delay block is enabled when the phase value is equal
to one of the following options:
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Address Width
1—The delay block is always enabled and captures all data passing
through the block (sampled at the rate 1).
10—The delay block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
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0100—The delay block is enabled on the second phase out of 4 and only
the second data out of 4 (sampled at the rate 1) passes through. In other
words, the data on phases 1, 3, and 4 do not pass through the delay block.
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Figure 3 shows an example using the Dual-Port RAM block.
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Altera Corporation
Storage Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 3. Dual-Port RAM Example
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Storage Blocks
Pattern Block
The Pattern block synchronizes different data rates between Altera library
blocks. The Pattern block generates a bit sequence in time. For example,
01100 yields 0110001100011000110001100011000110001100 in
time. The bit pattern generator output typically feeds the clock enable
input of data path blocks such as filters or delay units.
Tables 7 and 8 show the I/O formats and parameters, respectively.
Table 7. Pattern I/O Formats
Inputs
Simulink
Altera Corporation
Single bit [1]
Outputs
Simulink
Single bit [1]
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Storage Blocks
Table 7. Pattern I/O Formats
Inputs
HDL
Outputs
STD_LOGIC
HDL
STD_LOGIC
Name
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Table 8. Pattern Parameters
Value
Description
Binary Sequence
User Defined
Indicate the sequence you wish to use.
Use Control Inputs
On or Off
Indicate that you wish to use additional control inputs (clock
enable and reset).
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Figure 4 shows an example using the Pattern block.
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Figure 4. Pattern Example
ROM EAB Block
To use the embedded memory in an Altera device as ROM, use the ROM
EAB block to read in an Intel-format Hexadecimal File (.hex) containing
the ROM data.
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You can use the Quartus II software to generate a HEX File.
Search for “Creating a Memory Initialization File or
Hexadecimal (Intel-Format) File” in Quartus II Help for
instructions on creating this file.
Tables 9 and 10 show the I/O formats and parameters, respectively.
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Altera Corporation
Storage Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Table 9. ROM EAB I/O Formats
Outputs
Simulink
Signed Binary, Unsigned Binary, or SBF
HDL
STD_LOGIC_VECTOR
HDL
STD_LOGIC_VECTOR
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Unsigned Binary
Table 10. ROM EAB Parameters
Name
Storage Blocks
Inputs
Simulink
Value
Description
Signed Integer,
Choose the bus type format.
Signed
Fractional,
Unsigned Integer
[number of bits].[]
1 - 51
Indicate the number of bits stored on the left side of the binary point
including the sign bit.
[].[number of bits]
1-51
Indicate the number of bits stored on the right side of the binary point
including the sign bit. This option only applies to signed fractional
formats.
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Data Bus Type
2 - 20
Indicate the address width.
Clock Phase
Selection
User Defined
Phase selection. The delay block is enabled when the phase value is
equal to one of the following options:
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Address Width
1—The delay block is always enabled and captures all data passing
through the block (sampled at the rate 1).
10—The delay block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The delay block is enabled on the second phase out of 4 and
only the second data out of 4 (sampled at the rate 1) passes through.
In other words, the data on phases 1, 3, and 4 do not pass through the
delay block.
Input Hex File
User Defined;
<filename>.hex
Indiate the name of the HEX File to use.
Figure 5 shows an example using the ROM EAB block.
Altera Corporation
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DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Storage Blocks
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Figure 5. ROM EAB Example
Up Sampling
Block
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This block works with signed or unsigned data. The input data changes at
the up sampling rate value, which is the up sampling factor times the
Simulink sample rate value of the overall design (i.e., 1.0).
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The data must appear at the correct sampling rate. For example, when up
sampling by 3, the output data equals the input data every third clock
cycle and is stuck to zero on all other clock cycles.
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Tables 11 and 12 show the I/O formats and parameters, respectively.
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Table 11. Up Sampling I/O Formats
Inputs
Simulink
HDL
Outputs
SBF A[aL].[aR]
Simulink
SBF A[aL].[aR]
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
HDL
STD_LOGIC_VECTOR
A(aL + aR - 1 DOWNTO 0)
Table 12. Up Sampling Parameters
Name
Up Sampling Rate
Value
1 - 20
Description
Indicate the up sampling rate.
Figure 6 shows an example using the Up Sampling block.
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Altera Corporation
Storage Blocks
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
Figure 6. Up Sampling Example
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Storage Blocks
Altera Corporation
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Appendix
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Figures 1 through 4 show example Tcl scripts created by the
SignalCompiler block for the SinMdl design example described in “DSP
Builder Tutorial” on page 18.
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Figure 1. Example LeonardoSpectrum Tcl Script
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Appendix
Altera Corporation
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Appendix
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Figure 3. Example Quartus II Tcl Script
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Figure 2. Example Synplify Tcl Script
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Altera Corporation
Appendix
DSP Builder Quartus II & MATLAB/Simulink Interface User Guide
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Figure 4. Example ModelSim Tcl Script
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Appendix
Altera Corporation
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