FPGA Features: New Devices
Stratix GX
I/O Standards & Features
Configuration
Devices
Features
Density & Speed
EP1C4
6/03
Now
9/03
EP1C20
EP1C3
5/03
EP1C12
EP1SGX40G
Available Now
1.5 V, 0.13 µm
EP1SGX40D
7/03
EP1SGX25F
EP1SGX10D
7/03
EP1SGX25D
EP1SGX10C
EP1S80
Available Now
Logic Elements (LEs)
RAM (Kbits)
Total RAM Blocks
M512 RAM Blocks (512 bits + parity)
M4K RAM Blocks (4 Kbits + parity)
M-RAM Blocks (512 Kbits + parity)
Speed Grades
Available Embedded Processor
DSP Blocks
9x9 Embedded Multipliers
I/O Registers per Single-Ended Pin
True Dual-Port RAM
Global & Regional Clocks
Phase-Locked Loops (PLLs)/Unique Outputs
HardCopy™ Version Available
Configuration Size (Mbits)
Number of EPCS1 Devices (1 Mbit)
Number of EPCS4 Devices (4 Mbits)
Number of EPC2 Devices (1.7 Mbits)
Number of EPC4 Devices (4 Mbits+)
Number of EPC8 Devices (8 Mbits+)
Number of EPC16 Devices (16 Mbits+)
1.5-V, 1.8-V, 2.5-V & 3.3-V I/O
LVTTL/LVCMOS, 3.3-V PCI & SSTL-2 & -3 Class I & II
LVPECL & HSTL Class I & II & Differential
PCI-X, AGP, GTL+ & CTT
SSTL-18 Class I & II & Differential SSTL
ZBT, DDR, QDR, QDR II & FCRAM
Transceiver (SERDES) Data Rate (Gbps)
Transceiver (SERDES) Channels
True-LVDS™ Rate (Mbps)
True-LVDS Channels (Receive/Transmit)
Embedded Dynamic Phase Alignment (DPA)
Low-speed LVDS Rate (Mbps)
Low-speed LVDS Channels (Receive/Transmit)
LVPECL, PCML & HyperTransport™
On-Chip Termination
Programmable Drive Strength
Cyclone™
1.5 V, 0.13 µm
EP1S60
EP1S40
EP1S30
EP1S25
EP1S20
EP1S10
1.5 V, 0.13 µm
EP1C6
Stratix™
Visit the Altera web site at www.altera.com for the
latest version.
EP1SGX25C
April 7, 2003. This document is revised quarterly.
Available Now
10,570 18,460 25,660 32,470 41,250 57,120 79,040 10,570 10,570 25,660 25,660 25,660 41,250 41,250 2,910 4,000 5,980 12,060 20,060
899 1,630 1,899 3,239 3,344 5,093 7,253 899
899 1,899 1,899 1,899 3,344 3,344
58
76
90
234
288
155
278
364
470
571
872 1,140 155
155
364
364
364
571
571
13
17
20
52
64
94
194
224
295
384
574
767
94
94
224
224
224
384
384
60
82
138
171
183
292
364
60
60
138
138
138
183
183
13
17
20
52
64
1
2
2
4
4
6
9
1
1
2
2
2
4
4
-5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -6, -7
-6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -6, -7, -8 -6, -7, -8 -6, -7, -8 -6, -7, -8 -6, -7, -8
Nios®
6
48
6
Nios
10
80
6
Nios
10
80
6
Nios
12
96
6
Nios
14
112
6
Nios
18
144
6
Nios
22
176
6
Nios
6
48
6
Nios
6
48
6
Nios
10
80
6
Nios
10
80
6
Nios
10
80
6
Nios
14
112
6
Nios
14
112
6
Nios
3
3
3
3
3
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
32
6/32
No
3.53
N/A
N/A
3
1
1
1
32
6/32
No
5.90
N/A
N/A
4
1
1
1
32
6/32
Yes
7.89
N/A
N/A
5
N/A
1
1
32
6/32
No
3.58
N/A
N/A
3
1
1
1
32
6/32
No
3.58
N/A
N/A
3
1
1
1
32
6/32
TBD
7.95
N/A
N/A
5
N/A
1
1
32
6/32
TBD
7.95
N/A
N/A
5
N/A
1
1
32
6/32
TBD
7.95
N/A
N/A
5
N/A
1
1
8
1/3
No
0.63
1
1
1
1
1
1
8
2/6
No
0.93
1
1
1
1
1
1
8
2/6
No
1.17
1
1
1
1
1
1
8
2/6
No
2.32
N/A
1
2
1
1
1
8
2/6
No
3.56
N/A
1
2
1
1
1
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
DDR
DDR
DDR
DDR
DDR
311
34
311
129
311
72
311
103
311
129
✔
✔
✔
✔
✔
40
40
40
40
10/40 12/60 12/60 12/60
Yes
Yes
Yes
Yes
10.38 12.39 17.54 23.83
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7
8
11
15
N/A
N/A
N/A
N/A
1
1
N/A
N/A
1
1
1
1
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
40
40
12/60 12/60
TBD
TBD
12.53 12.53
N/A
N/A
N/A
N/A
8
8
N/A
N/A
1
1
1
1
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Nios
Nios
Nios
Nios
3.1875 3.1875 3.1875 3.1875 3.1875 3.1875 3.1875
4
8
4
8
16
8
20
840
840
840
840
840
840
840 1,000 1,000 1,000 1,000 1,000 1,000 1,000
44/44 66/66 78/78 80/80 80/80 80/80 80/80 22/22 22/22 39/39 39/39 39/39 45/45 45/45
✔
462
2/2
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
462
462
462
10/10 36/36 56/72
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
FPGA Package & I/O Matrix: New Devices
April 7, 2003. This document is revised quarterly. Visit the Altera web site at www.altera.com for the latest version.
EP1C4
Now
9/03
104
672-Pin BGA
426
683
683
683
173
185
185
683
324-Pin FBGA
249
400-Pin FBGA
301
484-Pin FBGA
335
361
672-Pin FBGA
345
426
473
780-Pin FBGA
426
586
597
589
615
706
726
773
330
773
330
426
542
773
249
233
301
426
542
548
548
822 1,022 1,203
FBGA
144
240
672
956
256
324
400
484
672
780
1,020
1,508
Nominal Length x Width (mm)
16x16
22x22
34.6x34.6
35x35
40x40
17x17
19x19
21x21
23x23
27x27
29x29
33x33
40x40
Maximum Surface Area (mm2)
262
493
1,215
1,239
1,616
296
369
449
538
740
853
1,102
1,616
Maximum Height (mm)
1.27
1.60
4.10
3.50
3.50
3.50
3.50
3.50
3.50
3.50
3.50
3.50
3.50
Nominal Lead Pitch (mm)
0.50
0.50
0.50
1.27
1.27
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
Maximum Lead Width (mm)
0.27
0.27
0.27
0.90
0.90
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
✔
✔
✔
✔
Available Now
8-Pin SOIC
20-Pin PLCC
✔
32-Pin TQFP
✔
✔
88-Pin UBGA*
100-Pin PQFP
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified
as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. HyperTransport is a trademark of the HyperTransport
Consortium. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights,
and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the applicationor use of any information, product, or service described herein except as expressly agreed to in writing
by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
EPCS4
Configuration Devices
EPCS1
BGA
EPC16
PQFP
100
SG-FPGAMTRX-1.0
185
473
256-Pin FBGA
TQFP
Available Now
98
240-Pin PQFP
345
EP1C20
EP1C3
6/03
EP1C12
EP1SGX40G
5/03
EP1C6
EP1SGX40D
EP1SGX25F
EP1SGX25D
EP1SGX25C
EP1SGX10D
EP1S80
EP1S60
EP1SGX10C
Available Now
144-Pin TQFP
1,508-Pin FBGA
Number of Pins
7/03
65
1,020-Pin FBGA
Package Statistics
7/03
100-Pin TQFP
956-Pin BGA
FineLine BGA® (F)
EP1S40
EP1S30
EP1S25
EP1S20
Available Now
EPC8
Ball-Grid Array (B)
Cyclone
1.5 V, 0.13 µm
EPC4
Plastic Quad Flat Pack (Q)
Stratix GX
1.5 V, 0.13 µm
EPC2
Thin-Quad Flat Pack (T)
Stratix
1.5 V, 0.13 µm
EP1S10
Device Available Now in Commercial (0 to 85º C) & Industrial
(-40 to 100º C) Temperatures
Device Available Now in Commercial Temperature; Industrial
Temperature Is Scheduled
Device Available Now in Commercial Temperature; Contact
Altera for Industrial Temperature
Device Scheduled for Commercial & Industrial Temperatures
Device Scheduled for Commercial Temperature; Contact
Altera for Industrial Temperature
Vertical Migration (Same VCC , GND, ISP & Input Pins)
✔
✔
✔
✔
✔
Data Compression
✔
✔
✔
Page Mode
✔
✔
✔
Reprogrammable
✔
✔
* UBGA: Ultra FineLine BGA