UTOPIA Level 3 Slave
MegaCore Function
(UTOPIA3SL)
September 2001; ver. 1.01
Data Sheet
Introduction
The UTOPIA Level 3 Slave MegaCore® Function (UTOPIA3SL) is
designed for use in physical layer (PHY) devices that transfer data to and
from asynchronous transfer mode (ATM) devices using the UTOPIA
Level 3 interface as defined by the ATM Forum standard.
Features
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Typical
Application
Configurable for receive or transmit directions
Supports single-PHY (SPHY) and multi-PHY(MPHY) operation
Configurable for up to 31 devices in MPHY mode
Optional configuration of port/address map
Configurable UTOPIA data width of 8, 16, or 32 bits
Configurable AtlanticTM slave interface data width of 8, 16, 32, or 64
bits
Configurable cell transfer length
Optional parity error detection
Optional direct status indication
Quartus® II software and OpenCore® feature allow place-and-route,
and static timing analysis of designs prior to licensing
Secure register transfer level (RTL) simulation models allow
simulation with user design in third-party simulators
Optimized for the Altera® APEXTM 20KE device architecture
Compliant with all applicable specifications, including:
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ATM Forum, UTOPIA 3 Physical Layer Interface Specification, afphy-0136.000, November 1999.
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Altera Corporation, Atlantic Interface Functional Specification.
Figure 1 shows an example system implementation of the UTOPIA3SL
interfacing to an ATM layer device.
Figure 1. Typical Application
UTOPIA
Level 3
Interface
ATM over
SONET/SDH
STS-48c/STM-16
Framer
UTOPIA
Level 3
Interface
Atlantic
Interface
UTOPIA
Level 3
Master
(UTOPIA3MS)
User
Logic
UTOPIA
Level 3
Slave
(UTOPIA3SL)
ATM
Layer
Device
APEX 20K Boundary
Altera Corporation
A-DS-IPUTOPIA3SL-1.01
1
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
Generating
Variants
To obtain a customized UTOPIA3SL variant, send a request to
[email protected] specifying the required parameters. Your
customized UTOPIA3SL will be e-mailed to you as an encrypted gate
level netlist and secure RTL simulation model, in one business day.
Table 1 shows the optional features available to generate all variants of the
UTOPIA3SL.
Table 1. Optional Features
Options
Parameters
Choices
Data flow
DIR
Bus parity
PRTY
RX / TX
Yes / No
Include FIFO buffer
FIFO
Yes / No
UTOPIA data width
UDAT
8 / 16 / 32
Atlantic data width (1)
ADAT
8 / 16 / 32 / 64
Cell length
CLEN
52
53 (n/a for UTOPIA data width of 16 or 32)
54 (n/a for UTOPIA data width of 8 or 32)
56 (n/a for UTOPIA data width of 8 or 16)
MPHY
Yes / No
Multi-PHY
Number of ports (2)
NPORTS
2 - 31 (only valid when MPHY = Yes)
Multi-PHY address
translation (2)
ATRANS
Direct (No translation)
Custom (Port to address mapping)
Direct status mode (3)
DSTAT
Yes / No
Notes:
(1)
(2)
(3)
Interfaces &
Protocols
FIFO buffer required, otherwise Atlantic data width must be equal to UTOPIA data
width.
Only applicable for multi-PHY configuration.
Only available for multi-PHY configuration with up to 4 ports.
UTOPIA Level 3 Interface
The UTOPIA Level 3 interface is an external protocol defined by the ATM
Forum. Depending on the variant chosen (see Table 1), the UTOPIA3SL
uses this interface to support: a data width of 8, 16, or 32 bits, SPHY or
MPHY operation, bus parity, 52, 53, 54, or 56 octet cells, and direct status
or polling mode.
If MPHY = No, the utxaddr[4:0]/urxaddr[4:0] address lines are
not present. If DSTAT = No, the utxclav[3:1]/urxclav[3:1] ports
are not present. If PRTY = No, the utxprty/urxprty ports are not
present.
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Altera Corporation
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
B
For further information on this interface, refer to the ATM Forum,
UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November
1999, available at http://www.atmforum.com.
Atlantic Interface
The Atlantic interface is a full-duplex synchronous bus protocol. The
UTOPIA3SL supports data widths of 8, 16, 32, and 64 bits on the Atlantic
interface. If PRTY = No, the arxpar/atxpar ports are not present.
If the chosen variant of the UTOPIA3SL is configured to include a multicell first in first out (FIFO) buffer for crossing the clock domain, the
Atlantic interface operates as a slave, otherwise it operates as a master.
B
Functional
Description
For further information on this interface, refer to the Atlantic Interface
Functional Specification, available at http://www.altera.com.
The UTOPIA3SL comprises two blocks: the UTOPIA block, and the FIFO
buffer as illustrated in Figures 2 and 3. The following is a list of their
respective functions.
UTOPIA Level 3 Block
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Cell-based handshaking
Cell available status indication
PHY address decoding
UTOPIA data bus parity checking
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Parity error indication
FIFO Buffer
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Data width conversion
Cell-based handshaking
Start of packet (SOP) error detection
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SOP indication
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SOP error indication
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Recovery from invalid cell lengths
End of packet (EOP) generation
Error (ERR) signal generation
Overflow indication
Underflow indication
For both UTOPIA and FIFO buffer sub-blocks, functionality is largely
dependent on the chosen variant, see Table 1.
Altera Corporation
3
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
Figure 2. RXUTOPIA3SL Block Diagram
FIFO Port 0 Clock Domain
UTOPIA Clock Domain
arxclk_0
arxreset_n_0
arxena_0
Atlantic
Interface
FIFO
arxdav_0
Port 0
arxdat_0[63/31/15/7:0]
arxpar_0
arxsop_0
arxerr_0
Global Signals
soc_0
soc_err_0
oflw_err_0
uflw_err_0
UTOPIA
Level 3
Block
FIFO Port N* Clock Domain
urxclk
urxreset_n
urxenb_n
urxaddr[4/3/2/1/0:0]
urxclav[3/0:0]
urxdata[31/15/7:0]
urxprty
urxsoc
prty_err
arxclk_N*
UTOPIA
Level 3
Interface
Global Signal
arxreset_n_N*
arxena_N*
arxdav_N*
Atlantic
Interface arxdat_N*[63/31/15/7:0]
FIFO
Port N* (1)
arxpar_N*
arxsop_N*
arxerr_N*
Global Signals
soc_N*
soc_err_N*
oflw_err_N*
uflw_err_N*
Note:
(1)
N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
RXUTOPIA3SL
I/O Signals
The following is a port list for the RXUTOPIA3SL. The signal direction is
indicated by (I) for input, or (O) for output. N * represents a number from
0 to 31, depending on the number of ports chosen as an option.
Global Signals: prty_err (O), soc_N* (O), soc_err_N* (O),
oflw_err_N* (O), uflw_err_N* (O); UTOPIA Level 3 Interface:
urxclk (I), urxreset_n (I), urxenb_n (I), urxaddr[4/3/2/1/0:0]
(I), urxclav[3/0:0] (O), urxdata[31/15/7:0] (O); urxprty (O);
urxsoc (O); Atlantic Interface: arxclk_N*(I), arxreset_n_N* (I),
arxena_N* (I), arxdav_N* (O), arxdat_N*[63/31/15/7:0] (I),
arxpar_N* (I), arxsop_N* (I), arxerr_N* (I).
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Altera Corporation
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
Figure 3. TXUTOPIA3SL Block Diagram
FIFO Port 0 Clock Domain
atxclk_0
atxreset_n_0
atxena_0
atxdav_0
Atlantic atxdat_0[63/31/15/7:0]
Interface
atxval_0
atxpar_0
atxsop_0
atxeop_0
atxerr_0
UTOPIA Clock Domain
FIFO
Port 0
soc_0
soc_err_0
oflw_err_0
uflw_err_0
Global Signals
UTOPIA
Level 3
Block
FIFO Port N* Clock Domain
utxclk
utxreset_n
utxenb_n
utxaddr[4/3/2/1/0:0]
utxclav[3/0:0]
utxdata[31/15/7:0]
utxprty
utxsoc
prty_err
atxclk_N*
atxreset_n_N*
atxena_N*
atxdav_N*
Atlantic atxdat_N*[63/31/15/7:0]
Interface
atxval_N*
atxpar_N*
atxsop_N*
atxeop_N*
atxerr_N*
Global Signals
UTOPIA
Level 3
Interface
Global Signal
FIFO
Port N* (1)
soc_N*
soc_err_N*
oflw_err_N*
uflw_err_N*
Note:
(1)
N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
TXUTOPIA3SL
I/O Signals
The following is a port list for the UTOPIA3SL. The signal direction is
indicated by (I) for input, or (O) for output. N * represents a number from
0 to 31, depending on the number of ports chosen as an option.
Global Signals: prty_err (O), soc_N* (O), soc_err_N* (O),
oflw_err_N* (O), uflw_err_N* (O); UTOPIA Level 3 Interface:
utxclk (I), utxreset_n (I), utxenb_n (I), utxaddr[4/3/2/1/0:0]
(I), utxclav[3/0:0] (O), utxdata[31/15/7:0] (I), utxprty (I),
utxsoc (I); Atlantic Interface: atxclk_N*(I), atxreset_n_N* (I),
atxena_N* (I), atxdav_N* (O), atxdat_N*[63/31/15/7:0] (O),
atxval_N* (O), atxpar_N* (O), atxsop_N* (O), atxeop_N* (O),
atxerr_N* (O).
Altera Corporation
5
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
Performance
Tables 2 to 4 show the estimated resource utilization and performance for
some sample configurations. The utilization and performance
information was generated with the Quartus II version 1.1 software, for an
APEX 20K400E-1 device
Table 2 lists the estimated resources and speed of a one port
RXUTOPIA3SL and TXUTOPIA3SL.
Utilization
Table 2. One Port Configuration
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3SL
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=No
313
3
160
TXUTOPIA3SL
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=No
315
3
152
Direction
Table 3 lists the estimated resources and speed of a four port
RXUTOPIA3SL and TXUTOPIA3SL.
Utilization
Table 3. Four Port Configuration
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3SL
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
1,189
12
120
TXUTOPIA3SL
PRTY=No, FIFO=Yes, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
1,064
12
150
Direction
Table 4 lists the estimated resources and speed of an RXUTOPIA3SL and
a TXUTOPIA3SL without FIFO buffers.
Utilization
Table 4. No FIFO Buffer Configuration
Performance
Parameters
LE
ESB
fMAX (MHz)
RXUTOPIA3SL
PRTY=No, FIFO=No, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
229
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213
TXUTOPIA3SL
PRTY=No, FIFO=No, UDAT=32, ADAT=32,
CLEN=52, MPHY=Yes, NPORTS=4,
ATRANS=No, DSTAT=No
307
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190
Direction
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Altera Corporation
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
Licensing
A license is not required to perform the following trial operations using
your own custom logic:
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Instantiation
Place-and-route
Static timing analysis
Simulation on a third-party simulator
Licenses are required to generate programming files. When you are ready,
contact your local Altera sales representative.
Deliverables
All current variants use a single license with ordering code:
PLSM-UTOPIA3SL.
The following elements are provided with the package:
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Data sheet
User guide
Atlantic interface functional specifications
Encrypted gate level netlist
Place-and-route constraints (where necessary)
Secure RTL simulation model
Demo testbench
Access to problem reporting system
L To obtain a customized UTOPIA3SL variant send a request to
[email protected] specifying the required parameters:
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Altera Corporation
DIR
PRTY
FIFO
UDAT
ADAT
CLEN
MPHY
NPORTS
ATRANS
DSTAT
Remember to include your preferred return e-mail address as
your customized UTOPIA3SL will be e-mailed to you as an
encrypted gate level netlist and secure RTL simulation model, in
one business day.
7
UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) Data Sheet
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