Stratix PCI
Development Board
May 2003, ver. 1.0
Features
Data Sheet
The Stratix™ PCI development board is a Stratix-device-based evaluation
and development platform for PCI, PCI-X, DDR SDRAM, and 10/100
Ethernet.
Components
■
■
■
■
■
■
■
Designed to accept the following Stratix device
–
EP1S25F1020
Short-form universal PCI (3.3 or 5.0 V) card
–
32-bit or 64-bit PCI per the PCI Local Bus Specification Revision 2.3
at 33 or 66 MHz
–
133-MHz PCI-X Revision 2.0 mode 1
Memory
–
256-MByte PC333 DDR SDRAM (SODIMM)
–
64-Mbit AMD DL-type, boot-block flash
FPGA device configuration
–
User-selectable on power-up via flash memory and the
EPM3256ATC144 device
–
Via ByteBlaster II download cable
Flexible clocking options
–
Socketed 33-MHz system clock oscillator
–
Socketed 100-MHz high-speed clock oscillator
–
SMA connector clock input
Switches and indicators
–
Four user-definable pushbutton switches
–
Eight-position user-definable dipswitch
–
Eight user-definable LEDs
Flexible power options
– PCI connector
– External power supply via adaptor cable
Expansion Interfaces
■
■
■
■
Altera Corporation
DS-PCIDVBD-1.0
Expansion Prototype Card (PROTO1)
10/100 Ethernet (RJ-45 connector)
Serial RS-232 (DB-9 connector)
Optrex LCD connector
1
Stratix PCI Development Board Data Sheet
Debugging Interfaces
■
■
Handling the
Board
General
Description
JTAG
32-bit Mictor probe
Observe the following precautions when handling the board.
■
Static Discharge Precaution—The board can be damaged without
proper anti-static handling; therefore, take anti-static precautions
while handling it.
■
Power Supply Precaution—The board has special power supply
circuitry that can be damaged if more than one power source is
applied to the board at the same time.
■
Environmental Requirements—The board should be stored between
-40° and 100° C. The recommended operating temperature is between
0° and 55° C.
The Stratix PCI development board allows designers to evaluate,
demonstrate, and develop system-level designs with PCI, PCI-X, DDR
SDRAM, and 10/100 Ethernet interfaces. Combined with intellectual
property (IP) from Altera and Altera Megafunction Partners Program
(AMPP™) partners, users can solve design problems that formerly
required custom solutions.
Components & Interfaces
Figure 1 shows a top view of the board components and interfaces.
2
Altera Corporation
Stratix PCI Development Board Data Sheet
Figure 1. Stratix PCI Development Board Components & Interfaces
System
Reset (PB3)
User
Pushbutton
DDR SDRAM
Configuration
Switches
(J10)
Done LED (D4)
(PB2, PB4)
User LEDs
Expansion Prototype
(D3, D5, D6,
User
Card (PROTO1)
User
D8, D10, D12,
Reset
(J2, J3, J4)
Dipswitch (S2)
D14, D15)
(PB1)
Test Points
(TP2, TP4,
TP5, TP7)
Power
Connector
(J18)
Ground Test
Point (TP6)
Board Settings
Dipswitch (S1)
Power LEDs
(D11, D13, D9)
ByteBlaster II
Connector (J1)
10/100 Ethernet
MAC/PHY (U11)
Optrex LCD
Interface (J5)
RJ-45 Connector
(RJ1)
Optrex LCD
Power (J19)
High-Speed Clock
Oscillator (J15)
Ground Test
Point (TP1)
Stratix Device
VCCIO Jumper (J20)
Mictor Probe
Connector (J6)
Stratix EP1S25
Device (U2)
RS-232 Activity
LEDs (D1, D2)
System Clock
Oscillator (J14)
RS-232
Connector (J7)
Flash
Memory
(U3)
SMA
(On Back)
Clock
Input (J16)
MAX
Configuration
Controller (U1)
Ground Test
Point (TP18)
Universal PCI &
PCI-X Interface (J11)
PCI Level Converters
(U13 through U22)
(Also on Back)
JTAG Chain
Jumper (J17)
Table 1 describes the major components on the board and the interfaces it
supports.
Altera Corporation
3
Stratix PCI Development Board Data Sheet
Table 1. Stratix PCI Development Board Components & Interfaces (Part 1 of 2)
Type
FPGA
Component/
Interface
Stratix device
Board
Reference
U2
Description
Configurable Stratix device. See Table 2 on page 6.
The EP1S25F1020 device is installed on the board for
the PCI Development Kit, Stratix Edition.
PCI
Memory
Configuration
Clock
Control
User input
PCI connector
J11
Universal PCI and PCI-X interface. See Table 3 on
page 7.
PCI level converters
U13 through
U22
Level converters for 5.0-V PCI compatibility.
DDR connector and
DDR SDRAM
J10
DDR SDRAM connector (SODIMM) with a
256-MByte PC333 DDR SDRAM memory module.
Flash
U3
64-Mbit AMD DL-family boot-block flash.
MAX configuration
controller
U1
Factory-programmed EPM3256ATC144-7 for Stratix
device configuration.
JTAG
J1, J17
JTAG test and control as well as ByteBlaster II
configuration interface. JTAG chain jumper.
Configuration done
LED (D4)
D4
Indicates Stratix configuration is complete.
System clock
oscillator
Installed at
J14
33.333-MHz system clock.
High-speed clock
oscillator
Installed at
J15
100-MHz high-speed reference clock.
SMA clock
J16
Clock input.
System reset
pushbutton switch
PB3
Reset hardware and reconfigure Stratix device.
User reset
pushbutton switch
PB1
User-defined hardware reset.
Board Settings
dipswitch
S1
System settings and configuration selection. See
Table 4 on page 7, Table 5 on page 7, Table 6 on
page 8, Table 7 on page 9, and Table 10 on page 12.
User pushbutton
switches
PB2, PB4
User configurable.
User dipswitch
S2
User configurable.
User output
User LEDs
D3, D5, D6,
D8, D10,
D12, D14,
D15
User configurable.
Power
Power connector
J18
External power supply adaptor.
4
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 1. Stratix PCI Development Board Components & Interfaces (Part 2 of 2)
Type
Power
Test point
Component/
Interface
Board
Reference
Description
+2.5 V power OK
LED
D11
2.5-V power supply indicator.
+1.5 V power OK
LED
D13
1.5-V power supply indicator.
+1.25 V power OK
LED
D9
1.25-V power supply indicator.
+3.3 V
TP4
3.3-V power testpoint.
+5.0 V
TP2
5.0-V power testpoint.
+12 V
TP7
12-V power testpoint.
-12 V
TP5
-12-V power testpoint.
Ground
TP6
Ground test point near DDR SDRAM.
TP18
Ground test point near SMA clock input.
TP1
Ground test point near LCD connector.
Nios peripheral Expansion Prototype J2, J3, J4
Card (PROTO1)
Interface to Expansion Prototype Card (PROTO1).
Display
LCD
J5, J19
Optrex LCD interface. +12-V output for LCD backlight
inverter.
I/O
10/100 Ethernet
U11, RJ1,
OSC1
10/100 Ethernet MAC/PHY. RJ-45 connector,
25-MHz oscillator.
Serial I/O
RS-232
U10, J7
RS-232 serial interface level shifter. DB9 connector.
RS-232 Tx LED
D1
RS-232 transmitter active indicator.
RS-232 Rx LED
D2
RS-232 receiver active indicator.
Mictor Probe
J6
Mictor probe interface for Agilent logic analyzers.
Debug
Functional
Description
Altera Corporation
This section describes the operation of the Stratix PCI development board.
Figure 2 shows a block diagram of the board.
5
Stratix PCI Development Board Data Sheet
Figure 2. Stratix PCI Development Board Block Diagram
PCI
256-MByte DDR SDRAM Memory
System Clock Oscillator
High-Speed Clock Oscilllator
SMA Clock Connector
Pushbutton Switches
Settings Dipswitches
Stratix
Device
User Dipswitches
Jumpers
Expansion Prototype
Card (PROTO1)
Mictor Probe
Debug Connector
10/100 Ethernet
LCD Display Connector
RS-232
64-Mbit Flash Memory
JTAG Connector
MAX Configuration Controller
+3.3 V
Power
Regulators
+2.5 V
+1.5 V
+1.25 V
Status LEDs
User LEDs
Power LEDs
Stratix Device
The Stratix device, located at U2, is connected to all of the components on
the board through appropriate on-chip interfaces and board circuitry.
Users can program the Stratix device to implement their system logic.
Table 2 shows the Stratix device that is installed on the board.
Table 2. Stratix Device
Product Code
PCI-BOARD/S25
f
6
Description
PCI Development Kit, Stratix Edition
Stratix Device
EP1S25F1020
For more information on Stratix devices, refer to the Stratix Programmable
Logic Device Family Data Sheet.
Altera Corporation
Stratix PCI Development Board Data Sheet
PCI
The Stratix PCI development board is compatible with the Altera
pci_mt64, pci_mt32, pci_t64, and pci_t32 MegaCore functions. It
can also be used with PCI and PCI-X IP cores from AMPP partners and
other third-party vendors. The Stratix device and PCI connector (J11)
support PCI revision 2.3 and PCI-X revision 2.0 mode 1 local bus
standards. See Table 3 for details.
Table 3. PCI Support
Application
Width (Bits)
Voltage (V)
Speed (MHz)
PCI
32 and 64
3.3 and 5.0
33 and 66
PCI-X revision 2.0 mode 1
32 and 64
3.3
66, 100, and 133
PCI Level Converters
U13 through U22 are IDT IDTQS3861Q level converters that convert
between 5.0-V PCI backplane signals and Stratix 3.3-V signals.
PCI Operating Mode
Board settings dipswitch S1 sets the PCI operating mode and speed as
shown in Tables 4, 5, and 6.
Table 4. PCI Operating Mode Selection
Board Settings Dipswitch
Switch S1 Position 3 (PSEL)
PCI Operating Mode
Off
PCI-X at the speed shown in Table 6.
On
PCI at the speed shown in Table 5.
Table 5. PCI Operating Speed Selection
Altera Corporation
Board Settings Dipswitch
Switch S1 Position 5 (PCIS)
PCI Operating Speed (MHz)
Off
66
On
33
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Stratix PCI Development Board Data Sheet
Table 6. PCI-X Operating Speed Selection
Board Settings Dipswitch
Switch S1 Position 4 (PCIXS)
PCI-X Operating Speed (MHz)
Off
133
On
66
DDR SDRAM Memory
The Stratix PCI development board was tested with the DDR SDRAM
Memory Controller MegaCore function version 1.2.0. A 256-MByte DDR
SDRAM memory module is installed in the 200-pin SODIMM connector
at J10 and connects to banks 3 and 4 of the Stratix device.
Designers can use other memory modules provided they meet the
following requirements:
■
■
■
200-pin SODIMM DDR SDRAM
PC266 or faster
64 bits (non-ECC) or 72 bits (ECC)
Flash Memory
The flash memory (U3) connects to the Stratix device and the MAX
configuration controller. The flash memory on the board is an Advanced
Micro Devices AM29DL640D 64-Mbit DL-family boot-block device that
connects to the Stratix device and the MAX configuration controller using
LVTTL signals.
The flash memory capacity is 8 MBytes (67,108,864 bits). The flash
memory contains one factory-programmed Stratix configuration image
and the remaining bits can be used to store up to 3 user-defined Stratix
configuration images and general-purpose user data such as Nios boot
code.
The flash memory operates in 8- or 16-bit modes, selected by the MAX
configuration controller and the Stratix device. Both the MAX
configuration controller and the Stratix device have full access to all
signals of the flash memory.
When the MAX configuration controller is not loading a design, it releases
control of the flash memory to the Stratix device, which can then perform
write and read operations on the flash memory.
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Altera Corporation
Stratix PCI Development Board Data Sheet
1
The flash memory has a read access time of 90 ns. Flash write
operations (erase or program) take microseconds or longer to
complete and require the designer to monitor the flash memory
status register for proper operation.
MAX Configuration Controller
The MAX configuration controller (U1) is an Altera EPM3256ATC144
device factory-programmed to configure the Stratix device from the flash
memory. It also allows the Stratix device to read and write the flash
memory in 8- or 16-bit mode. The MAX configuration controller
configures the Stratix device when it is triggered by one of the following
events:
■
■
■
The board powers up
The system reset pushbutton (PB3) is pressed
The Stratix device pulses the CPLD_USER0 signal low
If the load is successful, the configuration done LED (D4) illuminates.
Selecting Configuration Images
1 MByte of flash memory is reserved for each EP1S25F1020 device
configuration image. Table 7 shows how to select configuration images.
f
Refer to the PCI Development Kit, Stratix Edition Getting Started User Guide
for details on the flash memory map for configuration images and
general-purpose user data.
Table 7. Configuration Image Selection
Board Settings Dipswitch
Altera Corporation
Configuration Image
Switch S1 Position 9
(MPGM1)
Switch S1 Position 10
(MPGM0)
Off
Off
Factory-programmed image
Off
On
User image 1
On
Off
User image 2
On
On
User image 3
9
Stratix PCI Development Board Data Sheet
Clocks & Clock Distribution
In addition to the expansion connectors, the Stratix PCI development
board has three clock sources, including two clock oscillators and an SMA
clock input. These clocks can be used to clock components on the board,
including:
■
■
DDR SDRAM
Expansion Prototype Card (PROTO1)
Input Clocks
Table 8 lists the Stratix input clocks and their distribution on the board.
Clocks that are inputs to the Stratix device can be routed to the phase
locked loops (PLLs), depending on the design requirement.
f
Refer to AN 200: Using PLLs in Stratix Devices for more information.
Table 8. Stratix Input Clocks Note (1)
Signal Name
Source Pin
Stratix Pin (U2)
Stratix PLL
PCI_CLK
PCI Connector J11.B16 (through level shifter AM15
U14.13 and U14.11)
-
CLK_OSC_A
J14.5 (socketed 33.333-MHz oscillator)
AM19, A19, T4 (2)
PLL4, PLL5, PLL6
CLK_OSC_B
J15.5 (socketed 100-MHz oscillator)
U29, AK19, U2, C19
PLL2, PLL3, PLL5,
PLL6
CLK_SMA
SMA Clock Input Connector J16.1
T29, AK15
PLL1
CLK_FROM_SCRUZ
Expansion Prototype Card (PROTO1)
D15
-
DDR_CLK_FBIN
Stratix pin D18
D17
PLL5 FB
Note:
(1)
(2)
A global clock input can feed Stratix high-speed PLLs directly. This table shows the direct connections and does not
show the connection via global clock networks.
This signal is also an input to the MAX configuration controller U1.128, Altera Expansion Prototype Card J4.9.
SMA Clock Input
The SMA clock input CLK_SMA can be provided by an external signal
source through the connector J16. Use a 50-ohm signal source and cable
with an LVTTL-type signal (square-wave, with a voltage swing from 0.0
to +3.3 V). The maximum frequency of this input is 166 MHz.
10
Altera Corporation
Stratix PCI Development Board Data Sheet
Stratix Output Clocks
Table 9 lists the Stratix output clocks and their distribution on the board.
Table 9. Stratix Output Clocks
Stratix Source Pin (U2)
Stratix PLL
DDR_CLK0n
Signal Name
A16
PLL5
DDR SDRAM Memory Connector J10.37
Destination
DDR_CLK0p
B16
PLL5
DDR SDRAM Memory Connector J10.35
DDR_CLK1n
A17
PLL5
DDR SDRAM Memory Connector J10.158
DDR_CLK1p
B17
PLL5
DDR SDRAM Memory Connector J10.160
DDR_CLK2n
A18
PLL5
DDR SDRAM Memory Connector J10.91
DDR_CLK2p
B18
PLL5
DDR SDRAM Memory Connector J10.89
DDR_CLK_FBOUT
D18
PLL5
Stratix pin D17
CLK_TO_SCRUZ
AL16
PLL6
Expansion Prototype Card (PROTO1) J4.11
CLK_TO_MAX_A
AJ17
PLL6
MAX Configuration Controller U1.125
Power
The Stratix PCI development board receives power from one of two
sources:
■
■
1
PCI connector J11 supplies +3.3, +5.0, +12.0, and -12.0 V.
Power connector J18 supplies +3.3, +5.0, +12.0, and -12.0 V from the
external power adaptor cable plugged into an optional PC ATX
power supply.
The board has special power supply circuitry that can be
damaged if more than one power source is applied to the board
at the same time.
+2.5-V Regulators
The board contains two voltage regulators that generate +2.5 V from the
+3.3 V power for DDR SDRAM memory. The two voltage regulators U4
and U5 operate in parallel to supply the current required by the +2.5 V
supply. Amplifier U9 equalizes the current flowing through U4 and U5 by
monitoring and matching the current flowing through the resistors R13
and R15. See Figure 3 for more details.
Altera Corporation
11
Stratix PCI Development Board Data Sheet
Figure 3. 2.5-V Regulator
+3.3 V
Voltage Regulator
U4
VIN
VOUT
R13
+2.5 V
Voltage Regulator
U5 V
V
R15
IN
OUT
VREF
U9
Amplifier
+1.5-V Regulator
Linear regulator U7 generates +1.5 V for the Stratix device from +3.3 V.
+1.25-V Regulator
Linear regulator U12 generates +1.25 V for DDR SDRAM memory
termination and reference voltage.
External Power Adaptor Receptacle
J18 is a receptacle for power from a standard PC ATX power supply via
the external power adapter cable. The board settings dipswitch S1 enables
the external power supply as shown in Table 10.
Table 10. External Power Supply Enable
Board Settings Dipswitch
Switch S1 Position 1 (PWR)
Description
Off
Disable external power supply.
On
Enable external power supply.
Stratix Device VCCIO Jumper
J20 selects VCCIO power for banks 1 and 6 of the Stratix device. Set the
jumpers shown in Table 11.
Table 11. Stratix Device VCCIO Jumper
Shunt Connects
J20 pins 3 and 5
Description
Factory-default setting.
J20 pins 4 and 6
12
Altera Corporation
Stratix PCI Development Board Data Sheet
Test Points
Table 12 shows the power test points.
Table 12. Power Supply Test Points
Signal
Name
Board
Reference
Reference
Designator
3.3V
3.3V
TP4
3.3-V power.
5.0V
5.0V
TP2
5.0-V power.
+12V
+12V
TP7
+12-V power.
-12V
-12V
TP5
-12-V power.
TP1
Ground, near the LCD connector.
TP18
Ground, near the DDR SDRAM memory.
TP6
Ground, near the SMA clock input.
GND
Description
Expansion Interface Power Sourcing Capabilities
Table 22 on page 24 shows the power sourcing capability to the Expansion
Prototype Card (PROTO1) interface.
LEDs
The board has 3 power indication LEDs, 3 status LEDs, and 8 user LEDs.
Power LEDs
Table 13 shows the power indication LEDs.
Table 13. Power LEDs
Board Reference
Altera Corporation
Reference
Designator
Color
Description
2.5V
D11
Blue
2.5-V power is on.
1.5V
D13
Blue
1.5-V power is on.
1.25V
D9
Blue
1.25-V power is on.
13
Stratix PCI Development Board Data Sheet
Status LEDs
Table 14 shows the status LEDs.
Table 14. Status LEDs
Board
Reference
Reference
Designator
Color
Description
CONF DONE
D4
TX
D1
Red
RS-232 transmission active.
RX
D2
Red
RS-232 receive active.
Green The Stratix device has been configured
successfully.
User LEDs
D3, D5, D6, D8, D10, D12, D14, and D15 are the user LEDs, as shown in
Table 15. See “User LEDs” on page 32 for instructions on using the LEDs.
Table 15. User LEDs
14
User LEDs
Reference Designator
Color
Description
0
D3
Red
User defined.
1
D5
Red
User defined.
2
D6
Red
User defined.
3
D8
Red
User defined.
4
D10
Red
User defined.
5
D12
Red
User defined.
6
D14
Red
User defined.
7
D15
Red
User defined.
Altera Corporation
Stratix PCI Development Board Data Sheet
Board Settings Dipswitch
Table 16 describes the board settings dipswitch (S1).
Table 16. Board Settings Dipswitch
Board
Reference
Board Settings
Dipswitch
Factory
Default Setting
Description
PWR
Switch S1 Position 1
On
External power supply enable. See Table 10 on page 12.
CLR
Switch S1 Position 2
Off
Reserved.
PSEL
Switch S1 Position 3
On
PCIXS
Switch S1 Position 4
Off
Select PCI speed and mode. See Table 4 on page 7,
Table 5 on page 7, and Table 6 on page 8.
PCIS
Switch S1 Position 5
Off
RUnLU
Switch S1 Position 6
Off
MSEL2
Switch S1 Position 7
On
USE M
Switch S1 Position 8
Off
MPGM1
Switch S1 Position 9
Off
MPGM0
Switch S1 Position 10
Off
Reserved.
Stratix configuration image selection. Select the flash
memory block used to configure the Stratix device. See
Table 7 on page 9.
Pushbutton Switches
Table 17 describes the pushbutton switches on the board.
Table 17. Pushbutton Switches
Board
Reference
Altera Corporation
Reference
Designator
Description
SYS RESET
PB3
Resets the MAX configuration controller and
configures the Stratix device. Resets the Expansion
Prototype Card (PROTO1), if installed.
USER RESET
PB1
User defined.
USER_PB1
PB2
User defined.
USER_PB2
PB4
User defined.
15
Stratix PCI Development Board Data Sheet
User Dipswitch
Table 18 describes the user dipswitch (S2). See “User Dipswitch” on
page 34 for signal connections.
Table 18. User Dipswitch
User Dipswitch (S2)
1..8
Expansion
Interfaces
Description
User defined. These dipswitches are directly connected
to the Stratix device.
The Stratix PCI development board includes the following interfaces:
■
■
■
■
Expansion Prototype Card (PROTO1) Interface
RS-232 Serial Interface
10/100 Ethernet
LCD Display Interface
Expansion Prototype Card (PROTO1) Interface
J2 through J4 allow the Stratix PCI development board to accept optional
boards with a Expansion Prototype Card (PROTO1) interface. Compatible
boards include the Altera Nios Ethernet Development Kit (EDK) daughter
card. Additionally, these connectors can be used as a general purpose
debugging or expansion interface with 40 pins of LVTTL signals.
Table 19 shows the maximum current available to the Expansion
Prototype Card (PROTO1) interface.
Table 19. Maximum Allowed Current Draw for the Expansion Prototype Card
(PROTO1)
f
Voltage (V)
Maximum Current (A)
3.3
4
12
1
Refer to the Nios Development Board, Stratix Edition Data Sheet for details
about the Expansion Prototype Card (PROTO1) interface.
10/100 Ethernet
U11 is an SMSC LAN91C111 10/100 Ethernet MAC/Phy. RJ1 is an RJ-45
connector with integrated magnetics and activity LEDs.
16
Altera Corporation
Stratix PCI Development Board Data Sheet
RS-232 Serial Interface
J7 is a DB-9 connector wired as a RS-232 serial DTE device. U10 shifts the
RS-232 signals to LVTTL levels for connection to the Stratix device.
LCD Display Interface
J5 and J19 allow the Stratix PCI development board to accept an optional
LCD display. Compatible displays include the Optrex
T-51382D064J-FW-P-AA 6.4 display (not included with the kit).
1
Debugging
Interfaces
The LCD Interface shares Stratix signals with the Mictor probe
debug interface. Only one of the interfaces can be used at a time.
The Stratix PCI development board has the debugging interfaces
described in the following sections.
JTAG
J1 provides access to the JTAG chain of the Stratix PCI development
board. Figure 4 shows the JTAG chain. The factory-default setting for the
JTAG bypass jumper sets the chain to loop through the MAX
configuration controller and the Stratix device.
Figure 4. JTAG Chain
JTAG Bypass
Jumper
TDO
JTAG Connector
1
2
3
4
5
6
TDI
TDO
Configuration
Controller
TDI
TDO
Stratix Device
TDI
JTAG Chain Jumper
Table 20 shows the JTAG chain jumper.
Table 20. JTAG Chain Jumper
Shunt Connects
J17 pins 1 and 3
Description
Factory-default setting.
J17 pins 4 and 6
Altera Corporation
17
Stratix PCI Development Board Data Sheet
SignalTap II Logic Analyzer
The JTAG debug interface can also be used for Altera’s SignalTap II logic
analyzer.
f
Refer to AN 175: SignalTap Analysis in the Quartus II Software Version 2.0 for
a description of the SignalTap II logic analyzer.
Mictor Probe
J6 is a Mictor header that provides probing capability for internal Stratix
device signals. The Mictor probe is compatible with Agilent Technologies
E5346A Probe Adapter for use with Agilent Technologies Logic
Analyzers.
1
The Mictor Probe Debug Interface shares Stratix signals with the
LCD Interface. Only one of the interfaces can be used at a time.
The SignalProbe™ feature can be used to route internal Stratix signals to
J6. You do not need to recompile the Stratix design to use the SignalProbe
feature.
f
Using the
Board
Refer to Technical Brief 82: SignalProbe Compilation Enables Fast System
Debugging with the Quartus II Software for a description of the SignalProbe
feature.
When power is applied to the board, the user LEDs flash. At this time, the
Stratix device is automatically configured and, upon successful
configuration, the configuration done LED (D4) illuminates. To configure
the board with a new design, the designer should perform the following
steps, which are explained later in this section.
1.
Apply power to the board.
2.
Configure the Stratix device.
Apply Power
Power can be introduced by one of the following means:
■
■
1
18
Installing the board into a universal PCI slot
Attaching the board to an ATX power supply with the external power
adaptor cable
The board has special power supply circuitry that can be
damaged if more than one power source is applied to the board
at the same time.
Altera Corporation
Stratix PCI Development Board Data Sheet
Operating the Board with an External Power Supply
To operate the board with an external power supply, perform the
following steps:
1.
Insert the small 12-pin connector of the external power supply
adapter cable into J18.
2.
Insert the 20-pin connector into a standard ATX PC power supply.
3.
Set the board settings dipswitch, switch S1 position 1 (PWR), to the
on position. See Table 10 on page 12.
Configuration via the JTAG Interface
After power is applied to the Stratix PCI development board, the Stratix
device can be configured. The JTAG interface permits the Quartus® II
software to load the Stratix device with a user design through the
ByteBlaster II cable. The user design remains in the Stratix device until
power is removed from the board.
To configure the Stratix device using the Quartus II software and the
ByteBlaster II cable, perform the following steps:
1.
Attach the ByteBlaster II cable to J1.
2.
Open the Quartus II SRAM Object File (.sof) that you want to load
into the device, which launches the Quartus II Programmer.
3.
Select ByteBlaster II as the hardware. Search for “Changing the
Hardware Setup” in Quartus II Help for instructions.
4.
Set the mode to JTAG.
5.
Click Start.
1
If the board is installed into a computer’s PCI slot when it is
configured by the ByteBlaster II cable, the computer system
could lock up. If this happens, reset the computer. Do not
shutdown or the configuration will be lost. Restart the computer
to re-enumerate the PCI bus.
Upon successful configuration, the configuration done LED (D4)
illuminates.
f
Altera Corporation
Refer to Quartus II Help for instructions on how to use the ByteBlaster II
cable.
19
Stratix PCI Development Board Data Sheet
Configuration from the Flash Memory
The Stratix device is volatile; therefore, it must be configured each time
power is applied to the board. The Stratix PCI development board has a
non-volatile configuration scheme that automatically configures the
Stratix device with a factory default design, or, if selected, a user design,
after power is applied.
Upon power-up, the configuration circuit, comprised of the
EPM3256ATC144 device and flash memory, configures the Stratix device.
If the settings dipswitch selects a user configuration, the circuit attempts
to load the specified user design. If the load is unsuccessful, the
configuration done LED (D4) does not illuminate and the Stratix device is
not configured.
1
The configuration circuit uses a factory-programmed default
design in the EPM3256ATC144 device. Using the JTAG interface
to program the EPM3256ATC144 device can disable the
configuration circuit, requiring subsequent Stratix
configurations to be performed with the JTAG interface.
1
The factory-programmed default Stratix design resides at a fixed
location of flash memory. Altering this design results in
unspecified board operation upon power -up and can prevent
the configuration circuit from operating, thereby requiring
subsequent Stratix configurations to be performed with the
JTAG interface.
Factory Configuration
The user LEDs blink and the configuration done LED (D4) illuminates
when the factory-programmed design is loaded into the Stratix device.
f
Refer to the PCI Development Kit, Stratix Edition Getting Started User Guide
for details on the factory-programmed design.
Configuration Data
To configure the board, perform the following steps:
1.
Create a .hexout file for your design.
1
2.
20
Refer to Quartus II Help for instructions on creating a
.hexout.
Write the .hexout into flash memory. See the PCI Development Kit,
Stratix Edition Getting Started User Guide for instructions.
Altera Corporation
Stratix PCI Development Board Data Sheet
Pin-Outs &
Signal
Specifications
3.
Select the user configuration with the settings dipswitch.
4.
Force the device to configure by pressing the system reset
pushbutton (PB3).
This section provides the board’s pin-outs and signal specifications.
PCI & PCI-X
J11 is a 3.3/5.0-V universal PCI connector. U13 through U22 are level
converters that reduce 5.0-V PCI backplane signals to allowable
3.3-V ranges. Figure 5 shows the flow of PCI signals between the PCI
connector and the Stratix device.
Figure 5. PCI Level Converters
PCI Connector
Level Converters
Stratix Banks 7 and 8
Table 21 shows the connection of the PCI connector to the Stratix device .
The level converters are not shown.
Table 21. PCI Signals (Part 1 of 3)
PCI Signal
Altera Corporation
PCI Connector (J11) Stratix Pin (U2)
Local Signal
PCI_CLK
B16
AM15 (PLL12)
PCI_RSTn
A15
AL19
PCI_LOCKn
B39
AJ9
LPCI_LOCKn
PCI_INTAn
A6
AM4
LPCI_INTAn
PCI_IDSEL
A26
AK6
LPCI_IDSEL
PCI_REQn
B18
AK3
LPCI_REQn
PCI_GNTn
A17
AL3
LPCI_GNTn
PCI_REQ64n
A60
AC12
LPCI_REQ64n
PCI_ACK64n
B60
AD12
LPCI_ACK64n
PCI_FRAMEn
A34
AM9
LPCI_FRAMEn
PCI_DEVSELn
B37
AL9
LPCI_DEVSELn
PCI_IRDYn
B35
AC18
LPCI_IRDYn
PCI_TRDYn
A36
AL15
LPCI_TRDYn
PCI_STOPn
A38
AL10
LPCI_STOPn
PCI_PAR
A43
AE9
LPCI_PAR
PCI_PAR64
A67
AH13
LPCI_PAR64
PCI_PERRn
B40
AH9
LPCI_PERRn
LPCI_CLK
LPCI_RSTn
21
Stratix PCI Development Board Data Sheet
Table 21. PCI Signals (Part 2 of 3)
PCI Signal
22
PCI Connector (J11) Stratix Pin (U2)
Local Signal
PCI_SERRn
B42
AF9
LPCI_SERRn
PCI_CBEn0
A52
AF10
LPCI_CBEn0
PCI_CBEn1
B44
AD9
LPCI_CBEn1
PCI_CBEn2
B33
AH7
LPCI_CBEn2
PCI_CBEn3
B26
AJ6
LPCI_CBEn3
PCI_CBEn4
B66
AJ13
LPCI_CBEn4
PCI_CBEn5
A65
AK13
LPCI_CBEn5
PCI_CBEn6
B65
AL13
LPCI_CBEn6
PCI_CBEn7
A64
AM13
LPCI_CBEn7
PCI_AD0
A58
AE12
LPCI_AD0
PCI_AD1
B58
AJ12
LPCI_AD1
PCI_AD2
A57
AK12
LPCI_AD2
PCI_AD3
B56
AL12
LPCI_AD3
PCI_AD4
A55
AB11
LPCI_AD4
PCI_AD5
B55
AE11
LPCI_AD5
PCI_AD6
A54
AG11
LPCI_AD6
PCI_AD7
B53
AH11
LPCI_AD7
PCI_AD8
B52
AK11
LPCI_AD8
PCI_AD9
A49
AL11
LPCI_AD9
PCI_AD10
B48
AM11
LPCI_AD10
PCI_AD11
A47
AG10
LPCI_AD11
PCI_AD12
B47
AJ10
LPCI_AD12
PCI_AD13
A46
AK10
LPCI_AD13
PCI_AD14
B45
AK9
LPCI_AD14
PCI_AD15
A44
AC9
LPCI_AD15
PCI_AD16
A32
AK8
LPCI_AD16
PCI_AD17
B32
AL8
LPCI_AD17
PCI_AD18
A31
AM8
LPCI_AD18
PCI_AD19
B30
AJ8
LPCI_AD19
PCI_AD20
A29
AJ7
LPCI_AD20
PCI_AD21
B29
AK7
LPCI_AD21
PCI_AD22
A28
AL7
LPCI_AD22
PCI_AD23
B27
AM7
LPCI_AD23
PCI_AD24
A25
AL6
LPCI_AD24
PCI_AD25
B24
AM6
LPCI_AD25
PCI_AD26
A23
AH5
LPCI_AD26
PCI_AD27
B23
AJ5
LPCI_AD27
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 21. PCI Signals (Part 3 of 3)
PCI Signal
Altera Corporation
PCI Connector (J11) Stratix Pin (U2)
Local Signal
PCI_AD28
A22
AK5
LPCI_AD28
PCI_AD29
B21
AL5
LPCI_AD29
PCI_AD30
A20
AJ4
LPCI_AD30
PCI_AD31
B20
AK4
LPCI_AD31
PCI_AD32
A91
AK22
LPCI_AD32
PCI_AD33
B90
AL22
LPCI_AD33
PCI_AD34
A89
AM22
LPCI_AD34
PCI_AD35
B89
AJ21
LPCI_AD35
PCI_AD36
A88
AK21
LPCI_AD36
PCI_AD37
B87
AL21
LPCI_AD37
PCI_AD38
A86
AH20
LPCI_AD38
PCI_AD39
B86
AJ20
LPCI_AD39
PCI_AD40
A85
AK20
LPCI_AD40
PCI_AD41
B84
AL20
LPCI_AD41
PCI_AD42
A83
AM20
LPCI_AD42
PCI_AD43
B83
AB19
LPCI_AD43
PCI_AD44
A82
AD19
LPCI_AD44
PCI_AD45
B81
AA18
LPCI_AD45
PCI_AD46
A80
AH18
LPCI_AD46
PCI_AD47
B80
AJ18
LPCI_AD47
PCI_AD48
A79
AK18
LPCI_AD48
PCI_AD49
B78
AA15
LPCI_AD49
PCI_AD50
A77
AB15
LPCI_AD50
PCI_AD51
B77
AC15
LPCI_AD51
PCI_AD52
A76
AD15
LPCI_AD52
PCI_AD53
B75
AA14
LPCI_AD53
PCI_AD54
A74
AB14
LPCI_AD54
PCI_AD55
B74
AD14
LPCI_AD55
PCI_AD56
A73
AE14
LPCI_AD56
PCI_AD57
B72
AK14
LPCI_AD57
PCI_AD58
A71
AL14
LPCI_AD58
PCI_AD59
B71
AB13
LPCI_AD59
PCI_AD60
A70
AC13
LPCI_AD60
PCI_AD61
B69
AD13
LPCI_AD61
PCI_AD62
A68
AE13
LPCI_AD62
PCI_AD63
B68
AA12
LPCI_AD63
23
Stratix PCI Development Board Data Sheet
System Configuration
Table 22 shows the PCI system configuration signals.
Table 22. PCI System Configuration Signals
Board
Reference
Board Settings Dipswitch
(S1)
PCI Signal
PCI Connector
(J11)
Attribute
PCIS
Switch S1 Position 5
PCI_M66EN
B49
Ground
PSEL
Switch S1 Position 3
PCI_XCAP
B38
Ground
PCIXS
Switch S1 Position 4
10K resistor to ground
DDR SDRAM Memory
The DDR SDRAM memory module installed at J10 uses SSTL-2 signaling
and termination. A reference voltage of 1.25 V is supplied to banks 3 and
4 for SSTL-2 receiver biasing. Stratix Terminator™ technology performs
termination for the SSTL-2 signals inside the Stratix device. Termination
reference resistors are connected to banks 3 and 4.
On-board resistors provide fly-by termination at the DDR SDRAM
memory connector pins. J10 is the SODIMM connector for the DDR
SDRAM memory. Figure 6 shows the DDR SDRAM memory termination
connections.
Figure 6. DDR SDRAM Memory Termination Connections
Stratix Device Banks 3 & 4
Stratix Terminator Technology
DDR SDRAM Memory Connector
256-MByte DDR SDRAM Memory Module
Fly-By Termination Resistors
Table 23 shows the DDR SDRAM memory and fly-by termination
connections.
Table 23. DDR SDRAM Memory & Fly-By Terminators (Part 1 of 5)
DDR SDRAM Signal
DDR SDRAM
Connector (J10)
Fly-By Terminator
Stratix Pin
(U2)
96
RN29.13
C14
DDR_CLKEN1
95
RN29.14
B14
DDR_CS0n
121
RN12.16
F24
DDR_CLKEN0
24
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 23. DDR SDRAM Memory & Fly-By Terminators (Part 2 of 5)
DDR SDRAM Signal
Altera Corporation
DDR SDRAM
Connector (J10)
Fly-By Terminator
Stratix Pin
(U2)
DDR_CS1n
122
RN12.15
G24
DDR_RASn
118
RN33.11
H22
DDR_CASn
120
RN33.9
H23
DDR_WEn
119
RN33.10
J24
DDR_A0
112
RN33.15
H20
DDR_A1
111
RN33.16
H19
DDR_A2
110
RN31.9
G23
DDR_A3
109
RN31.10
G21
DDR_A4
108
RN31.11
G20
DDR_A5
107
RN31.12
F23
DDR_A6
106
RN31.13
F20
DDR_A7
105
RN31.14
F19
DDR_A8
102
RN31.15
H11
DDR_A9
101
RN31.16
H12
DDR_A10
115
RN33.14
H13
DDR_A11
100
RN29.9
H14
DDR_A12
99
RN29.10
F13
DDR_A13
97
RN29.12
F12
DDR_BA0
117
RN33.12
L21
DDR_BA1
116
RN33.13
J22
DDR_BA2
98
RN29.11
J23
DDR_DQS0
11
RN11.12
C5
DDR_DQS1
25
RN14.10
E7
DDR_DQS2
47
RN20.16
A7
DDR_DQS3
61
RN23.14
D11
DDR_DQS4
133
RN12.10
D20
DDR_DQS5
147
RN18.16
D22
DDR_DQS6
169
RN21.14
B26
DDR_DQS7
183
RN24.12
B27
DDR_DQS8
77
RN26.12
D12
DDR_DM0
12
RN11.11
F7
DDR_DM1
26
RN14.9
F8
DDR_DM2
48
RN20.15
F9
DDR_DM3
62
RN23.13
F10
DDR_DM4
134
RN12.9
D29
DDR_DM5
148
RN18.15
D28
25
Stratix PCI Development Board Data Sheet
Table 23. DDR SDRAM Memory & Fly-By Terminators (Part 3 of 5)
DDR SDRAM Signal
26
DDR SDRAM
Connector (J10)
Fly-By Terminator
Stratix Pin
(U2)
DDR_DM6
170
RN21.13
C30
DDR_DM7
184
RN24.11
E28
DDR_DM8
78
RN26.11
G12
DDR_DP0
71
RN26.16
A11
DDR_DP1
73
RN26.14
B12
DDR_DP2
79
RN26.10
C12
DDR_DP3
83
RN29.16
C13
DDR_DP4
72
RN26.15
D13
DDR_DP5
74
RN26.13
E13
DDR_DP6
80
RN26.9
A13
DDR_DP7
84
RN29.15
B13
DDR_DQ0
5
RN11.16
D5
DDR_DQ1
7
RN11.14
C3
DDR_DQ2
13
RN11.10
E5
DDR_DQ3
17
RN14.16
C4
DDR_DQ4
6
RN11.15
D4
DDR_DQ5
8
RN11.13
A4
DDR_DQ6
14
RN11.9
B4
DDR_DQ7
18
RN14.15
B3
DDR_DQ8
19
RN14.14
D6
DDR_DQ9
23
RN14.12
C6
DDR_DQ10
29
RN17.16
B5
DDR_DQ11
31
RN17.14
C7
DDR_DQ12
20
RN14.13
A5
DDR_DQ13
24
RN14.11
D7
DDR_DQ14
30
RN17.15
A6
DDR_DQ15
32
RN17.13
B6
DDR_DQ16
41
RN17.12
B7
DDR_DQ17
43
RN17.10
D8
DDR_DQ18
49
RN20.14
B8
DDR_DQ19
53
RN20.12
E9
DDR_DQ20
42
RN17.11
A8
DDR_DQ21
44
RN17.9
C9
DDR_DQ22
50
RN20.13
C8
DDR_DQ23
54
RN20.11
D9
DDR_DQ24
55
RN20.10
E11
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 23. DDR SDRAM Memory & Fly-By Terminators (Part 4 of 5)
DDR SDRAM Signal
Altera Corporation
DDR SDRAM
Connector (J10)
Fly-By Terminator
Stratix Pin
(U2)
DDR_DQ25
59
RN23.16
B9
DDR_DQ26
65
RN23.12
D10
DDR_DQ27
67
RN23.10
C10
DDR_DQ28
56
RN20.9
A9
DDR_DQ29
60
RN23.15
B11
DDR_DQ30
66
RN23.11
C11
DDR_DQ31
68
RN23.9
B10
DDR_DQ32
127
RN12.14
A20
DDR_DQ33
129
RN12.12
B20
DDR_DQ34
135
RN15.16
C20
DDR_DQ35
139
RN15.14
E20
DDR_DQ36
128
RN12.13
B21
DDR_DQ37
130
RN12.11
C21
DDR_DQ38
136
RN15.15
D21
DDR_DQ39
140
RN15.13
A22
DDR_DQ40
141
RN15.12
B22
DDR_DQ41
145
RN15.10
C22
DDR_DQ42
151
RN18.14
B23
DDR_DQ43
153
RN18.12
C23
DDR_DQ44
142
RN15.11
A24
DDR_DQ45
146
RN15.9
E22
DDR_DQ46
152
RN18.13
B24
DDR_DQ47
154
RN18.11
D23
DDR_DQ48
163
RN18.10
D24
DDR_DQ49
165
RN21.16
A25
DDR_DQ50
171
RN21.12
C24
DDR_DQ51
175
RN21.10
B25
DDR_DQ52
164
RN18.9
C25
DDR_DQ53
166
RN21.15
D25
DDR_DQ54
172
RN21.11
A26
DDR_DQ55
176
RN21.9
E24
DDR_DQ56
177
RN24.16
C26
DDR_DQ57
181
RN24.14
A28
DDR_DQ58
187
RN24.10
A27
DDR_DQ59
189
RN27.16
D26
DDR_DQ60
178
RN24.15
C27
27
Stratix PCI Development Board Data Sheet
Table 23. DDR SDRAM Memory & Fly-By Terminators (Part 5 of 5)
DDR SDRAM Signal
DDR SDRAM
Connector (J10)
Fly-By Terminator
Stratix Pin
(U2)
DDR_DQ61
182
RN24.13
B28
DDR_DQ62
188
RN24.9
D27
DDR_DQ63
190
RN27.15
E26
Clocks
Table 24 shows the DDR SDRAM memory clocks.
Table 24. DDR SDRAM Memory Clocks
Clock Signal
DDR SDRAM Memory
(J10)
Stratix Pin (U2)
DDR_CLK0N
37
A16
DDR_CLK0P
35
B16
DDR_CLK1N
158
A17
DDR_CLK1P
160
B17
DDR_CLK2N
91
A18
DDR_CLK2P
89
B18
DDR_CLK_FBIN
-
B15, D17
DDR_CLK_FBOUT
-
D18
Flash Memory
Table 25 shows the connections from the flash memory to the Stratix
device and the MAX configuration controller.
Table 25. Flash Memory (Part 1 of 3)
Flash Memory
Signal
28
Flash Memory
(U3)
Stratix Pin
(U2)
MAX
Configuration
Controller (U1)
FLASH_RESETn
12
-
122
FLASH_CEn
26
AM27
60
FLASH_WEn
11
AM28
62
FLASH_WPn
14
-
-
FLASH_OEn
28
AK26
61
FLASH_RDY_BSYn
15
-
63
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 25. Flash Memory (Part 2 of 3)
Flash Memory
Signal
Altera Corporation
Flash Memory
(U3)
Stratix Pin
(U2)
MAX
Configuration
Controller (U1)
FLASH_BYTEn
47
-
65
FLASH_A0
25
AJ26
56
FLASH_A1
24
AK27
55
FLASH_A2
23
AL28
113
FLASH_A3
22
AJ27
112
FLASH_A4
21
AH26
111
FLASH_A5
20
AL27
110
FLASH_A6
19
AC20
109
FLASH_A7
18
AH19
108
FLASH_A8
8
AL26
107
FLASH_A9
7
AH24
106
FLASH_A10
6
AJ24
103
FLASH_A11
5
AJ25
102
FLASH_A12
4
AK25
101
FLASH_A13
3
AL25
100
FLASH_A14
2
AK24
99
FLASH_A15
1
AM25
98
FLASH_A16
48
AM26
81
FLASH_A17
17
AJ22
80
FLASH_A18
16
AJ23
79
FLASH_A19
9
AL24
78
FLASH_A20
10
AH22
75
FLASH_A21
13
AM24
74
FLASH_D0
29
E14
121
FLASH_D1
31
F14
120
FLASH_D2
33
F15
119
FLASH_D3
35
C16
118
FLASH_D4
38
G19
117
FLASH_D5
40
J19
116
FLASH_D6
42
K19
97
FLASH_D7
44
J20
96
FLASH_D8
30
AB20
93
FLASH_D9
32
AF22
92
FLASH_D10
34
AD21
91
FLASH_D11
36
AG23
90
29
Stratix PCI Development Board Data Sheet
Table 25. Flash Memory (Part 3 of 3)
Flash Memory
Signal
Flash Memory
(U3)
Stratix Pin
(U2)
MAX
Configuration
Controller (U1)
FLASH_D12
39
AC21
88
FLASH_D13
41
AD22
87
FLASH_D14
43
AB21
86
FLASH_D15
45
AA21
84
MAX Configuration Controller
U1 is a factory programmed EPM3256ATC144 device. Table 26 shows the
connections between the MAX configuration controller, Stratix device,
and flash memory, which configure the Stratix device.
Table 26. MAX Configuration Controller Connections (Part 1 of 2)
Configuration Signal
MAX Configuration
Controller (U1)
Stratix Pin (U2)
Flash Memory (U3)
DCLK
23
E19
-
EP1S_CONF_DONE
7
G18
-
EP1S_INIT_DONE
141
AE15
-
9
J18
-
EP1S_nSTATUS
8
G16
-
FLASH_RESETn
122
-
12
FLASH_CEn
60
AM27
26
FLASH_WEn
62
AM28
11
FLASH_OEn
61
AK26
28
FLASH_RDY_BSYn
63
-
15
FLASH_BYTEn
65
-
47
FLASH_A0
56
AJ26
25
FLASH_A1
55
AK27
24
FLASH_A2
113
AL28
23
FLASH_A3
112
AJ27
22
FLASH_A4
111
AH26
21
FLASH_A5
110
AL27
20
FLASH_A6
109
AC20
19
FLASH_A7
108
AH19
18
FLASH_A8
107
AL26
8
FLASH_A9
106
AH24
7
EP1S_nCONFIG
30
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 26. MAX Configuration Controller Connections (Part 2 of 2)
Configuration Signal
MAX Configuration
Controller (U1)
Stratix Pin (U2)
Flash Memory (U3)
FLASH_A10
103
AJ24
6
FLASH_A11
102
AJ25
5
FLASH_A12
101
AK25
4
FLASH_A13
100
AL25
3
FLASH_A14
99
AK24
2
FLASH_A15
98
AM25
1
FLASH_A16
81
AM26
48
FLASH_A17
80
AJ22
17
FLASH_A18
79
AJ23
16
FLASH_A19
78
AL24
9
FLASH_A20
75
AH22
10
FLASH_A21
74
AM24
13
FLASH_D0
121
E14
29
FLASH_D1
120
F14
31
FLASH_D2
119
F15
33
FLASH_D3
118
C16
35
FLASH_D4
117
G19
38
FLASH_D5
116
J19
40
FLASH_D6
97
K19
42
FLASH_D7
96
J20
44
FLASH_D8
93
AB20
30
FLASH_D9
92
AF22
32
FLASH_D10
91
AD21
34
FLASH_D11
90
AG23
36
FLASH_D12
88
AC21
39
FLASH_D13
87
AD22
41
FLASH_D14
86
AB21
43
FLASH_D15
84
AA21
45
Table 27 shows the settings connections between the MAX configuration
controller and board settings dipswitch.
Altera Corporation
31
Stratix PCI Development Board Data Sheet
Table 27. Board Settings Dipswitch (S1) Connections
Board
Reference
Board Settings Dipswitch
Signal
MAX
Configuration
Controller (U1)
USE M
Switch S1 Position 8
USE_MPGM
36
MPGM1
Switch S1 Position 9
MPGM1
34
MPGM0
Switch S1 Position 10
MPGM0
35
Table 28 shows the user connections between the MAX configuration
controller and the Stratix device.
Table 28. User Connections
User Signal
MAX Configuration
Controller (U1)
Stratix Pin (U2)
CPLD_USER0
67
AL4
CPLD_USER1
68
AG12
User LEDs
Signals USER_LED0 through USER_LED7 are driven by the Stratix device
through the MAX configuration controller to the user LEDs as shown in
Figure 7 and Table 29. Set the control signal to a logic ‘1’ to illuminate the
LED.
Figure 7. User LED Drive & Control Signals
MAX Configuration
Controller
Stratix
Device
32
Stratix Control Signal
~
~
MAX Configuration
Controller LED Drive Signal
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 29. User LEDs
Label
Reference
Designator
Stratix Device
Control Signal
Stratix Pin
(U2)
MAX
Configuration
Controller Input
(U1)
MAX
Configuration
Controller
Output (U1)
MAX Configuration
Controller LED
Drive Signal
0
D3
USER_LED0
AK28
37
38
USER_LED_DRV0
1
D5
USER_LED1
AH28
137
138
USER_LED_DRV1
2
D6
USER_LED2
AK30
134
136
USER_LED_DRV2
3
D8
USER_LED3
AJ28
132
133
USER_LED_DRV3
4
D10
USER_LED4
AJ29
19
131
USER_LED_DRV4
5
D12
USER_LED5
AK29
16
18
USER_LED_DRV5
6
D14
USER_LED6
AL30
14
15
USER_LED_DRV6
7
D15
USER_LED7
AL29
11
12
USER_LED_DRV7
Board Settings Dipswitch
Table 30 describes the signal names and pin connections for the board
settings dipswitch (S1).
Table 30. Board Settings Dipswitch
Board
Reference
Board Settings Dipswitch
Signal
Destination Pin
PWR
Switch S1 Position 1
MAIN_SW
External power connector J18.6
CLR
Switch S1 Position 2
DEV_CLRn
Stratix pin (U2) AH14
PSEL
Switch S1 Position 3
PCI_XCAP
PCI connector J11.B38
PCIXS
Switch S1 Position 4
PCIS
Switch S1 Position 5
PCI_M66EN
PCI connector J11.B49
RUnLU
Switch S1 Position 6
RUnLU
Stratix pin (U2) AF14
MSEL2
Switch S1 Position 7
SMSEL2
Stratix pin (U2) AE19
USE MPGM
Switch S1 Position 8
USE_MPGM
MAX configuration controller U1.36
MPGM1
Switch S1 Position 9
MPGM1
MAX configuration controller U1.34
MPGM0
Switch S1 Position 10
MPGM0
MAX configuration controller U1.35
Altera Corporation
33
Stratix PCI Development Board Data Sheet
User Dipswitch
Table 31 shows the signal names and pin connections for the user
dipswitch (S2).
Table 31. User Dipswitches
Board Reference
User Dipswitch
Signal
Stratix Pin
(U2)
USER DIPSWITCH 0
Switch 2 Position 1
USER_DIPSW0
AD23
USER DIPSWITCH 1
Switch 2 Position 2
USER_DIPSW1
AE24
USER DIPSWITCH 2
Switch 2 Position 3
USER_DIPSW2
AE23
USER DIPSWITCH 3
Switch 2 Position 4
USER_DIPSW3
AF24
USER DIPSWITCH 4
Switch 2 Position 5
USER_DIPSW4
AC22
USER DIPSWITCH 5
Switch 2 Position 6
USER_DIPSW5
AG24
USER DIPSWITCH 6
Switch 2 Position 7
USER_DIPSW6
AB22
USER DIPSWITCH 7
Switch 2 Position 8
USER_DIPSW7
AF23
Pushbutton Switches
Table 32 shows the signal names and pin connections for the pushbutton
switches.
Table 32. Pushbuttons
Board Reference
Pin
Signal
Stratix Pin (U2)
SYS RESET
PB3.2
SYS_RESETn
AG13
USER RESET
PB1.2
USER_RESETn
AG22
USER_PB1
PB2.2
USER_PB1
AG9
USER_PB2
PB4.2
USER_PB2
AM5
External Power Header
Table 33 shows the connections for J18, the external power header.
Table 33. External Power Header (Part 1 of 2)
Supply Voltage
34
External Power Header (J18)
3.3 V
1, 2, 11, 12
5.0 V
5
+12 V
7
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 33. External Power Header (Part 2 of 2)
-12 V
8
GND
3, 4, 9, 10
MAIN_SW
6
Expansion Prototype Card (PROTO1)
Table 34 shows the Expansion Prototype Card (PROTO1) interface.
Table 34. Expansion Prototype Card (PROTO1) Connectors (Part 1 of 2)
Signal
Altera Corporation
Connector
Stratix Pin (U2)
SYS_RESETN
J3.1
AG13
CLK_TO_SCRUZ
J4.11
AL16 (through resistor R101)
CLK_OSC_A
J4.9
T4 (through resistor R111)
A19 (through resistor R112)
AM19 (through resistor R106)
CLK_FROM_SCRUZ
J4.13
D15
SCRUZ_CARDSELN
J3.38
G28
SCRUZ_IO0
J3.3
T31
SCRUZ_IO1
J3.4
T32
SCRUZ_IO2
J3.5
R29
SCRUZ_IO3
J3.6
R26
SCRUZ_IO4
J3.7
R25
SCRUZ_IO5
J3.8
R24
SCRUZ_IO6
J3.9
R23
SCRUZ_IO7
J3.1
P260
SCRUZ_IO8
J3.1
P251
SCRUZ_IO9
J3.1
R272
SCRUZ_IO10
J3.13
R28
SCRUZ_IO11
J3.14
P27
SCRUZ_IO12
J3.15
P28
SCRUZ_IO13
J3.16
N26
SCRUZ_IO14
J3.17
N25
SCRUZ_IO15
J3.18
P24
SCRUZ_IO16
J3.21
P23
SCRUZ_IO17
J3.23
N28
SCRUZ_IO18
J3.25
N27
SCRUZ_IO19
J3.27
N23
35
Stratix PCI Development Board Data Sheet
Table 34. Expansion Prototype Card (PROTO1) Connectors (Part 2 of 2)
Signal
Connector
Stratix Pin (U2)
SCRUZ_IO20
J3.28
N24
SCRUZ_IO21
J3.29
M25
SCRUZ_IO22
J3.31
M24
SCRUZ_IO23
J3.32
M27
SCRUZ_IO24
J3.33
M26
SCRUZ_IO25
J3.35
L26
SCRUZ_IO26
J3.36
L27
SCRUZ_IO27
J3.37
K25
SCRUZ_IO28
J3.39
K26
SCRUZ_IO29
J2.4
K27
SCRUZ_IO30
J2.5
K28
SCRUZ_IO31
J2.6
J26
SCRUZ_IO32
J2.7
J25
SCRUZ_IO33
J2.8
H26
SCRUZ_IO34
J2.9
H25
SCRUZ_IO35
J2.10
J28
SCRUZ_IO36
J2.11
J27
SCRUZ_IO37
J2.12
H27
SCRUZ_IO38
J2.13
H28
SCRUZ_IO39
J2.14
G27
RS-232
Table 35 shows the RS-232 Serial interface.
Table 35. RS-232 Serial Interface
Connector Signal
Connector Pin
Level Shifter A
Level Shifter B
Stratix Pin (U2)
DB9_TXD
J7.2
U10.14
U10.11
AC14
RS232_TXD
DB9_RXD
J7.3
U10.13
U10.12
AF12
RS232_RXD
DB9_RTS
J7.7
U10.8
U10.9
AF13
RS232_RTS
DB9_CTS
J7.8
U10.7
U10.10
AM14
RS232_CTS
36
Stratix Signal
Altera Corporation
Stratix PCI Development Board Data Sheet
LCD Header
Table 36 shows the LCD header connections.
Table 36. LCD Header
Signal
Altera Corporation
Connector Pin (J5)
Stratix Pin (U2)
MICTOR_CLKE
2
F32
MICTOR_DE0
6
G30
MICTOR_DE1
7
H30
MICTOR_DE2
8
H29
MICTOR_DE3
9
G31
MICTOR_DE4
10
G32
MICTOR_DE5
11
H31
MICTOR_DE6
13
H32
MICTOR_DE7
14
J29
MICTOR_DE8
15
J30
MICTOR_DE9
16
K30
MICTOR_DE10
17
K29
MICTOR_DE11
18
J32
MICTOR_DE12
3
J31
MICTOR_DE13
27
K31
MICTOR_DE14
31
L32
MICTOR_DE15
30
M28
MICTOR_DO0
20
M29
MICTOR_DO1
21
L30
MICTOR_DO2
22
L31
MICTOR_DO3
23
M31
MICTOR_DO4
24
M30
MICTOR_DO5
25
N29
MICTOR_DO6
4
N30
37
Stratix PCI Development Board Data Sheet
JTAG
Table 37 shows the connections to the JTAG header.
Table 37. JTAG
JTAG Signal
JTAG Connector (J1)
JTAG_TCK
1
JTAG_CONN_TDO
9
JTAG_CONN_TDI
3
5
JTAG_TMS
GND
2, 10
3.3V
4, 6
Mictor Header
Table 38 shows the connections to the Mictor header.
Table 38. Mictor Header (Part 1 of 2)
Signal
38
Mictor Header Pin (J6)
Stratix Pin (U2)
MICTOR_CLKO
6
G29
MICTOR_CLKE
5
F32
MICTOR_DE0
37
G30
MICTOR_DE1
35
H30
MICTOR_DE2
33
H29
MICTOR_DE3
31
G31
MICTOR_DE4
29
G32
MICTOR_DE5
27
H31
MICTOR_DE6
25
H32
MICTOR_DE7
23
J29
MICTOR_DE8
21
J30
MICTOR_DE9
19
K30
MICTOR_DE10
17
K29
MICTOR_DE11
15
J32
MICTOR_DE12
13
J31
MICTOR_DE13
11
K31
MICTOR_DE14
9
L32
MICTOR_DE15
7
M28
MICTOR_DO0
38
M29
Altera Corporation
Stratix PCI Development Board Data Sheet
Table 38. Mictor Header (Part 2 of 2)
Signal
Schematics
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
[email protected]
39
Mictor Header Pin (J6)
Stratix Pin (U2)
MICTOR_DO1
36
L30
MICTOR_DO2
34
L31
MICTOR_DO3
32
M31
MICTOR_DO4
30
M30
MICTOR_DO5
28
N29
MICTOR_DO6
26
N30
MICTOR_DO7
24
N31
MICTOR_DO8
22
N32
MICTOR_DO9
20
P29
MICTOR_DO10
18
P30
MICTOR_DO11
16
P31
MICTOR_DO12
14
P32
MICTOR_DO13
12
R32
MICTOR_DO14
10
R31
MICTOR_DO15
8
R30
The subsequent pages provide the schematics for the Stratix PCI
development board.
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service
marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and
other countries. All other product or service names are the property of their respective holders. Altera products
are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and
copyrights. Altera warrants performance of its semiconductor products to current
specifications in accordance with Altera’s standard warranty, but reserves the right to
make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product,
or service described herein except as expressly agreed to in writing by Altera Corporation.
Altera customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services.
All rights reserved.
Altera Corporation
8
7
6
E
2.
3.
4
Altera Stratix Schematic Symbol Breakdown:
(a) Bank1 - HSDI
(b) Bank2 - HSDI
(c) Bank3 - GPIO/DDR/PCI
(d) Bank4 - GPIO/DDR/PCI
(e) Bank5 - HSDI
( f) Bank6 - HSDI
(g) Bank7 - GPIO/DDR/PCI
(h) Bank8 - GPIO/DDR/PCI
(i) Configuration/GPIO
(j) Clocks/GPIO
(k) VCCINT/GND
(l) VCCIO/GND
Board is to be powered from any ONE of the following interfaces at any one time:
(a) PCI Edge Connector
(b) ATX Power Connector
Related Documents
Raw PCB
(a) 100-0216200-01
Gerber Files
(b) 110-0216200-01
PCB Design Files
(c) 120-0216200-01
Assembly Drawing
(d) 130-0216200-01
Fab Drawing
(e) 140-0216200-01
Schematic
( f) 150-0216200-01
Film
(g) 160-0216200-01
BOM
(h) 170-0216200-01
3
REV
506 Parts, 50 Library Parts, 846 Nets, 3967 Pins
NOTES:
1.
5
A
B
2
DATE
PAGES
12/02/2002
02/12/2003
All
10, 13-14,
16-18
1
DESCRIPTION
Changed to Rev A, first fabricated PCB revision.
Modified J8/J9 symbols to add chamfer, Changed J13 symbol TX/RX naming, Pulled
down LAN_ADSn & LAN_LCLK, Labelled RS-232 RX/TX LEDs, Modified 2.5V
Regulator Circuit, Changed B1/B6 VCCIO select fuses to jumpers, Separated
CONF_DONEn LED signal from CONF_DONE config signal, Changed C1/C2 to
47uF.
E
Stratix Package Top View
BANK 4
BANK 3
VCCIO = 2.5V
VCCIO = 2.5V
DDR SDRAM DATA LANES 0, 1, 2, 3
DDR SDRAM ADDRESS, PARITY BITS
DDR SDRAM DATA LANES 4, 5, 6, 7
DDR SDRAM ADDRESS, MASK BITS
D
D
PAGE
BANK 5
VCCIO = 3.3V
BANK 6
SAMTEC QTE-060
EDGE CONNECTOR
1x 8-BIT HIGH-SPEED PORT
Primary PCI
3
PCI Voltage Limit Switches
4
PCI Voltage Switch Bypass Resistors
BANK 2
5
Stratix Bank 7, 8, LEDs
VCCIO = 3.3V
6
DDR SDRAM SO-DIMM
7
DDR-SDRAM Terminations
8
Stratix Bank 2, 5
9
Stratix Bank 3, 4
10
Bank 1 HSDI Top/Bottom Connectors
11
Bank 1 Debug, Bank 6 HSDI Connector
12
Stratix Bank 1, 6
13
10/100 Ethernet Interface
14
Santa Cruz Card, RS-232, LCD Header
15
Clocking, JTAG Bypass Jumper
16
Power
17
CPLD, Flash, Board-Specific DIP Switches
18
Decoupling
19
-
20
-
21
-
22
-
23
-
24
-
25
-
SAMTEC QTE-080
TOP/BOT CONNECTORS
2x 8-BIT HIGH-SPEED PORTS
BANK 8
VCCIO = 3.3V
PCI SIGNALS
FLASH ADDRESS, DATA
USER LEDS
Ground
Title
Stratix PCI Development Board
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
7
Date:
6
B
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
B
8
C
VCCIO = 3.3V
PCI SIGNALS
USER DIPSWITCH
Analog Ground
2
VCCIO = 2.5V -or- 3.3V
BANK 7
A
Title, Notes, Revision History
BANK 1
VCCIO = 2.5V -or- 3.3V
B
1
MICTOR, LCD HEADER
PUSHBUTTONS
SANTA CRUZ DAUGHTERCARD
10/100 MAC/PHY
RS-232 SIGNALS
C
DESCRIPTION
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
1
of
1
18
A
8
7
6
5
Notes:
(1)
(2)
(3)
(4)
(5)
4
3
2
1
Primary PCI
Pin B38 = GND in PCI 2.2 and PCI-XCAP in PCI-X. It can be grounded or 10K pullup here.
Pin A14 = 3.3Vauxin PCI2.2 but is unused for our board and PCI core.
Pins B9 & B11 are power requirement strapping pins. We are strapped for maximum 25W power.
Pin B49 is M66EN and is selectable 33 or 66MHz for PCI via DIPswitch
PMEn pin A19 not connected. Board does not support Power Management features.
E
E
3.3V
5.0V
32-Bit Standard
PCI Connector
-12V
+12V
5.0V
3.3V
J11A
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
D
-12V
TCK
GND1
TDO
+5V1
+5V2
INTBn
INTDn
PRSNT1n
RESERVED1
PRSNT2n
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
TRSTn
+12V
TMS
TDI
+5V5
INTAn
INTCn
+5V6
RESERVED3
VCCIO3
RESERVED4
3,4 PCI_AD[63..0]
3,4 PCI_CBEn[7..0]
3,4 PCI_INTAn
64-bit Extensions
J11B
3.3V Keyway
PCI_CLK 3,4
PCI_REQn 3,4
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_CBEn3
PCI_AD23
C
PCI_AD21
PCI_AD19
PCI_AD17
PCI_CBEn2
PCI_IRDYn 3,4
PCI_DEVSELn 3,4
PCI_XCAP 17
PCI_LOCKn 3,4
PCI_PERRn 3,4
PCI_SERRn 3,4
PCI_CBEn1
PCI_AD14
B
PCI_AD12
PCI_AD10
PCI_M66EN 17
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
RESERVED2
GND2
CLK
GND3
REQn
VCCIO1
AD(31)
AD(29)
GND4
AD(27)
AD(25)
+3.3V1
CBEn(3)
AD(23)
GND5
AD(21)
AD(19)
+3.3V2
AD(17)
CBEn(2)
GND6
IRDYn
+3.3V3
DEVSELn
PCIXCAP
LOCKn
PERRn
+3.3V4
SERRn
+3.3V5
CBEn(1)
AD(14)
GND7
AD(12)
AD(10)
M66EN
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD(8)
AD(7)
+3.3V6
AD(5)
AD(3)
GND10
AD(1)
VCCIO2
ACK64n
+5V3
+5V4
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
RESERVED5
RSTn
VCCIO4
GNTn
GND11
PMEn
AD(30)
+3.3V7
AD(28)
AD(26)
GND12
AD(24)
IDSEL
+3.3V8
AD(22)
AD(20)
GND13
AD(18)
AD(16)
+3.3V9
FRAMEn
GND14
TRDYn
GND15
STOPn
+3.3V10
RESERVED6
RESERVED7
GND16
PAR
AD(15)
+3.3V11
AD(13)
AD(11)
GND17
AD(9)
D
3,4 PCI_RSTn
PCI_CBEn6
PCI_CBEn4
3,4 PCI_GNTn
PCI_AD63
PCI_AD61
PCI_AD30
PCI_AD59
PCI_AD57
PCI_AD28
PCI_AD26
PCI_AD55
PCI_AD53
PCI_AD24
3,4 PCI_IDSEL
PCI_AD51
PCI_AD49
PCI_AD22
PCI_AD20
PCI_AD47
PCI_AD45
PCI_AD18
PCI_AD16
PCI_AD43
PCI_AD41
3,4 PCI_FRAMEn
3,4 PCI_TRDYn
PCI_AD39
PCI_AD37
3,4 PCI_STOPn
PCI_AD35
PCI_AD33
3,4 PCI_PAR
3,4 PCI_AD15
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
RESERVED8
GND21
CBEn(6)
CBEn(4)
GND22
AD(63)
AD(61)
VCCIO6
AD(59)
AD(57)
GND23
AD(55)
AD(53)
GND24
AD(51)
AD(49)
VCCIO7
AD(47)
AD(45)
GND25
AD(43)
AD(41)
GND26
AD(39)
AD(37)
VCCIO8
AD(35)
AD(33)
GND27
RESERVED9
RESERVED10
GND28
GND29
CBEn(7)
CBEn(5)
VCCIO9
PAR64
AD(62)
GND30
AD(60)
AD(58)
GND31
AD(56)
AD(54)
VCCIO10
AD(52)
AD(50)
GND32
AD(48)
AD(46)
GND33
AD(44)
AD(42)
VCCIO11
AD(40)
AD(38)
GND34
AD(36)
AD(34)
GND35
AD(32)
RESERVED11
GND36
RESERVED12
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
PCI_CBEn7
PCI_CBEn5
3,4
PCI_PAR64
PCI_AD62
PCI_AD60
PCI_AD58
PCI_AD56
PCI_AD54
PCI_AD52
PCI_AD50
C
PCI_AD48
PCI_AD46
PCI_AD44
PCI_AD42
PCI_AD40
PCI_AD38
PCI_AD36
PCI_AD34
PCI_AD32
PCI64_CONN
PCI_AD13
PCI_AD11
PCI_AD9
B
PCI_M66EN
5V Keyway
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
PCI_ACK64n 3,4
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
CBEn(0)
+3.3V12
AD(6)
AD(4)
GND20
AD(2)
AD(0)
VCCIO5
REQ64n
+5V7
+5V8
PCI_CBEn0
PCI_XCAP
C234
0.1uF
X7R
PCI_AD6
PCI_AD4
C235
0.1uF
X7R
PCI_AD2
PCI_AD0
3,4 PCI_REQ64n
PCI64_CONN
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
2
of
1
18
A
5
4
3
PCI Voltage Translation Switch
Threshold (gate) Voltage
5.0V
2
D
R56
4.7K
TOP #1
U15
NC
VCC
LPCI_AD19
2
LPCI_AD21
3
LPCI_AD23
4
LPCI_CBEn3
5
LPCI_AD25
6
LPCI_AD27
7
LPCI_AD29
8
LPCI_AD31
9
LPCI_REQn 4,5 10
LPCI_CLK 4,15 11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
24
4.3V_VCC
22
21
20
19
18
17
16
15
2,4
14
2,4
13
PCI_AD19
PCI_AD21
PCI_AD23
PCI_CBEn3
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
PCI_REQn
PCI_CLK
LPCI_AD49
LPCI_AD51
LPCI_AD53
LPCI_AD55
LPCI_AD57
LPCI_AD59
LPCI_AD61
LPCI_AD63
LPCI_CBEn4
LPCI_CBEn6
12
NC
VCC
24
2
3
4
5
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
22
21
20
19
18
17
16
15
14
13
23
BE
GND
12
23
PCI_AD49
PCI_AD51
PCI_AD53
PCI_AD55
PCI_AD57
PCI_AD59
PCI_AD61
PCI_AD63
PCI_CBEn4
PCI_CBEn6
1
NC
VCC
LPCI_INTAn 4,5 2
LPCI_RSTn 4,5 3
LPCI_GNTn 4,5 4
LPCI_AD30
5
LPCI_AD28
6
LPCI_AD26
7
LPCI_AD24
8
LPCI_IDSEL 4,5 9
LPCI_AD22
10
LPCI_AD20
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BE
GND
24
4.3V_VCC
22
21
20
2,4
19
2,4
18
2,4
17
2,4
16
2,4
15
14
13
PCI_AD12
PCI_AD14
PCI_CBEn1
PCI_SERRn
PCI_PERRn
PCI_LOCKn
PCI_DEVSELn
PCI_IRDYn
PCI_CBEn2
PCI_AD17
LPCI_AD33
LPCI_AD35
LPCI_AD37
LPCI_AD39
LPCI_AD41
LPCI_AD43
LPCI_AD45
LPCI_AD47
12
QS3861_SO_2
4.3V_VCC
2,4
22
2,4
21
2,4
20
19
18
17
16
2,4
15
14
13
PCI_INTAn
PCI_RSTn
PCI_GNTn
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCI_IDSEL
PCI_AD22
PCI_AD20
BOTTOM #4
U16
12
BOTTOM #2
U19
NC
24
QS3861_SO_2
TOP #5
U18
LPCI_AD12
2
LPCI_AD14
3
LPCI_CBEn1
4
LPCI_SERRn 4,5 5
LPCI_PERRn 4,5 6
LPCI_LOCKn 4,5 7
LPCI_DEVSELn 4,5
8
LPCI_IRDYn 4,5 9
LPCI_CBEn2
10
LPCI_AD17
11
4.3V_VCC
QS3861_SO_2
TOP #2
1
U13
1
QS3861_SO_2
C
U17
1
NC
VCC
24
2
3
4
5
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
22
21
20
19
18
17
16
15
14
13
23
BE
GND
12
4.3V_VCC
1
NC
VCC
PCI_AD33
PCI_AD35
PCI_AD37
PCI_AD39
PCI_AD41
PCI_AD43
PCI_AD45
PCI_AD47
LPCI_AD18
2
LPCI_AD16
3
LPCI_FRAMEn 4,54
LPCI_TRDYn 4,155
LPCI_STOPn 4,5 6
LPCI_PAR 4,5
7
LPCI_AD15
8
LPCI_AD13
9
LPCI_AD11
10
LPCI_AD9
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
QS3861_SO_2
24
4.3V_VCC
22
21
2,4
20
2,4
19
2,4
18
2,4
17
16
15
14
13
PCI_AD18
PCI_AD16
PCI_FRAMEn
PCI_TRDYn
PCI_STOPn
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
1
NC
VCC
2
3
4
LPCI_AD6
5
LPCI_AD4
6
7
LPCI_AD2
8
LPCI_AD0
9
10
LPCI_REQ64n 4,5
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
U22
LPCI_ACK64n 4,52
LPCI_AD1
3
LPCI_AD3
4
LPCI_AD5
5
LPCI_AD7
6
LPCI_AD8
7
LPCI_AD10
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
4.3V_VCC
2,4
22
21
20
19
18
17
16
15
14
13
PCI_ACK64n
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_AD10
LPCI_CBEn7
2
LPCI_CBEn5
3
LPCI_PAR64 4,5 4
LPCI_AD62
5
LPCI_AD60
6
LPCI_AD58
7
LPCI_AD56
8
LPCI_AD54
9
LPCI_AD52
10
LPCI_AD50
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
23
BE
GND
LPCI_CBEn0
24
4.3V_VCC
22
21
2,4
20
19
18
17
16
15
14
13
PCI_CBEn7
PCI_CBEn5
PCI_PAR64
PCI_AD62
PCI_AD60
PCI_AD58
PCI_AD56
PCI_AD54
PCI_AD52
PCI_AD50
C
12
U20
12
LPCI_AD48
LPCI_AD46
LPCI_AD44
LPCI_AD42
LPCI_AD40
LPCI_AD38
LPCI_AD36
LPCI_AD34
LPCI_AD32
U21
24
VCC
QS3861_SO_2
TOP #3
VCC
NC
BOTTOM #5
BOTTOM #3
NC
1
QS3861_SO_2
B
1
D
BOTTOM #1
TOP #4
U14
1
2,4 PCI_CBEn[7..0]
4,5 LPCI_CBEn[7..0]
(a) Remove these switches and populate the
bypass resistor packs on the next page.
(3.3V PCI signalling only)
(b) Connect the 4.3V VCC net to an acceptable
voltage per the desired application (see
manufacturer's datasheet for specs).
4.3V_VCC
MMSD701T1
2,4 PCI_AD[63..0]
4,5 LPCI_AD[63..0]
NOTE: Systems without a 5V power source must
either:
PCI Voltage Limit Switches
D16
1
24
4.3V_VCC
22
21
20
19
18
17
16
15
14
2,4
13
PCI_CBEn0
PCI_AD6
PCI_AD4
1
NC
VCC
24
4.3V_VCC
2
3
4
5
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
22
21
20
19
18
17
16
15
14
13
PCI_AD48
PCI_AD46
PCI_AD44
PCI_AD42
PCI_AD40
PCI_AD38
PCI_AD36
PCI_AD34
PCI_AD32
23
BE
GND
12
B
QS3861_SO_2
PCI_AD2
PCI_AD0
PCI_REQ64n
12
QS3861_SO_2
12
QS3861_SO_2
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
5
Date:
4
3
2
Document Number
Rev
150-0216000-01
Wednesday, February 12, 2003
Sheet
1
3
B
of
18
8
7
6
5
4
3
2
1
PCI Voltage Switch Bypass Resistors
NOTE: These resistor packs are NOT installed by
default. They are ONLY installed when
the proceeding page's FET switches are
not installed (mutually exclusive).
2,3 PCI_AD[63..0]
3,5 LPCI_AD[63..0]
2,3 PCI_CBEn[7..0]
3,5 LPCI_CBEn[7..0]
E
E
TOP #4
TOP #1
LPCI_AD19
LPCI_AD21
LPCI_AD23
LPCI_CBEn3
LPCI_AD25
D
LPCI_AD27
LPCI_AD29
LPCI_AD31
LPCI_REQn 3,5
LPCI_CLK 3,15
RN38
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN41
0
16
15
14
13
12
11
10
9
0
16
15
14
2,3
13
2,3
12
11
10
9
PCI_AD19
PCI_AD21
PCI_AD23
PCI_CBEn3
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
PCI_REQn
PCI_CLK
LPCI_AD49
LPCI_AD51
LPCI_AD53
LPCI_AD55
LPCI_AD57
LPCI_AD59
LPCI_AD61
LPCI_AD63
LPCI_CBEn4
LPCI_CBEn6
TOP #2
RN45
1
2
3
LPCI_AD12
4
LPCI_AD14
5
LPCI_CBEn1
6
LPCI_SERRn 3,5 7
LPCI_PERRn 3,5 8
C
LPCI_LOCKn 3,5 1
LPCI_DEVSELn 3,5
2
LPCI_IRDYn 3,5 3
LPCI_CBEn2
4
LPCI_AD17
5
6
7
8
RN49
B
RN36
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN39
0
16
15
14
13
12
11
10
9
0
16
15
14
13
12
11
10
9
BOTTOM #1
RN37
1
2
3
LPCI_INTAn 3,5 4
LPCI_RSTn 3,5 5
LPCI_GNTn 3,5 6
LPCI_AD30
7
LPCI_AD28
8
PCI_AD49
PCI_AD51
PCI_AD53
PCI_AD55
PCI_AD57
PCI_AD59
PCI_AD61
PCI_AD63
PCI_CBEn4
PCI_CBEn6
LPCI_AD26
1
LPCI_AD24
2
LPCI_IDSEL 3,5 3
LPCI_AD22
4
LPCI_AD20
5
6
7
8
RN40
16
15
14
13
12
11
2,3
10
92,3
0
2,3
16
2,3
15
2,3
14
13
12
11
10
9
PCI_AD12
PCI_AD14
PCI_CBEn1
PCI_SERRn
PCI_PERRn
LPCI_AD33
LPCI_AD35
LPCI_AD37
LPCI_AD39
LPCI_AD41
LPCI_AD43
LPCI_AD45
LPCI_AD47
RN43
1
2
3
4
5
6
7
8
RN44
1
2
3
LPCI_AD18
4
LPCI_AD16
5
LPCI_FRAMEn 3,56
LPCI_TRDYn 3,157
LPCI_STOPn 3,5 8
0
16
15
14
13
12
11
10
9
PCI_AD33
PCI_AD35
PCI_AD37
PCI_AD39
PCI_AD41
PCI_AD43
PCI_AD45
PCI_AD47
LPCI_PAR 3,5
LPCI_AD15
LPCI_AD13
LPCI_AD11
LPCI_AD9
PCI_LOCKn
PCI_DEVSELn
PCI_IRDYn
PCI_CBEn2
PCI_AD17
0
16
15
2,3
14
13
12
11
10
9
PCI_INTAn
PCI_RSTn
PCI_GNTn
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCI_IDSEL
PCI_AD22
PCI_AD20
RN42
1
2
3
LPCI_CBEn7
4
LPCI_CBEn5
5
LPCI_PAR64 3,5 6
LPCI_AD62
7
LPCI_AD60
8
1
2
3
4
5
6
7
8
RN48
0
16
15
14
13
12
2,3
11
2,3
10
92,3
0
2,3
16
15
14
13
12
11
10
9
RN51
1
2
LPCI_AD6
3
LPCI_AD4
4
5
LPCI_AD2
6
LPCI_AD0
7
LPCI_REQ64n 3,58
0
LPCI_CBEn0
2,3
16
15
14
13
12
11
10
9
PCI_ACK64n
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_AD10
D
BOTTOM #4
LPCI_AD58
LPCI_AD56
LPCI_AD54
LPCI_AD52
LPCI_AD50
PCI_AD18
PCI_AD16
PCI_FRAMEn
PCI_TRDYn
PCI_STOPn
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
1
2
3
4
5
6
7
8
RN46
0
16
15
14
PCI_CBEn7
13
PCI_CBEn5
12
2,3 PCI_PAR64
11
PCI_AD62
10
PCI_AD60
9
0
16
15
14
13
12
11
10
9
PCI_AD58
PCI_AD56
PCI_AD54
PCI_AD52
PCI_AD50
C
BOTTOM #5
LPCI_AD48
LPCI_AD46
LPCI_AD44
LPCI_AD42
LPCI_AD40
BOTTOM #3
TOP #3
RN52
LPCI_ACK64n 3,51
LPCI_AD1
2
LPCI_AD3
3
LPCI_AD5
4
LPCI_AD7
5
LPCI_AD8
6
LPCI_AD10
7
8
16
15
14
2,3
13
2,3
12
2,3
11
10
9
BOTTOM #2
TOP #5
0
0
RN50
1
2
3
4
5
6
7
8
0
16
15
14
13
12
11
10
9
PCI_AD48
PCI_AD46
PCI_AD44
PCI_AD42
PCI_AD40
B
0
16
15
14
13
12
11
10
92,3
PCI_CBEn0
LPCI_AD38
LPCI_AD36
LPCI_AD34
LPCI_AD32
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_REQ64n
A
1
2
3
4
5
6
7
8
RN53
0
16
15
14
13
12
11
10
9
PCI_AD38
PCI_AD36
PCI_AD34
PCI_AD32
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
4
of
1
18
A
8
7
6
5
4
3
Stratix Bank 7, Bank 8, LEDs
BANK 7
(3.3V PCI & 3.3V LVTTL)
E
D
C
AK4
AK3
AH5
AJ5
AJ4
AM4
AL4
AL3
AK5
DQ0B0
DQ0B1
DQ0B2
DQ0B3
DQ0B4
DQ0B5
DQ0B6
DQ0B7
DQS0B
LPCI_CBEn3 3,4
LPCI_IDSEL 3,4
LPCI_AD29
LPCI_AD21
USER_PB2
LPCI_AD20
LPCI_AD25
LPCI_AD24
LPCI_CBEn2 3,4
AJ6
AK6
AL5
AK7
AM5
AJ7
AM6
AL6
AH7
DQ1B0
DQ1B1
DQ1B2
DQ1B3
DQ1B4
DQ1B5
DQ1B6
DQ1B7
DQS1B
LPCI_AD22
LPCI_AD19
LPCI_AD23
LPCI_PERRn 3,4
LPCI_AD18
LPCI_AD14
LPCI_LOCKn 3,4
LPCI_AD17
LPCI_AD16
AL7
AJ8
AM7
AH9
AM8
AK9
AJ9
AL8
AK8
DQ2B0
DQ2B1
DQ2B2
DQ2B3
DQ2B4
DQ2B5
DQ2B6
DQ2B7
DQS2B
LPCI_AD7
LPCI_AD12
LPCI_DEVSELn 3,4
LPCI_FRAMEn 3,4
LPCI_AD13
LPCI_AD9
LPCI_AD8
LPCI_STOPn 3,4
CPLD_CSn 17
AH11
AJ10
AL9
AM9
AK10
AL11
AK11
AL10
AJ11
DQ3B0
DQ3B1
DQ3B2
DQ3B3
DQ3B4
DQ3B5
DQ3B6
DQ3B7
DQS3B
LPCI_AD10
LPCI_AD3
LPCI_AD2
LPCI_CBEn5
LPCI_CBEn4
LPCI_PAR64
LPCI_CBEn7
LPCI_CBEn6
LPCI_AD1
AM11
AL12
AK12
AK13
AJ13
AH13
AM13
AL13
AJ12
DQ4B0
DQ4B1
DQ4B2
DQ4B3
DQ4B4
DQ4B5
DQ4B6
DQ4B7
DQS4B
3,4
3,4
3,4
3,4
3,4
U2H
FCLK4
FCLK5
AF12
AM14
14 RS232_RXD
14 RS232_CTS
RDN7
RUP7
AC14
AF13
14
14
GPIO_B7_0
GPIO_B7_1
GPIO_B7_2
GPIO_B7_3
GPIO_B7_4
GPIO_B7_5
GPIO_B7_6
GPIO_B7_7
GPIO_B7_8
GPIO_B7_9
GPIO_B7_10
GPIO_B7_11
GPIO_B7_12
GPIO_B7_13
AE12
AC12
AA12
AD12
AB11
AE11
AF10
AG10
AG11
AD9
AG9
AC9
AE9
AF9
GPIO_B7_14
GPIO_B7_15
GPIO_B7_16
GPIO_B7_17
GPIO_B7_18
GPIO_B7_19
GPIO_B7_20
AD14
AB13
AG13
AC13
AE13
AD13
AG12
GPIO_B7_21
GPIO_B7_22
GPIO_B7_23
GPIO_B7_24
GPIO_B7_25
GPIO_B7_26
GPIO_B7_27
GPIO_B7_28
GPIO_B7_29
GPIO_B7_30
GPIO_B7_31
AA18
AB15
AA15
AD15
AC15
AK14
AC18
AL14
AB14
AA14
AE14
LPCI_AD45
LPCI_AD50
LPCI_AD49
LPCI_AD52
LPCI_AD51
LPCI_AD57
3,4 LPCI_IRDYn
LPCI_AD58
LPCI_AD54
LPCI_AD53
LPCI_AD56
GPIO_B7_32
GPIO_B7_33
GPIO_B7_34
GPIO_B7_35
GPIO_B7_36
GPIO_B7_37
GPIO_B7_38
AA13
AB12
AC11
AD10
AD11
AE10
AF11
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
RS232_TXD
RS232_RTS
LPCI_AD0
3,4 LPCI_REQ64n
LPCI_AD63
3,4 LPCI_ACK64n
LPCI_AD4
LPCI_AD5
3,4 LPCI_CBEn0
LPCI_AD11
LPCI_AD6
3,4 LPCI_CBEn1
USER_PB1
LPCI_AD15
3,4 LPCI_PAR
3,4 LPCI_SERRn
LPCI_AD55
LPCI_AD59
SYS_RESETn
LPCI_AD60
LPCI_AD62
LPCI_AD61
CPLD_USER1
on
on
on
on
on
on
on
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
LPCI_AD42
LPCI_AD41
LPCI_AD40
LPCI_AD38
LPCI_AD37
LPCI_AD36
LPCI_AD35
LPCI_AD34
LPCI_AD39
AM20
AL20
AK20
AH20
AL21
AK21
AJ21
AM22
AJ20
DQ5B0
DQ5B1
DQ5B2
DQ5B3
DQ5B4
DQ5B5
DQ5B6
DQ5B7
DQS5B
LPCI_AD33
LPCI_AD32
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
AL22
AK22
AL23
AK23
AM24
AH22
AL24
AJ23
AJ22
DQ6B0
DQ6B1
DQ6B2
DQ6B3
DQ6B4
DQ6B5
DQ6B6
DQ6B7
DQS6B
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
AM26
AM25
AK24
AL25
AK25
AJ25
AJ24
AH24
AL26
DQ7B0
DQ7B1
DQ7B2
DQ7B3
DQ7B4
DQ7B5
DQ7B6
DQ7B7
DQS7B
FLASH_OEn 17
FLASH_WEn 17
FLASH_CEn 17
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
AK26
AM28
AM27
AJ26
AK27
AL28
AJ27
AH26
AL27
DQ8B0
DQ8B1
DQ8B2
DQ8B3
DQ8B4
DQ8B5
DQ8B6
DQ8B7
DQS8B
USER_LED7
USER_LED6
USER_LED5
USER_LED4
USER_LED3
USER_LED2
USER_LED1
USER_LED0
AM29
AL29
AL30
AK29
AJ29
AJ28
AK30
AH28
AK28
DQ9B0
DQ9B1
DQ9B2
DQ9B3
DQ9B4
DQ9B5
DQ9B6
DQ9B7
DQS9B
USER_LED_DRV0
USER_LED_DRV1
USER_LED_DRV2
USER_LED_DRV3
USER_LED_DRV4
USER_LED_DRV5
USER_LED_DRV6
USER_LED_DRV7
B
USER LEDs
RED
A
USER_LED_RES1
D6
LED
C
RED
A
USER_LED_RES2
D8
LED
C
RED
A
D10
LED
C
RED
A
D12
LED
C
A
RED
A
D14
LED
C
RED
A
D15
LED
C
RED
A
RN34
1
2
3
4
5
6
7
8
USER_LED_RES0
D5
LED
C
7
AF21
AE21
RDN8
RUP8
AC20
AH19
FLASH_A6
FLASH_A7
GPIO_B8_0
GPIO_B8_1
GPIO_B8_2
GPIO_B8_3
GPIO_B8_4
GPIO_B8_5
GPIO_B8_6
GPIO_B8_7
GPIO_B8_8
AB19
AD20
AG21
AG20
AE20
AD19
AJ18
AH18
AK18
LPCI_AD43
GPIO_B8_9
GPIO_B8_10
GPIO_B8_11
GPIO_B8_12
GPIO_B8_13
GPIO_B8_14
GPIO_B8_15
GPIO_B8_16
GPIO_B8_17
AA21
AB21
AD22
AC21
AG23
AD21
AF22
AB20
AG22
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
USER_RESETn
GPIO_B8_18
GPIO_B8_19
GPIO_B8_20
GPIO_B8_21
GPIO_B8_22
GPIO_B8_23
GPIO_B8_24
GPIO_B8_25
GPIO_B8_26
GPIO_B8_27
GPIO_B8_28
GPIO_B8_29
16,17
AB24
16,17
AC24
AC23 16
AD24 16
AD23
AE24
AE23
AF24
AC22
AG24
AB22
AF23
OVERTEMPn
ALERTn
SMB_CLK
SMB_DATA
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
GPIO_B8_30
AE22
E
17 USER_LED[7..0]
17 USER_LED_DRV[7..0]
8,14,17
8,17
17
8,17
LPCI_AD44
LPCI_AD47
LPCI_AD46
LPCI_AD48
SYS_RESETn
USER_RESETn
CPLD_USER[1..0]
USER_PB[2..1]
D
C
(n/c on 1S25)
POWER & CONFIG LEDs
56
16
15
14
13
12
11
10
9
EP1S_CONF_DONEn 17
CRC_ERRORn 17
USER_LED_RES3
USER_LED_RES4
USER_LED_RES5
USER_LED_RES6
D7
LED
C
D4
LED
C
USER DIPSWITCH
3.3V
GREEN
A
YELLOW
A
D9
LED
C
BLUE
A
D11
LED
C
BLUE
A
D13
LED
C
BLUE
A
CONF_DONE_RESn
R51
56
R52
56
S2
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
VCC_1.25_LED
R53
RN35
1
2
3
4
5
6
7
8
570
2.5V
VCC_2.5_LED
R54
570
1.5V
VCC_1.5_LED
R55
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
B
10K
16
15
14
13
12
11
10
9
570
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
USER_LED_RES7
Size
B
Date:
5
1
2
3
4
5
6
7
8
3.3V
1.25V
-12V
6
1
2
3
4
5
6
7
8
TDA08H0SK1
CRC_ERROR_LED
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
17 FLASH_A[21..0]
17 FLASH_D[15..0]
FCLK2
FCLK3
EP1S40F1020
3.3V
RED
A
3,4 LPCI_AD[63..0]
3,4 LPCI_CBEn[7..0]
(3.3V PCI & 3.3V LVTTL)
EP1S40F1020
D3
LED
C
1
BANK 8
U2G
LPCI_AD31
LPCI_REQn 3,4
LPCI_AD26
LPCI_AD27
LPCI_AD30
LPCI_INTAn 3,4
CPLD_USER0
LPCI_GNTn 3,4
LPCI_AD28
2
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
5
of
1
18
A
8
7
6
5
4
3
2
1
DDR SDRAM SO-DIMM
7,9 DDR_DQ[63..0]
2.5V
2.5V
E
7,9 DDR_BA[2..0]
J10B
DDR_DQ35
DDR_DQ40
DDR_DP3
B
DDR_CLK2p 15
DDR_CLK2n 15
DDR_CLKEN1
DDR_A13
DDR_A12
DDR_A9
DDR_A10
DDR_BA0
DDR_WEn 7,9
DDR_CS0n 7,9
A
Address & Control
DDR_A7
DDR_A5
DDR_A3
DDR_A1
Byte Lane 8
DDR_DQS8
DDR_DP2
DDR_DQ13
DDR_DM1
DDR_DQS6
DDR_DQ50
DDR_DQ14
DDR_DQ15
DDR_DQ51
DDR_DQ56
DDR_DQ57
DDR_DQS7
DDR_DQ58
DDR_DQ59
DDR_DQ20
DDR_DQ21
SPD_SDA 9
SPD_SCL 9
DDR_DM2
DDR_DQ22
DDR_DQ46
DDR_DQ47
15
15
DDR_CLK1n
DDR_CLK1p
D
DDR_DQ52
DDR_DQ53
DDR_DM6
DDR_DQ54
DDR_DQ55
DDR_DQ60
DDR_DQ61
DDR_DM7
DDR_DQ62
DDR_DQ63
SPD_A
R48
10K
C
SO_DIMM_200
DDR_DQ23
DDR_DQ28
TP6
DDR_DQ29
DDR_DM3
DDR_DQ30
DDR_DQ31
DDR_DP4
DDR_DP5
2.5V
1.25V
SSTL2_VREF
DDR_DM8
DDR_DP6
U12
1
2
3
4
DDR_DP7
SSTL2_VREF 16
NC
VTT
GND
PVIN
VSENSE AVIN
VREF
VDDQ
8
7
6
5
B
LP2995M
C231
0.1uF
X7R
DDR_CLKEN0
DDR_BA2
DDR_A11
DDR_A8
DDR_A6
DDR_A4
DDR_A2
DDR_A0
7,9
7,9
7,9
C232
0.1uF
X7R
C233
0.1uF
X7R
+
C228
100uF
10V
Tantalum
1
DDR_DP0
DDR_DP1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
DDR_DQ48
DDR_DQ49
DDR_DQ45
DDR_DM5
+
C229
100uF
10V
Tantalum
+
2
DDR_DQ26
DDR_DQ27
Byte Lane 3
DDR_DQ25
DDR_DQS3
DQ20
DQ21
VDD9
DM2
DQ22
VSS11
DQ23
DQ28
VDD11
DQ29
DM3
VSS13
DQ30
DQ31
VDD13
CB4
CB5
VSS15
DM8
CB6
VDD15
CB7
NC2
VSS17
VSS18
VDD16
VDD18
CKE0
BA2
A11
A8
VSS20
A6
A4
A2
A0
VDD20
BA1
RAS_n
CAS_n
S1_n
NC4
VSS35
DDR_DQ7
DDR_DQ12
7,9 DDR_DP[7..0]
1
DDR_DQ19
DDR_DQ24
DQ16
DQ17
VDD8
DQS2
DQ18
VSS10
DQ19
DQ24
VDD10
DQ25
DQS3
VSS12
DQ26
DQ27
VDD12
CB0
CB1
VSS14
DQS8
CB2
VDD14
CB3
NC1
VSS16
CK2
CK2_n
VDD17
CKE1
A13
A12
A9
VSS19
A7
A5
A3
A1
VDD19
A10_AP
BA0
WE_n
S0_n
NC3
VSS34
Byte Lane 2
DDR_DQS2
DDR_DQ18
C
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
DDR_DM0
DDR_DQ6
EEPROM
DDR_DQ16
DDR_DQ17
DDR_DQ42
DDR_DQ43
Byte Lane 7
DDR_CLK0p 15
DDR_CLK0n 15
DDR_DQ4
DDR_DQ5
7,9 DDR_CLKEN[1..0]
DDR_DQ39
DDR_DQ44
2
DDR_DQ10
DDR_DQ11
Byte Lane 1
DDR_DQ9
DDR_DQS1
DDR_DQ41
DDR_DQS5
Byte Lane 6
DDR_DQ3
DDR_DQ8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
7,9 DDR_DM[8..0]
DDR_DM4
DDR_DQ38
2
DDR_DQS0
DDR_DQ2
VREF2
VSS2
DQ4
DQ5
VDD2
DM0
DQ6
VSS4
DQ7
DQ12
VDD4
DQ13
DM1
VSS6
DQ14
DQ15
VDD6
VDD7
VSS7
VSS9
7,9 DDR_DQS[8..0]
1
D
DDR_DQ0
DDR_DQ1
VREF1
VSS1
DQ0
DQ1
VDD1
DQS0
DQ2
VSS3
DQ3
DQ8
VDD3
DQ9
DQS1
VSS5
DQ10
DQ11
VDD5
CK0
CK0_n
VSS8
Byte Lane 0
C227
0.1uF
X7R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Byte Lane 5
J10A
SSTL2_VREF
DQ36
DQ37
VDD22
DM4
DQ38
VSS24
DQ39
DQ44
VDD24
DQ45
DM5
VSS26
DQ46
DQ47
VDD26
CK1_n
CK1
VSS29
DQ52
DQ53
VDD29
DM6
DQ54
VSS31
DQ55
DQ60
VDD31
DQ61
DM7
VSS33
DQ62
DQ63
VDD33
SA0
SA1
SA2
NC10
1
DDR_DQS4
DDR_DQ34
2.5V
DQ32
DQ33
VDD21
DQS4
DQ34
VSS23
DQ35
DQ40
VDD23
DQ41
DQS5
VSS25
DQ42
DQ43
VDD25
VDD27
VSS27
VSS28
DQ48
DQ49
VDD28
DQS6
DQ50
VSS30
DQ51
DQ56
VDD30
DQ57
DQS7
VSS32
DQ58
DQ59
VDD32
SDA
SCL
VDDSPD
NC9
E
7,9 DDR_A[13..0]
DDR_DQ36
DDR_DQ37
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
2.5V
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Byte Lane 4
DDR_DQ32
DDR_DQ33
C230
100uF
10V
Tantalum
SSTL2 TERMINATION VOLTAGE REGULATOR
(1.5A / 3.0A Peak)
DDR_BA1
DDR_RASn
DDR_CASn
DDR_CS1n
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
SO_DIMM_200
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
6
of
1
18
A
8
7
6
5
4
3
2
1
DDR SDRAM TERMINATIONS
6,9 DDR_CS0n
6,9 DDR_CS1n
FLY-BY TERMINATION RESISTORS
E
FLY-BY TERMINATION BYPASSING CAPS
1.25V
1.25V
1.25V
CN1A
1
8
2
CN2A
1
8
CN3A
1
8
1
8
2
8
2
8
CN7A
1
8
C
8
8
CN10A
1
8
8
8
CN13A
1
8
7
3
3
6
6
6
7
3
6
4
3
6
4
3
6
3
6
4
3
6
3
6
3
6
3
6
5
CN10D
4
RN26
56
5
CN11D
4
5
CN12D
4
CN13C
7
RN23
56
5
CN9D
4
CN12C
7
5
CN8D
4
CN11C
7
RN20
56
5
CN7D
4
CN10C
7
5
CN6D
CN9C
7
RN17
56
5
CN5D
4
CN8C
7
5
CN4D
CN7C
7
RN14
56
5
CN3D
CN6C
CN13B
2
4
CN5C
7
CN12B
2
6
5
CN2D
CN4C
CN11B
2
CN12A
1
3
CN10B
2
CN11A
1
7
CN9B
2
4
CN3C
CN8B
2
CN9A
1
3
CN7B
2
CN8A
1
7
CN6B
2
6
RN11
56
CN1D
CN2C
CN5B
2
CN6A
1
3
CN4B
CN5A
1
7
CN3B
CN4A
D
CN1C
CN2B
2
1.25V
1.25V
CN1B
RN29
56
5
CN13D
4
5
B
CN14A
1
8
CN14B
2
CN15A
1
8
CN14C
7
3
CN15B
2
6
CN14D
4
CN15C
7
3
6
FLY-BY TERMINATION RESISTORS
RN31
56
5
CN15D
4
5
RN33
56
NOTE: THE FOLLOWING 0.1uF BYPASS CAPS ARE TO BE
PLACED IN PARALLEL WITH EVERY OTHER 56 OHM
PULL UP RESISTOR.
6,9 DDR_WEn
1.25V
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
DDR_DQ6
DDR_DQ2
DDR_DM0
DDR_DQS0
DDR_DQ5
DDR_DQ1
DDR_DQ4
DDR_DQ0
DDR_DM1
DDR_DQS1
DDR_DQ13
DDR_DQ9
DDR_DQ12
DDR_DQ8
DDR_DQ7
DDR_DQ3
DDR_DQ21
DDR_DQ17
DDR_DQ20
DDR_DQ16
DDR_DQ15
DDR_DQ11
DDR_DQ14
DDR_DQ10
DDR_DQ28
DDR_DQ24
DDR_DQ23
DDR_DQ19
DDR_DQ22
DDR_DQ18
DDR_DM2
DDR_DQS2
DDR_DQ31
DDR_DQ27
DDR_DQ30
DDR_DQ26
DDR_DM3
DDR_DQS3
DDR_DQ29
DDR_DQ25
DDR_DP6
DDR_DP2
DDR_DM8
DDR_DQS8
DDR_DP5
DDR_DP1
DDR_DP4
DDR_DP0
DDR_A11
DDR_A12
DDR_BA2
DDR_A13
DDR_CLKEN0
DDR_CLKEN1
DDR_DP7
DDR_DP3
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_CASN
DDR_WEn
DDR_RASN
DDR_BA0
DDR_BA1
DDR_A10
DDR_A0
DDR_A1
RN12
56
RN15
56
RN18
56
RN21
56
RN24
56
RN27
56
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
DDR_DM4
DDR_DQS4
DDR_DQ37
DDR_DQ33
DDR_DQ36
DDR_DQ32
DDR_CS1n
DDR_CS0n
DDR_DQ45
DDR_DQ41
DDR_DQ44
DDR_DQ40
DDR_DQ39
DDR_DQ35
DDR_DQ38
DDR_DQ34
DDR_DQ52
DDR_DQ48
DDR_DQ47
DDR_DQ43
DDR_DQ46
DDR_DQ42
DDR_DM5
DDR_DQS5
DDR_DQ55
DDR_DQ51
DDR_DQ54
DDR_DQ50
DDR_DM6
DDR_DQS6
DDR_DQ53
DDR_DQ49
DDR_DQ62
DDR_DQ58
DDR_DM7
DDR_DQS7
DDR_DQ61
DDR_DQ57
DDR_DQ60
DDR_DQ56
6,9 DDR_CLKEN1
6,9 DDR_RASn
6,9 DDR_CASn
6,9 DDR_BA[2..0]
6,9 DDR_DM[8..0]
6,9 DDR_A[13..0]
6,9 DDR_DQS[8..0]
D
6,9 DDR_DP[7..0]
6,9 DDR_DQ[63..0]
C
DDR_DQ63
DDR_DQ59
NOTE: ALL OF THE 56 OHM PULL UP RESISTORS MUST
BE PLACED AFTER THE SODIMM (i.e. AFTER THE
CONNECTOR) AND AS CLOSE AS POSSIBLE TO THE
SODIMM.
A
B
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
NOTE: PLACE ONE QUAD CAPACITOR NETWORK AS
CLOSE AS POSSIBLE TO ONE ROCTAL RESISTOR PACK.
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
E
6,9 DDR_CLKEN0
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
7
of
1
18
A
5
4
3
2
Stratix Bank 2, Bank 5, Buttons
BANK 5
D
C
LAN_A9
LAN_A10
LAN_A11
LAN_A12
LAN_A13
LAN_A14
LAN_RESET
LAN_AEN
LAN_ IOCHRDY
LAN_INTRQ0
LAN_LDEVn
LAN_IORn
LAN_IOWn
LAN_LOOPBACK
B1_USER_A0
B1_USER_A1
B1_USER_B0
B1_USER_B1
B1_USER_C0
B1_USER_C1
B1_USER_D0
B1_USER_D1
B1_USER_E0
B1_USER_E1
13 LAN_D[31..0]
(3.3V LVTTL)
U2E
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
14 SCRUZ_IO[39..0]
BANK 2
(3.3V LVTTL)
(n/c on
(n/c on
(n/c on
(n/c on
(n/c on
(n/c on
LAN_D0
LAN_BEn3
LAN_BEn2
LAN_BEn1
LAN_BEn0
LAN_A0
LAN_A1
LAN_A2
LAN_A3
LAN_A4
LAN_A5
LAN_A6
LAN_A7
LAN_A8
1
13 LAN_A[14..0]
U2B
F5
E4
E2
E1
F3
F4
G3
G4
F1
F2
H3
H4
G1
G2
H1
H2
J3
J4
K4
K3
DIFFIO_RX45n
DIFFIO_RX45p
DIFFIO_RX46n
DIFFIO_RX46p
DIFFIO_RX47n
DIFFIO_RX47p
DIFFIO_RX48n
DIFFIO_RX48p
DIFFIO_RX49n
DIFFIO_RX49p
DIFFIO_RX50n
DIFFIO_RX50p
DIFFIO_RX51n
DIFFIO_RX51p
DIFFIO_RX52n
DIFFIO_RX52p
DIFFIO_RX53n
DIFFIO_RX53p
DIFFIO_RX54n
DIFFIO_RX54p
DIFFIO_TX45n
DIFFIO_TX45p
DIFFIO_TX46n
DIFFIO_TX46p
DIFFIO_TX47n
DIFFIO_TX47p
DIFFIO_TX48n
DIFFIO_TX48p
DIFFIO_TX49n
DIFFIO_TX49p
DIFFIO_TX50n
DIFFIO_TX50p
DIFFIO_TX51n
DIFFIO_TX51p
DIFFIO_TX52n
DIFFIO_TX52p
DIFFIO_TX53n
DIFFIO_TX53p
DIFFIO_TX54n
DIFFIO_TX54p
G7
G8
G6
G5
H8
H7
H5
H6
J7
J8
J5
J6
K8
K7
K5
K6
L6
L7
M6
M7
(n/c on 1S25)
(n/c on 1S25)
LAN_D2
LAN_D3
LAN_D4
LAN_D5
LAN_D6
LAN_D7
LAN_D8
LAN_D9
LAN_D10
LAN_D11
LAN_D12
LAN_D13
LAN_D14
LAN_D15
LAN_D16
LAN_D17
LAN_D18
LAN_D19
J2
J1
L1
K2
M4
M5
L2
L3
M2
M3
N3
N4
N1
N2
P3
P4
P1
P2
R3
R4
R1
R2
T2
T1
DIFFIO_RX55n
DIFFIO_RX55p
DIFFIO_RX56n
DIFFIO_RX56p
DIFFIO_RX57n/RDN5
DIFFIO_RX57p/RUP5
DIFFIO_RX58n
DIFFIO_RX58p
DIFFIO_RX59n
DIFFIO_RX59p
DIFFIO_RX60n
DIFFIO_RX60p
DIFFIO_RX61n
DIFFIO_RX61p
DIFFIO_RX62n
DIFFIO_RX62p
DIFFIO_RX63n
DIFFIO_RX63p
DIFFIO_RX64n
DIFFIO_RX64p
DIFFIO_RX65n
DIFFIO_RX65p
DIFFIO_RX66n
DIFFIO_RX66p
DIFFIO_TX55n
DIFFIO_TX55p
DIFFIO_TX56n
DIFFIO_TX56p
DIFFIO_TX57n
DIFFIO_TX57p
DIFFIO_TX58n
DIFFIO_TX58p
DIFFIO_TX59n
DIFFIO_TX59p
DIFFIO_TX60n
DIFFIO_TX60p
DIFFIO_TX61n
DIFFIO_TX61p
DIFFIO_TX62n
DIFFIO_TX62p
DIFFIO_TX63n
DIFFIO_TX63p
DIFFIO_TX64n
DIFFIO_TX64p
DIFFIO_TX65n
DIFFIO_TX65p
DIFFIO_TX66n
DIFFIO_TX66p
M8
M9
N10
N9
N5
N6
P9
P10
N7
N8
P6
P5
R10
R9
R5
R6
P7
P8
R7
R8
P11
N11
T11
R11
LAN_D20
LAN_D21
LAN_D22
LAN_D23
LAN_D24
LAN_D25
LAN_D26
LAN_D27
LAN_D28
LAN_D29
LAN_D30
LAN_D31
B1_REQn
B1_RESETn
B1_SYS_RESETn
B1_PWROK
B1_STOPn
B1_SMBDAT
B1_SMBCLK
LAN_D1
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
SCRUZ_IO0
SCRUZ_IO1
SCRUZ_IO2
MICTOR_DO15
MICTOR_DO14
MICTOR_DO13
MICTOR_DO12
MICTOR_DO11
MICTOR_DO10
MICTOR_DO9
MICTOR_DO8
MICTOR_DO7
MICTOR_DO6
MICTOR_DO5
MICTOR_DO4
MICTOR_DO3
MICTOR_DO2
MICTOR_DO1
MICTOR_DO0
MICTOR_DE15
MICTOR_DE14
MICTOR_DE13
MICTOR_DE12
MICTOR_DE11
MICTOR_DE10
MICTOR_DE9
MICTOR_DE8
MICTOR_DE7
MICTOR_DE6
MICTOR_DE5
MICTOR_DE4
MICTOR_DE3
MICTOR_DE2
MICTOR_DE1
MICTOR_DE0
MICTOR_CLKO
MICTOR_CLKE
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
on
on
on
on
on
on
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
T31
T32
R29
R30
R31
R32
P32
P31
P30
P29
N32
N31
N30
N29
M30
M31
L31
L30
M29
M28
L32
K31
J31
J32
K29
K30
J30
J29
H32
H31
G32
G31
H29
H30
G30
G29
F32
F31
F30
F29
E31
E32
F28
E29
13 LAN_BEn[3..0]
DIFFIO_RX23n
DIFFIO_RX23p
DIFFIO_RX24n
DIFFIO_RX24p
DIFFIO_RX25n
DIFFIO_RX25p
DIFFIO_RX26n
DIFFIO_RX26p
DIFFIO_RX27n
DIFFIO_RX27p
DIFFIO_RX28n
DIFFIO_RX28p
DIFFIO_RX29n
DIFFIO_RX29p
DIFFIO_RX30n
DIFFIO_RX30p
DIFFIO_RX31n
DIFFIO_RX31p
DIFFIO_RX32n/RDN2
DIFFIO_RX32p/RUP2
DIFFIO_RX33n
DIFFIO_RX33p
DIFFIO_RX34n
DIFFIO_RX34p
DIFFIO_RX35n
DIFFIO_RX35p
DIFFIO_RX36n
DIFFIO_RX36p
DIFFIO_RX37n
DIFFIO_RX37p
DIFFIO_RX38n
DIFFIO_RX38p
DIFFIO_RX39n
DIFFIO_RX39p
DIFFIO_RX40n
DIFFIO_RX40p
DIFFIO_RX41n
DIFFIO_RX41p
DIFFIO_RX42n
DIFFIO_RX42p
DIFFIO_RX43n
DIFFIO_RX43p
DIFFIO_RX44n
DIFFIO_RX44p
DIFFIO_TX23n
DIFFIO_TX23p
DIFFIO_TX24n
DIFFIO_TX24p
DIFFIO_TX25n
DIFFIO_TX25p
DIFFIO_TX26n
DIFFIO_TX26p
DIFFIO_TX27n
DIFFIO_TX27p
DIFFIO_TX28n
DIFFIO_TX28p
DIFFIO_TX29n
DIFFIO_TX29p
DIFFIO_TX30n
DIFFIO_TX30p
DIFFIO_TX31n
DIFFIO_TX31p
DIFFIO_TX32n
DIFFIO_TX32p
DIFFIO_TX33n
DIFFIO_TX33p
DIFFIO_TX34n
DIFFIO_TX34p
DIFFIO_TX35n
DIFFIO_TX35p
DIFFIO_TX36n
DIFFIO_TX36p
DIFFIO_TX37n
DIFFIO_TX37p
DIFFIO_TX38n
DIFFIO_TX38p
DIFFIO_TX39n
DIFFIO_TX39p
DIFFIO_TX40n
DIFFIO_TX40p
DIFFIO_TX41n
DIFFIO_TX41p
DIFFIO_TX42n
DIFFIO_TX42p
DIFFIO_TX43n
DIFFIO_TX43p
DIFFIO_TX44n
DIFFIO_TX44p
P22
N22
M22
M23
R26
R25
R24
R23
P26
P25
R27
R28
P27
P28
N26
N25
P24
P23
N28
N27
N23
N24
M25
M24
M27
M26
L26
L27
K25
K26
K27
K28
J26
J25
H26
H25
J28
J27
H27
H28
G27
G28
G26
G25
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
(n/c on 1S25)
SCRUZ_IO3
SCRUZ_IO4
SCRUZ_IO5
SCRUZ_IO6
SCRUZ_IO7
SCRUZ_IO8
SCRUZ_IO9
SCRUZ_IO10
SCRUZ_IO11
SCRUZ_IO12
SCRUZ_IO13
SCRUZ_IO14
SCRUZ_IO15
SCRUZ_IO16
SCRUZ_IO17
SCRUZ_IO18
SCRUZ_IO19
SCRUZ_IO20
SCRUZ_IO21
SCRUZ_IO22
SCRUZ_IO23
SCRUZ_IO24
SCRUZ_IO25
SCRUZ_IO26
SCRUZ_IO27
SCRUZ_IO28
SCRUZ_IO29
SCRUZ_IO30
SCRUZ_IO31
SCRUZ_IO32
SCRUZ_IO33
SCRUZ_IO34
SCRUZ_IO35
SCRUZ_IO36
SCRUZ_IO37
SCRUZ_IO38
SCRUZ_IO39
14 SCRUZ_CARDSELn
(n/c on 1S25)
(n/c on 1S25)
13
13
13
13
13
13
13
13
LAN_RESET
LAN_INTRQ0
LAN_AEN
LAN_IORn
LAN_IOWn
LAN_IOCHRDY
LAN_LDEVn
LAN_LOOPBACK
D
HSDI CONTROL SIGNALS (TTL)
10
10
10,17
10,17
10
10
10
B1_STOPn
B1_REQn
B1_RESETn
B1_PWROK
B1_SYS_RESETn
B1_SMBCLK
B1_SMBDAT
HSDI USER DEFINED SIGNALS
10
10
10
10
10
C
B1_USER_A[1..0]
B1_USER_B[1..0]
B1_USER_C[1..0]
B1_USER_D[1..0]
B1_USER_E[1..0]
EP1S40F1020
EP1S40F1020
14 MICTOR_DE[15..0]
14 MICTOR_DO[15..0]
B
B
14 MICTOR_CLKO
PB1
PB2
14 MICTOR_CLKE
USER_RESETn
Button is intended to reset
internal Stratix logic
(analagous to a soft reset)
3.3V
RN9
1
2
3
4
5
6
7
8
2.5V
10K
16
15
14
13
12
11
10
9
2
1
1
PB
2
USER_PB1
PB
SYS_RESETn
USER_RESETn
USER_PB2
USER_PB1
Two user-defined
pushbuttons for any
use.
B1_REQn
B1_RESETn
B1_SYS_RESETn
PB3
SYS_RESETn
Button resets board and
re-loads Stratix device
from flash memory.
A
2
5,17
5,14,17
5,17
5,17
USER_PB[2..1]
SYS_RESETn
USER_RESETn
CPLD_USER[1..0]
PB4
1
1
PB
2
USER_PB2
PB
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
5
Date:
4
3
2
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
Sheet
1
8
B
of
18
8
7
6
5
4
3
2
1
Stratix Bank 3, Bank 4
E
E
Bank 4
Bank 3
(2.5V SSTL-2 / 2.5V LVTTL)
(2.5V SSTL-2 / 2.5V LVTTL)
U2D
U2C
D
C
B
B6_IO_AD31
B6_IO_AD30
B6_IO_AD29
B6_IO_AD28
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7
B6_IO_AD27
A29
B29
B30
C29
D29
D28
C30
E28
C28
DQ9T0
DQ9T1
DQ9T2
DQ9T3
DQ9T4
DQ9T5
DQ9T6
DQ9T7
DQS9T
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
DDR_DQS7
C26
A28
A27
D26
C27
B28
D27
E26
B27
DQ8T0
DQ8T1
DQ8T2
DQ8T3
DQ8T4
DQ8T5
DQ8T6
DQ8T7
DQS8T
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQS6
D24
A25
C24
B25
C25
D25
A26
E24
B26
DQ7T0
DQ7T1
DQ7T2
DQ7T3
DQ7T4
DQ7T5
DQ7T6
DQ7T7
DQS7T
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQS5
B22
C22
B23
C23
A24
E22
B24
D23
D22
DQ6T0
DQ6T1
DQ6T2
DQ6T3
DQ6T4
DQ6T5
DQ6T6
DQ6T7
DQS6T
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQS4
A20
B20
C20
E20
B21
C21
D21
A22
D20
DQ5T0
DQ5T1
DQ5T2
DQ5T3
DQ5T4
DQ5T5
DQ5T6
DQ5T7
DQS5T
FCLK0
FCLK1
F22
G22
11,17 B6_RESETn
11,17 B6_PWROK
RDN3
RUP3
L19
F21
RD N3
RUP3
GPIO_B3_0
GPIO_B3_1
GPIO_B3_2
GPIO_B3_3
GPIO_B3_4
GPIO_B3_5
GPIO_B3_6
GPIO_B3_7
K18
F19
F20
L18
K20
H19
G20
H20
GPIO_B3_8
GPIO_B3_9
GPIO_B3_10
GPIO_B3_11
GPIO_B3_12
GPIO_B3_13
GPIO_B3_14
GPIO_B3_15
GPIO_B3_16
GPIO_B3_17
G21
F23
L20
J21
K21
L21
H22
K22
J22
L22
GPIO_B3_18
GPIO_B3_19
GPIO_B3_20
GPIO_B3_21
GPIO_B3_22
GPIO_B3_23
GPIO_B3_24
GPIO_B3_25
GPIO_B3_26
GPIO_B3_27
GPIO_B3_30
GPIO_B3_31
G23
H23
F24
J24
G24
J23
K23
F25
F26
L23
K24
L24
DDR_A7
DDR_A6
DDR_A1
DDR_A4
DDR_A0
DDR_A3
DDR_A5
DDR_BA0
6,7
DDR_RASn
11,17 B6_IO_OEn
DDR_BA1
B6_IO_AD26
6,7
6,7
6,7
6,7
11,17
6
6
11,17
11,17
11,17
DDR_A2
DDR_CASn
DDR_CS0n
DDR_WEn
DDR_CS1n
DDR_BA2
B6_IO_CSn
SPD_SCL
SPD_SDA
B6_IO_RDYn
B6_IO_RESETn
B6_IO_WRn
DDR_DP0
DDR_DP1
DDR_DP2
DDR_DP3
DDR_DP4
DDR_DP5
DDR_DP6
DDR_DP7
DDR_DQS8
A11
B12
C12
C13
D13
E13
A13
B13
D12
DQ4T0
DQ4T1
DQ4T2
DQ4T3
DQ4T4
DQ4T5
DQ4T6
DQ4T7
DQS4T
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQS3
E11
B9
D10
C10
A9
B11
C11
B10
D11
DQ3T0
DQ3T1
DQ3T2
DQ3T3
DQ3T4
DQ3T5
DQ3T6
DQ3T7
DQS3T
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQS2
B7
D8
B8
E9
A8
C9
C8
D9
A7
DQ2T0
DQ2T1
DQ2T2
DQ2T3
DQ2T4
DQ2T5
DQ2T6
DQ2T7
DQS2T
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQS1
D6
C6
B5
C7
A5
D7
A6
B6
E7
DQ1T0
DQ1T1
DQ1T2
DQ1T3
DQ1T4
DQ1T5
DQ1T6
DQ1T7
DQS1T
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQS0
D5
C3
E5
C4
D4
A4
B4
B3
C5
DQ0T0
DQ0T1
DQ0T2
DQ0T3
DQ0T4
DQ0T5
DQ0T6
DQ0T7
DQS0T
6,7 DDR_DQ[63..0]
DDR_DM8
FCLK6
FCLK7
G12
A14
RDN4
RUP4
J13
G13
GPIO_B4_0
GPIO_B4_1
GPIO_B4_2
GPIO_B4_3
GPIO_B4_4
GPIO_B4_5
H11
J12
K12
H12
K13
F12
DDR_A8
GPIO_B4_6
GPIO_B4_7
GPIO_B4_8
GPIO_B4_9
GPIO_B4_10
GPIO_B4_11
GPIO_B4_12
GPIO_B4_13
GPIO_B4_14
GPIO_B4_15
GPIO_B4_16
F13
L14
H13
C14
B14
H14
J15
J14
K14
K15
L15
DDR_A12
B6_IO_AD25
DDR_A10
DDR_CLKEN0
DDR_CLKEN1
DDR_A11
GPIO_B4_17
GPIO_B4_18
GPIO_B4_19
GPIO_B4_20
GPIO_B4_21
GPIO_B4_22
GPIO_B4_23
GPIO_B4_24
GPIO_B4_25
GPIO_B4_26
GPIO_B4_27
GPIO_B4_28
GPIO_B4_29
GPIO_B4_30
F7
K9
F8
J9
M10
G9
H9
L9
K11
L11
J11
F9
G10
F10
DDR_DM0
GPIO_B4_31
GPIO_B4_32
GPIO_B4_33
GPIO_B4_34
GPIO_B4_35
GPIO_B4_36
GPIO_B4_37
GPIO_B4_38
F11
G11
H10
J10
K10
L10
M11
L12
6,7 DDR_DP[7..0]
6,7 DDR_A[13..0]
RD N4
RUP4
6,7 DDR_BA[2..0]
6,7 DDR_DM[8..0]
DDR_A9
6,7 DDR_DQS[8..0]
DDR_A13
6,7 DDR_CLKEN[1..0]
D
12
B6_IO_AD[31..24]
B6_IO_AD24
DDR_DM1
C
DDR_DM2
DDR_DM3
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
on
on
on
on
on
on
on
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
EP1S40F1020
B
EP1S40F1020
On-chip termination biasing resistors
On-chip termination biasing resistors
2.5V
RUP3
RD N3
R37
R38
2.5V
250
250
RUP4
RD N4
R35
R36
250
250
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
9
of
1
18
A
8
7
3.3V
J8
E
JTAG_SAMTEC_TDO
B1_USER_A0
B1_USER_B0
B1_USER_D0
B1_USER_E0
JTAG_TRST
JTAG_TCK
B1B_TX_CADp0
B1B_TX_CADn0
B1B_TX_CADp1
B1B_TX_CADn1
B1B_TX_CADp2
B1B_TX_CADn2
B1B_TX_CADp3
B1B_TX_CADn3
D
B1B_TX_CLKp
B1B_TX_CLKn
B1B_TX_CADp4
B1B_TX_CADn4
B1B_TX_CADp5
B1B_TX_CADn5
B1B_TX_CADp6
B1B_TX_CADn6
B1B_TX_CADp7
B1B_TX_CADn7
B1B_TX_CTLp
B1B_TX_CTLn
C
B1A_RX_CTLn
B1A_RX_CTLp
B1A_RX_CADn7
B1A_RX_CADp7
B1A_RX_CADn6
B1A_RX_CADp6
B1A_RX_CADn5
B1A_RX_CADp5
B1A_RX_CADn4
B1A_RX_CADp4
B1A_RX_CLKn
B1A_RX_CLKp
B
B1A_RX_CADn3
B1A_RX_CADp3
B1A_RX_CADn2
B1A_RX_CADp2
B1A_RX_CADn1
B1A_RX_CADp1
B1A_RX_CADn0
B1A_RX_CADp0
A
B1_REQn
B1_RESETn
B1_USER_C1
B1_SYS_RESETn
B1_REF_CLK_IN
3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
161
162
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
165
166
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
169
170
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
173
174
6
Top Side
PIN_1
PIN_3
PIN_5
PIN_7
PIN_9
PIN_11
PIN_13
PIN_15
PIN_17
PIN_19
PIN_21
PIN_23
PIN_25
PIN_27
PIN_29
PIN_31
PIN_33
PIN_35
PIN_37
PIN_39
GND1 Internal Ground
GND2
PIN_41
PIN_43
PIN_45
PIN_47
PIN_49
PIN_51
PIN_53
PIN_55
PIN_57
PIN_59
PIN_61
PIN_63
PIN_65
PIN_67
PIN_69
PIN_71
PIN_73
PIN_75
PIN_77
PIN_79
GND5 Internal Ground
GND6
PIN_81
PIN_83
PIN_85
PIN_87
PIN_89
PIN_91
PIN_93
PIN_95
PIN_97
PIN_99
PIN_101
PIN_103
PIN_105
PIN_107
PIN_109
PIN_111
PIN_113
PIN_115
PIN_117
PIN_119
GND9 Internal Ground
GND10
PIN_121
PIN_123
PIN_125
PIN_127
PIN_129
PIN_131
PIN_133
PIN_135
PIN_137
PIN_139
PIN_141
PIN_143
PIN_145
PIN_147
PIN_149
PIN_151
PIN_153
PIN_155
PIN_157
PIN_159
GND13 Internal Ground
GND14
Plane
Plane
Plane
Plane
5
4
3.3V
3.3V
J9
PIN_2
PIN_4
PIN_6
PIN_8
PIN_10
PIN_12
PIN_14
PIN_16
PIN_18
PIN_20
PIN_22
PIN_24
PIN_26
PIN_28
PIN_30
PIN_32
PIN_34
PIN_36
PIN_38
PIN_40
Pins GND3
GND4
PIN_42
PIN_44
PIN_46
PIN_48
PIN_50
PIN_52
PIN_54
PIN_56
PIN_58
PIN_60
PIN_62
PIN_64
PIN_66
PIN_68
PIN_70
PIN_72
PIN_74
PIN_76
PIN_78
PIN_80
Pins GND7
GND8
PIN_82
PIN_84
PIN_86
PIN_88
PIN_90
PIN_92
PIN_94
PIN_96
PIN_98
PIN_100
PIN_102
PIN_104
PIN_106
PIN_108
PIN_110
PIN_112
PIN_114
PIN_116
PIN_118
PIN_120
Pins GND11
GND12
PIN_122
PIN_124
PIN_126
PIN_128
PIN_130
PIN_132
PIN_134
PIN_136
PIN_138
PIN_140
PIN_142
PIN_144
PIN_146
PIN_148
PIN_150
PIN_152
PIN_154
PIN_156
PIN_158
PIN_160
Pins GND15
GND16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
163
164
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
167
168
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
171
172
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
175
176
B1_REF_CLK_OUT
JTAG_TMS
B1_USER_C0
B1_SMBCLK
B1_SMBDAT
B1A_TX_CADp0
B1A_TX_CADn0
B1A_TX_CADp1
B1A_TX_CADn1
B1A_TX_CADp2
B1A_TX_CADn2
B1A_TX_CADp3
B1A_TX_CADn3
B1A_TX_CLKp
B1A_TX_CLKn
JTAG_STRATIX_TDO
B1_USER_A1
B1_USER_B1
B1_USER_D1
B1_USER_E1
JTAG_TRST
JTAG_TCK
B1B_RX_CADp0
B1B_RX_CADn0
B1B_RX_CADp1
B1B_RX_CADn1
B1B_RX_CADp2
B1B_RX_CADn2
B1B_RX_CADp3
B1B_RX_CADn3
B1B_RX_CLKp
B1B_RX_CLKn
B1A_TX_CADp4
B1A_TX_CADn4
B1A_TX_CADp5
B1A_TX_CADn5
B1A_TX_CADp6
B1A_TX_CADn6
B1A_TX_CADp7
B1A_TX_CADn7
B1A_TX_CTLp
B1A_TX_CTLn
B1B_RX_CTLn
B1B_RX_CTLp
B1B_RX_CADn7
B1B_RX_CADp7
B1B_RX_CADn6
B1B_RX_CADp6
B1B_RX_CADn5
B1B_RX_CADp5
B1B_RX_CADn4
B1B_RX_CADp4
B1B_RX_CADp4
B1B_RX_CADn4
B1B_RX_CADp5
B1B_RX_CADn5
B1B_RX_CADp6
B1B_RX_CADn6
B1B_RX_CADp7
B1B_RX_CADn7
B1B_RX_CTLp
B1B_RX_CTLn
B1A_TX_CTLn
B1A_TX_CTLp
B1A_TX_CADn7
B1A_TX_CADp7
B1A_TX_CADn6
B1A_TX_CADp6
B1A_TX_CADn5
B1A_TX_CADp5
B1A_TX_CADn4
B1A_TX_CADp4
B1B_RX_CLKn
B1B_RX_CLKp
B1B_RX_CADn3
B1B_RX_CADp3
B1B_RX_CADn2
B1B_RX_CADp2
B1B_RX_CADn1
B1B_RX_CADp1
B1B_RX_CADn0
B1B_RX_CADp0
B1_STOPn
B1_PWROK
B1_USER_E1
B1_USER_D1
B1_USER_B1
B1_USER_A1
JTAG_STRATIX_TDO
B1A_TX_CLKn
B1A_TX_CLKp
B1A_TX_CADn3
B1A_TX_CADp3
B1A_TX_CADn2
B1A_TX_CADp2
B1A_TX_CADn1
B1A_TX_CADp1
B1A_TX_CADn0
B1A_TX_CADp0
B1_REQn
B1_RESETn
B1_USER_C0
B1_SYS_RESETn
B1_REF_CLK_OUT
3.3V
3.3V
QSE-080
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
161
162
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
165
166
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
169
170
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
173
174
3
Bottom Side
PIN_1
PIN_3
PIN_5
PIN_7
PIN_9
PIN_11
PIN_13
PIN_15
PIN_17
PIN_19
PIN_21
PIN_23
PIN_25
PIN_27
PIN_29
PIN_31
PIN_33
PIN_35
PIN_37
PIN_39
GND1 Internal Ground
GND2
PIN_41
PIN_43
PIN_45
PIN_47
PIN_49
PIN_51
PIN_53
PIN_55
PIN_57
PIN_59
PIN_61
PIN_63
PIN_65
PIN_67
PIN_69
PIN_71
PIN_73
PIN_75
PIN_77
PIN_79
GND5 Internal Ground
GND6
PIN_81
PIN_83
PIN_85
PIN_87
PIN_89
PIN_91
PIN_93
PIN_95
PIN_97
PIN_99
PIN_101
PIN_103
PIN_105
PIN_107
PIN_109
PIN_111
PIN_113
PIN_115
PIN_117
PIN_119
GND9 Internal Ground
GND10
PIN_121
PIN_123
PIN_125
PIN_127
PIN_129
PIN_131
PIN_133
PIN_135
PIN_137
PIN_139
PIN_141
PIN_143
PIN_145
PIN_147
PIN_149
PIN_151
PIN_153
PIN_155
PIN_157
PIN_159
GND13 Internal Ground
GND14
Plane
Plane
Plane
Plane
PIN_2
PIN_4
PIN_6
PIN_8
PIN_10
PIN_12
PIN_14
PIN_16
PIN_18
PIN_20
PIN_22
PIN_24
PIN_26
PIN_28
PIN_30
PIN_32
PIN_34
PIN_36
PIN_38
PIN_40
Pins GND3
GND4
PIN_42
PIN_44
PIN_46
PIN_48
PIN_50
PIN_52
PIN_54
PIN_56
PIN_58
PIN_60
PIN_62
PIN_64
PIN_66
PIN_68
PIN_70
PIN_72
PIN_74
PIN_76
PIN_78
PIN_80
Pins GND7
GND8
PIN_82
PIN_84
PIN_86
PIN_88
PIN_90
PIN_92
PIN_94
PIN_96
PIN_98
PIN_100
PIN_102
PIN_104
PIN_106
PIN_108
PIN_110
PIN_112
PIN_114
PIN_116
PIN_118
PIN_120
Pins GND11
GND12
PIN_122
PIN_124
PIN_126
PIN_128
PIN_130
PIN_132
PIN_134
PIN_136
PIN_138
PIN_140
PIN_142
PIN_144
PIN_146
PIN_148
PIN_150
PIN_152
PIN_154
PIN_156
PIN_158
PIN_160
Pins GND15
GND16
3.3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
163
164
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
167
168
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
171
172
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
175
176
Bank 1 HSDI Connectors
HSDI BANK 1A TX INTERFACE
12
12
12
12
B1A_RX_CADp0
B1A_RX_CADn0
5
4
E
12 B1A_TX_CADp[7..0]
12 B1A_TX_CADn[7..0]
B1A_RX_CADp2
B1A_RX_CADn2
HSDI BANK 1A RX INTERFACE
11,15
11,15
11,12
11,12
B1A_RX_CADp3
B1A_RX_CADn3
B1A_RX_CLKp
B1A_RX_CLKn
B1A_RX_CTLp
B1A_RX_CTLn
11,12 B1A_RX_CADp[7..0]
11,12 B1A_RX_CADn[7..0]
B1A_RX_CLKp
B1A_RX_CLKn
D
HSDI BANK 1B TX INTERFACE
B1A_RX_CADp4
B1A_RX_CADn4
12
12
12
12
B1A_RX_CADp5
B1A_RX_CADn5
B1A_RX_CADp6
B1A_RX_CADn6
B1B_TX_CLKp
B1B_TX_CLKn
B1B_TX_CTLp
B1B_TX_CTLn
12 B1B_TX_CADp[7..0]
12 B1B_TX_CADn[7..0]
B1A_RX_CADp7
B1A_RX_CADn7
HSDI BANK 1B RX INTERFACE
B1A_RX_CTLp
B1A_RX_CTLn
15
15
12
12
B1B_TX_CTLn
B1B_TX_CTLp
B1B_RX_CLKp
B1B_RX_CLKn
B1B_RX_CTLp
B1B_RX_CTLn
C
12 B1B_RX_CADp[7..0]
12 B1B_RX_CADn[7..0]
B1B_TX_CADn7
B1B_TX_CADp7
B1B_TX_CADn6
B1B_TX_CADp6
OTHER HSDI CONTROL SIGNALS
B1B_TX_CADn5
B1B_TX_CADp5
15
15
8
8
8
8,17
8,17
8
8
B1B_TX_CADn4
B1B_TX_CADp4
B1B_TX_CLKn
B1B_TX_CLKp
B1_REF_CLK_IN
B1_REF_CLK_OUT
B1_STOPn
B1_REQn
B1_SYS_RESETn
B1_RESETn
B1_PWROK
B1_SMBCLK
B1_SMBDAT
B1B_TX_CADn3
B1B_TX_CADp3
B
HSDI JTAG INTERFACE
17
15
17
17
15,17
B1B_TX_CADn2
B1B_TX_CADp2
B1B_TX_CADn1
B1B_TX_CADp1
B1B_TX_CADn0
B1B_TX_CADp0
JTAG_TMS
JTAG_SAMTEC_TDO
JTAG_TRSTn
JTAG_TCK
JTAG_STRATIX_TDO
HSDI USER SIGNALS
8
8
8
8
8
B1_STOPn
B1_PWROK
B1_USER_E0
B1_USER_D0
B1_USER_B0
B1_USER_A0
JTAG_SAMTEC_TDO
B1_USER_A[1..0]
B1_USER_B[1..0]
B1_USER_C[1..0]
B1_USER_D[1..0]
B1_USER_E[1..0]
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
3.3V
Stratix PCI Development Board
Size
B
Date:
6
B1A_TX_CLKp
B1A_TX_CLKn
B1A_TX_CTLp
B1A_TX_CTLn
B1A_RX_CADp1
B1A_RX_CADn1
QTE-080
7
1
B1_REF_CLK_IN
JTAG_TMS
B1_USER_C1
B1_SMBCLK
B1_SMBDAT
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
2
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
10
of
1
18
A
8
7
6
5
4
3
2
1
BANK 1A HDSI DEBUG
Bank 1 Debug, Bank 6 HSDI Connector
PLACE 226 OHM RESISTORS AS CLOSE TO THE
DATAPATH TAP AS POSSIBLE (MINIMIZE THE
STUB LENGTH)
E
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
226
226
226
226
226
226
226
226
226
226
226
226
226
226
226
226
SAMTEC_RX_CADn0
SAMTEC_RX_CADp0
SAMTEC_RX_CADn1
SAMTEC_RX_CADp1
SAMTEC_RX_CADn2
SAMTEC_RX_CADp2
SAMTEC_RX_CADn3
SAMTEC_RX_CADp3
SAMTEC_RX_CADn4
SAMTEC_RX_CADp4
SAMTEC_RX_CADn5
SAMTEC_RX_CADp5
SAMTEC_RX_CADn6
SAMTEC_RX_CADp6
SAMTEC_RX_CADn7
SAMTEC_RX_CADp7
D
B1A_RX_CTLn
B1A_RX_CTLp
B1A_RX_CLKn
B1A_RX_CLKp
R73
R74
R75
R76
226
226
226
226
SAMTEC_RX_CTLn
SAMTEC_RX_CTLp
SAMTEC_RX_CLKn
SAMTEC_RX_CLKp
C
PLACE THE 75 OHM RESISTORS AS CLOSE TO
THE SAMTEC CONNECTOR TERMINATION PIN AS
POSSIBLE.
B
SAMTEC_RX_CADn0
SAMTEC_RX_CADp0
SAMTEC_RX_CADn1
SAMTEC_RX_CADp1
SAMTEC_RX_CADn2
SAMTEC_RX_CADp2
SAMTEC_RX_CADn3
SAMTEC_RX_CADp3
R77
R78
R79
R80
R81
R82
R83
R84
75
75
75
75
75
75
75
75
SAMTEC_RX_CADn4
SAMTEC_RX_CADp4
SAMTEC_RX_CADn5
SAMTEC_RX_CADp5
SAMTEC_RX_CADn6
SAMTEC_RX_CADp6
SAMTEC_RX_CADn7
SAMTEC_RX_CADp7
R85
R86
R87
R88
R89
R90
R91
R92
75
75
75
75
75
75
75
75
SAMTEC_RX_CTLn
SAMTEC_RX_CTLp
SAMTEC_RX_CLKn
SAMTEC_RX_CLKp
R93
R94
R95
R96
75
75
75
75
7
8
11
12
15
16
19
20
23
24
27
28
31
32
35
36
39
40
43
44
47
48
51
52
55
56
59
60
63
64
67
68
79
80
3
4
71
72
75
76
83
84
87
88
91
92
97
98
99
100
10,15 B1A_RX_CLKp
10,15 B1A_RX_CLKn
Edge-Mount
3.3V
3.3V
10,12 B1A_RX_CTLp
10,12 B1A_RX_CTLn
E
J13
J12
B1A_RX_CADn0
B1A_RX_CADp0
B1A_RX_CADn1
B1A_RX_CADp1
B1A_RX_CADn2
B1A_RX_CADp2
B1A_RX_CADn3
B1A_RX_CADp3
B1A_RX_CADn4
B1A_RX_CADp4
B1A_RX_CADn5
B1A_RX_CADp5
B1A_RX_CADn6
B1A_RX_CADp6
B1A_RX_CADn7
B1A_RX_CADp7
10,12 B1A_RX_CADp[7..0]
10,12 B1A_RX_CADn[7..0]
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
D4N
D4P
D5N
D5P
D6N
D6P
D7N
D7P
D8N
D8P
D9N
D9P
D10N
D10P
D11N
D11P
D12N
D12P
D13N
D13P
D14N
D14P
D15N
D15P
CLKN
CLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
1
2
5
6
9
10
13
14
17
18
21
22
25
26
29
30
33
34
37
38
41
42
45
46
49
50
53
54
57
58
61
62
65
66
69
70
73
74
77
78
81
82
85
86
89
90
93
94
95
96
B6_RESETn 9,17
B6_PWROK 9,17
B6_RX_CTLn 12
B6_RX_CTLp 12
B6_RX_CADn7
B6_RX_CADp7
B6_RX_CADn6
B6_RX_CADp6
B6_RX_CADn5
B6_RX_CADp5
B6_RX_CADn4
B6_RX_CADp4
B6_RX_CLKn 15
B6_RX_CLKp 15
B6_RX_CADn3
B6_RX_CADp3
B6_RX_CADn2
B6_RX_CADp2
B6_RX_CADn1
B6_RX_CADp1
B6_RX_CADn0
B6_RX_CADp0
ASP-65067-01
3.3V
PCB Solder-Side (Bottom)
Bank 6 Receive (Inputs to this board)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
VDD33_1
VDD33_3
VDDLDT_1
GND1
TCK
TMS
TDI
TDO
TRST_L
SCL
SDA
LDT_RESET_L
LDT_PWROK
GND4
LDT_TX_CTLn
LDT_TX_CTLp
GND6
LDT_TX_CADn7
LDT_TX_CADp7
GND8
GND10
LDT_TX_CADn6
LDT_TX_CADp6
GND12
LDT_TX_CADn5
LDT_TX_CADp5
GND14
LDT_TX_CADn4
LDT_TX_CADp4
GND16
GND18
LDT_TX_CLKn
LDT_TX_CLKp
GND20
LDT_TX_CADn3
LDT_TX_CADp3
GND22
LDT_TX_CADn2
LDT_TX_CADp2
GND24
GND26
LDT_TX_CADn1
LDT_TX_CADp1
GND28
LDT_TX_CADn0
LDT_TX_CADp0
GND30
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
GND32
VDDLDT_3
VDD33_5
VDD33_7
121
123
125
127
129
131
GND34
GND36
GND38
GND40
GND42
GND44
VDD33_2
VDD33_4
VDDLDT_2
GND2
CLK100
GND3
RDY
OE_L
WR_L
CS_L0
CS_L1
INT
RESET_L
GND5
LDT_RX_CADp0
LDT_RX_CADn0
GND7
LDT_RX_CADp1
LDT_RX_CADn1
GND9
GND11
LDT_RX_CADp2
LDT_RX_CADn2
GND13
LDT_RX_CADp3
LDT_RX_CADn3
GND15
LDT_RX_CLKp
LDT_RX_CLKn
GND17
GND19
LDT_RX_CADp4
LDT_RX_CADn4
GND21
LDT_RX_CADp5
LDT_RX_CADn5
GND23
LDT_RX_CADp6
LDT_RX_CADn6
GND25
GND27
LDT_RX_CADp7
LDT_RX_CADn7
GND29
LDT_RX_CTLp
LDT_RX_CTLn
GND31
AD9
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
GND33
VDDLDT_4
VDD33_6
VDD33_8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
GND35
GND37
GND39
GND41
GND43
GND45
122
124
126
128
130
132
Internal Ground
Plane Pins
BANK 6 HSDI
12 B6_RX_CADp[7..0]
12 B6_RX_CADn[7..0]
B6_REF_CLK
B6_IO_RDYn
B6_IO_OEn
B6_IO_WRn
B6_IO_CSn
12 B6_TX_CADp[7..0]
12 B6_TX_CADn[7..0]
B6_IO_RESETn
BANK 6 USER BUS
B6_TX_CADp0
B6_TX_CADn0
D
12 B6_IO_AD[31..24]
B6_TX_CADp1
B6_TX_CADn1
B6_TX_CADp2
B6_TX_CADn2
B6_TX_CADp3
B6_TX_CADn3
B6_TX_CLKp
B6_TX_CLKn
12
12
12 B6_REF25_CLK
R254
0
B6_TX_CADp4
B6_TX_CADn4
B6_REF_CLK
C
B6_TX_CADp5
B6_TX_CADn5
R255
0
B6_TX_CADp6
B6_TX_CADn6
12
B6_REF60_CLK
B6_TX_CADp7
B6_TX_CADn7
B6_TX_CTLp
B6_TX_CTLn
12
12
B6_IO_AD24
B6_IO_AD25
B6_IO_AD26
B6_IO_AD27
B6_IO_AD28
B6_IO_AD29
B6_IO_AD30
B6_IO_AD31
B
3.3V
PCB Component-Side (Top)
Bank 6 Transmit (Outputs from this board)
QTE-060-EM
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
11
of
1
18
A
8
7
6
5
Bank 1
4
3
2
Stratix Bank 1, Bank 6
(Switchable 2.5V HyperTransport / 3.3V LVDS)
HSDI BANK 1A TX INTERFACE
10
10
10
10
U2A
E
D
C
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
on
on
on
on
on
on
B1B_RX_CADn0
B1B_RX_CADp0
B1B_RX_CADn4
B1B_RX_CADp4
B1B_RX_CADn1
B1B_RX_CADp1
B1B_RX_CADn5
B1B_RX_CADp5
B1B_RX_CADn2
B1B_RX_CADp2
B1B_RX_CADn6
B1B_RX_CADp6
B1B_RX_CADn7
B1B_RX_CADp7
B1B_RX_CADn3
B1B_RX_CADp3
B1B_RX_CTLn
B1B_RX_CTLp
B1A_RX_CADn0
B1A_RX_CADp0
B1A_RX_CADn4
B1A_RX_CADp4
B1A_RX_CADn5
B1A_RX_CADp5
B1A_RX_CADn1
B1A_RX_CADp1
B1A_RX_CADn6
B1A_RX_CADp6
B1A_RX_CADn2
B1A_RX_CADp2
B1A_RX_CADn7
B1A_RX_CADp7
B1A_RX_CADn3
B1A_RX_CADp3
B1A_RX_CTLn
B1A_RX_CTLp
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
AG28
AH29
AH31
AH32
AG26
AG25
AG29
AG30
AG32
AG31
AF29
AF30
AF31
AF32
AE29
AE30
AE31
AE32
AD29
AD30
AC30
AC29
AD31
AD32
AC31
AB32
AA29
AA28
AB30
AB31
AA30
AA31
Y29
Y30
Y31
Y32
W29
W30
W31
W32
V29
V30
V31
V32
U27
U28
DIFFIO_RX00n
DIFFIO_RX00p
DIFFIO_RX01n
DIFFIO_RX01p
DIFFIO_RX02n
DIFFIO_RX02p
DIFFIO_RX03n
DIFFIO_RX03p
DIFFIO_RX04n
DIFFIO_RX04p
DIFFIO_RX05n
DIFFIO_RX05p
DIFFIO_RX06n
DIFFIO_RX06p
DIFFIO_RX07n
DIFFIO_RX07p
DIFFIO_RX08n
DIFFIO_RX08p
DIFFIO_RX09n
DIFFIO_RX09p
DIFFIO_RX10n
DIFFIO_RX10p
DIFFIO_RX11n
DIFFIO_RX11p
DIFFIO_RX12n
DIFFIO_RX12p
DIFFIO_RX13n/RDN1
DIFFIO_RX13p/RUP1
DIFFIO_RX14n
DIFFIO_RX14p
DIFFIO_RX15n
DIFFIO_RX15p
DIFFIO_RX16n
DIFFIO_RX16p
DIFFIO_RX17n
DIFFIO_RX17p
DIFFIO_RX18n
DIFFIO_RX18p
DIFFIO_RX19n
DIFFIO_RX19p
DIFFIO_RX20n
DIFFIO_RX20p
DIFFIO_RX21n
DIFFIO_RX21p
DIFFIO_RX22n
DIFFIO_RX22p
B1B_TX_CADn3
B1B_TX_CADp3
B1B_TX_CTLn
B1B_TX_CTLp
B1B_TX_CADn2
B1B_TX_CADp2
B1B_TX_CADn7
B1B_TX_CADp7
B1B_TX_CADn1
B1B_TX_CADp1
B1B_TX_CADn6
B1B_TX_CADp6
B1B_TX_CADn5
B1B_TX_CADp5
B1B_TX_CADn0
B1B_TX_CADp0
B1B_TX_CADn4
B1B_TX_CADp4
B1B_TX_CLKn
B1B_TX_CLKp
B1A_TX_CADn3
B1A_TX_CADp3
B1A_TX_CTLn
B1A_TX_CTLp
B1A_TX_CADn0
B1A_TX_CADp0
B1A_TX_CADn6
B1A_TX_CADp6
B1A_TX_CADn7
B1A_TX_CADp7
B1A_TX_CLKn
B1A_TX_CLKp
B1A_TX_CADn2
B1A_TX_CADp2
B1A_TX_CADn1
B1A_TX_CADp1
B1A_TX_CADn5
B1A_TX_CADp5
B1A_TX_CADn4
B1A_TX_CADp4
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
DIFFIO_TX00n
DIFFIO_TX00p
DIFFIO_TX01n
DIFFIO_TX01p
DIFFIO_TX02n
DIFFIO_TX02p
DIFFIO_TX03n
DIFFIO_TX03p
DIFFIO_TX04n
DIFFIO_TX04p
DIFFIO_TX05n
DIFFIO_TX05p
DIFFIO_TX06n
DIFFIO_TX06p
DIFFIO_TX07n
DIFFIO_TX07p
DIFFIO_TX08n
DIFFIO_TX08p
DIFFIO_TX09n
DIFFIO_TX09p
DIFFIO_TX10n
DIFFIO_TX10p
DIFFIO_TX11n
DIFFIO_TX11p
DIFFIO_TX12n
DIFFIO_TX12p
DIFFIO_TX13n
DIFFIO_TX13p
DIFFIO_TX14n
DIFFIO_TX14p
DIFFIO_TX15n
DIFFIO_TX15p
DIFFIO_TX16n
DIFFIO_TX16p
DIFFIO_TX17n
DIFFIO_TX17p
DIFFIO_TX18n
DIFFIO_TX18p
DIFFIO_TX19n
DIFFIO_TX19p
DIFFIO_TX20n
DIFFIO_TX20p
DIFFIO_TX21n
DIFFIO_TX21p
DIFFIO_TX22n
DIFFIO_TX22p
AF25
AF26
AF28
AF27
AE26
AE25
AE27
AE28
AD25
AD26
AD27
AD28
AC28
AC27
AC26
AC25
AB26
AB27
AA26
AA27
AA24
AA25
Y24
Y23
W24
W23
Y27
Y28
Y25
Y26
V23
V24
W28
W27
W26
W25
V27
V28
V25
V26
Y22
Y21
W22
W21
V22
U22
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
GPIO_2B1_0
GPIO_2B1_1
AA22
AB23
(n/c on 1S25)
(n/c on 1S25)
on
on
on
on
on
on
Bank 6
(Switchable 2.5V HyperTransport / 3.3V LVDS)
Differential RX Termination Resistors
DIFFIO_RX67n
DIFFIO_RX67p
DIFFIO_RX68n
DIFFIO_RX68p
DIFFIO_RX69n
DIFFIO_RX69p
DIFFIO_RX70n
DIFFIO_RX70p
DIFFIO_RX71n
DIFFIO_RX71p
DIFFIO_RX72n
DIFFIO_RX72p
DIFFIO_TX67n
DIFFIO_TX67p
DIFFIO_TX68n
DIFFIO_TX68p
DIFFIO_TX69n
DIFFIO_TX69p
DIFFIO_TX70n
DIFFIO_TX70p
DIFFIO_TX71n
DIFFIO_TX71p
DIFFIO_TX72n
DIFFIO_TX72p
W11
W12
Y11
Y12
AB10
AA11
W8
W7
V8
V7
V5
V6
B6_RX_CADn5
B6_RX_CADp5
B6_RX_CADn0
B6_RX_CADp0
Y4
Y3
AA3
AA2
AB3
AB2
AA4
AA5
AC2
AB1
AD2
AD1
AD3
AD4
DIFFIO_RX73n
DIFFIO_RX73p
DIFFIO_RX74n
DIFFIO_RX74p
DIFFIO_RX75n
DIFFIO_RX75p
DIFFIO_RX76n/RDN6
DIFFIO_RX76p/RUP6
DIFFIO_RX77n
DIFFIO_RX77p
DIFFIO_RX78n
DIFFIO_RX78p
DIFFIO_RX79n
DIFFIO_RX79p
DIFFIO_TX73n
DIFFIO_TX73p
DIFFIO_TX74n
DIFFIO_TX74p
DIFFIO_TX75n
DIFFIO_TX75p
DIFFIO_TX76n
DIFFIO_TX76p
DIFFIO_TX77n
DIFFIO_TX77p
DIFFIO_TX78n
DIFFIO_TX78p
DIFFIO_TX79n
DIFFIO_TX79p
V9
V10
W10
W9
Y10
Y9
W5
W6
Y7
Y8
Y5
Y6
AA9
AA8
B6_RX_CADn4
B6_RX_CADp4
B6_RX_CADn6
B6_RX_CADp6
B6_RX_CADn1
B6_RX_CADp1
B6_RX_CADn7
B6_RX_CADp7
B6_RX_CADn2
B6_RX_CADp2
B6_RX_CTLn
B6_RX_CTLp
B6_RX_CADn3
B6_RX_CADp3
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
AC3
AC4
AE2
AE1
AE4
AE3
AF2
AF1
AF4
AF3
AG1
AG2
AG4
AG3
AG7
AG8
AH2
AH1
AG5
AH4
DIFFIO_RX80n
DIFFIO_RX80p
DIFFIO_RX81n
DIFFIO_RX81p
DIFFIO_RX82n
DIFFIO_RX82p
DIFFIO_RX83n
DIFFIO_RX83p
DIFFIO_RX84n
DIFFIO_RX84p
DIFFIO_RX85n
DIFFIO_RX85p
DIFFIO_RX86n
DIFFIO_RX86p
DIFFIO_RX87n
DIFFIO_RX87p
DIFFIO_RX88n
DIFFIO_RX88p
DIFFIO_RX89n
DIFFIO_RX89p
DIFFIO_TX80n
DIFFIO_TX80p
DIFFIO_TX81n
DIFFIO_TX81p
DIFFIO_TX82n
DIFFIO_TX82p
DIFFIO_TX83n
DIFFIO_TX83p
DIFFIO_TX84n
DIFFIO_TX84p
DIFFIO_TX85n
DIFFIO_TX85p
DIFFIO_TX86n
DIFFIO_TX86p
DIFFIO_TX87n
DIFFIO_TX87p
DIFFIO_TX88n
DIFFIO_TX88p
DIFFIO_TX89n
DIFFIO_TX89p
AA6
AA7
AB7
AB6
AC7
AC8
AC5
AC6
AD8
AD7
AE6
AE5
AD6
AD5
AE7
AE8
AF5
AF6
AF8
AF7
(n/c on 1S25)
AB9
GPIO_B6_0
R115
R117
R119
R121
R123
R125
R127
R129
R131
B1B_RX_CADp0
B1B_RX_CADp1
B1B_RX_CADp2
B1B_RX_CADp3
B1B_RX_CADp4
B1B_RX_CADp5
B1B_RX_CADp6
B1B_RX_CADp7
B1B_RX_CTLp
A
on
on
on
on
on
on
AC10
GPIO_B6_1
(n/c
(n/c
(n/c
(n/c
(n/c
(n/c
on
on
on
on
on
on
1S25)
1S25)
1S25)
1S25)
1S25)
1S25)
B6_TX_CADn2
B6_TX_CADp2
B6_TX_CADn7
B6_TX_CADp7
B6_TX_CTLn
B6_TX_CTLp
HSDI BANK 1A RX INTERFACE
10,11 B1A_RX_CTLp
10,11 B1A_RX_CTLn
10,11 B1A_RX_CADp[7..0]
10,11 B1A_RX_CADn[7..0]
B6_TX_CADn6
B6_TX_CADp6
B6_TX_CADn3
B6_TX_CADp3
B6_TX_CADn5
B6_TX_CADp5
B6_TX_CADn1
B6_TX_CADp1
B6_TX_CADn4
B6_TX_CADp4
B6_TX_CLKn
B6_TX_CLKp
B6_TX_CADn0
B6_TX_CADp0
HSDI BANK 1B TX INTERFACE
10
10
10
10
D
B1B_TX_CLKp
B1B_TX_CLKn
B1B_TX_CTLp
B1B_TX_CTLn
10 B1B_TX_CADp[7..0]
10 B1B_TX_CADn[7..0]
HSDI BANK 1B RX INTERFACE
10 B1B_RX_CTLp
10 B1B_RX_CTLn
C
10 B1B_RX_CADp[7..0]
10 B1B_RX_CADn[7..0]
B6_TESTn0
B6_TESTp0
HSDI BANK 6 TX INTERFACE
B6_TESTn1
B6_TESTp1
11
11
11
11
B6_TESTn2
B6_TESTp2
(n/c on 1S25)
B6_TX_CLKp
B6_TX_CLKn
B6_TX_CTLp
B6_TX_CTLn
11 B6_TX_CADp[7..0]
11 B6_TX_CADn[7..0]
B
Differential I/O Test Points
TP8
TP9
TP10
TP11
TP12
R116
R118
R120
R122
R124
R126
R128
R130
R132
B1A_RX_CADp0
B1A_RX_CADp1
B1A_RX_CADp2
B1A_RX_CADp3
B1A_RX_CADp4
B1A_RX_CADp5
B1A_RX_CADp6
B1A_RX_CADp7
B1A_RX_CTLp
Differential RX Termination Resistors
TP13
B6_TESTp0
B6_TESTn0
B6_TESTp1
B6_TESTn1
HSDI BANK 6 RX INTERFACE
100
B6_RX_CADn0
B6_RX_CADn1
B6_RX_CADn2
B6_RX_CADn3
B6_RX_CADn4
B6_RX_CADn5
B6_RX_CADn6
B6_RX_CADn7
B6_RX_CTLn
100
B1A_RX_CADn0
B1A_RX_CADn1
B1A_RX_CADn2
B1A_RX_CADn3
B1A_RX_CADn4
B1A_RX_CADn5
B1A_RX_CADn6
B1A_RX_CADn7
B1A_RX_CTLn
E
10 B1A_TX_CADp[7..0]
10 B1A_TX_CADn[7..0]
EP1S40F1020
100
B1B_RX_CADn0
B1B_RX_CADn1
B1B_RX_CADn2
B1B_RX_CADn3
B1B_RX_CADn4
B1B_RX_CADn5
B1B_RX_CADn6
B1B_RX_CADn7
B1B_RX_CTLn
B1A_TX_CLKp
B1A_TX_CLKn
B1A_TX_CTLp
B1A_TX_CTLn
U2F
U5
U6
V2
V1
V4
V3
W2
W1
W4
W3
Y2
Y1
EP1S40F1020
B
1
R133
R134
R135
R136
R137
R138
R139
R140
R141
11 B6_RX_CTLp
11 B6_RX_CTLn
B6_RX_CADp0
B6_RX_CADp1
B6_RX_CADp2
B6_RX_CADp3
B6_RX_CADp4
B6_RX_CADp5
B6_RX_CADp6
B6_RX_CADp7
B6_RX_CTLp
11 B6_RX_CADp[7..0]
11 B6_RX_CADn[7..0]
B6_TESTp2
B6_TESTn2
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
12
of
1
18
A
8
7
6
5
4
3
2
1
10/100 Ethernet Interface
3.3V
LAN_RESET
LAN_ADSn
LAN_LCLK
LAN_ IOCHRDY
LAN_RDYRTNn
LAN_INTRQ0
LAN_LDEVn
LAN_IORn
LAN_IOWn
LAN_CYCLEn
LAN_W_Rn
A
30
37
42
38
46
43
29
45
31
32
34
35
36
40
RESET
ADSn
LCLK
ARDY
RDYRTNn
SRDYn
INTR0
LDEVn
RDn
WRn
DATACSn
CYCLEn
W_Rn
VLBUSn
LAN91C111
22
23
RXD3
RXD2
RXD1
RXD0
121
122
123
124
TXD3
TXD2
TXD1
TXD0
113
114
115
116
TXEN100
CRS100
COL100
RXDV
RXER
MDI
MDO
MCLK
RX25
TX25
111
119
112
125
126
25
26
27
118
109
IOS0
IOS1
IOS2
ENEEP
ENDO
ENDI
EESK
EECS
3
4
5
6
7
8
9
10
XTAL2
128
XTAL1
127
CSOUTn
X25OUT
R30 1
R31 1
2 24.9
2 24.9
R32
VCCA
LAN_RXDp
LAN_RXDn
0
OCT
NC0
TDN
TDP
TCT
RCT
RDN
RDP
RJ45INTLED
LAN_LOOPBACK
14
E
15
MNT0
2
8
7
3
1
2
5
6
4
SMNT1
1
1
1
LAN_TXDp
LAN_TXDn
RJ1
MNT1
LEDAn
LEDBn
R29
24.9
D4
12
D3
11
D2
10
D1
9
R33
Integrated RJ45
LAN_LEDA_n
LAN_LEDB_n
11K
D
3.3V
(includes LEDs and magnetics)
L10
1
VCCA
C224
0.1uF
X7R
47nH
2
C225
0.001uF
X7R
C226
1.0uF
X7R
3.3V
LAN_ENEEP
R34
330
LAN_D16
LAN_D17
LAN_D18
LAN_D19
LAN_D20
LAN_D21
LAN_D22
LAN_D23
RN6
1
2
3
4
5
6
7
8
10K
16
15
14
13
12
11
10
9
LAN_D24
LAN_D25
LAN_D26
LAN_D27
LAN_D28
LAN_D29
LAN_D30
LAN_D31
RN7
1
2
3
4
5
6
7
8
10K
16
15
14
13
12
11
10
9
RN8
LAN_CYCLEn 1
LAN_W_Rn
2
LAN_RDYRTNn3
LAN_ADSn
4
LAN_LCLK
5
LAN_BEn3
6
LAN_BEn2
7
LAN_OSC_EN 8
10K
16
15
14
13
12
11
10
9
C
8 LAN_D[31..0]
8 LAN_A[14..0]
8 LAN_BEn[3..0]
8
8
8
8
8
8
8
8
LAN_RESET
LAN_INTRQ0
LAN_AEN
LAN_IORn
LAN_IOWn
LAN_IOCHRDY
LAN_LDEVn
LAN_LOOPBACK
B
CLK_25MHZ
3.3V
2
47
OSC1
1
2
3
EN
NC1
GND
OUT
NC2
VCC
CLK_25MHZ
4
5
6
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
OSC_SMT
Title
Stratix PCI Development Board
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
7
LAN_LEDA_n
LAN_RBIAS
Size
B
8
LAN_LEDB_n
16
20
21
28
12
C223
0.001uF
X7R
SMNT0
LNKn
LBK
CNTRLn
RBIAS
R28
24.9
2
11
16
14
15
17
18
R27
24.9
2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
2
107
106
105
104
102
101
100
99
76
75
74
73
71
70
69
68
66
65
64
63
61
60
59
58
56
55
54
53
51
50
49
48
PHY
LAN_D0
LAN_D1
LAN_D2
LAN_D3
LAN_D4
LAN_D5
LAN_D6
LAN_D7
LAN_D8
LAN_D9
LAN_D10
LAN_D11
LAN_D12
LAN_D13
LAN_D14
LAN_D15
LAN_D16
LAN_D17
LAN_D18
LAN_D19
LAN_D20
LAN_D21
LAN_D22
LAN_D23
LAN_D24
LAN_D25
LAN_D26
LAN_D27
LAN_D28
LAN_D29
LAN_D30
LAN_D31
LAN91C111
MII INTERFACE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
EEPROM
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
AVSS_13
AVSS_19
AEN
LAN_A0
LAN_A1
LAN_A2
LAN_A3
LAN_A4
LAN_A5
LAN_A6
LAN_A7
LAN_A8
LAN_A9
LAN_A10
LAN_A11
LAN_A12
LAN_A13
LAN_A14
VDD_1
VDD_33
VDD_44
VDD_62
VDD_77
VDD_98
VDD_110
VDD_120
41
TPO+
TPOTPI+
TPI-
ENET_AGND
2
3.3V
13
19
B
LAN_AEN
LOCAL BUS INTERFACE PINS
C
BE3n
BE2n
BE1n
BE0n
24
39
52
57
67
72
93
103
108
117
D
97
96
95
94
VSS_24
VSS_39
VSS_52
VSS_57
VSS_67
VSS_72
VSS_93
VSS_103
VSS_108
VSS_117
LAN_BEn3
LAN_BEn2
LAN_BEn1
LAN_BEn0
R26
24.9
AVDD_11
AVDD_16
1
33
44
62
77
98
110
120
1
E
U11
1
C222
0.01uF
X7R
13
MAC/PHY
3.3V
R25
23
3.3V
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
13
of
1
18
8
7
6
5
4
3
2
Expansion Prototype Card (PROTO1), RS-232, LCD, Mictor
1
SANTA CRUZ
8 SCRUZ_IO[39..0]
MICTOR / LCD
J2
1
3
5
7
9
11
13
E
SCRUZ_IO30
SCRUZ_IO32
SCRUZ_IO34
SCRUZ_IO36
SCRUZ_IO38
+12V
Vunreg on
NIOS
Board
2
4
6
8
10
12
14
J3
SYS_RESETn 5,8,17
SCRUZ_IO0
SCRUZ_IO2
SCRUZ_IO4
SCRUZ_IO6
SCRUZ_IO8
SCRUZ_IO10
SCRUZ_IO12
SCRUZ_IO14
SCRUZ_IO29
SCRUZ_IO31
SCRUZ_IO33
SCRUZ_IO35
SCRUZ_IO37
SCRUZ_IO39
HDR2X7
3.3V
J4
1
3
5
7
9
11
13
15
17
19
CLK_OSC_A 15,17
CLK_TO_SCRUZ 15
D
1
3
5
7
9
11
13
2
4
6
8
10
12
14
CLK_FROM_SCRUZ 15
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
SCRUZ_IO16
SCRUZ_IO17
SCRUZ_IO18
SCRUZ_IO19
SCRUZ_IO21
SCRUZ_IO22
SCRUZ_IO24
SCRUZ_IO25
SCRUZ_IO27
SCRUZ_IO28
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
8 MICTOR_DE[15..0]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SCRUZ_IO1
SCRUZ_IO3
SCRUZ_IO5
SCRUZ_IO7
SCRUZ_IO9
SCRUZ_IO11
SCRUZ_IO13
SCRUZ_IO15
E
8 MICTOR_DO[15..0]
8 MICTOR_CLKO
8 MICTOR_CLKE
SCRUZ_IO20
SCRUZ_IO23
SCRUZ_IO26
8 SCRUZ_CARDSELn
D
HDR2X20
3.3V
HDR2X10
R22
1K
R21
47
C216
10pF
LCD HEADER
5.0V
5.0V
J5
C
MICTOR_DE12
C217
0.1uF
X7R
C218
0.1uF
X7R
MICTOR CONNECTOR
RS232 LEVEL SHIFTER
3.3V
J6
U10
1
3
4
5
B
C1+
C1C2+
C2-
VCC
V+
VGND
16
2
6
15
RS232_TXD 5
RS232_CTS 5
11
10
TX1IN TX1OUT
TX2IN TX2OUT
14
7
RS232_RXD 5
RS232_RTS 5
12
9
RX1OUT RX1IN
RX2OUT RX2IN
13
8
C219
0.1uF
X7R
C220
0.1uF
X7R
C221
0.1uF
X7R
LTC1386
FEMALE
RS232 CONNECTOR
RS232 ACTIVITY INDICATORS
J7
3.3V
TX
D1 LED
RS232_TXD R23
200
C
DB9_CTS
DB9_RXD
DB9_RTS
DB9_TXD
A
RX
A
D2 LED
RS232_RXD R24
200
C
MICTOR_DE1
MICTOR_DE3
MICTOR_DE5
MICTOR_DE6
MICTOR_DE8
MICTOR_CLKE
MICTOR_DE15
MICTOR_DE14
MICTOR_DE13
MICTOR_DE12
MICTOR_DE11
MICTOR_DE10
MICTOR_DE9
MICTOR_DE8
MICTOR_DE7
MICTOR_DE6
MICTOR_DE5
MICTOR_DE4
MICTOR_DE3
MICTOR_DE2
MICTOR_DE1
MICTOR_DE0
5
9
4
8
3
7
2
6
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
5VDC
GND
CLKE
D15E
D14E
D13E
D12E
D11E
D10E
D9E
D8E
D7E
D6E
D5E
D4E
D3E
D2E
D1E
D0E
SCL
SDA
CLKO
D15O
D14O
D13O
D12O
D11O
D10O
D9O
D8O
D7O
D6O
D5O
D4O
D3O
D2O
D1O
D0O
GND1
GND2
GND3
GND4
GND5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
39
40
41
42
43
MICTOR_DE10
MICTOR_CLKO
MICTOR_DO15
MICTOR_DO14
MICTOR_DO13
MICTOR_DO12
MICTOR_DO11
MICTOR_DO10
MICTOR_DO9
MICTOR_DO8
MICTOR_DO7
MICTOR_DO6
MICTOR_DO5
MICTOR_DO4
MICTOR_DO3
MICTOR_DO2
MICTOR_DO1
MICTOR_DO0
MICTOR_DO1
MICTOR_DO3
MICTOR_DO5
MICTOR_DE13
MICTOR_DE14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
17
19
21
23
25
27
29
31
MICTOR TO LCD SIGNAL MAP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
MICTOR_CLKE
MICTOR_DO6
MICTOR_DE0
MICTOR_DE2
MICTOR_DE4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
MICTOR_DE7
MICTOR_DE9
MICTOR_DE11
MICTOR_DO0
MICTOR_DO2
MICTOR_DO4
MICTOR_DE15
DF9B-31P-1V
C
MICTOR_CLKE => LCD_CLK
MICTOR_DE0
MICTOR_DE1
MICTOR_DE2
MICTOR_DE3
MICTOR_DE4
MICTOR_DE5
=>
=>
=>
=>
=>
=>
LCD_RED0
LCD_RED1
LCD_RED2
LCD_RED3
LCD_RED4
LCD_RED5
MICTOR_DE6
MICTOR_DE7
MICTOR_DE8
MICTOR_DE9
MICTOR_DE10
MICTOR_DE11
=>
=>
=>
=>
=>
=>
LCD_GREEN0
LCD_GREEN1
LCD_GREEN2
LCD_GREEN3
LCD_GREEN4
LCD_GREEN5
MICTOR_DO0
MICTOR_DO1
MICTOR_DO2
MICTOR_DO3
MICTOR_DO4
MICTOR_DO5
=>
=>
=>
=>
=>
=>
LCD_BLUE0
LCD_BLUE1
LCD_BLUE2
LCD_BLUE3
LCD_BLUE4
LCD_BLUE5
MICTOR_DE12
MICTOR_DE13
MICTOR_DE14
MICTOR_DE15
MICTOR_DO6
=>
=>
=>
=>
=>
LCD_HSYNC
LCD_DISABLE
LCD_UP_N_DOWN
LCD_RIGHT_N_LEFT
LCD_VSYNC
B
MICTOR_HDR
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
DB9
A
1
3
5
7
9
11
13
15
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
14
of
1
18
A
8
7
6
5
4
3
Clocking, JTAG Bypass Jumper
Configuration / System Clock
1
Differential input termination resistors for
High-Speed Bank 1 and Bank 6 clock inputs.
(socketed half-can oscillator)
3.3V
2
B1A_RX_CLKp
R97
100
B1A_RX_CLKn
14,17 CLK_OSC_A
B1B_RX_CLKp
R98
100
B1B_RX_CLKn
Also drives MAX3256A for configuration and
Santa Cruz Daughtercard for potential use on
a daughtercard. AC termination on sheet 14.
B6_RX_CLKp
R99
100
B6_RX_CLKn
J14
1
E
NC
8
C236
0.1uF
X7R
C237
0.01uF
X7R
VDD
C238
1.0uF
X7R
OUTPUT
5
GND
4
CLK_OSC_A
1108800
E
PLL5 Output Vcc = 2.5V
(Default = 33 MHz)
PLL6 Output Vcc = 3.3V
U2J
(place near socketed oscillators)
CLK_SMA
CLK_SMA
TP18
B1_REF_CLK_IN 10
B1A_RX_CLKn 10,11
B1A_RX_CLKp 10,11
CLK_OSC_B
D
R103
High-Speed Clock
30
CLK_OSC_A
CLK_OSC_B
(socketed half-can oscillator)
3.3V
R110
CLK_OSC_B_PLL2
R106
LPCI_RSTn 3,4
CLK_OSC_A_PLL6
30
30
CLK_OSC_B_PLL6
CLK_SMA
CLK_SMA
LPCI_TRDYn 3,4
LPCI_CLK 3,4
J15
C239
0.1uF
X7R
C240
0.01uF
X7R
C241
1.0uF
X7R
1
NC
8
VDD
OUTPUT
5
GND
4
CLK_OSC_B
B6_RX_CLKn 11
B6_RX_CLKp 11
R108
30
A15
B15
C15
CLK_FROM_SCRUZ 14 D15
B19
CLK_OSC_A_PLL5
A19
D19
CLK_OSC_B_PLL5
C19
CLK12n
CLK12p
CLK13n
CLK13p
CLK14n
CLK14p
CLK15n
CLK15p
CLK_OSC_B_PLL3
B6_REF25_CLK16
CLK_OSC_A
R111
30
CLK_OSC_A_PLL4
DDR_CLK_FBIN
CLK_OSC_A
CLK_OSC_B
SMA Connector
R113
R112
30
30
(n/c on 1S25)
(n/c on 1S25)
(external clock source)
B1B_RX_CLKn 10
B1B_RX_CLKp 10
3
B
GND1
GND2
GND3
Output
4
1
GND4
5
1053378-1
(n/c on 1S25)
JTAG BYPASS JUMPERS
POSITION
SHUNT ONE
SHUNT TWO
SINGLE (default)
-n/a-
PIN1-PIN3
PIN4-PIN6
DOUBLE (w/bank 1)
NEAR
PIN1-PIN3
PIN2-PIN4
DOUBLE (w/bank 1)
FAR
PIN3-PIN5
PIN2-PIN4
JTAG_CONN_TDO 17
PLL6
PLL12
PLL9
PLL3
PLL10
PLL4
PLL7
(n/c on 1S25)
(n/c on 1S25)
L5
L4
FPLL10CLKn
FPLL10CLKp
B6_REF60_CLK16
(n/c on 1S25)
AB4
AB5
DDR_CLK_FBIN
PLL_ENA
PLL5_FBn
PLL5_FBp
AM17
AL17
PLL6_FBn
PLL6_FBp
PLL5_OUT1n
PLL5_OUT1p
A17
B17
6 DDR_CLK1n
6 DDR_CLK1p
PLL5_OUT2n
PLL5_OUT2p
A18
B18
6 DDR_CLK2n
6 DDR_CLK2p
PLL5_OUT3n
PLL5_OUT3p
C18
D18
PLL6_OUT0n
PLL6_OUT0p
AM16
AL16
R101
50
14 CLK_TO_SCRUZ
PLL6_OUT1n
PLL6_OUT1p
AK16
AJ16
R102
50
10 B1_REF_CLK_OUT
PLL6_OUT2n
PLL6_OUT2p
AK17
AJ17
R104
50
17 CLK_TO_MAX_A
PLL6_OUT3n
PLL6_OUT3p
AM18
AL18
D
DDR_CLK_FBOUT R251
50
DDR_CLK_FBIN
(DD_CLK_FBOUT/DDR_CLK_FBIN)
FPLL7CLKn
FPLL7CLKp
C17
D17
6 DDR_CLK0n
6 DDR_CLK0p
PLL5
L28
L29
AF19
A16
B16
PLL11
(n/c on 1S25)
(n/c on 1S25)
FPLL9CLKn
FPLL9CLKp
PLL5_OUT0n
PLL5_OUT0p
C
PLL8
PLL_ENA 16
BOARDS IN CHAIN
PLL7
PLL2
FPLL8CLKn
FPLL8CLKp
CLK_SMA
R114
50
PLL7
PLL1
AB29
AB28
J16
2
CLK4n
CLK4p
CLK5n
CLK5p
CLK6n
CLK6p
CLK7n
CLK7p
CLK8n
CLK8p
CLK9n
CLK9p
CLK10n
CLK10p
CLK11n
CLK11p
(Default = 100 MHz)
C
AL19
AM19
AJ19
AK19
AJ15
AK15
AL15
AM15
CLK0n
CLK0p
CLK1n
CLK1p
CLK2n
CLK2p
CLK3n
CLK3p
U3
U4
U1
U2
T5
T6
T3
T4
1108800
CLK_OSC_B
T30
T29
T28
T27
U32
U31
U30
U29
Note: DDR_CLK_FB fed into upper bank pin to be
designated for generation of the strobe skew
delays. CLK12p pin should be designated for
DQS shifting. (Clock Input Pin B15)
PLL10
Note: DDR_CLK_FB can be used for board-level
de-skew of DDR clocks between the internal
Stratix registers and the DDR SO_DIMM's
memory. (Clock Input Pin C17)
PLL9
B
EP1S40F1020
10 JTAG_SAMTEC_TDO
J17
1
3
5
JTAG_MAX_TDI 17
A
2
4
6
CON6A
JTAG_CONN_TDI
17 JTAG_CONN_TDI
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
10,17 JTAG_STRATIX_TDO
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
7
Date:
6
5
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
15
of
1
18
A
7
6
L1
60R100M6A 2.5V
1
2
IN
SHDN
GND
2.5V_RAW
4
6
5
OUT
GNDPAD
SENSE/ADJ
1
3.3V_INPUT1
2
2.5V_SHDNn 1
3
2
U5
3.3V_INPUT2
2
1
3
1
2
1
1
R17
2.2K
IN
SHDN
GND
4
6
5
OUT
GNDPAD
SENSE/ADJ
R19
1K
R18
4.12K
+12V
U9
3.3V_SENSE2
3.3V_SENSE1
3.3V
1
2
3
4
3.3V
OUTA
INAINA+
V-
V+
OUTB
INBINB+
8
7
6
5
J19
CON4PIN
AUX_IN
1
2
3
4
LT1366
D17
SB5100
U7
MIC29502BU
GND
2
+1.5V @ 5A
4
1.5V_RAW
ADJ
5
R252
64.9
1
VO
ADJ
+
2
+
TAB
1
3
EN
VI
6
1
2
VCC2.6
C189
100uF
10V
Tantalum
Keep 2.5V_SE NSE
nod e at 1.21V DC
2.5V_SENSE_AMPOUT
C188
0.01uF
X7R
D
U2K
2.5V_SENSE
LT1764AEQ
2
2
R16
2.2K
C243
0.01uF
X7R
R14
4.42K
2
R15
0.01
L2
60R100M6A
1
2
C190
100uF
10V
Tantalum
+12V
LCD BACK LIGHT INVERTER
P OWER CONNECTOR
1.5V
5.0V 3.3V
EXTERNAL POWER I NPUT
3.3V
-12V
J18
1
3
5
7
9
11
R253
310
2
4
6
8
10
12
17
MAIN_SW
CON12A
L11
600R100M1A
1
2
L12
600R100M1A
1
2
TEMPERATURE SENSE
C
U8
TEMPDIODEp
TEMPDIODEn
3.3V
6
10
ADD1
ADD0
3
4
DXP
DXN
R20
C191
0.1uF
X7R
200
15
1
STBY
VCC
OVERT
ALERT
9
11
SMBCLK
SMBDATA
14
12
5,17 OVERTEMPn
5,17 ALERTn
5
5
VCCA_PLL3_PLL9
C197
0.1uF
X7R
L6
600R100M1A
1
2
C198
0.01uF
X7R
L3
600R100M1A
1
2
C199
0.001uF
X7R
1.5V
VCCA_PLL5_PLL11
C192
2.2uF
X7R
C193
0.1uF
X7R
VCCA_PLL4_PLL10
C201
0.1uF
X7R
L8
600R100M1A
1
2
C202
0.01uF
X7R
L7
600R100M1A
1
2
C194
0.01uF
X7R
C195
0.001uF
X7R
1.5V
C200
2.2uF
X7R
C203
0.001uF
X7R
1.5V
A
L5
600R100M1A
1
2
1.5V
C196
2.2uF
X7R
VCCA_PLL1_PLL7
VCCA_PLL2_PLL8
VCCA_PLL3_PLL9
VCCA_PLL4_PLL10
VCCA_PLL5_PLL11
VCCA_PLL6_PLL12
VCCA_PLL1_PLL7
VCCA_PLL2_PLL8
VCCA_PLL3_PLL9
VCCA_PLL4_PLL10
VCCA_PLL5_PLL11
VCCA_PLL6_PLL12
L13
600R100M1A
1
2
MAX1619
L4
600R100M1A
1
2
TEMPDIODEn
TEMPDIODEp
L14
600R100M1A
1
2
1.5V
B
SMB_CLK
SMB_DATA
2
7
8
GND1
GND2
GND3
VCCA_PLL6_PLL12
M12
M14
M19
M21
N13
N15
N18
N20
P12
P14
P16
P17
P19
P21
R13
R15
R18
R20
T14
T16
T17
T19
U14
U16
U17
U19
V13
V15
V18
V20
W14
W16
W17
W19
Y13
Y15
Y18
Y20
VCCINT1
VCCINT2
VCCINT3
VCCINT4
VCCINT5
VCCINT6
VCCINT7
VCCINT8
VCCINT9
VCCINT10
VCCINT11
VCCINT12
VCCINT13
VCCINT14
VCCINT15
VCCINT16
VCCINT17
VCCINT18
VCCINT19
VCCINT20
VCCINT21
VCCINT22
VCCINT23
VCCINT24
VCCINT25
VCCINT26
VCCINT27
VCCINT28
VCCINT29
VCCINT30
VCCINT31
VCCINT32
VCCINT33
VCCINT34
VCCINT35
VCCINT36
VCCINT37
VCCINT38
F18
E18
TEMPDIODEn
TEMPDIODEp
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
C208
2.2uF
X7R
C209
0.1uF
X7R
C210
0.01uF
X7R
C211
0.001uF
X7R
H24
AA16
AA17
AC1
AC32
AL1
AL2
AL31
AL32
AM10
AM2
AM23
AM31
B1
B2
B31
B32
K1
K32
M13
M15
M16
M17
AD17
AF17
J17
H18
M18
M20
N12
N14
N16
N17
N19
N21
P13
P15
P18
U2L
VCCIO_B1
3.3V
2.5V
3.3V
J20
CON6A
2.5V
SSTL2_VREF 6
2.5V
3.3V
VCCA_PLL1
VCCA_PLL2
VCCA_PLL3
VCCA_PLL4
VCCA_PLL5
VCCA_PLL6
VCCA_PLL07
VCCA_PLL08
VCCA_PLL09
VCCA_PLL10
VCCA_PLL11
VCCA_PLL12
GNDA_PLL1
GNDA_PLL2
GNDA_PLL3
GNDA_PLL4
GNDA_PLL5
GNDA_PLL6
GNDA_PLL07
GNDA_PLL08
GNDA_PLL09
GNDA_PLL10
GNDA_PLL11
GNDA_PLL12
T26
U26
U7
T7
F17
AH17
D32
AJ32
AJ1
D1
E17
AH16
R22
U24
V11
T9
J16
AD16
D30
AJ30
AJ3
D3
H16
AF16
VCCG_PLL1
VCCG_PLL2
VCCG_PLL3
VCCG_PLL4
VCCG_PLL5
VCCG_PLL6
VCCG_PLL07
VCCG_PLL08
VCCG_PLL09
VCCG_PLL10
VCCG_PLL11
VCCG_PLL12
GNDG_PLL1
GNDG_PLL2
GNDG_PLL3
GNDG_PLL4
GNDG_PLL5
GNDG_PLL6
GNDG_PLL07
GNDG_PLL08
GNDG_PLL09
GNDG_PLL10
GNDG_PLL11
GNDG_PLL12
T22
T24
U11
U9
L16
AB16
E30
AH30
AH3
E3
H15
AE16
VCCIO_B6 18
3.3V
3.3V
VCCIO1_1
VCCIO1_2
VCCIO1_3
VCCIO1_4
VREF2B1
VREF3B1
VREF4B1
C31
C32
M32
T23
R21
L25
F27
VCCIO2_1
VCCIO2_2
VCCIO2_3
VCCIO2_4
VREF2B2
VREF3B2
VREF4B2
A21
A30
K17
E27
E25
E23
E21
VCCIO3_1
VCCIO3_2
VCCIO3_3
VREF2B3
VREF3B3
VREF4B3
VREF5B3
A12
A3
K16
E12
E10
E8
E6
VCCIO4_1
VCCIO4_2
VCCIO4_3
VREF2B4
VREF3B4
VREF4B4
VREF5B4
C1
C2
M1
T10
F6
L8
R12
VCCIO5_1
VCCIO5_2
VCCIO5_3
VCCIO5_4
VREF2B5
VREF3B5
VREF4B5
AA1
AK1
AK2
U10
AA10
AB8
AG6
VCCIO6_1
VCCIO6_2
VCCIO6_3
VCCIO6_4
VREF2B6
VREF3B6
VREF4B6
AC16
AM12
AM3
AH6
AH8
AH10
AH12
VCCIO7_1
VCCIO7_2
VCCIO7_3
VREF2B7
VREF3B7
VREF4B7
VREF5B7
AC17
AM21
AM30
AH21
AH23
AH25
AH27
VCCIO8_1
VCCIO8_2
VCCIO8_3
VREF2B8
VREF3B8
VREF4B8
VREF5B8
TP4
C204
2.2uF
X7R
C205
0.1uF
X7R
L9
600R100M1A
1
2
C206
0.01uF
X7R
C207
0.001uF
X7R
C213
0.1uF
X7R
C214
0.01uF
X7R
OVERTEMPn
ALERTn
SMB_CLK
SMB_DATA
PLL_ENA 15
AUX_IN
C215
0.001uF
X7R
2.5V_SHDNn
RN5
1
2
3
4
5
6
7
8
10K
16
15
14
13
12
11
10
9
5
TP2
3.3V
VCC_PLL5_OUTA
VCC_PLL5_OUTB
H17
L17
VCC_PLL6_OUTA
VCC_PLL6_OUTB
AE17
AB17
E
D
2.5V
C
3.3V
B
TP7
TP5
5.0V
+12V
-12V
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Date:
6
P20
R14
R16
R17
R19
T12
T13
T15
T18
T20
T21
U12
U13
U15
U18
U20
U21
V14
V16
V17
V19
W13
W15
W18
W20
Y14
Y16
Y17
Y19
A10
A2
A23
A31
3.3V
VCCA_PLL2_PLL8
C212
2.2uF
X7R
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
EP1S40F1020
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
7
AA32
AK31
AK32
U23
AB25
AA23
V21
EP1S40F1020
Size
B
8
1
VCCIO_B1 18
VCCIO_B6
T25
U25
U8
T8
G17
AG17
D31
AJ31
AJ2
D2
E16
AG16
1.5V
VCCA_PLL1_PLL7
2
BANK 1 / BANK 6
VCCIO SELECT
1.5V
C242
47uF
10V
TAN
+
LT1764AEQ-2.5
E
3
2
4
6
U4
1
4
Power, Temperature Sense
+2.5V @ 6A (3A each)
R13
0.01
3.3V
5
1
3
5
8
4
3
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
2
Sheet
B
16
of
1
18
A
8
7
6
5
4
3
CPLD, Flash Memory, Dipswitches
3.3V
2
1
5 FLASH_D[15..0]
5,8 USER_PB[2..1]
5 FLASH_A[21..0]
GCLK1
GCLK2
GCLRn
OE1
JTAG_MAX_TDI 15
JTAG_TMS
JTAG_TCK
JTAG_MAX_TDOA
0
TDI
TMS
TCK
TDO
4
20
89
104
2
OVERTEMPn
1
ALERTn
143
142
EP1S_INIT_DONE
141
140
EP1S_CONF_DONEn 5 139
D
EP1S_nCONFIG
EP1S_nSTATUS
EP1S_CONF_DONE
CRC_ERROR
CRC_ERRORn 5
USE_MPGM
MPGM0
MPGM1
B1_RESETn
B1_PWROK
B6_RESETn
B6_PWROK
C
8,10
8,10
9,11
9,11
USER_LED_DRV0
USER_LED0
B
10
9
8
7
6
5
B19
B21
B24
B25
B27
B29
36
35
34
32
31
30
29
28
C33
C35
C37
C40
C41
C43
C45
C48
44
43
42
41
40
39
38
37
D49
D51
D53
D54
D56
D59
D61
D64
USER_LED_DRV1
USER_LED1
USER_LED_DRV2
USER_LED2
USER_LED_DRV3
USER_LED3
USER_LED_DRV4
138
137
136
134
133
132
131
E69
E72
E73
E75
E77
E78
E80
USER_LED4
USER_LED_DRV5
USER_LED5
USER_LED_DRV6
USER_LED6
USER_LED_DRV7
USER_LED7
19
18
16
15
14
12
11
F83
F85
F88
F89
F91
F93
F96
DCLK
21
22
23
25
27
G109
G107
G105
G104
G99
USER_RESETn 5,8
EPM3256ATC144
129
124
57
52
GNDINT1
GNDINT2
GNDINT3
GNDINT4
TP1
A
130
123
58
51
A3
A5
A6
A11
A13
A14
A16
DEV_CLRn
P241
P243
P245
P246
P249
P253
P256
66
67
68
69
70
71
72
5 CPLD_CSn
CPLD_USER0
CPLD_USER1
O227
O229
O233
O235
O237
O240
74
75
78
79
80
81
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
N211
N213
N216
N217
N219
N221
98
99
100
101
102
103
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
M193
M195
M197
M200
M201
M203
M206
M208
106
107
108
109
110
111
112
113
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
L179
L181
L184
L185
L187
L189
L192
55
56
60
61
62
63
65
FLASH_A1
FLASH_A0
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RDY_BSYn
FLASH_BYTEn
K163
K165
K168
K169
K171
K173
82
83
84
86
87
88
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
J147
J149
J152
J153
J157
J160
90
91
92
93
96
97
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
I131
I133
I136
I137
I139
I141
I144
116
117
118
119
120
121
122
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_RESETn
H115
H117
H120
H121
H123
H125
H128
54
53
49
48
47
46
45
SPGM0
SPGM1
SPGM2
GNDIO1
GNDIO2
GNDIO3
GNDIO4
GNDIO5
GNDIO6
GNDIO7
GNDIO8
GNDIO9
GNDIO10
GNDIO11
GNDIO12
GNDIO13
JTAG_MAX_TDO
R10
CLK_TO_MAX_A 15 125
CLK_OSC_A 14,15
128
SYS_RESETn 5,8,14 127
126
USER_PB2
USER_PB1
EP1S_nSTATUS
EP1S_nCONFIG
EP1S_CONF_DONE
FLASH_WEn
FLASH_OEn
FLASH_BYTEn
FLASH_A21
FLASH_CEn
PORSEL
nIO_PULLUP
RN1
1
2
3
4
5
6
7
8
10K
16
15
14
13
12
11
10
9
RN2
1
2
3
4
5
6
7
8
10K
16
15
14
13
12
11
10
9
2 PCI_XCAP
2 PCI_M66EN
5,16 OVERTEMPn
5,16 ALERTn
7
E
5 USER_LED_DRV[7..0]
5
5
5
U2I
H21
EP1S_CONF_DONE
EP1S_nCONFIG
EP1S_nSTATUS
EP1S_INIT_DONE
3.3V
U3
G18
J18
G16
AE15
DCLK
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RESETn
FLASH_BYTEn
26
28
11
12
47
CE
OE
WE
RESET
BYTE
VCC
37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15_A_1
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
RY/BY
15
FLASH_RDY_BSYn
WP/ACC
14
FLASH_WPn
VSS1
VSS2
27
46
E19
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
E14
F14
F15
C16
G19
J19
K19
J20
AG19
AC19
D14
AB18
AA19
PORSEL
nIO_PULLUP
AG15
AF15
AJ14
AF18
JTAG_TRSTn
JTAG_TCK
JTAG_MAX_TDO
JTAG_STRATIX_TDO_RS
JTAG_TMS
TRST
TCK
TDI
TDO
TMS
G15
G14
D16
F16
E15
PGM2
PGM1
PGM0
AA20
AG14
AD18
SPGM2
SPGM1
SPGM0
MSEL0
MSEL1
MSEL2
AG18
AE18
AE19
SMSEL0
SMSEL1
SMSEL2
RUnLU
AF14
RUnLU
CRC_ERROR
AF20
CRC_ERROR
DEV_CLRn/IO7
PORSEL
nIO_PULLUP
DEV_OE
VCCSEL
NC1
NC2
AH14
DEV_CLRn
CLKUSR
CONF_DONE
nCONFIG
nSTATUS
INIT_DONE
D
DCLK
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
CS
nCS
nWS
nRS
RDYnBSY
nCE
nCEO
RN3
1
2
3
4
5
6
7
8
MAIN_SW
S1
DEV_CLRn
PCI_XCAP
C
L13
V12
AG27
AH15
1K
16
15
14
13
12
11
10
9
10
FLASH_WPn
JTAG_TRSTn
B
3.3V
PCI_M66EN
RUnLU
SMSEL2
USE_MPGM
MPGM1
MPGM0
J1
2
4
6
8
10
10 JTAG_TCK
15 JTAG_CONN_TDI
10 JTAG_TMS
1
3
5
7
9
15 JTAG_CONN_TDO
HEADER
SW_DIP
3.3V
JTAG Chain Devices:
(1) Max 3K
(2) Stratix
(3) B1 Samtec Connector
ByteBlaster / MasterBlaster Header
(uses JTAG mode only)
10K
16
15
14
13
12
11
10
9
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Date:
6
5
0
0
3.3V
16
PCI_M66EN
RUnLU
SMSEL2
USE_MPGM
MPGM1
MPGM0
R11
R12
EP1S40F1020
AM29DL640D
RN4
1
2
3
4
5
6
7
8
FLASH_OEn
FLASH_CEn
FLASH_WEn
10,15 JTAG_STRATIX_TDO
0
JTAG_STRATIX_TDO_RS
R9
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
8
5 USER_LED[7..0]
PCIX_66SEL133
135
114
105
94
85
77
64
59
33
26
17
13
3
E
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
U1
VCCINT1
VCCINT2
VCCINT3
VCCINT4
144
115
95
76
73
50
24
5 CPLD_USER[1..0]
3.3V
4
3
Document Number
Rev
150-0216000-01
Wednesday, February 12, 2003
2
Sheet
B
17
of
1
18
A
2
1
C29
0.1uF
X7R
C30
0.1uF
X7R
C31
0.1uF
X7R
C32
0.1uF
X7R
C52
0.01uF
X7R
C53
0.01uF
X7R
C54
0.01uF
X7R
C55
0.01uF
X7R
C56
0.01uF
X7R
3.3V
Place near J13 Bank 6 HSDI Connector
2
C153
0.01uF
X7R
D
C154
0.01uF
X7R
C155
0.01uF
X7R
C157
0.01uF
X7R
C158
0.01uF
X7R
C159
0.01uF
X7R
+
C2
47uF
10V
TAN
1
C1
47uF
10V
TAN
+
2
1
C28
0.1uF
X7R
1
Place near EP1S25F780 (Bank 1 split plane)
VCCIO_B1 16
C112
+ 4.7uF
10V
TAN
Place near U4/U5 output
(under)
2.5V
C3
4.7uF
10V
TAN
+
C4
4.7uF
10V
TAN
+
2
Place near U4/U5 input
(under)
3.3V
1
Decoupling
2
3
1
4
2
5
D
Place near EP1S25F780 (Bank 6 split plane)
C23
0.01uF
X7R
C24
0.01uF
X7R
C25
0.01uF
X7R
C26
0.01uF
X7R
C27
0.01uF
X7R
Bulk Decoupling
3.3V
2.5V
C33
0.01uF
X7R
Place near EP1S25F780
C43
0.1uF
X7R
C44
0.1uF
X7R
C45
0.1uF
X7R
C46
0.1uF
X7R
C47
0.01uF
X7R
C48
0.01uF
X7R
C49
0.01uF
X7R
C50
0.01uF
X7R
C34
0.01uF
X7R
C35
0.01uF
X7R
C63
0.1uF
X7R
C64
0.1uF
X7R
C65
0.1uF
X7R
C66
0.1uF
X7R
C67
0.01uF
X7R
C68
0.01uF
X7R
C69
0.01uF
X7R
C70
0.01uF
X7R
C57
0.01uF
X7R
C58
0.01uF
X7R
C59
0.01uF
X7R
C60
0.01uF
X7R
+
2.5V
C38
100uF
10V
Tantalum
+
3.3V
C39
100uF
10V
Tantalum
+
C40
100uF
10V
Tantalum
Place near MAX3256A
C5
0.1uF
X7R
Place near EP1S25F780
C62
0.1uF
X7R
C37
0.01uF
X7R
C51
0.01uF
X7R
3.3V
3.3V
C36
0.01uF
X7R
2
C42
0.1uF
X7R
1.5V
Place near J8 Bank 1 HSDI Connector
1
C22
0.1uF
X7R
2
C21
0.1uF
X7R
1
C20
0.1uF
X7R
2
C19
0.1uF
X7R
2
C18
0.1uF
X7R
1
1
VCCIO_B6 16
C113
+ 4.7uF
10V
TAN
C71
0.01uF
X7R
C6
0.1uF
X7R
C7
0.1uF
X7R
C8
0.1uF
X7R
C9
0.1uF
X7R
C10
0.1uF
X7R
C11
0.1uF
X7R
C12
0.1uF
X7R
C13
0.1uF
X7R
C14
0.1uF
X7R
C15
0.1uF
X7R
Place near PCI Connector
1.5V
3.3V
Place near EP1S25F780
C
C80
0.1uF
X7R
C81
0.1uF
X7R
C82
0.1uF
X7R
C83
0.1uF
X7R
1.5V
C84
0.1uF
X7R
C85
0.01uF
X7R
C86
0.01uF
X7R
C87
0.01uF
X7R
C88
0.01uF
X7R
C89
0.01uF
X7R
C108
0.01uF
X7R
C109
0.01uF
X7R
C110
0.01uF
X7R
C111
0.01uF
X7R
Place near PCI Connector
C72
0.1uF
X7R
C73
0.1uF
X7R
C74
0.1uF
X7R
C75
0.1uF
X7R
5.0V
C76
0.1uF
X7R
C77
0.1uF
X7R
+12V
Place near PCI Connector
C78
0.1uF
X7R
C79
0.1uF
X7R
-12V
C100
0.1uF
X7R
C
C101
0.1uF
X7R
Place near EP1S25F780
C106
0.1uF
X7R
2
+
1
C114
4.7uF
10V
TAN
+
2
1
Place near EP1S25F780
(under)
2.5V
C107
0.01uF
X7R
1.5V
C115
4.7uF
10V
TAN
Place near 25MHz Oscillator
3.3V
3.3V
+
C116
4.7uF
10V
TAN
+
2.5V
PLL5 VCCIO
C90
0.1uF
X7R
Place near EP1S25F780
(under)
1
C105
0.1uF
X7R
2
C104
0.1uF
X7R
1
C103
0.1uF
X7R
2
C102
0.1uF
X7R
C91
0.01uF
X7R
3.3V
PLL6 VCCIO
C92
0.1uF
X7R
C93
0.01uF
X7R
Place near FLASH
C16
0.1uF
X7R
C17
0.1uF
X7R
C98
0.1uF
X7R
C99
0.01uF
X7R
C126
0.1uF
X7R
C127
0.1uF
X7R
C128
0.1uF
X7R
C129
0.1uF
X7R
C130
0.1uF
X7R
C131
0.1uF
X7R
C140
0.01uF
X7R
C141
0.01uF
X7R
C142
0.01uF
X7R
C143
0.01uF
X7R
C144
0.01uF
X7R
C145
0.01uF
X7R
C182
0.01uF
X7R
C183
0.01uF
X7R
C184
0.01uF
X7R
C185
0.01uF
X7R
C186
0.01uF
X7R
C187
0.01uF
X7R
C117
4.7uF
10V
TAN
Place near DDR SDRAM
2.5V
Place near 91C111 ethernet MAC/PHY
3.3V
B
C146
0.1uF
X7R
C147
0.1uF
X7R
C148
0.1uF
X7R
C149
0.1uF
X7R
C150
0.1uF
X7R
C151
0.1uF
X7R
C118
0.1uF
X7R
C152
0.1uF
X7R
C119
0.1uF
X7R
C120
0.1uF
X7R
C121
0.1uF
X7R
C122
0.1uF
X7R
C123
0.1uF
X7R
C124
0.1uF
X7R
C125
0.1uF
X7R
B
Place near DDR SDRAM
2.5V
Place near 91C111 ethernet MAC/PHY
3.3V
C167
0.001uF
X7R
C168
0.001uF
X7R
C169
0.001uF
X7R
C170
0.001uF
X7R
C171
0.001uF
X7R
C172
0.001uF
X7R
C132
0.01uF
X7R
C173
0.001uF
X7R
C133
0.01uF
X7R
C134
0.01uF
X7R
C135
0.01uF
X7R
C136
0.01uF
X7R
5.0V
R1
39
R2
39
R3
39
R4
39
R5
39
R6
39
R7
39
R8
39
C138
0.01uF
X7R
C139
0.01uF
X7R
Place near DDR SDRAM
2.5V
Power Resistors: For use if extra current draw is
needed on 5 Volts due to Power Supply requirement.
C137
0.01uF
X7R
C174
0.01uF
X7R
C175
0.01uF
X7R
C176
0.01uF
X7R
C177
0.01uF
X7R
C178
0.01uF
X7R
C179
0.01uF
X7R
C180
0.01uF
X7R
C181
0.01uF
X7R
A
A
DO NOT INSTALL
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Stratix PCI Development Board
Size
B
Copyright (c) 2003, Altera Corporation. All Rights Reserved.
5
Date:
4
3
2
Document Number
Rev
150-0216200-01
Wednesday, February 12, 2003
Sheet
1
18
B
of
18