PCI Compiler
February 2003, ver. 1.2
Features
Data Sheet
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General
Description
Altera Corporation
DS-PCIVIEW-1.2
pci_mt64, pci_mt32, pci_t64, and pci_t32 MegaCore®
functions
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Flexible general-purpose interfaces that can be customized for
specific peripheral requirements
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Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 timing and functional
requirements
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66-MHz compliant when used with 66-MHz PCI-compliant
Altera devices
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Extensively tested with the Phoenix Technology testbench and in
hardware using the Altera FLEX® 10KE and APEX™ 20KE PCI
development boards
PCI MegaWizard® Plug-Ins easily generate a custom instance of the
PCI function
Behavioral models functionally simulate the pci_mt64, pci_mt32,
pci_t64, and pci_t32 functions in third-party simulation tools
Verilog HDL and VHDL testbench for simulation in third-party tools
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Easy-to-use commands to perform basic PCI transactions
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Includes a simple reference design that performs 32- and 64-bit
single/burst cycle memory read/write and 32-bit I/O
read/write transactions
Reference designs for popular functions implemented on the local
side of the PCI MegaCore functions, including:
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DMA engine
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Data path FIFOs
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SDRAM interface
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Local master and target control logic
The Altera PCI compiler provides a complete solution to implement a PCI
interface in a design. The compiler includes the master/target and targetonly PCI MegaCore functions for 64- and 32-bit applications, specifically,
pci_mt64, pci_mt32, pci_t64, and pci_t32. The compiler also
includes behavioral models and a testbench to verify the design
(including the PCI MegaCore function) in third-party Verilog HDL or
VHDL environments. Additionally, reference designs are provided as
examples of popular functions implemented on the local side of a PCI
interface.
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PCI Compiler Data Sheet
The PCI compiler enhances your productivity by allowing you to focus
your efforts on the custom logic surrounding the PCI interface. The
functions are optimized for Altera APEX™, ACEX™, FLEX®, Excalibur™,
Stratix™, and Cyclone™ devices and are fully tested to meet the
requirements of the PCI Special Interest Group (SIG) PCI Local Bus
Specification, Revision 2.2 and Compliance Checklist, Revision 2.2. The
designer can test-drive Altera PCI MegaCore functions using the
OpenCore® feature to compile and simulate the functions within the
design’s custom logic. When the designer is ready to license a function,
the designer should contact an local Altera sales representative.
In addition to the PCI compiler, Altera provides PCI hardware
prototyping platforms with the APEX 20KE PCI Development Kit and
FLEX 10KE PCI Development Kit. The kits include a PCI development
board, a reference design (also included in the PCI compiler), software
drivers, and a graphical user interface to help the designer evaluate the
PCI solution in a system.
Device Family
Support
Every Altera MegaCore function offers a specific level of support to each
of the Altera device families. The following list describes the three levels
of support:
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Full—The core meets all functional and timing requirements for
thedevice family and may be used in production designs
Preliminary—The core meets all functional requirements, but may still
be undergoing timing analysis for the device family; may be used in
production designs.
No support—The core has no support for device family and cannot be
compiled for the device family in the Quartus® II software.
Table 1 shows the level of support offered by the PCI MegaCore functions
to each of the Altera device families.
Table 1. Device Family Support
Device Family
2
Support
Stratix
Preliminary
Cyclone
Preliminary
Excalibur
Full
APEX II
Full
APEX 20KC
Full
APEX 20KE
Full
FLEX 10KE
Full
ACEX 1K
Full
Altera Corporation
PCI Compiler Data Sheet
Performance
Table 2 shows the speed and approximate device utilization of the PCI
MegaCore functions in an APEX 20KE -1 speed grade device. The device
resources utilized are estimated based on the default parameter settings
for the MegaCore functions. Using different parameter options may result
in additional logic generated within the function. For example, this
estimate is based on a PCI function implementing one base address
register (BAR) with 1 MByte of space reserved; implementing a second
BAR would generate additional logic in the MegaCore function.
Table 2. PCI MegaCore Function Performance
PCI Function
Logic Elements
(LEs)
Embedded System
Blocks (ESBs)
fMAX (MHz)
pci_mt64
1,400
0
> 66
pci_t64
1,250
0
> 66
pci_mt32
1,050
0
> 66
700
0
> 66
pci_t32
Functional
Description
The PCI compiler contains everything the designer needs to use Altera
PCI solutions, including the MegaCore functions, behavioral models,
testbench, and reference designs. The compiler also includes a wizarddriven interface, which lets the designer create an instance of the PCI
MegaCore function required for an application with the desired
parameterizable features enabled.
PCI MegaCore Functions
The Altera pci_mt64, pci_t64, pci_mt32, and pci_t32 MegaCore
functions are hardware-tested, high-performance, flexible
implementations of PCI interfaces. These functions handle the complex
PCI protocol and stringent timing requirements internally, and their backend interface is designed for easy integration. Therefore, the designer can
focus engineering efforts on value-added custom development,
significantly reducing time-to-market.
Optimized for the Altera APEX, ACEX, FLEX, Excalibur, Stratix, and
Cyclone device families, the PCI functions support configuration, I/O,
and memory operations. With the high density of Altera devices, the
designer has ample resources for custom local logic after implementing
the PCI interface. The high performance of Altera devices also enables
these functions to support unlimited cycles of zero-wait-state memoryburst transactions. These functions can run at either 33-MHz or 66-MHz
PCI bus clock speeds; they thus achieve 132 MBytes/second throughput
in a 32-bit, 33-MHz PCI bus system and up to 528-MBytes/second
throughput in a 64-bit, 66-MHz PCI bus system.
Altera Corporation
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PCI Compiler Data Sheet
To ensure timing and protocol compliance, PCI MegaCore functions have
been vigorously simulated and hardware tested. Simulation was
performed using the Phoenix Technologies PCI testbench. Hardware
verification was performed in real systems using the HP 2928A PCI Bus
Exerciser and Analyzer with the Altera APEX 20KE PCI development
board and FLEX 10KE PCI development board, along with other PCI
agents in the system (e.g., host bridge, Ethernet network adapter, and
video graphics card). The Altera PCI development boards were
programmed with the reference designs included in the PCI compiler.
As parameterized functions, pci_mt64, pci_mt32, pci_t64, and
pci_t32 have features and configuration registers that can be modified
for the designer’s application needs upon instantiation. These features
provide scalability, adaptability, and efficient silicon implementation. As
a result, the same MegaCore functions can be used in multiple PCI
projects with varying requirements.
Figures 1 through 4 show the block diagrams for the pci_mt64,
pci_mt32, pci_t64, and pci_t32 functions.
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Altera Corporation
PCI Compiler Data Sheet
Figure 1. pci_mt64 Functional Block Diagram
pci_mt64
Parameterized
Configuration
Registers
clk
rstn
idsel
ad[63..0]
cben[7..0]
cmd_reg[5..0]
stat_reg[5..0]
cache[7..0]
PCI Address/
Data Buffer
Local Master
Control
gntn
reqn
lm_req32n
lm_req64n
lm_lastn
lm_rdyn
lm_ackn
lm_adr_ackn
lm_dxfrn
lm_tsr[9..0]
PCI Master
Control
Local Address/
Data/Command/
Byte Enable
framen
req64n
irdyn
trdyn
devseln
ack64n
stopn
l_ldat_ackn
l_hdat_ackn
PCI Target
Control
Local Target
Control
intan
par
par64
perrn
serrn
Altera Corporation
l_disc_64_extn
l_adi[63..0]
l_cbeni[7..0]
l_dato[63..0]
l_adro[63..0]
l_beno[7..0]
l_cmdo[3..0]
Parity Checker &
Generator
lt_rdyn
lt_discn
lt_abortn
lirqn
lt_framen
lt_ackn
lt_dxfrn
lt_tsr[11..0]
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PCI Compiler Data Sheet
Figure 2. pci_mt32 Functional Block Diagram
pci_mt32
Parameterized
Configuration
Registers
clk
rstn
idsel
ad[31..0]
cben[3..0]
cmd_reg[5..0]
stat_reg[5..0]
cache[7..0]
PCI Address/
Data Buffer
lm_req32n
Local Master
Control
gntn
reqn
lm_lastn
lm_rdyn
lm_ackn
lm_adr_ackn
lm_dxfrn
lm_tsr[9..0]
PCI Master
Control
Local Address/
Data/Command/
Byte Enable
l_adi[31..0]
l_cbeni[3..0]
l_dato[31..0]
l_adro[31..0]
l_beno[3..0]
l_cmdo[3..0]
framen
irdyn
trdyn
devseln
PCI Target
Control
stopn
Local Target
Control
intan
par
par64
perrn
serrn
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Parity Checker &
Generator
lt_rdyn
lt_discn
lt_abortn
lirqn
lt_framen
lt_ackn
lt_dxfrn
lt_tsr[11..0]
Altera Corporation
PCI Compiler Data Sheet
Figure 3. pci_t64 Functional Block Diagram
pci_t64
Parameterized
Configuration
Registers
clk
rstn
idsel
ad[63..0]
cben[7..0]
cmd_reg[5..0]
stat_reg[5..0]
PCI Address/
Data Buffer
Local Address/
Data/Command/
Byte Enable
framen
req64n
irdyn
trdyn
devseln
ack64n
stopn
l_ldat_ackn
l_hdat_ackn
PCI Target
Control
Local Target
Control
intan
par
par64
perrn
serrn
Altera Corporation
l_disc_64_extn
l_adi[63..0]
l_dato[63..0]
l_adro[63..0]
l_beno[7..0]
l_cmdo[3..0]
Parity Checker &
Generator
lt_rdyn
lt_discn
lt_abortn
lirqn
lt_framen
lt_ackn
lt_dxfrn
lt_tsr[11..0]
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PCI Compiler Data Sheet
Figure 4. pci_t32 Functional Block Diagram
pci_t32
Parameterized
Configuration
Registers
clk
rstn
idsel
ad[31..0]
cben[3..0]
cmd_reg[5..0]
stat_reg[5..0]
PCI Address/
Data Buffer
Local Address/
Data/Command/
Byte Enable
l_adi[31..0]
l_dato[31..0]
l_adro[31..0]
l_beno[3..0]
l_cmdo[3..0]
framen
irdyn
trdyn
devseln
PCI Target
Control
stopn
Local Target
Control
intan
par
perrn
serrn
Parity Checker &
Generator
lt_rdyn
lt_discn
lt_abortn
lirqn
lt_framen
lt_ackn
lt_dxfrn
lt_tsr[11..0]
PCI Compiler MegaWizard Plug-In
The PCI compiler MegaWizard Plug-In is a Java-based, platformindependent wizard interface that streamlines the design entry process,
making it easier and less time-consuming to design with Altera MegaCore
functions. The designer can either launch the PCI compiler MegaWizard
Plug-In from within the Quartus™ II software, or from the command line.
The PCI compiler wizard is used to generate an Altera hardware
description language (AHDL), VHDL, or Verilog HDL instance of the
Altera PCI MegaCore function.
The PCI MegaCore functions offer parameters to customize the function
for an application. The instance of the PCI MegaCore function created
with the wizard includes all of the parameter settings specific to the
required design; the designer should implement this instance as a module
in the design.
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Altera Corporation
PCI Compiler Data Sheet
The wizard also includes a utility to generate device-specific constraint
files for the Quartus II software to ensure that the PCI MegaCore function
achieves PCI timing requirements in the design. More information on the
recommended devices for 33 or 66 MHz PCI systems is available in the
device family data sheets and on the IP MegaStore section of the Altera
web site.
Figure 5 shows page 3 of the wizard, where the designer can choose which
PCI MegaCore function is implemented in the design, as well as the
technology and application speed capabilities.
Figure 5. PCI Compiler Wizard
Third-Party Tool Simulation
The designer can simulate Altera PCI MegaCore functions in third-party
simulation tools, as well as in the Quartus II software. The Altera PCI
testbench and behavioral models provide a fast and efficient way to
develop and test designs utilizing Altera PCI MegaCore functions. The
testbench is a functional simulation environment that allows the designer
to verify the PCI transactions used in an application with other PCI agents.
The PCI testbench and behavioral models are provided for both
Verilog HDL and VHDL environments, and can be used with the
OpenCore evaluation feature. The designer can use the PCI testbench to
perform pre- and post-synthesis simulation of an application. The
testbench provides test modules to communicate with an application as a
target or master. The testbench also includes a bus monitor and arbitration
modules, as shown in Figure 6.
Altera Corporation
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PCI Compiler Data Sheet
Figure 6. Altera PCI Testbench Block Diagram
Testbench Modules
PCI Bus
Master
Transactor
Target
Transactor
Altera Device
Altera PCI
MegaCore
Function
User
Application
Bus
Monitor
Clock Generator
Arbiter
Pull Ups
Reference Designs
The reference designs included with the PCI compiler are design
examples illustrating how to interface local logic to the pci_mt64 and
pci_mt32 MegaCore functions. The logic relevant to the local target
interface can also be used as an example when working with the pci_t64
or pci_t32 functions. The reference designs include a target and a master
interface to the PCI function, DMA engine, FIFO buffers, and an SDRAM
memory controller. The DMA engine has standard and scatter gather
modes and controls the master mode operation of the pci_mt64 or
pci_mt32 functions. The FIFO buffers allow zero-wait state transfers
between the SDRAM memory and the PCI bus.
Figure 7 shows a block diagram of the reference design. The reference
design consists of the following elements:
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Master control logic
Target control logic
DMA engine
Data path FIFO functions
SDRAM interface
Altera Corporation
PCI Compiler Data Sheet
Figure 7. Reference Design Block Diagram
PCI Master/Target Function
Local
Interface
Bus
Parameterized
Configuration
Registers
PCI
Master
Control
PCI
Target
Control
Parity
Checker
&
Generator
Obtaining &
Installing the
PCI Compiler
DMA Engine
Local
Master
Control
Master
Control
Logic
DMA Control Logic
DMA Registers
DMA Descriptor FIFO
Local
Address/
Data/
Command/
Byte
Enable
Target
Control
Logic
Local
Target
Control
Data Path FIFOs
SDRAM Module
PCI
Address/
Data
Buffer
SDRAM Controller
PCI
Bus
Reference Design
PCI-to-SDRAM FIFO
SDRAM-to-PCI FIFO
Before the designer can start using Altera MegaCore functions, the
designer must obtain the PCI compiler and install it. The following
instructions describe this process.
Licensing
The four PCI MegaCore functions are available for evaluation with the
OpenCore feature. The OpenCore feature allows the designer to
instantiate the MegaCore functions in a design, synthesize the design,
verify timing through static timing analysis, and functionally simulate the
design using Altera software or third-party tools. A license is required to
generate programming files; when the designer is ready to program an
Altera device with a design that includes a PCI MegaCore function, the
designer should contact a local Altera or distributor sales office to obtain
a license.
1
Altera Corporation
Although all of the Altera PCI MegaCore functions are included
with the PCI compiler, the PCI MegaCore functions are
individually licensed.
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PCI Compiler Data Sheet
Software Requirements
The PCI compiler requires:
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The Quartus II software version 2.2 SP1 or later
The Java Runtime Environment (JRE) version 1.3.0 is required for the
PCI compiler wizard. The JRE is installed automatically during the
PCI compiler installation process.
The PCI behavioral models can be used in most third-party EDA
simulation tools. Refer to AN 169 (Simulating the PCI MegaCore
Function Behavioral Models) for more information on the supported
tools.
Installing the PCI compiler on UNIX systems requires the GNU zip
utility.
Obtaining the PCI Compiler MegaCore Function
If the designer has Internet access, he or she can download the PCI
compiler from the Altera web site at www.altera.com. If the designer does
not have Internet access, he or she can obtain the compiler from a local
Altera or distributor representative. Follow the instructions below to
obtain the PCI compiler via the Internet.
1.
Point a web browser to www.altera.com/IPmegastore.
2.
Enter PCI compiler in the Keywords box of the IP MegaSearch
area and click Submit.
3.
Click the link for the Altera PCI compiler MegaCore function.
4.
Follow the online instructions to download the compiler and save it
to hard disk.
Installing the PCI Compiler Files
To install the PCI Compiler files on Windows PCs, follow the instructions
below:
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1.
Choose Run (Start menu).
2.
Type <path name>\pci_compiler.v2.3.0.exe, where <path
name> is the location of the downloaded PCI compiler.
3.
Click OK.
Altera Corporation
PCI Compiler Data Sheet
The MegaCore Installer dialog box appears. Follow the online
instructions to finish the installation.
4.
After the designer has finished installing the compiler files, the
designer must specify the directory in which they were installed
(e.g., <path>/pci_compiler_2.3.0/lib) as a user library in the Quartus
II software. Search for “User Libraries” in the Quartus II Help system
for instructions on how to add these libraries.
1
The designer must add the lib directory as a user library for
proper operation of the PCI compiler wizard and for
compilation.
To install PCI compiler on UNIX machines, change to the directory in
which the downloaded PCI compiler function was saved and type the
following commands:
1.
gunzip pci_compiler_v2.3.0.tar.gz r
2.
tar xvf pci_compiler_v2.3.0.tar r
The PCI compiler installs into the current directory.
PCI Compiler Directory Structure
The PCI compiler installs the directories shown in Figure 8. Many of the
directories contain subdirectories, which are described in the
documentation for each PCI compiler component. Refer to “Available
Documentation” on page 14 for a list of PCI compiler documents.
Altera Corporation
13
PCI Compiler Data Sheet
Figure 8. PCI Compiler Directory Structure
Common
Contains common elements used by Altera MegaCore functions.
jre
Contains the Java Runtime Environment version 1.3.0.
pci_compiler_v2.3.0
Contains all of the PCI compiler files.
Doc
Contains all PCI compiler documentation, including user guides, application notes, and
white papers.
Lib
Contains the encrypted lower-level design files and the PCI compiler wizard files. After
installing the PCI compiler, the designer should add a user library in the Quartus II software
that points to this directory. This library allows the designer to use all of the PCI MegaCore fu
and the PCI compiler wizard in a project.
Pci_mt32
Contains the pci_mt32 MegaCore function files.
Pci_mt64
Contains the pci_mt64 MegaCore function files.
Pci_t32
Contains the pci_t32 MegaCore function files.
Pci_t64
Contains the pci_t64 MegaCore function files.
Sim_lib
Contains the behavioral models for the pci_mt32, pci_mt64,
pci_t32, and pci_t64 MegaCore functions.
Testbench
Contains the Verilog HDL and VHDL testbenches for the pci_mt32,
pci_mt64, pci_t32, and pci_t64 MegaCore functions.
Ref_designs
Contains reference designs for common functions implemented with the PCI MegaCore
functions.
Available
Documentation
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Altera provides additional technical documentation for the PCI
MegaCore functions, the PCI testbench and behavioral models, and the
reference designs.
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PCI MegaCore Function User Guide—Provides a detailed technical
description of the pci_mt64, pci_t64, pci_mt32, and pci_t32
functions.
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PCI Testbench User Guide—Describes the VHDL and Verilog HDL
testbench and how to use them with the pci_mt64, pci_t64,
pci_mt32, and pci_t32 MegaCore functions.
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AN 169: Simulating the PCI MegaCore Function Behavioral Models—
Describes how to use the Verilog HDL and VHDL pci_mt64,
pci_t64, pci_mt32, and pci_t32 behavioral models in thirdparty simulation tools.
Altera Corporation
PCI Compiler Data Sheet
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
[email protected]
15
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FS 10 (pci_mt64 MegaCore Function Reference Design)—Describes the
pci_mt64 reference design modules.
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FS 12 (pci_mt32 MegaCore Function Reference Design)—Describes the
pci_mt32 reference design modules.
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SDR SDRAM Controller White Paper—Describes the SDRAM
controller used in the PCI reference design.
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo,
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marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and
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make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product,
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Altera customers are advised to obtain the latest version of device specifications before
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All rights reserved.
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