T3 Mapper MegaCore
Function (T3MAP)
February 20, 2001; ver. 1.00
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Features
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Typical
Applications
Data Sheet
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants
QuartusTMII software and OpenCoreTM feature allow place-androute, and static timing analysis of designs prior to licensing
Secure Register Transfer Level (RTL) simulation models allow
simulation with user design in third-party simulators
Asynchronously maps clear channel synchronous/asynchronous T3
signal over Synchronous Optical Network (SONET) Synchronous
Transport Signal level 1 (STS-1)
Provides serial interface connection to a T3 Framer MegaCore
Function (T3FRM) (optional)
Supports nominal T3 rates of 44.736 megabits per second (Mbps)+/895 bits per second (bps)
Provides outputs to allow control of plesiochronous T3 oscillator
Complies with all applicable standards, including:
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Telcordia, Synchronous Optical Network (SONET) Transport
Systems: Common Generic Criteria, GR-253-CORE, Issue 2,
Revision 2, January 1999.
Optimized for the Altera® APEXTM 20KE device architecture
Figure 1 shows an example system implementation of the T3MAP
interfacing with two other Altera MegaCore variants via the Midbus, and
T3 Mapper interfaces. See “Interfaces & Protocols” on page 3.
Figure 1. Typical Applications
T3 Mapper
Interface
Midbus
rxclk
Line
Interface
Circuit
Clock
Data
Recovery
Serializer
Deserializer
SONET STS-1
Framer
(STS1FRM)
T3 Mapper
(T3MAP)
T3 Framer
(T3 FRM)
T3
Line
txclk
External
Processor
CPU Bus
Processor
Interface
AIRbus
APEX 20KE Boundary
Altera Corporation
A-DS-IPT3MAPPER-1.0
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T3 Mapper MegaCore Function (T3MAP) Data Sheet
Functional
Description
The T3MAP interfaces to a data bit stream at a data rate of up to 44.736
Mbps +/- 895 bps—via bit stuffing—to accommodate standard T3 rates.
It supports STS-1, STS-3, and STS-12 data paths. The T3MAP comprises
two major blocks, EXTRACT and INSERT, illustrated in Figure 2.
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The following list of functions is based on a full feature T3MAP.
EXTRACT
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Supports the standard T3 rate via adaptive control of the external
Voltage Controlled Oscillator (VCO)
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A software programmable threshold will assert either
vco_increase, or vco_decrease, when violated. This
indicates a change is required in the T3 clock rate. See “Core
Clocking” on page 5. The FIFO buffer is 32 bytes deep.
Accepts data bytes from a SONET framer
Performs destuffing
Extracts a raw T3 bit stream, and forwards it optionally to a T3FRM
INSERT
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Performs asynchronous mapping
Uses a 32-byte FIFO buffer
Performs payload bit stuffing
Provides payload bytes to a SONET framer
Accepts a T3 bit stream that is either raw or from a T3FRM
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While it is expected that the T3 input stream will be within the
standard limits of 44.736 Mbps +/- 895 bps, the T3MAP supports
rates between 44.712 Mbps and 44.784 Mbps.
Altera Corporation
T3 Mapper MegaCore Function (T3MAP) Data Sheet
Interfaces &
Protocols
Three interfaces—illustrated in Figure 2—support the T3MAP: the
Middle interface (Midbus), the Access to Internal Registers (AIRbus)
interface, and the T3 Mapper interface.
Midbus
The Midbus interface is a simple synchronous full-duplex data path bus.
The T3MAP Midbus transports data over a single byte lane in each
direction. The required frequency varies depending on the SONET framer
supported.
In the receive direction (RX), the data is transferred from the Midbus
master to the slave (T3MAP). In the transmit direction (TX), data is
transferred from the slave (T3MAP) to the Midbus master. In each
direction the Midbus can carry eight bits per clock cycle. It includes
midbus receive data (mrxdat[7:0]) and midbus receive enable
(mrxena) lines to indicate a valid data transfer in the RX direction, and
midbus transmit data (mtxdat[7:0]) and midbus transmit enable
(mtxena) lines to indicate a valid data request in the TX direction.
AIRbus
The AIRbus interface provides access to internal registers using a simple
synchronous internal processor bus protocol. This consists of separate
read (rdata) and write (wdata) data buses, a data transfer acknowledge
(dtack) signal, and a select (sel) signal. An address bus (addr[3:0])
and read (read) signal indicate the location and type of access within the
block. The rdata buses and dtack signals can be merged from multiple
blocks using a simple OR function. The dtack signal is sustained until the
block sel is removed (four-way handshaking) meaning the AIRbus can
cross clock domain boundaries. The T3MAP is an AIRbus slave with a
data width of eight bits.
f
Altera Corporation
For more detailed information on the Midbus and AIRbus refer to the
Altera web site at http://www.altera.com/IPmegastore.
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T3 Mapper MegaCore Function (T3MAP) Data Sheet
T3 Mapper Interface
The T3 Mapper interface is used to convey full T3 data, including framing,
to the T3MAP.
Figure 2 illustrates the T3MAP, including Midbus and AIRbus interfaces.
Midbus
mrxdat[7:0]
mrxena
mrxfoh
mrxeoh
mrxval
vco_increase
vco_decrease
Figure 2. Block Diagram
ds3_txclk
EXTRACT
ds3_txdata
T3 Mapper
Interface
rxclk_en
rxclk
rxreset_n
T3MAP (T3 Mapper)
Midbus
mtxdat[7:0]
mtxena
mtxfoh
mtxeoh
mtxval
ds3_rxclk
INSERT
ds3_rxdata
T3 Mapper
Interface
read
sel
irq
dtack
rdata[7:0]
addr[3:0]
wdata[7:0]
txclk_en
txclk
txreset_n
AIRbus
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Altera Corporation
T3 Mapper MegaCore Function (T3MAP) Data Sheet
Figure 3 shows the T3MAP providing asynchronous mapping of T3 data
over STS1FRM. It also depicts the interface to an external VCO, for the
purpose of adjusting the ds3_txclk clock.
Figure 3. Core Clocking
rxclk
RX
EXTRACT
mrxdat (2)
STS1FRM (1)
(SONET STS-1
Framer)
ds3_txclk
ds3_txdata
T3MAP (T3 Mapper)
txclk
TX
VCO
vco_increase
vco_decrease
Low-Pass
Filter
INSERT
INSERT
mtxdat (2)
ds3_rxclk
ds3_rxdata
Notes:
(1)
(2)
The T3 Mapper also supports SONET STS-3 and STS-12 framers.
For a more detailed view of the Midbus interface see Figure 2.
Performance
Table 1 shows the required speed and estimated gate count of the T3MAP
in an APEX 20KE device.
Table 1. Performance
Note (1)
LEs
ESBs
fMAX (MHz) (2)
875
2
44.784 required
Notes:
(1)
(2)
Altera Corporation
All Logic Element (LE) and Embedded System Block (ESB) numbers are
approximate as of Feb. 20, 2001.
If the T3MAP interfaces to an STS-12 line rate the fMAX will be 77.76 MHz.
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T3 Mapper MegaCore Function (T3MAP) Data Sheet
Licensing
No license is required to perform the following trial operations using your
own custom logic:
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Instantiation
Place-and-Route
Static Timing Analysis
Simulation on a third-party simulator
Only when you are ready to generate programming files, do you need to
obtain licenses through your local Altera representative.
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Deliverables
The following elements are provided with the T3MAP package:
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101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
[email protected]
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All current variants use a single license with ordering code:
PLSM-T3MAP.
Data Sheet
User Guide
Midbus and AIRbus Interface Functional Specifications
MegaWizard Plug-In
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Encrypted gate level netlist
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Place-and-Route constraints (where necessary)
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Secure RTL simulation model
Sanity testbench
Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are
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Copyright  2001 Altera Corporation. All rights reserved.
Altera Corporation