a6402
Universal Asynchronous
Receiver/Transmitter
November 2002, ver. 1.1
Features
Data Sheet
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General
Description
Optimized for the Stratix™ GX, Cyclone™, Stratix, APEX®, APEX II,
and FLEX® device families
Uses approximately 162 logic elements (LEs)
Programmable word length, stop bits, and parity
Full duplex operation
Includes status flags for parity, framing, and overrun errors
Functionally based on the Harris HD-6402 device, except as noted in
the “Variations & Clarifications” on page 8
The a6402 function implements a universal asynchronous
receiver/transmitter (UART), which provides an interface between a
microprocessor and a serial communications channel. Figure 1 shows the
a6402 symbol.
Figure 1. a6402 Symbol
A6402
en_rx
en_tx
cls1
cls2
crl
ndrr
epe
mr
pi
rrc
rri
sbs
ntbrl
tbr[7..0]
trc
Altera Corporation
DS-A6402-1.1
dr
fe
oe
pe
rbr[7..0]
tbre
tre
tro
1
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Signals
Table 1 shows the input and output signals for the a6402.
Table 1. a6402 Signals (Part 1 of 2)
Name
Type
Polarity
Description
en_rx
en_tx
Input
High
cls1
cls2
Input
–
crl
Input
High
Control register load. Controls how the data word is loaded into the control
register.
ndrr
Input
Low
Data received reset. Clears the dr output.
epe
Input
High/low Even parity enable. When high, even parity; when low, odd parity.
mr
Input
High
Master reset. Clears the pe, fe, dr, and oe outputs, and asserts the tre
and tbre outputs.
pi
Input
High
Parity inhibit. When pi is asserted, parity is neither generated nor checked.
rrc
Input
–
Receiver register clock. Operates at 16 times the receive data rate.
rri
Input
–
Receiver register input. Serial input data.
sbs
Input
High/low Stop bit select. When high, sbs generates 2 stop bits (1.5 stop bits for 5-bit
format); when low, sbs
generates 1 stop bit.
ntbr1
Input
Low
tbr[7:0]
Input
–
Transmitter buffer register input bus.
trc
Output
–
Transmitter register clock. Operates at 16 times the transmit data rate.
dr
Output
High
Data received. Indicates that a data word has been transferred to the
receiver buffer register.
fe
Output
High
Framing error. Asserted when the expected stop bit(s) is not detected.
oe
Output
High
Overrun error. Asserted when data in the receiver buffer register is
overwritten while the dr output is still asserted.
pe
Output
High/low Parity error. Set when the calculated parity does not match the received
parity. When pi is asserted, pe is set low.
rbr[7:0]
Output
–
tbre
Output
High
2
Clock enables. The en_rx and en_tx signals allow the UART to remain
fully synchronous with the system high-speed clock, while operating at the
receive and transmit enable frequencies. The en_rx and en_tx signals are
pulses that are high for one system clock period and are at a rate 16 times
the rate of the desired receive and transmit data rates.
Character length select bits. These bits determine the length of the data
word.
00 = 5-bit word format
01 = 6-bit word format
10 = 7-bit word format
11 = 8-bit word format
Transmitter buffer register load. Enables load of the transmitter buffer
register.
Receiver buffer register bus.
Transmitter buffer register empty. Indicates that the transmitter buffer
register is empty.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 1. a6402 Signals (Part 2 of 2)
Name
Type
Polarity
tre
Output
High
tro
Output
–
Description
Transmitter register empty. Indicates that the data word is completely
transmitted out of the transmitter register.
Transmitter register output. Serial output data.
Configurations
The a6402 receives and transmits data in a variety of configurations,
including 5-, 6-, 7-, or 8-bit data words; odd, even, or no parity; and 1, 1.5,
or 2 stop bits. Table 2 shows the available configuration options.
Table 2. a6402 Available Configurations (Part 1 of 2)
Character Format
Data bits
5
6
7
Parity Bit
Start Bit
Control Word
Stop Bits
cls2
cls1
pi
epe (1)
sbs
Odd
1
1
0
0
0
0
0
Odd
1
1.5
0
0
0
0
1
Even
1
1
0
0
0
1
0
Even
1
1.5
0
0
0
1
1
None
1
1
0
0
1
X
0
None
1
1.5
0
0
1
X
1
Odd
1
1
0
1
0
0
0
Odd
1
2
0
1
0
0
1
Even
1
1
0
1
0
1
0
Even
1
2
0
1
0
1
1
None
1
1
0
1
1
X
0
None
1
2
0
1
1
X
1
Odd
1
1
1
0
0
0
0
Odd
1
2
1
0
0
0
1
Even
1
1
1
0
0
1
0
Even
1
2
1
0
0
1
1
None
1
1
1
0
1
X
0
None
1
2
1
0
1
X
1
Altera Corporation
3
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 2. a6402 Available Configurations (Part 2 of 2)
Character Format
Data bits
8
Parity Bit
Control Word
Start Bit
Stop Bits
cls2
cls1
pi
epe (1)
sbs
Odd
1
1
1
1
0
0
0
Odd
1
2
1
1
0
0
1
Even
1
1
1
1
0
1
0
Even
1
2
1
1
0
1
1
None
1
1
1
1
1
X
0
None
1
2
1
1
1
X
1
Note:
(1)
4
The X indicates “don’t care.”
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Functional
Description
Figure 2 shows a block diagram of the a6402.
Figure 2. a6402 Block Diagram
crl
cls2
cls1
pi
epe
sbs
Control
Register
Transmitter
tbre
tre
Transmitter
Control
mr
ntbrl
trc
tbr
Start
Transmitter
Buffer
Register
8
Transmitter
Register
Parity
Generator
Transmitter
Multiplexer
tro
Stop
Receiver
dr
oe
Receiver
Control
mr
ndrr
rrc
rbr
rri
8
Receiver
Buffer
Register
8
Receiver
Register
8
pe
fe
Altera Corporation
Parity
Check
Stop
Check
5
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Master Reset
When the mr input is asserted, the pe, fe, oe, and dr outputs are
asynchronously cleared and tbre and tre are asserted. The assertion of
mr also sets all state machines to a default idle state. This condition does
not affect the receiver buffer register. The mr input must be pulsed high at
least once after power-up. When mr is deasserted, normal operation
resumes at the next rising edge of trc or rrc.
1
Once the pe, fe, and oe outputs are set, the only exit condition
available is through asserting mr.
Control Register
The control register contains the configuration of the data word, including
the number of bits, calculated parity, and the number of stop bits. The crl
input, an active high register enable, controls how the data word is loaded
into the control register. When crl is asserted, the cls2, cls1, pi, epe,
and sbs inputs are loaded on the next rising edge of the trc input.
Transmitter
The transmitter consists of the following elements:
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Transmitter control—The transmitter control contains three
interconnected state machines. The first state machine regulates the
baud rate by performing a divide-by-16 operation on the trc input.
The second state machine detects the low-to-high transition on
ntbrl, starts the serial transmission through tro, transfers data
from the transmitter buffer register to the transmitter register, and
generates the status signals tbre and tre. The third state machine
controls the multiplexing of data bits to the tro output.
Transmitter buffer register—The transmitter buffer register is loaded
via ntbrl, an active-low register enable, that causes tbr[7..0] to
be loaded from the microprocessor on the next trc clock edge.
Transmitter register—The transmitter register loads the data from the
transmitter buffer register and holds that data until transmission is
complete.
Parity generator—The parity generator calculates the appropriate
parity value depending on the epe input (even or odd parity) and the
cls inputs (data word length).
Transmitter multiplexer—The transmitter multiplexer selects a
single-bit data value and drives the tro output. Inputs to the
transmitter multiplexer include the start bit, all eight bits from the
transmitter register, the parity bit, and a stop or idle bit.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Receiver
The receiver consists of the following elements:
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Altera Corporation
Receiver control—The receiver control contains three interconnected
state machines. The first state machine performs a divide-by-16
operation on the rrc clock to determine when to sample the rri
serial input. The second state machine detects the high-to-low
transition on rri, determines if a valid start bit has been received,
transfers data from the receiver register to the receiver buffer register,
and generates the status signals dr and oe. The third state machine
loads the individual bits of the receiver register and the fe and pe
outputs.
Receiver register—The receiver register loads the number of data bits
determined by the cls inputs. If the data word is less than eight bits,
the data is right-justified with the MSBs filled with logic lows. When
the stop bit is detected, the receiver register transfers its contents to
the receiver buffer register.
Parity check—The parity check calculates the parity of the data word
and the parity bit. If an error occurs, the pe output is asserted. Once
asserted, the pe output can only be cleared by asserting the mr input.
Stop check—The stop check samples the middle of the first expected
stop bit. If an error occurs, the fe output is asserted. Once asserted,
the fe output can only be cleared by asserting the mr input.
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a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Timing
Waveforms
Figure 3 shows the timing waveforms for the a6402.
Figure 3. a6402 Functional Timing Waveforms
Data Input Cycle
trc
tbr[7..0]
Valid Data
ntbr l
Control Register Input Cycle
trc
cls[2..1], pi
epe , sbs
Valid Data
crl
Serial Data Format (7 Bits, 1 Parity Bit, 1 Stop Bit)
Start Data
LSB
Data Parity Stop
MSB
tro
Variations &
Clarifications
The following characteristics distinguish the Altera® a6402 from the
Harris HD-6402:
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The a6402 does not contain the sfd and rrd inputs, and the outputs
are not tri-stated.
In the a6402, the control and transmitter buffer registers are
implemented as registers and use trc as a clock source; these
registers are implemented as latches in the HD-6402 device.
In the a6402, after mr is deasserted, normal operation can resume on
the next rrc or trc rising clock edge. In the HD-6402 device, normal
operation does not resume for 18 clock cycles.
Due to the synchronization process in the a6402, tbre is deasserted
two clock cycles after the low-to-high transition of ntbrl. In the HD6402 device, tbre is deasserted immediately after the low-to-high
transition of ntbrl.
In the a6402, the tro output is registered to remove glitches. This
register uses trc as the clock source.
Once the pe, fe, and oe outputs are asserted, the HD-6402 device has
no exit condition other than through asserting mr.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Directory
Structure
Figure 4 shows the directory structure of the a6402.
Figure 4. Directory Structure
a6402-<version>
clear_wrappers
Contains both a Verilog HDL and VHDL wrapper file that show the core pinouts.
doc
Contains the documentation.
lib
Contains the encrypted core.
sim_lib
Contains simulation libraries.
native
Contains the VHDL model.
testbench
Contains the testbench files.
visualip
Contains the precompiled libraries for the Visual IP software.
Simulate with
the Models
Altera provides a VHDL model that you can use to simulate the function
in your system. Altera also provides Visual IP models, which you can use
with the Visual IP software and are supported by other simulators. The
VHDL model is supplied as pre-compiled libraries for the ModelSim
simulation tool and is installed in the sim_lib\native\vhdl\modelsim
directory. You can integrate this model into your system, speeding the
simulation process.
The following instructions describe how to set up your system and how to
simulate the VHDL model using the ModelSim simulation tool.
Within the sim_lib\native\vhdl\modelsim directory is a precompiled
library, auk_a6402, which is required.
1
1.
You can also use the ModelSim graphical user interface (GUI) to
create a logical map. Refer to the ModelSim online help for
details.
Run the ModelSim simulation tool and create a logical map called
auk_a6402 to the directory containing the compiled library by typing
the following command in the ModelSim software:
vmap auk_a6402 <Drive:>/<Core Path>
/sim_lib/native/vhdl/ModelSim/auk_a6402r
Altera Corporation
9
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
2.
You must refresh the compiled library by typing the command:
vcom -work auk_a6402 -refreshr
Using the VHDL Testbenches
In addition to the model, Altera provides a sample VHDL testbench (in
the sim_lib\testbench\ directory). The VHDL testbench lets you easily
simulate the function. To compile these files in the ModelSim software,
follow the steps below:
1
To use the sample VHDL testbench, the VHDL model must be
available and setup for ModelSim as described earlier.
1.
Open the ModelSim simulation tool. Choose Change Directory (File
menu) and change the directory to your working directory.
2.
Select Create a New Library (Design Menu). Select a new library and
a logical mapping to it. In the Library Box type work.
3.
Select Compile (Design menu), in the Compile HDL Source Files
dialog box, select the \sim_lib\testbench directory in the Look In
drop-down list box. Select a6402_tb.vhd and click Compile; select
tippytop.vhd and click Compile.
1
The file tippytop.vhd is the top-level file, which is required
for simulation (see Figure 5).
Figure 5. Tippytop.vhd Block Diagram
Tippytop
a6402
Testbench
4.
a6402 Clear
Wrapper
When the compilation finishes, click Done. You are now ready to run
the simulation.
Visual IP Models
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
10
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
1.
Point your web browser at
https://www.altera.com/support/software/download/
eda_software/visualip/dnl-visualip.jsp.
2.
Follow the online instructions to download the software and save it
to your hard disk.
To use the Visual IP model, perform the following steps:
1.
Set up your system to use the Visual IP software, as detailed in the
Visual IP documentation (Simulating Visual IP Models with the
ModelSim Simulator for PCs White Paper, Simulating the Visual IP
Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX)
Simulators White Paper).
2.
Compile the wrapper for the core model into the auk_a6402 library.
The Verilog HDL version of the wrapper is in the
visualip\<operating system>\a6402\interface\pli directory;
the corresponding VHDL version is in the
visualip\<operating system>\a6402\interface\mti directory.
3.
Compile either your testbench or the open-source VHDL testbench
model, a6402_tb, which is in the sim_lib\testbench directory.
4.
Compile the appropriate wrapper file from the \clear_wrappers
directory.
The Visual IP model is now ready for use in your simulator.
Synthesis,
Compilation &
Place & Route
Altera Corporation
After you have verified that your design is functionally correct, you are
ready to perform synthesis and place-and-route. Synthesis can be
performed by the Quartus® II development tool.
Before you compile and place-and-route, you must create a new Quartus
II project and add your chosen file to the project. With the New Project
wizard, you specify the working directory for the project, assign the
project name, and designate the name of the top-level design entity. You
will also specify the a6402 user library. To create a new project, perform
the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software if you prefer.
2.
Choose New Project Wizard (File menu).
11
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project.
5.
Specify the name of the project.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\a6402-<version>\lib\ into the Library name box,
where <path> is the directory in which you installed the a6402
UART. The default installation directory is c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
12. Click Finish.
You are finished creating your new Quartus II project.
To add your chosen file to the project, perform the following steps:
1
This walkthrough adds the example instantiation from the
\clear_wrappers directory.
1.
Choose Add/Remove File (Project menu).
2.
Browse to the examples instantiations \clear_wrappers directory.
3.
Choose either the VHDL or the Verilog HDL file.
To use the Quartus II software to compile and place-and-route your
design, perform the following steps:
12
1.
Select Compile mode (Processing menu).
2.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Compile your design. The Quartus II compiler synthesizes and
performs place-and-route on your design.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
1
Altera Corporation
Refer to Quartus II Help for further instructions on
performing compilation.
13
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
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Applications Hotline:
(800) 800-EPLD
Literature Services:
[email protected]
14
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