Using the Quartus II
Chip Editor
June 2003, ver. 1.0
Introduction
Application Note 310
Altera® FPGAs have made tremendous advances in capacity and
performance. Today, Altera Stratix™ and Stratix GX devices are equipped
with embedded memory, dedicated DSP blocks, and advanced I/O
standards. Given these advancements, previous design flows need to be
supplemented to maximize productivity. Newer, more advanced features
must be added to the tool suite to take full advantage of Stratix and
Stratix GX architectural advancements.
To address this need, Altera provides the Quartus® II chip editor, the most
powerful post, place-and-route design-modification tool in the industry.
The chip editor enhances productivity by enabling you to design a
system-on-a programmable-chip (SOPC) within a very limited timeframe.
With the chip editor, you can easily perform last-minute engineering
change orders, correct functional flaws, and optimize timing. The changes
are made to the post, place-and-route netlists rather than the source
code—allowing you to avoid the process of re-synthesizing and placeand-routing the entire design again.
With the Quartus II software version 3.0 chip editor, you can:
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View detailed, architecture-specific information
Modify properties within the Altera device
With the chip editor, you can view the following architecture-specific
information related to your design:
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AN-310-1.0
Graphical display of the exact FPGA routing resources used by your
design. For example, you can visually examine how two blocks are
physically connected, as well as the signal routing that connects the
two blocks.
Device utilization information: You can view how each resource
within an Altera device is used. For example, you can view which
logic element (LE) inputs are used, if the LE utilizes the register or the
look-up table (LUT) or both, as well as the signal flow through the LE.
Stratix I/O utilization information: You can view what Stratix device
I/O resources are used. For example, you can view what components
of the I/O are used, if the delay chain settings are enabled, and the
signal flow through the I/O.
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With the chip editor, you can modify the following properties within the
Altera device:
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Logic elements
I/O cells
Phase-locked loops (PLL)
When design changes are made via the chip editor, they are logged in the
Change Manager. The Change Manager is an interface that displays the
status of a change. If a design change results in incorrect behavior, you can
easily restore the previous value.
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For more information on the Change Manager, see “Change Manager” on
page 20.
The Quartus II software version 3.0 supports the chip editor flow for the
following devices:
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Chip Editor
Design Flow
Stratix
Stratix GX
Cyclone™
An ideal FPGA design flow starts with developing design specifications,
developing register transfer level (RTL) code that describes the design
specifications, verifying that the RTL code performs the correct
functionality, verifying that the placed-and-routed design satisfies the
design’s timing constraints, and ends with successfully programming the
targeted FPGA.
Unfortunately, similar to most difficult processes, the ideal design flow
rarely occurs. Oftentimes, designers experience bugs in the RTL code—or
worse—the design specifications change midway through the design
cycle. The challenge lies in efficiently accommodating these types of
design issues. Traditionally, designers go back to the source RTL code,
make the appropriate changes, and then go through the entire design flow
process again.
With the Altera chip editor, the design flow process is significantly less
time consuming. You can make changes directly to the post, place-androute netlist, generate a new programming file, and test the revised design
without ever modifying the RTL code. See Figure 1.
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Figure 1. Chip Editor Design Flow
Design Specification
Design Entry
RTL Simulation
Synthesis
Place & Route
Timing
Analysis
PCB Implementation
Gate-Level
Simulation
Chip Editor
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Chip Editor
Overview
The chip editor contains many advanced features that enable you to
quickly and efficiently make design changes. The advanced features are
offered through the chip editor’s integrated tool set, including:
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Device resource viewing tools
Resource editors that allow you make modifications to your post,
place-and-route design
A Change Manager to track all design changes
Device Resource Viewing Tools
A Chip viewer tool allows you to quickly and easily view design postcompilation placement and routing information. You can launch the chip
viewer in one of two ways:
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Click the chip editor icon in the tool bar
Choose Chip Editor (Assignments menu)
The chip editor uses a hierarchical zoom viewer that shows various
abstraction levels of the targeted Altera device. As you increase the zoom
level, the level of abstraction also increases.
First (Highest) Level View
The first (highest) zoom level provides a high-level view of the entire
device floorplan, and is similar to the Quartus II Timing Closure
floorplan. This view allows you to easily locate and determine the
placement of any node in your design. Figure 2 shows the chip editor’s
first level view.
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For more information on the Quartus II Timing Closure floorplan, refer to
AN 198: Timing Closure with the Quartus II Software.
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Figure 2. Chip Editor’s First (Highest) Level View: Default Level View
MRAM Block
DSP Block
Logic Element
M4K Block
M512 Block
The chip editor uses an equivalent device resource, color-coding scheme
to that used in the Timing Closure Floorplan. The TriMatrix™ memory
blocks are colored blue with varying widths differentiating between the
MRAM, M4K, and M512 memory blocks. DSP blocks are colored orange,
and logic elements are colored green.
After a full compilation, the chip editor displays all used device resources
and routing channels in yellow. Figure 3 shows the chip editor after a full
compilation.
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Figure 3. Chip Editor View After a Full Compilation
Second Level View
The second zoom level provides a similar view to the first (highest) level
view. Each device resource is highlighted with their respective color code
as described in the “First (Highest) Level View” on page 4. The chip editor
displays all used device resources and routing channels in yellow.
Figure 4 shows the second level view.
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Figure 4. Second Level View
DSP Block
Logic Element
MRAM Block
M4K Block
Routing Channels
M512 Block
The second level view provides tooltips similar to that in the first level
view, except that in the second level view you can examine the routing
channels. Figure 5 shows the routing channel tooltip information.
Figure 5. Routing Channel Tooltip Message: Second Level View
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1
To change the magnification level, select the Zoom Tool icon
(chip editor toolbar) and left click to zoom in and right click to
zoom out.
Third Level View
The third zoom level is similar to the highest zoom level view except that
connections in and out of the device resource are now shown. The chip
editor displays all used device resources and routing channels in yellow.
Figure 6 shows the third zoom level view.
Figure 6. Third Level View
DSP Block
Logic Element
M4K Block
MRAM Block
M512 Block
Routing Channels
Fourth Level View
The fourth zoom level provides the highest level of abstraction of the
device floorplan, and it depicts exact routing channels and how each
device resource is driving the routing channels. The chip editor displays
all used device resources and routing channels in yellow. Figure 7 shows
the fourth zoom level view.
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Figure 7. Fourth Level View
M4K Block
M512 Block
Fifth Level View
The fifth zoom level expands upon the fourth zoom level by depicting the
highest abstraction of the LAB structure. The fifth level view depicts all
available routing channels within each LAB. Figure 8 shows the fifth
zoom level.
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Figure 8. Fifth Level View
Output Channels
Input Channels
Output Channels
Input Channels
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Table 1 describes the chip editor’s zoom level and it’s corresponding view
description.
Table 1. Chip Editor’s Zoom Level & View Description
Zoom Level
Resource
Editors
View Description
First level (highest)
High level view of the device floorplan. Shows used device
resources and routing channels.
Second level
Shows both used and unused row and column routing
channels.
Third level
Shows routing channels in and out of device. This view
depicts routes in and out of device resources.
Fourth level
Detailed view depicting exact routing channels in and out
of device resources. Shows individual logic elements.
Fifth level (lowest)
Exact routing channels in and out of Logic Elements.
This section describes the following resource editors:
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LE editor
I/O editor
PLL editor
LE Editor
The smallest unit of logic in the Stratix architecture is a logic element (LE).
The LE contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register that can be fed by the output of the LUT or an
independent function generated in a separate LE. Figure 9 shows a view
of what the LE looks like in the chip editor.
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For a description of the editable fields in the LE Editor, refer to Quartus II
Help.
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Figure 9. Stratix Device LE Architecture
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For a detailed description of the Startix device LE, refer Volume 1 of the
Stratix Device Handbook.
Properties of the Logic Element
This section discusses the properties of the logic element that can be
examined by the LE Editor, including:
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Operation mode
LUT equation
LUT mask
Synchronous mode
Register cascade mode
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AN 310: Using the Quartus II Chip Editor
Operation Mode
The operation of an LE can either be set to normal or arithmetic. However,
the operation mode cannot be edited in the Quartus II software,
version 3.0, i.e., an LE cannot be converted from one mode to another.
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For more information on the modes of operation, refer to Volume 1 of the
Stratix Device Handbook.
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When configured in normal mode, the LUT can implement a function
of four inputs.
When configured in arithmetic mode, the LUT is broken into two,
three-input LUTs. The first LUT is used to generate the signal that
drives the output of the LUT, while the second LUT is used to
generate the carry-out signal. The carry-out signal can only drive a
carry-in signal of another LE. When the LE is in arithmetic mode the
data input is not available as an input.
LUT Equation
The LUT equation box allows you to change the equation that is currently
implemented by the LUT. When in normal mode you can only change the
SUM equation. When in arithmetic mode you can change both the SUM
and the CARRY equation.
When a change is made to the LUT equation, the Quartus II software
automatically changes the LUT mask.
To change the function implemented by the LUT you must first
understand how the LUT works. A LUT contains storage cells that are
used to implement small logic blocks as a function of the inputs. Each
storage cell is capable of holding a logic value, either a 0 or a 1. The Stratix
FPGA is built with a four–input LUT, and thus, has 16 storage cells. The
LUT will store the 16 output values in its storage cells. The output value
seen from the LUT will depend on what is driven into the input ports of
the LUT.
Assume that you need to build the following logic function:
(A XOR B) or (C AND D)
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Table 2 lists the truth-table for the sample logic function.
Table 2. Truth Table of Sample Logic Function
D Input
C Input
B Input
A Input
Output
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
LUT Mask
Table 2 describes how the LUT mask is generated. The LUT mask is
simply the hexadecimal representation of the LUT output. For example,
the LUT output of (A XOR B) or (C AND D) can be represented by the
following binary string: 1111011001100110. The LUT mask, in
hexadecimal for this binary string is: F666
When the LE is set to arithmetic mode the first eight bits in the LUT mask
represent the SUM equation output. The second set of eight bits represents
the CARRY equation.
When a change is made to the LUT mask, the Quartus II software
automatically changes the LUT equation.
Synchronous Mode
The synchronous mode controls the synchronous signals of the register.
When the LE is in synchronous mode the sload and sclr signals are
enabled.
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You can invert either the sload or sclr signal feeding into the LE. The
sload signal, if used in an LE, must be the same for all other LEs in the
same LAB. This includes the inversion state of the signal. For example, if
two LEs in a LAB have the sload signal connected, both LEs must have
the sload signal set to the same value. The same is true for the sclr
signal.
Register Cascade Mode
When register cascade mode is enabled, the cascade-in port feeds the
input to the register. The register cascade mode is most often used when
the design implements a series of shift registers.
Legal Changes to an LE
The following lists the properties that can potentially be modified in the
LE viewer:
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LUT equation: You can change the LUT equation for the LE with the
Altera chip editor. When changing the LUT equation you cannot add
inputs that previously were not used. The following provides an
example of a legal change:
Valid change: A&B#C → B&C
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Using the feedback path in the LE: You can use the feedback path that
connects the register output to the datac input of the LUT. You have
the ability of changing the existing route that is used within the LE. If
the LE is configured to use the datac or the cin input, you can reroute the channels and instead use the feedback path. To use this
feature, the LE must be configured to use the register. Once the
feedback path is used, datac and cin can no longer be selected to
drive the LUT
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Invert inputs: You can invert signals that feed the input of the LUT.
This feature is useful when you want to change the active level of a
signal. For example, if you want to make your load signal active low,
simply invert the sload signal that feeds the LE.
Unsupported Changes to an LE
The following unsupported changes to an LE will be supported in a future
version of the Quartus II software:
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Addition of LE inputs: As stated earlier you cannot add inputs to the
LE. To support this feature, the unused ports have to be enabled and
new routes from driving LE’s must be established. No routing
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changes are supported in the Quartus II software, version 3.0 chip
editor. However, routing changes will be supported in a future
version. The following is an invalid change that is not supported in
the chip editor:
Invalid Change: !B & C → A $ B # !C
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Changing an LE from arithmetic to normal mode (or vice versa): This
change is not supported in the Quartus II software, version 3.0 chip
editor. To configure an LE in arithmetic mode, you have to enable the
cin and cout signals. However, because you cannot add inputs to
the LE, enabling the cin and cout signals is not possible.
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Enabling the register: If the Quartus II Fitter does not utilize the
register in the LE, there is no way to enable it with the chip editor—
because doing so will require adding additional inputs to the LE.
The IO Editor
The I/O in Stratix FPGAs contains a bi-directional I/O buffer, six
registers, and a latch for a complete embedded bi-directional single data
rate or DDR transfer. The I/O can use both input registers to capture DDR
input and both output registers to drive DDR outputs. See Figure 10.
Figure 10. Stratix Device I/O
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For a detailed description of the Startix device I/O, refer to Volume 1 of the
Stratix Device Handbook.
Properties of the I/O
This section discusses the Stratix device I/O properties, including:
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Delay chain settings in input mode
Delay chain settings in output mode
Delay chain settings when using the output enable
Delay Chain Settings in Input Mode
Table 3 describes the delay chain input mode settings.
Table 3. Delay Chain Input Mode Settings
Setting
Description
Pad to register delay chain
Possible Value
This setting allows you to reduce the delay to the On
input register from the pin.
Off
Pad to core delay chain0 (or chain1) This setting allows you to adjust the delay to the
core logic from the pin.
Off
Small
Medium
Large
Clock enable to input register chain
Off
Small
Large
This setting allows you to adjust the delay of the
clock enable signal that feeds the input register.
Delay Chain Settings in Output Mode
Table 4 describes the delay chain output mode settings.
Table 4. Delay Chain Output Mode Settings
Setting
Description
Possible Value
Core to register delay chain
This setting allows you to reduce the delay to the On
output register from the core.
Off
TCO delay chain
This setting allows you to adjust the delay to the
pin from the core logic.
Clock enable to output register chain
This setting allows you to adjust the delay of the Off
clock enable signal that feeds the output register. Small
Large
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Off
Small
Medium
Large
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Delay Chain Settings When Using the Output Enable
Table 5 describes the delay chain settings when using the output enable,
and lists possible values.
Table 5. Delay Chain Settings When Using the Output Enable
Setting
Description
Possible Value
Clock enable to output enable register
chain
This setting allows you to adjust the delay of the
clock enable signal that feeds the output enable
register.
Off
Small
Large
ZBT delay chain
A logic option that supports zero bus turnaround
(ZBT) by increasing the propagation delay of the
falling edge of the output enable signal.
Off
On
TCOE delay chain
This setting allows you to adjust the delay from the Off
output enable path to the tri-state path.
On
Other Legal Changes in the I/O
This section describes other legal changes in the Stratix device I/O.
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Signal inversion: You can invert signals that drive the input of the
I/O viewer, with the exception of the PAD. This feature is especially
handy when you would like to change the active level of a particular
signal.
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Reset mode: You can change the reset mode—both the synchronous
and asynchronous signals of the registers. Each I/O register’s reset
mode can be changed according to Table 6.
Table 6. Reset Mode Changes
From/To
Reset
Clear
None
Yes
No
No
Reset
Yes
Yes
Yes
Clear
Yes
Yes
Yes
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None
Power-up state: You can independently set the power-up state to
either high or low for each I/O register. If an I/O register uses
asynchronous clear, the power-up state must be low. If an I/O
register uses asynchronous preset, the power-up state must be high.
If neither asynchronous preset nor clear is used, the power-up state
can be high or low.
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Bus hold: Each Stratix device I/O pin provides an optional bus-hold
feature. The bus-hold circuitry can weakly hold the signal on an I/O
pin at its last driven state.
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Slow slew rate: The output buffer for each Stratix device I/O pin has
a programmable output slew-rate control that can be configured for
low-noise or high-speed performance.
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I/O standard: Stratix I/O pins can be configured to certain I/O
standards. Not all pins can be set to every standard.
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Programmable drive strength: The output buffer for each Stratix
device I/O pin has a programmable drive strength control for certain
I/O standards.
The PLL Editor
PLLs are used to modify and generate clock signals to meet design
requirements. Additionally, PLLs are used for distributing clock signals to
different devices in a design, reducing clock skew between devices, and
generating internal clock signals.
Properties of the PLL
You can change many properties with the PLL Editor that will help you
generate the correct output clock frequencies that are necessary for
various design specifications. With the PLL Editor you can modify many
of the internal parameters of the PLL. Some of the settings that can be
modified include:
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M
N
M2
N2
SS
Counter high
Counter low
M initial
Loop filter R
Loop filter C
Charge pump current
Counter PH
Counter initial
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For a detailed description of all the settings, refer to Quartus II Help. For
more information on Stratix device PLLs, refer to the PLL section of
Volume 1 of the Stratix Device Handbook.
Change Manager
The Change Manager provides detailed tracking information on all
design changes made with the chip editor. Table 7 summaries the Change
Manager’s information.
Table 7. Change Manager Information
Change Manager
Column Name
Node name
Description
Name of the node that is modified with the chip editor
Change type
Type of change made to the node
Old value
Old value of the modified node
New value
New value of the modified node
Current value
Current value of the node as contained within the assembler netlist
Status
Current state of the change made to the node specified
Comments
User comments
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If a change is made that does not result in the correct behavior,
you can revert back to the original setting(s). You can also export
all changes to a Quartus II tools command language (Tcl) file.
The status of a change can also be seen in the Change Manager. When the
design rule checker (DRC) is run on the changes that have been made, you
can see the status of the change in the Change Manager. See Figure 11.
Figure 11. Change Manager Results
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Common
Applications
The chip editor can help you with four specific design challenges:
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Design analysis
Functional flaws in the design
Timing verification
Last minute design changes
Design Analysis
The ability to determine and isolate all FPGA design critical paths is
extremely important. Without this ability, achieving design timing
closure will be difficult and tedious. The chip editor’s various features
allow you to easily and efficiently locate and determine critical paths—as
well as the exact routes used within the Altera device.
Viewing Critical Path & Routing Delays from the Timing Analysis Report
Because the chip editor is a fully integrated tool within the Quartus II
software, the interaction with other Quartus II tools is both intuitive and
simple. An example of this is the viewing of critical paths and routing
delays in the Chip Editor.
After any Quartus II design compilation, a Timing Analysis report is
generated. The Timing Analysis report lists all design paths. Figure 12
shows a sample Timing Analysis report. By right-clicking any path and
choosing Locate in Chip Editor, you can easily locate any path from the
Timing Analysis report to the chip editor floorplan.
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Figure 12. Sample Timing Analysis Report
Figure 13 shows the register-to-register path that is located in the chip
editor from the Timing Analysis report.
Figure 13. Critical Path Location in the Chip Editor
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By locating the path in the chip editor, you are given the exact path that
the source register requires to reach the destination register. The
Quartus II software reports the timing delay between the source and
destination registers.
By right-clicking the path label and choosing Expand, you can view the
exact path traversed by the source register to reach the destination
register. See Figure 14.
Figure 14. View the Exact Path Traversed by the Source Register
With the expanded view, you can see node-to-node connection delays.
You can further expand the view to see each connection and the routing
channel used. Figure 15 shows the expanded view.
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Individual connections can also be selected, which allows you to
zoom in to any particular connection and expand it.
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Figure 15. Expanded View of Exact Path Traversed by the Source Register
Viewing Path & Routing Delays from Any Logic Elements
The chip editor can display the fan-in and fan-out from any arbitrary LE,
as well as the exact routing channels used from the source LE to
destination LE. Figure 16 shows a view of the LAB at the abstraction level
with an LE selected.
Figure 16. Logic Element Selection
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By choosing the Expand Fan-In Connections and Expand Fan-Out
Connections icons you can see the fan-in and fan-out of the selected LE.
Figure 17 shows the chip editor view with the expand fan-in and fan-out
icons turned on.
Expand Fan-In Connections icon:
Expand Fan-Out Connections icon:
Figure 17. Expand Fan-In & Fan-Out Connections From Selected LE
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By choosing the Show Route Fan-In and Show Route Fan-out icons you
can see the exact routing channels used by the selected LE’s fan-in and
fan-out connections. Figure 18 shows the chip editor view with the show
route fan-in and fan-out icons turned on.
Show Route Fan-In Icon:
Show Route Fan-Out Icon:
Figure 18. Show Route Fan-In & Fan-Out Connections From Selected LE
1
To remove the fan-in and fan-out connections drawn in the chip
editor, you can use the Clear Connections icon at any point in
the process.
Clear Connections Icon:
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Functional Flaws
Functional flaws may be found in the verification stage. Traditionally,
these flaws (bugs) are corrected by modifying the RTL code, and then
going through the entire design flow again, which is very time-consuming
because many tools and processes are required to be re-run to re-validate
the design. However, with the chip editor, the debugging process can
usually be simplified. This section provides examples of how the chip
editor simplifies the debugging process.
Correcting a Design with the LUT Equation
You can use the chip editor to modify the design’s LUT equation. The
following shows:
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An example design circuit with a functional flaw in the RTL code
How you can correct the problem with chip editor
Assume that the design specifications call for the implementation of the
circuit shown in Figure 19.
Figure 19. Example Design Circuit
dataa
datab
Input
AND2
Input
inst
OR2
datac
datad
Input
NOT
inst8
AND2
Output
data_out
inst9
Input
inst7
However, when the design is converted into the equivalent RTL code, a
functional flaw is generated.
// Verilog code for AND-OR-INVERT gate
module and_or_invertor (dataa, datab, datac, datad,
data_out);
input dataa, datab, datac, datad;
output data_out;
wire data_out;
wire AB, CD, or_out;
assign AB = dataa & datab;
assign CD = datac & datad;
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//top AND
//bottom AND
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assign or_out = AB | CD; // or output
assign data_out = or_out; //invert for final
result
endmodule
// end of Verilog code
The mistake is very obvious—the inversion did not occur in the last
assignment, see the following code line:
assign data_out = or_out; //invert for final result
This type of functional flaw appears quite often in HDL designs. In this
scenario, you need to modify the LUT equation section (combinatorial
logic) that implements the NOT function. There are many ways that you
can modify the LUT equation. The easiest way is to look through the RTL
code, highlight the signal that implements the incorrect logic, right-click,
and choose Locate in Chip Editor. Figure 20 illustrates this process.
Figure 20. Modifying the LUT Equation with the Chip Editor
Because the Quartus II synthesis process may change your RTL node
names, there can be situations where the Locate in Chip Editor option
(from the RTL code) will not find the LE. If this occurs, you can try the
following method to locate the problem LE:
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Find the input (or output) that drives (or is driven) the problem LE. Once
you have found the pin, open the Resource Property Editor and choose Go
to destination ATOM option (or Go to source ATOM option) until the
problem LE is found. The following steps illustrate this method:
1.
Find the data_out signal
2.
Launch the Resource Property Editor on the data_out signal
3.
Highlight the datain port of the pin
4.
Choose Go to source ATOM option
This process will find the LE that drives the output pin. Continue going
through this iterative process until the problem LE is found.
The Quartus II synthesis process will further optimize your design, which
can sometimes make modifying the LUT equation somewhat difficult.
Before modifying the LUT equation it is very important that you first
understand the fine design details and how the design is implemented in
the FPGA.
Once you have located the problem LE in the chip editor, right-click and
choose Locate in Resource Property Editor. See Figure 21.
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Figure 21. Locating the Specific LE via the Resource Property Editor
Next, modify the equation to invert the output of the LE. The new
equation for the LE is now set to !(C#D). Figures 22 and 23 show the LUT
equation before and after the inversion process.
Figure 22. Before Inversion Process
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Figure 23. After Inversion Process
1
Notice that the LUT mask changes to reflect the new equation.
Once the equation has been verified, save the results.
When you are satisfied that the new logic assignment is correct, you must
perform a Check Netlist and Save operation in the Change Manager. See
Figure 24.
Figure 24. Check Netlist & Save Operation in the Change Manager
Finally, either generate a programming file so you can test the circuit on
the PCB, generate a simulation netlist that will allow you to verify the
functionality in a third-party simulator, or run Quartus II Timing
Analysis. See Figure 25.
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Figure 25. Run Quartus II Timing Analysis
If you perform any of the steps discussed in this section and determine
that the new results do not meet your design’s specifications, you can
easily revert back to the previous results. To revert back to the previous
results, open the Change Manager and choose Restore Old Value. See
Figure 26.
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Figure 26. Change Manager’s Restore Old Value Function
Timing Verification
One of the major concerns when designing an FPGA is timing restrictions.
If an FPGA design implementation does not satisfy timing constraints,
timing optimization must be performed. This section discusses timing
optimization techniques using delay chain settings.
Assume that your design specification calls for a minimum clock-to-out
(TCO) time of 5 ns. When the Quartus II Static Timing Analyzer is run, the
following results are attained for the minimum tCO on a specific path in
the design:
■
■
■
■
■
■
Slack: -0.077 ns
Required minimum tCO: 5.000 ns
Actual minimum tCO: 4.923 ns
Source register name: inst3
Destination output pin name: data_out1
Clock source: clk
See Figure 27.
Figure 27. Minimum TCO
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Further investigation on the path results in the following:
■
■
Minimum slack time is -0.0077 ns for clk between source register
inst3 and destination pin data_out1
Shortest register to pin delay is 2.445 ns
–
1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
IOC_X44_Y31_N2; REG Node = inst3
–
2: + IC(0.000 ns) + CELL(2.445 ns) = 2.445 ns; Loc. = Pin_D7; PIN
Node = data_out1
–
Total cell delay = 2.445 ns
Because the interconnect delay is 0 ns, the only way to increase the delay
from the register to the output pin is to use one of the delay chain settings
in the I/O element. Thus, to meet the design specifications, you need to
enable the TCO delay chain. See Figure 28.
Figure 28. Enabling the TCO Delay Chain using the Resource Property Editor
After the delay chain setting is enabled, save the changes and run the
Quartus II Static Timing Analyzer.
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The compilation report generated by the Quartus II Static Timing
Analyzer yields the following results:
■
■
■
■
■
■
Slack: 0.300 ns
Required minimum tCO: 5.000 ns
Actual minimum tCO: 5.300 ns
Source name: inst3
Destination name: data_out1
Clock source: clk
See Figure 29.
Figure 29. Minimum TCO After the Delay Chain is Enabled
The delay chain adjustment corrected the timing issue in the example
design. The whole process is complete in far less time than the traditional
design flow, which requires a design re-synthesis, and another place-androute cycle.
Last-Minute Design Changes
Usually, design specifications change during the later part of a design
cycle. In some cases, last-minute design changes can be disastrous, as they
can impact the design’s overall functionality. Accordingly, last-minute
design changes should be made in the quickest, most efficient manner
possible. The longer the change(s) takes to implement, the less time you
have to verify functionality, which can be very costly.
To accommodate last-minute design changes, your design tools need to
very flexible. The chip editor is a flexible design tool that can quickly
implement last-minute design changes. This section provides design
examples and discusses techniques to quickly implement and verify lastminute design changes, including:
■
■
Altera Corporation
Using the INVERT function
Adjusting the PLL properties
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Using the INVERT Function
Assume that the following counter is implemented in a design:
module behav_counter( d, clk, clear, load, up_down,
qd);
// Port Declaration
input
input
input
input
input
output
[7:0] d;
clk;
clear;
load;
up_down;
[7:0] qd;
reg
[7:0] cnt;
assign qd = cnt;
always @ (posedge clk)
begin
if (!clear)
cnt = 8'h00;
else if (load)
cnt = d;
else if (up_down)
cnt = cnt + 1;
else
cnt = cnt - 1;
end
endmodule
From this design example, you can see that the clear signal is active low
(logic 0); i.e., when the clear signal is de-asserted the count register is
cleared.
Assume that an Engineering Change Order request is received calling for
the clear signal to be active high (logic 1). Traditionally, you would need
to change each statement in the RTL code that is dependent on the active
level of the clear signal. However, with the chip editor’s LE viewer this
process is significantly simplified. Instead of directly changing the RTL
code, you can use the chip editor to change the functionality.
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The first step in correcting the polarity of the clear signal is to find the
registers in the design that are impacted by the ECO request. There are a
number of methods that can be used to find the impacted registers. The
easiest method to select a large number of registers is to use the Node
Finder to find all of the registers. Once the registers are found, open the
LE property editor of all the registers, and make the change to the polarity.
See Figure 30.
Figure 30. Changing Register Polarity with the LE Viewer & Property Editor
Again, the next step is to generate a programming file and/or simulation
netlist. The whole process is complete in far less time then the traditional
design flow, which requires a change to the RTL code, design re-synthesis,
and another post, place-and-route cycle.
Adjusting the PLL Properties
With chip editor you can change many of the PLL parameters within the
PLL instantiation. Assume that your design calls for the circuit
implementation shown in Figure 31.
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Figure 31. Example Design Implementation
Input
inclk0
shift_pll
inclk0
VCC
inclk[] frequency: 100 MHz
Operation mode: Normal
clk Ratio Ph (dg) Td (ns) DC (%)
c0 4/3
0.00
0.00
50
c1 2/1
0.00
0.00
50
c2 2/1
0.00
1.00
50
c0
c0
c1
c2
c3
c3
locked output
locked
inst
VCC
TFF
PRN
Q
T
Output
tff0
c0
CLRN
inst2
TFF
T
PRN
Q
Output
tff1
c1
CLRN
inst4
TFF
T
PRN
Q
Output
tff2
c2
CLRN
inst5
The three output clocks feed the clock ports of the toggle flip-flops.
Assume that the original design specification calls for output frequencies
of 120 MHz, 200 MHz, and 200 MHz respectively. Now, assume that the
design specification change requires output frequencies of 30 MHz,
150 MHz, and 250 MHz respectively. Using the PLL Editor, making these
changes is fairly simple.
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The first step in implementing the new system is to locate the PLL in the
chip editor. Once the PLL has been located, the values of PLL properties
need to be adjusted so that the output frequencies meet the design
specifications. Once this change is made, the values of M and N need to be
adjusted so that the output frequencies meet the new design
specifications. See Figure 32.
Figure 32. Using the PLL Viewer
After all of the changes are implemented, save the new values and
generate a new programming object file (.pof).
Without the chip editor, you will have to re-generate the MegaWizard file
for the PLL instance, re-synthesize, run another post-and-route cycle, and
another timing analysis cycle. However, with the chip editor you can
quickly make the design changes via the PLL viewer and run another
timing analysis. Thus, the entire process is completed in a fraction of the
time.
Design Rule
Checker
The DRC ensures that all changes made via the chip editor are valid and
adhere to all architectural restrictions. There are two DRC levels,
■
■
DRC selected atoms
DRC netlist
The DRC selected atoms level provides a check for internal consistency.
Even if the atom level check passes, the change may not be valid.
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Altera Corporation
As stated earlier, the control signals that feed a LAB must have
the same polarity throughout. For example, if there are two LEs
in a LAB, the control signals such as sload and sclr must have
the same polarity. If you change the polarity for one of the
control signals in the LAB and do not change the other signal,
both LEs will pass the independent ATOM level checks;
however, when a Circuit Level DRC is run, you will get the
following error message:
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Error: LAB has 2 sload signals, but only 1 signal
is allowed.
The DRC netlist level provides a check that uses a fitter to perform an
overall thorough check of the design change. If the DRC netlist level fails
the check, all changes are reversed but listed in the Change Manager. If the
DRC netlist level passes, all changes are finalized and the assembler,
timing analysis or simulation can be run on the new changes.
Options After
Running the
Chip Editor
After a design change is made via the chip editor, there are a number of
processes that can be started. For example, you can run the Quartus II
Static Timing Analyzer, the Netlist Writer, and/or Assembler.
Running the Static Timing Analyzer
When you make design changes with the chip editor, you should process
the changes through the Quartus II Static Timing Analyzer—to ensure
that they do not adversely effect the design’s timing requirements.
For example, when you enable one of the delay chain settings of a specific
pin you will adjust the I/O timing. Thus, to ensure that all timing
requirements are still met, you need to process the design change through
the Static Timing Analyzer.
The Static Timing Analyzer must be started by either choosing Start
Timing Analysis (Processing menu), or by clicking the Start Timing
Analyzer button from the Compiler Tool dialog box (Tools menu).
Figure 33 shows the Compiler Tool dialog box.
Figure 33. Compiler Tool Dialog Box
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Running the Netlist Writer
When chip editor is used to correct a functional flaw you will sometimes
need to verify the behavior of the change. This verification not only
verifies the modified section of the design, but also the entire design. You
can run the Netlist Writer to generate a gate level netlist that allows you
to perform a simulation in a third-party simulation tool such as ModelSim.
The Netlist Writer must be started by either choosing Start, Start EDA
Netlist Writer (Processing menu), or by clicking the Start EDA Netlist
Writer button from the Compiler Tool dialog box (Tools menu). Figure 33
shows the Compiler Tool dialog box.
Start Assembler
Once you have run design changes through the Quartus II Static Timing
Analyzer and a third-party simulator—and are confident that the changes
meet the design’s requirements—you can generate a programming file.
The programming file allows you to test the circuit in a real-life
environment.
The Assembler must be started by choosing Start Assembler (Processing
menu), or by choosing Start Assembler from the Compiler Tool dialog
box (Tools menu). Figure 33 shows the Compiler Tool dialog box.
Conclusion
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
[email protected]
41
As the time to market pressure mounts, it is increasingly important to be
able to produce a fully-functional design in the shortest amount of time.
To address this challenge, Altera developed the Quartus II version 3.0
chip editor. The chip editor enables you to modify the post, place-androute properties of your design. Specifically, you can change certain key
properties of an LE, I/O, and PLL. Most importantly, all changes made via
the chip editor do not require a full re-compilation—eliminating the
lengthy process of RTL modification, re-synthesis, and another place-androute cycle.
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the
stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their
respective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, mask work rights, and copyrights. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera’s standard
warranty, but reserves the right to make changes to any products and services at any time
without notice. Altera assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed
to in writing by Altera Corporation. Altera customers are advised to obtain the latest
version of device specifications before relying on any published information and before
placing orders for products or services.
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AN 310: Using the Quartus II Chip Editor
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