LeonardoSpectrum and
Quartus II LogicLock
Design Flow
September 2002, ver. 2.1
Introduction
Application Note 164
The LogicLockTM block-based design flow enables users to design,
optimize, and lock down a design one section at a time. With the
LogicLock methodology, you can independently create and implement
each logic module into a hierarchical or team-based design. With this
method, you can preserve the performance of each module during system
integration and have more control over placement of your design. To
maximize the benefits of the LogicLock design methodology in the
Altera® Quartus® II software, you can partition a new design into a
hierarchy of netlist files during synthesis in the LeonardoSpectrumTM
software.
The LogicLock design methodology supports CycloneTM , StratixTM ,
APEXTM II, APEX 20KC, APEX 20KE, APEX 20K, MercuryTM (limited
support), and ExcaliburTM devices. This application note describes how to
create and utilize multiple electronic design interchange format (EDIF)
netlist files for a hierarchical and incremental design approach using the
Mentor Graphics® LeonardoSpectrum software.
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Software
Requirements
For more information on LogicLock regions and the LogicLock design
flow, see AN 161: Using the LogicLock Methodology in the Quartus II Design
Software.
This application note assumes that you have installed and licensed the
LeonardoSpectrum software.
You can download and obtain a license for the LeonardoSpectrum -Altera
(Level 1) software from the Altera web site at http://www.altera.com. You
can license the software through a software T-guard fixed license, a
network/server floating license, or a network interface card (NIC) fixed
license. You may also purchase a license directly from Mentor Graphics
and obtain the full (Level 2 or Level 3) version of the software from
http://www.mentor.com.
1
Altera Corporation
AN-164-2.1
The LogicLock design flow was introduced in the
LeonardoSpectrum software version 2002a; this application note
applies to both the Altera and Mentor Graphics-distributed
versions (any differences will be noted). References to the
Quartus II software refer to version 2.1.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
To use the LeonardoSpectrum software, set the LM_LICENSE_FILE
environment variable to the location of the license file.
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Design
Hierarchy
For details on setting up the Altera license, see AN 205: Understanding
Altera Software Licensing.
As a part of your design hierarchy, you can define different modules in
different files and instantiate them in a top-level file. For larger designs,
such as those used for Stratix devices, a group of designers can work on
different modules of a design at the same time. Figure 1 shows an example
of a design hierarchy.
Figure 1. Design Hierarchy
Designer 1
A
B
D
Designer 2
C
E
F
Designer 3
In Figure 1, the top-level design A is assigned to one engineer
(Designer 1), while two engineers work on the lower levels of the design.
Designer 2 works on B and its submodules D and E, while Designer 3
works on C and its submodule F.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
You can treat each module or a group of modules as one block of the
design for incremental synthesis. Each block of submodules will have its
own netlist file after synthesis. A submodule can be a Verilog HDL
module, a VHDL entity, an EDIF netlist file, or any combination of the
three. To combine these submodules into a block for synthesis, they
should form a single tree in the design. For example, you cannot create
one netlist file for the two submodules E and C while A and B are in
different netlists because E and C are in different trees or branches of the
design. You can have individual netlists for A, B, C, and E or one netlist
for the whole tree under the top-level design A.
LogicLock
With a hierarchical approach, the LogicLock design methodology allows
you to individually optimize your block(s) for the Altera device. Using the
LogicLock design methodology, you can place each block’s logic into a
fixed or floating region in an Altera device. You then have the opportunity
to maintain the placement and the performance of your blocks in the
Altera device.
Using the LogicLock Design Flow with LeonardoSpectrum
The LeonardoSpectrum software allows you to create different netlist files
for different sections of a design hierarchy. Different netlist files mean that
each section is independent of the others. When synthesizing the entire
project, only portions of a design that have been updated have to be resynthesized when you compile the design. You can make changes,
optimize and re-synthesize your section of a design without affecting
other sections.
You can place each netlist file into a separate LogicLock region in the
Quartus II software. If a design region changes, only the netlist associated
with the changed region is affected. During place-and-route in the
Quartus II software, you only need to recompile the LogicLock region
associated with the changed netlist file. You may need to remove previous
back-annotated assignments for the modified block because the node
names may be different in the newly synthesized version.
If all the netlists are contained in one Quartus II project, use the LogicLock
flow to back-annotate the logic within the other regions. In this case, when
you recompile with one new EDIF netlist file, the placement and
assignments for unchanged netlist files assigned to different LogicLock
regions are not affected. Therefore, one designer can make changes to a
piece of code that exists in an independent block and not interfere with
another designer’s changes, even if all the blocks are integrated in a toplevel design. With the LogicLock design methodology, separate pieces of
a design can evolve from development to testing without affecting other
areas of a design.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
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For more information on the LogicLock incremental design capabilities,
refer to AN 161: Using the LogicLock Methodology in the Quartus II Design
Software.
Hierarchy & Design Considerations
You must plan your design’s structure and partitioning carefully to use
the LogicLock features effectively. Optimal hierarchical design practices
include partitioning the blocks at functional boundaries, registering the
boundaries of different blocks, minimizing the I/O between each block,
separating timing-critical blocks, and keeping the critical path within one
hierarchical block.
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For more tips on design planning, refer to AN 225: LeonardoSpectrum &
Quartus II Design Methodology.
To ensure the proper functioning of the synthesis tool, you can only apply
the LogicLock option to modules, entities, or netlist files. In addition, each
module or entity should have its own design file. If two different modules
are in the same design file but are defined as being part of different
regions, it is difficult to maintain incremental synthesis since both regions
would have to be recompiled when you change one of the modules or
entities.
If you use boundary tri-states in a lower-level block, the
LeonardoSpectrum software pushes (or “bubbles”) the tri-states through
the hierarchy to the top-level because Altera devices only have tri-state
drivers on output pins (not internally). Because bubbling tri-states
requires optimizing through hierarchies, lower-level tri-states are not
supported with a block-level design methodology. You should use tristate drivers only at the external output pins of the device and at the toplevel block in the hierarchy.
If the hierarchy is flattened during synthesis, logic is optimized across
boundaries, preventing you from making LogicLock assignments to the
flattened blocks. Altera recommends preserving the hierarchy when
compiling the design. In the Optimize command of your script, use
Hierarchy Preserve or in the user interface select Preserve in the
Hierarchy section on the Optimize FlowTab.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
If you are an advanced user and are compiling your design with a script,
you can use an alternative method for preventing optimization across
boundaries. In this case, use the Auto hierarchy setting and set the
auto_dissolve attribute to false on the instances or views that you
want to preserve (i.e., the modules with LogicLock assignments) using the
following syntax:
set_attribute -name auto_dissolve -value false
.work.<block1>.INTERFACE.
This alternative method flattens your design according to the
auto_dissolve limits, but will not optimize across boundaries where
you apply the attribute as described.
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Creating a
Design with
Multiple EDIF
Files
For more details on LeonardoSpectrum attributes and hierarchy levels,
refer to the LeonardoSpectrum on-line documentation by choosing Open
Manuals Bookcase (Help menu).
The first stage of a hierarchical design flow is to generate multiple EDIF
files, enabling you to take advantage of the LogicLock incremental design
flow in the Quartus II software. If the whole design is in one EDIF file,
changes in one block affect other blocks because of possible node name
changes. You can generate multiple EDIF files either by using the
LogicLock option in the LeonardoSpectrum software, or by manually
black boxing each block that you want to be part of a LogicLock region.
Once you have created multiple EDIF files using one of these two
methods, you need to create the appropriate Quartus II project(s) to placeand-route the design.
Generating Multiple EDIF Files Using the LogicLock Option
This section describes how to generate multiple EDIF files using the
LogicLock option in the LeonardoSpectrum software. When synthesizing
a top-level design that includes LogicLock regions, follow these general
steps:
Altera Corporation
1.
Read in the HDL source files.
2.
Add LogicLock constraints.
3.
Optimize and write output netlist files, or Run Flow.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
To set the correct constraints and compile the design, follow these detailed
steps:
1.
Switch to the Advanced FlowTab in the Tools menu instead of the
Quick Setup tab in the LeonardoSpectrum software.
2.
Set the target technology and speed grade for the device on the
Technology FlowTab, as shown in Figure 2.
Figure 2. Technology FlowTab
3.
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Open the input source files on the Input FlowTab, as shown in
Figure 3.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Figure 3. Input FlowTab
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4.
Click Read on the Input FlowTab. This action reads in the source
files but does not begin optimization.
5.
Select the Module PowerTab on the Constraints FlowTab located at
the bottom of the window, as shown in Figure 4.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Figure 4. Constraints FlowTab & Module PowerTab
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6.
Click on a module to be placed in a LogicLock region (Modules
section).
7.
Turn on the LogicLock option.
8.
Type your desired LogicLock region name in the text field under the
LogicLock option. As shown in Figure 4, the u1[taps] module has
been chosen and the LogicLock region will be called taps_region.
9.
Click Apply. Repeat steps 6-9 for any other modules that you want to
place in LogicLock regions.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
1
In some cases, you will be prompted to save your LogicLock
(and other non-global) constraints in a constraints file (.ctr) when
you click anywhere off the Constraints FlowTab. The default
name is <project name>.ctr. This file will be added to your Input
file list, and must be manually included later if you re-create the
project.
The command written into the LeonardoSpectrum Information
or Transcript Window is the tool command language (Tcl)
command that gets written into the CTR file. The format of the
“path” for the module specified in the command should be
work.<module>.INTERFACE. To ensure that you don’t see an
optimized version of the module, do not perform a Run Flow on
the Quick Setup tab prior to setting LogicLock constraints.
Always use the Read command, as described in step 1.
10. Continue making any other settings as required on the Constraints
tab.
11. Select Preserve in the Hierarchy section on the Optimize tab to
ensure that the hierarchy names are not flattened during
optimization, as shown in Figure 5.
Figure 5. Optimize FlowTab
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
12. Continue making any other settings as required on the Optimize tab.
13. Run your synthesis flow using each FlowTab (in the Level 3 version
of the tool), or Click Run Flow (available on each tab in Level 1
Altera versions, or available on the Quick Setup tab in Level 3
versions).
Synthesis creates an EDIF file for each module with a LogicLock
assignment in the Constraints FlowTab. You can now use these files in the
LogicLock incremental design flow in the Quartus II software.
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You may occasionally see multiple EDIF files and LogicLock
commands for the same module. An “unfolded” version of a
module is created when you instantiate a module more than
once and the boundary conditions of the instances are different.
For example, if you apply a constant to one instance of the block,
it might be optimized to eliminate unneeded logic. In this case,
the LeonardoSpectrum software must create a separate module
for each instantiation (unfolding). If this unfolding occurs, you
will see more than one EDIF file, and each EDIF file will have a
LogicLock assignment to the same LogicLock region. When you
import the EDIF files to the Quartus II software, the EDIF files
created from the module are placed in different LogicLock
regions. Any optimizations performed in the Quartus II software
using the LogicLock methodology must be performed separately
for each EDIF netlist.
Creating a Quartus II Project for Multiple EDIF Files Including LogicLock
Regions
The LeonardoSpectrum software creates Tcl files that provide the Quartus
II software with the appropriate LogicLock assignments, creating a region
for each EDIF file along with the information to set up a Quartus II project.
The Tcl file contains the following commands for each LogicLock region.
This example is for module taps where the name taps_region was
typed as the LogicLock region name in the Constraints tab within the
LeonardoSpectrum software, as shown in Figure 4.
project add_assignment {taps} {taps_region} {} {}
{LL_AUTO_SIZE} {ON}
project add_assignment {taps} {taps_region} {} {}
{LL_STATE} {FLOATING}
project add_assignment {taps} {taps_region} {} {}
{LL_MEMBER_OF} {taps_region}
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
These commands will create a LogicLock region with Auto Size and
Floating Origin properties. This flexible LogicLock region allows the
Quartus II Compiler to select the size and location of the region.
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For more information on Tcl commands, refer to AN 195: Scripting with Tcl
in the Quartus II Software.
You can use the following methods to import the EDIF and corresponding
Tcl file into the Quartus II software:
■
Use the Tcl file that is created for each EDIF file by the
LeonardoSpectrum software. This method allows you to generate
multiple Quartus II projects, one for each block in the design. Each
designer in the project can optimize their block separately within the
Quartus II software and back-annotate their blocks. Altera
recommends this method for incremental and hierarchical design
methodology because it allows each block in the design to be treated
separately; each block can be back-annotated and brought into one
top-level project using the LogicLock import function.
or
■
Use the <top-level project>.tcl file that contains the assignments for
all blocks within the project. This method allows the top-level
designer to import all the blocks into one Quartus II project. You can
optimize all modules within the project at once. If additional
optimization is required for individual blocks, each designer can take
their EDIF file and create a separate project at that time. New
assignments would then have to be added to the top-level project
through the LogicLock import function.
In both methods, you can use the steps below to create the Quartus II
project, import the appropriate LogicLock assignments, and compile the
design:
1.
Place the EDIF and Tcl files in the same directory.
2.
Open the Quartus II Tcl Console by choosing Auxiliary Windows
(View menu), as shown in Figure 6.
Figure 6. Opening the Tcl Console Window
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
3.
Type source <path>/<project name>.tcl r. See Figure 7.
Figure 7. Tcl Console Window with Source Command
4.
Open the new project by Choosing Open Project (File menu),
browsing to the project name, and clicking Open.
5.
Choose Start Analysis & Elaboration (Project menu).
6.
Import the assignments by choosing Import LogicLock Regions
(Tools menu). See Figure 8.
Figure 8. Import LogicLock Regions Command
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7.
Check the settings and accept the desired choice (the default is
generally acceptable for your first pass) by clicking OK.
8.
Choose Start Compilation (Processing menu).
For more information on importing LogicLock assignments, refer to AN
161: Using the LogicLock Methodology in the Quartus II Design Software.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Generating Multiple EDIF Files Using Black Boxes
This section describes how to manually generate multiple EDIF files using
a black boxing technique. The following manual flow was supported in
previous versions of the LeonardoSpectrum software. The manual flow is
discussed here because some designers want more control over the project
for each submodule.
To create multiple EDIF files in the LeonardoSpectrum software, create a
separate project for each module and top-level design that you want to
maintain as a separate EDIF file. Implement black-box instantiations of
lower-level modules in your top-level project.
When synthesizing the projects for the lower-level modules and the toplevel design, follow these general guidelines.
For lower-level modules:
■
■
■
■
Turn off Map IO Registers for the target technology on the
Technology FlowTab.
Read the HDL files for the modules.
–
Modules may include black-box instantiations of lower-level
modules that are also maintained as separate EDIF files.
Add constraints.
Turn off Add I/O Pads to optimize the design on the Optimize
FlowTab.
For the top-level design:
■
■
■
Turn on Map IO Registers if you want to implement input and/or
output registers in the I/O elements (IOEs) for the target technology
on the Technology FlowTab.
Read the HDL files for the top-level design.
–
Black-box lower-level modules in the top-level design.
Add constraints (clock settings should be made here).
The sections below describe an example of black-boxing modules using
the files described in Figure 1 on page 2. To create multiple EDIF files:
Altera Corporation
1.
Generate an EDIF file for module C. Use C.v and F.v as the source
files.
2.
Generate an EDIF file for module B. Use B.v, D.v, and E.v as the
source files.
3.
Generate a top-level EDIF file A.v for module A. Ensure that you
black box modules B and C, which were optimized separately in the
previous steps.
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Black Boxing in Verilog HDL
Any design block that is not defined in the project, or included in the list
of files to be read for a project, will be treated as a black box by the
software. In Verilog HDL, you must also provide an empty module
declaration for the module that you will be treating as a black box.
Figure 9 shows an example of the A.v top-level file. If any of your lowerlevel files also contain a black-boxed lower-level file in the next level of
hierarchy, follow the same procedure.
Figure 9. A.v Top-Level File Black-Boxing Example
module A (data_in,clk,e,ld,data_out);
input data_in, clk, e, ld;
output [15:0] data_out;
reg [15:0] cnt_out;
reg [15:0] reg_a_out;
B U1 ( .data_in (data_in),.clk (clk), .e(e), .ld (ld),
.data_out(cnt_out) );
C U2 ( .d(cnt_out), .clk (clk), .e(e), .q (reg_out));
// Any other code in A.v goes here.
endmodule
// Empty Module Declarations of Sub-Blocks B and C follow here.
// These module declarations (including ports) are required for black boxing.
module B (data_in,e,ld,data_out );
input data_in, clk, e, ld;
output [15:0] data_out;
endmodule
module C (d,clk,e,q );
input d, clk, e;
output [15:0] q;
endmodule
1
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Previous versions of the LeonardoSpectrum software required
an attribute statement //exemplar attribute U1 NOOPT
TRUE, which instructs the software to treat the instance U1 as a
black box. This attribute is no longer required, although it is still
supported in the software.
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Black Boxing in VHDL
Any design block that is not defined in the project, or included in the list
of files to be read for a project, will be treated as a black box by the
software. In VHDL, you need a component declaration for the black box
which is normal for any other block in the design.
Figure 10 shows an example of the A.vhd top-level file. If any of your
lower-level files also contain a black-boxed lower-level file in the next
level of hierarchy, follow the same procedure.
Figure 10. A.vhd Top-Level File Black-Boxing Example
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY A IS
PORT ( data_in : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15
);
END A;
ARCHITECTURE a_arch OF A IS
COMPONENT B PORT(
data_in : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
COMPONENT C PORT(
d : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
q : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
-- Other component declarations in A.vhd go here
signal cnt_out : INTEGER RANGE 0 TO 15;
signal reg_a_out : INTEGER RANGE 0 TO 15;
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
BEGIN
CNT : C
PORT MAP (
data_in => data_in,
clk => clk,
e => e,
ld => ld,
data_out => cnt_out
);
REG_A : D
PORT MAP (
d => cnt_out,
clk => clk,
e => e,
q => reg_a_out
);
-- Any other code in A.vhd goes here
END a_arch;
1
Previous versions of the LeonardoSpectrum software required
the attribute statement noopt of C: component is TRUE,
which instructed the software to treat the component C as a black
box. This attribute is no longer required, although it is still
supported in the software.
After you have completed the steps outlined in this section, you will have
different EDIF netlist files for each block of code. These files can now be
used in the LogicLock incremental design methodology in the Quartus II
software.
Creating a Quartus II Project for Multiple EDIF Files
The LeonardoSpectrum software creates a Tcl file for each EDIF file,
providing the Quartus II software with the information to set up a project.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
As in the previous section, there are two different methods for bringing
each EDIF and corresponding Tcl file into the Quartus II software:
■
Use the Tcl file that is created for each EDIF file by the
LeonardoSpectrum software. This method generates multiple
Quartus II projects, one for each block in the design. Each designer in
the project can optimize their block separately within the Quartus II
software and back-annotate their blocks. Designers should create a
LogicLock region for each block; the top-level designer should then
import all the blocks and assignments into the top-level project.
Altera recommends this method for incremental and hierarchical
design methodology because it allows each block in the design to be
treated separately; each block can be back-annotated and brought
into one top-level project.
or
■
f
Use the <top-level project>.tcl file that contains the information to set
up the top-level project. This method allows the top-level designer to
create LogicLock regions for each block and bring all the blocks into
one Quartus II project. Designers can optimize all modules within the
project at once. If additional optimization is required for individual
blocks, each designer can take their EDIF file and create a separate
Quartus II project at that time. New assignments would then have to
be added to the top-level project manually or through the LogicLock
import function.
For more information on importing LogicLock regions, refer to AN 161:
Using the LogicLock Methodology in the Quartus II Design Software.
In both methods, you can use the steps below to create the Quartus II
project and compile the design:
Altera Corporation
1.
Place the EDIF and Tcl files in the same directory.
2.
Open the Quartus II Tcl Console by choosing Auxiliary Windows
(View menu).
3.
Type source <path>/<project name>.tcl r
4.
Open the new project by Choosing Open Project (File menu),
browsing to the project name, and clicking Open.
5.
Create LogicLock assignments using the LogicLock Regions
window (Tools menu).
6.
Choose Start Compilation (Processing menu).
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Incremental
Synthesis Flow
If you make changes to one or more submodules, you can manually create
new projects in the LeonardoSpectrum software to generate a new EDIF
netlist file when there are changes to the source files (this methodology is
not documented here). Alternatively, you can use incremental synthesis to
generate a new netlist for the changed submodule(s). To perform
incremental synthesis in the LeonardoSpectrum software, use the script
described in this section to re-optimize and generate a new EDIF netlist for
only the affected modules using the LeonardoSpectrum top-level project.
This method applies only when you are using the LogicLock option in the
LeonardoSpectrum software.
Modifications Required for the LogicLock_Incremental.tcl Script
File
There are three sets of entries in the file that you must modify before you
can begin incremental synthesis. The variables in the Tcl file are
surrounded by angle brackets (< >).
1.
Add the list of source files that are included in the project. You can
enter the full path to the file or the file name if the files are located in
the working directory.
2.
Indicate which modules in the design have changed. These will be
the EDIF files that are re-generated by the LeonardoSpectrum
software. They are modules that had a LogicLock assignment in the
original compile.
Obtain LeonardoSpectrum’s path for each of these modules by
looking at the CTR file that contains the LogicLock assignments from
the original project. Each LogicLock assignment is applied to a
particular module in the design.
3.
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Enter the target Altera technology (device family) using the
keywords shown in Table 1.
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Table 1. Keywords for Target Altera Technology (Device Family)
Device Family
Keyword
APEX 20K
apex20k (1)
APEX 20KE
apex20ke (1)
APEX 20KC
apex20kc (1)
APEX II
apexii
Excalibur
excalibur_arm
Mercury
mercury
Stratix
stratix
Cyclone
cyclone
Note to Table 1:
(1)
Device keywords in the LeonardoSpectrum software (versions lower than 2002c)
do not include the letter “k” for APEX devices.
Figure 11 shows the LogicLock_Incremental.tcl file for the incremental
synthesis flow. You must modify the Tcl file before you can use it for your
project.
Figure 11. LogicLock_Interface.tcl Script file for Incremental Synthesis
##############################################
#### LogicLock Incremental Synthesis Flow ####
##############################################
## You must indicate which modules have changed (based on the source files that have
## changed) and provide the complete path to each module
## You must also specify the list of design files and the target Altera technology
## being used
# Read the design source files.
read <list of design files separated by spaces (such as block1.v block2.v)>
#
#
#
#
Get the list of modified modules in bottom-up "depth first search" order where
the lower-level blocks are listed first (these should be modules that had LogicLock
assignments and separate EDIF netlist files in the first pass and had their
source code modified)
set list_of_modified_modules {.work.<block2>.INTERFACE .work.<block1>.INTERFACE}
foreach module $list_of_modified_modules {
set err_rc [regexp {\.(.*)\.(.*)\.(.*)} $module unused lib module_name arch]
present_design $module
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AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
# Run optimization preserving hierarchy. You must specify a technology:
# apex20k, apex20ke, apex20kc, excalibur_arm, apexii, mercury, or
# stratix
optimize -ta <technology> -hierarchy preserve
# Ensure that the lower-level module is not optimized again when optimizing
# higher-level modules.
dont_touch $module
}
foreach module $list_of_modified_modules {
set err_rc [regexp {\.(.*)\.(.*)\.(.*)} $module unused lib module_name arch]
present_design $module
undont_touch $module
auto_write $module_name.edf
# Ensure that the lower-level module is not written out in the EDIF file of the
# higher-level module.
noopt $module
}
Running the Tcl Script File in LeonardoSpectrum
Once you have modified the Tcl script as described in the previous
section, you can compile your design using the script.
In the Level 3 version of the software, you can run the script in batch mode
at the command prompt using the following command:
spectrum -file <Tcl_file> r
In all versions of the LeonardoSpectrum software (including the
LeonardoSpectrum-Altera Level 1 version), you can execute the script
from the interface by choosing Run Script (File menu), then browsing to
your Tcl file and clicking Open.
Conclusion
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The LogicLock incremental design flow uses module-based design to help
you preserve performance of modules and have control over placement.
By tagging which modules require separate EDIF files associated with
them, you can make multiple EDIF files for use with the Quartus II
software and the LogicLock block-based design feature from a single
LeonardoSpectrum software project.
Altera Corporation
AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow
Revision
History
The information contained in AN 164: LeonardoSpectrum and Quartus II
LogicLock Design Flow version 2.1 supersedes information published in
previous versions.
Version 2.1
AN 164: LeonardoSpectrum and Quartus II LogicLock Design Flow version 2.1
contains the following changes:
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Updated page 1 to include Cyclone devices.
Updated Table 1 to include Cyclone devices.
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stylized Altera logo, specific device designations, and all other words and logos that are identified as
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