Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 21
Arithmetic: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan berbagai jenis operasi
aritmatika didalam sistem komputer digital
( C4 ) ( No TIK : 10 )
2
Chapter 6.
Arithmetic: I
(OFC5)
3
xi
yi
Carry-in ci
Sumsi
Carry-outci +1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i  yi  ci
ci +1 = yi ci + xi ci + xi yi
Example:
X
7
+Y = +6
Z
13
0
= + 00
1
1
1
1
1
1
1
1
0
0
1
0
1
0
Carry-out
ci+1
xi
yi
si
Carry-in
ci
Legend for stagei
Figure 6.1. Logic specification for a stage of binary addition.
4
n-bit adder
cn
c0
sn -
1
s1
s0
Figure 6.3. Binary addition-subtraction logic netw
ork.
5
x15-12
c16
y15-12
4-bit adder
x11-8
c12
G3I
P3I
y11-8
4-bit adder
s15-12
x7-4
c8
G2I
P2I
y7-4
4-bit adder
s11-8
x3-0
G1I
P1I
y3-0
c4
4-bit adder
s7-4
.
c0
s3-0
G0I
P0I
Carry -lookahead logic
G0II
P0II
Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders (see b).
Figure 6.4
6

Sign extension is
shown in blue
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
0
0
1
( - 13)
( + 11)
( - 143)
Figure 6.8. Sign extension of negative multiplicand.
7
0
0
0
1 0 1 1 0
0 +1 +1 + 1+1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0 1
0 +1
0
0
1
0
1 0
0 -1
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
2's complement of
the multiplicand
Figure 6.9. Normal and Booth multiplication schemes.
8
0
0
1
0
0 +1 -1 +1
1
1
0 - 1
0
0
1
1
1
0
1
0
0 +1
0
0 - 1 +1 - 1 + 1
1
1
0
0
0 - 1
0
0
Figure 6.10. Booth recoding of a multiplier.
9
0 1 1 0 1
 1 1 0 1 0
( + 13)
(- 6)
0 1 1 0 1
0 - 1 +1 - 1 0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0 0 0 0
0 1 1
0 1
1
1 1 1 0 1 1 0 0 1 0
( - 78)
Figure 6.11. Booth multiplication with a negative multiplier.
10
Multiplier
Version of multiplicand
selected by biti
Bit i
Bit i -1
0
0
0M
0
1
+1M
1
0
1M
1
1
0M
Figure 6.12. Booth multiplier recoding table.
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Worst-case
multiplier
+1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
Ordinary
multiplier
0 -1 0
0 +1 - 1 +1
0 - 1 +1
0
0
0 -1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0 +1
0
0
0
0 -1
0
0
0 +1
0
0 -1
Good
multiplier
Figure 6.13. Booth recoded multipliers.
12
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 22
Arithmetic: II
13
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan berbagai jenis operasi
aritmatika didalam sistem komputer digital
( C4 ) ( No TIK : 10 )
14
Chapter 6.
Arithmetic: II
(OFC6)
15
0
m3q0
m3q1
FA
m3q2
FA
m3q3
FA
p7
p6
FA
m2q3
FA
p5
p4
m1q0
m1q1
m0q0
m0q1
FA
m1q2
FA
0
m0q2
FA
m1q3
FA
m2q0
m2q1
FA
m2q2
FA
0
m0q3
FA
p3
0
p2
p1
p0
(a) Ripple-carry array (Figure 6.6 structure)
16
0
m3q0
m2q2
FA
FA
p7
p6
m2q0
m2q1
m3q1
m3q2
m2q3
m3q3
FA
FA
FA
FA
FA
p5
p4
m0q2
FA
m0q3
FA
m1q0
m0q1
m1q1
m1q2
FA
m1q3
p3
FA
m0q0
0
0
FA
0
p2
p1
p0
(b) Carry -sav e array
Figure 6.16. Ripple-carry and carry-save arrays for the
multiplication operationx M
Q = P for 4-bit operands.
Figure 6.16. Ripple-carry and carry-save arrays for the multiplication operation M  Q = P for 4-bit operands.
17
1
0
1
1
0
1
(45)
M
1
1
1
1
1
1
(63)
Q
1
0
1
1
0
1
A
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
0
0
X
1
B
C
D
E
F
1
0
0
1
1
(2,835)
Product
Figure 6.17. A multiplication example used to illustrate carry-save addition as shown in Figure 6.18.
18
Figure 6.19. Schematic representation of the carry-save
addition operations in Figure 6.18.
Figure 6.19. Schematic representation of the carry-save addition operations in Figure 6.18.
19
13
21
274
26
14
13
1
10101
1101 100010010
1101
10000
1101
1110
1101
1
Figure 6.20. Longhand division examples.
20
Shift left
an
an - 1
a0
q
q
n- 1
A
0
Dividend Q
Quotient
setting
Add/Subtract
n +1-bit
adder
Control
sequencer
0
mn - 1
m0
Divisor M
Figure 6.21. Circuit arrangement for binary division.
21
excess-127 exponent
0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 ...
(There is no implicit 1 to the left of the binary point.)
Value represented= + 0.0010110  29
(a) Unnormalized value
0 1 0 0 0 0 1 0 1 0 1 1 0 ...
6
Value represented= + 1.0110  2
(b) Normalized version
Figure 6.25. Floating-point normalization in IEEE single-precision format.
22
Representation
Examples
Sign and magnitude
+526
526
+70
70
9's complement
0526
9473
0070
9929
10's complement
0526
9474
0070
9930
Figure P6.1. Signed numbers in base 10 used in Problem 6.3.
23
12 bits
1 bit for sign of number
0 signifies+
1 signifies-
5 bits
excess-15
exponent
6 bits
fractional
mantissa
Figure P6.2. Floating-point format used in Problem 6.25.
24
(3)
+( - 5)
-2
0
+ 0 1
1
1
0
0
0
1
1
1
1
1
0
1
0
0
1
0
0
1
0
(6)
+ ( - 3)
3
0 1
+ 1 101
0 0
0 0
1
1
0
0
0
0
1
0
1
1
1
0
Figure P6.3. 1's-complement addition used in Problem 6.36.
25