Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 17
Internal Memory: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menghubungkan konsep internal memory
dalam mendesain sistem komputer ( C4 )
( No TIK : 8 )
2
Chapter 5.
Internal Memory: I
3
Processor
k-bit
address bus
Memory
MAR
n-bit
data bus
MDR
Up to 2k addressable
locations
Word length =n bits
Control lines
( R / W , MFC, etc.)
Figure 5.1. Connection of the memory to the processor.
4
b7
b7
b1
b1
b0
b0
W0
•
•
•
FF
A0
A2
•
•
•
A1
W1
FF
Address
decoder
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Memory
cells
A3
•
•
•
W15
Sense / Write
circuit
Data input/output lines: b7
Sense / Write
circuit
b1
Sense / Write
circuit
R/W
CS
b0
Figure 5.2. Organization of bit cells in a memory chip.
5
5-bit row
address
W0
W1
5-bit
decoder
32  32
memory cell
array
W31
10-bit
address
Sense/Write
circuitry
32-to-1
output multiplexer
and
input demultiplexer
R/ W
CS
5-bit column
address
Data
input/output
Figure 5.3. Organization of a 1K  1 memory chip.
6
b
b
T1
X
Y
T2
Word line
Bit lines
Figure 5.4. A static RAM cell.
7
Word line
Bit lines
Figure 5.5. An example of a CMOS memory cell.
8
Bit line
Word line
T
C
Figure 5.6. A single-transistor dynamic memory cell
9
RA S
Row
address
latch
A20 - 9  A 8 -
Row
decoder
4096 (512  8)
cell array
Sense / Write
circuits
0
Column
address
latch
CA S
CS
R/ W
Column
decoder
D7
D0
Figure 5.7. Internal organization of a 2M  8 dynamic memory chip.
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Refresh
counter
Row
address
latch
Row
decoder
Cell array
Column
address
counter
Column
decoder
Read/Write
circuits & latches
Row/Column
address
Clock
RA S
CA S
R/ W
Mode register
and
timing control
Data input
register
Data output
register
CS
Data
Figure 5.8. Synchronous DRAM.
11
Clock
R/ W
RAS
CAS
Address
Data
Row
Col
D0
D1
D2
D3
Figure 5.9. Burst read of length 4 in an SDRAM.
12
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 18
Internal Memory: II
13
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menghubungkan konsep internal memory
dalam mendesain sistem komputer ( C4 )
( No TIK : 8 )
14
Chapter 5.
Internal Memory: II
15
21-bit
addresses
19-bit internal chip address
A0
A1
A19
A20
2-bit
decoder
512K  8
memory chip
D31-24
D23-16
D 15-8
D7-0
512K  8 memory chip
19-bit
address
8-bit data
input/output
Chip select
Figure 5.10. Organization of a 2M  32 memory module using 512K  8 static memory chips.
16
Row/Column
address
Address
RAS
R/ W
Request
Memory
controller
Processor
CAS
R/ W
CS
Clock
Memory
Clock
Data
Figure 5.11. Use of a memory controller.
17
Bit line
Word line
T
P
Not connected to store a 1
Connected to store a 0
Figure 5.12. A ROM cell.
18
Processor
Registers
Increasing
size
Primary L1
cache
Increasing Increasing
speed cost per bit
SecondaryL2
cache
Main
memory
Magnetic disk
secondary
memory
19
Figure 5.13. Memory hierarchy.
Processor
Cache
Main
memory
Figure 5.14. Use of a cache memory.
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Main
memory
Block 0
Block 1
tag
Cache
Block 127
Block 0
Block 128
tag
Block 1
Block 129
tag
Block 127
Block 255
Block 256
Block 257
Block 4095
T ag
5
Block
7
Word
4
Main memory address
Figure 5.15. Direct-mapped cache.
21
Main
memory
Block 0
Block 1
Cache
tag
Block 0
tag
Block 1
Block
tag
i
Block 127
Block 4095
T ag
12
W ord
4
Main memory address
Figure 5.16. Associative-mapped cache.
22
Main
memory
Block 0
Block 1
Cache
tag
Set 0
tag
tag
Set 1
tag
tag
Set 63
tag
Block 0
Block 63
Block 1
Block 64
Block 2
Block 65
Block 3
Block 127
Block 126
Block 128
Block 127
Block 129
Block 4095
T ag
6
Set
6
W ord
4
Main memory address
Figure 5.17. Set-associative-mapped cache with two blocks per set.
23
Memory address
Contents
(7A00)
0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0
A(0,0)
(7A01)
0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1
A(1,0)
(7A02)
0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0
A(2,0)
(7A03)
0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1
A(3,0)
(7A04)
0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0
A(0,1)
(7A24)
0 1 1 1 1 0 1 0 0 0 1 0 0 1 0 0
A(0,9)
(7A25)
0 1 1 1 1 0 1 0 0 0 1 0 0 1 0 1
A(1,9)
(7A26)
0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0
A(2,9)
(7A27)
0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1
A(3,9)
Tag for direct mapped
Tag for set-associati
ve
Tag for associati
ve
Figure 5.18. An array stored in the main memory
.
24