Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 25
Pipelining: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Mengkombinasikan Metode Pipeline
dalam mendesain sistem komputer ( C5 )
( No TIK : 12 )
2
Chapter 8.
Pipelining: I
3
I1
I2
F1
E1
F2
T ime
I3
E2
F3
E3
(a) Sequential execution
Interstage buffer
B1
Instruction
fetch
unit
Ex ecution
unit
(b) Hardware organization
Clock cycle
1
2
F1
E1
3
4
T ime
Instruction
I1
I2
F2
I3
E2
F3
E3
(c) Pipelined execution
Figure 8.1. Basic idea of instruction pipelining.
4
LOOP
100
104
Move
Move
N,R1
#NUM1,R2
108
112
116
Clear
Add
Add
R0
(R2),R0
#4,R2
120
124
128
132
Decrement
Branch>0
Move
R1
LOOP
R0,SUM
SUM
N
200
204
NUM1
NUM2
208
212
NUM n
604
100
5
I2
F2
I3
D2
E2
W2
F3
D3
E3
W3
F4
D4
E4
I4
W4
(a) Instruction execution div ided into f our steps
Interstageuff
b ers
D : Decode
instruction
and f etch
operands
F : Fetch
instruction
B1
E: Execute
operation
B2
W : Write
results
B3
(b) Hardware organization
Fi gure 8.2. A 4-stage pi pel i ne.
6
Clock c
y cle
1
2
3
F1
D1
E1
4
5
7
8
D2
E2
W2
F3
6
D3
E3
Time
9
Instruction
I1
I2
W1
F2
I3
W3
(a) Instruction execution steps in successiv e clock cy cles
Clock c
y cle
1
2
3
4
5
6
7
8
Time
9
Stage
F: Fetch
D: Decode
E: Execute
W: Write
F1
F2
F2
D1
idle
idle
idle
D2
E1
idle
idle
idle
E2
E3
W1
F2
idle
F2
idle
F3
idle
W2
D3
W3
(b) Function perf ormed by each processor stage in successiv e clock cy cles
Fi gure 8.4. Pi pel i ne stal l caused by a cache m i ss i n F2.
7
Register
f ile
ALU
RSLT
Destination
(a) Datapath
SRC1,SRC2
RSLT
E: Execute
(ALU)
W: Write
(Register f ile)
Forwarding path
(b) Position of the source and result registers in the processor pipeline
Fi gure 8.7. Operand forw
a rdi ng i n a pi pel i ned processor
.
8
Fk +1
I k +1
Dk +1
Ek +1
(a) Branch address com puted iecute
n Ex stage
Time
Clock c
y cle
I1
I 2 (Branch)
I3
Ik
I k +1
1
2
3
4
F1
D1
E1
W1
F2
D2
F3
5
6
7
X
Fk
Dk
Ek
Wk
Fk +1
D k +1
Ek +1
(b) Branch address com puted i n Decode stage
Fi gure 8.9. Branch ti m i ng.
9
I3
I4
I5
F3
D3
E3
F4
D4
W3
E4
W4
F5
D5
E5
Figure 8.3. Effect of an xecution
e
operation taking more than one ycle.
clock c
10
I3
I4
I5
F3
D3
E3
F4
D4
W3
E4
F5
D5
Figure 8.5. Effect of a Load instruction on pipeline timing.
11
I 2 (Add)
I3
I4
F2
D2
F3
D2A
E2
W2
D3
E3
W3
F4
D4
E4
W4
Figure 8.6. Pipeline stalled by data dependenc
y between 2Dand W1.
Figure 8.6. Pipeline stalled by data dependency between D2 and W1.
12
Ik
I k+1
Fk
Ek
Fk+1
Ek+1
Figure 8.8. An idle yccle caused by a branch instruction.
13
Instruction fetch unit
Instruction queue
F : Fetch
instruction
D : Dispatch/
Decode
unit
E : Execute
instruction
W : Write
results
Figure 8.10. Use of an instruction queue in the hardware organization of Figure 8.2b.
14
Clock cycle
1
2
3
4
5
6
7
8
9
10
Queue length
1
1
1
1
2
3
2
1
1
1
I1
F1
D1
E1
E1
E1
W1
F2
D2
E2
W2
F3
D3
E3
W3
D4
E4
W4
Dk
Ek
I2
I3
F4
I4
I 5 (Branch)
I6
Ik
I k+1
F5
Time
D5
F6
X
Fk
Fk+1
Wk
D k+1 Ek+1
Figure 8.11. Branch timing in the presence of an instruction queue.
Branch target address is computed in the D stage.
15
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 26
Pipelining: II
16
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Mengkombinasikan Metode Pipeline
dalam mendesain sistem komputer ( C5 )
( No TIK : 12 )
17
Chapter 8.
Pipelining: II
18
Pipelining
•
•
•
•
•
•
Fetch instruction
Decode instruction
Calculate operands (i.e. EAs)
Fetch operands
Execute instructions
Write result
• Overlap these operations
19
Two Stage Instruction Pipeline
20
Timing of Pipeline
21
Branch in a Pipeline
22
Six Stage
Instruction Pipeline
23
Alternative
Pipeline
Depiction
24
Speedup Factors with
Instruction Pipelining
25