Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 9
Mesin ARM: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan implementasi instruksi
mesin untuk Arsitektur Komputer ARM
( C4 ) ( No TIK : 4 )
2
Chapter 3.
ARM
Instruction Set: I
3
LOOP
LDR
LDR
MOV
LDR
ADD
SUBS
BGT
STR
R1,N
R2,POINTER
R0,#0
R3,[R2],#4
R0,R0,R3
R1,R1,#1
LOOP
R0,SUM
Load count into R1.
Load addressNUM1 into R2.
Clear accumulator R0.
Load next number into R3.
Add numberinto R0.
Decremen
t loop counter R1.
Branch back if not done.
Store sum.
Figure 3.7. An ARM program for adding numbers.
4
Memory
address
label
Operation
Addressing
or data
information
Assembler directives
AREA
ENTRY
CODE
Statementsthat
generate
machine
instructions
LDR
LDR
MOV
LDR
ADD
SUBS
BGT
STR
R1,N
R2,POINTER
R0,#0
R3,[R2],#4
R0,R0,R3
R1,R1,#1
LOOP
R0,SUM
AREA
DCD
DCD
DCD
DCD
END
DATA
0
5
NUM1
3,  17,27, 12,322
LOOP
Assembler directives
SUM
N
POINTER
NUM1
Figure 3.8. ARM assembly language source program for the program in Figure 3.7.
5
N - Negativ e
Z - Zero
Processor mode bits
Interrupt disable bits
C - Carry
V- Ov erf low
Condition code f lags
Figure 3.1. ARM register structure.
6
31
28 27
Condition
20 19 16 15 12 11
OP code
Rn
Rd
4 3
Other inf o
0
Rm
Figure 3.2. ARM instruction format.
7
LDR
LDRB
LDRB
AND
ORR
STRB
R0,POINTER
R1,[R0]
R2,[R0,#1]
R2,R2,#&F
R2,R2,R1,LSL#4
R2,PACKED
Load addressLOC into R0.
Load ASCI I characters
into R1 and R2.
Clear high-order28 bits of R2.
Or [R1] shifted left into [R2].
Storepacked BCD digits
into PACKED.
Figure 3.5. An ARM program for packing two 4-bit decimal digits into a byte.
8
(b) Determination of a branch target address
Figure 3.6.
ARM branch instructions.
9
10
11
12
13
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 10
Mesin ARM: II
14
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan implementasi instruksi
mesin untuk Arsitektur Komputer ARM
( C4 ) ( No TIK : 4 )
15
Chapter 3.
ARM
Instruction Set: II
16
READ
ECHO
LDR
TST
BEQ
LDRB
STRB
LDR
TST
BEQ
STRB
TEQ
BNE
R3,[R1]
R3,#8
READ
R3,[R1,#4]
R3,[R0],#1
R4,[R2]
R4,#8
ECHO
R3,[R2,#4]
R3,#CR
READ
Load [INSTATUS] and
wait for character.
Read the character and
store it in memory.
Load [OUTSTATUS] and
wait for display
to be ready.
Sendcharacterto display.
If not carriagereturn,
read morecharacters.
Figure 3.9. An ARM program that reads a line of characters and displays it.
17
Calling program
LDR
LDR
BL
STR
..
.
R1,N
R2,POINTER
LISTADD
R0,SUM
STMFD
R13!,{ R3,R14}
MOV
LDR
ADD
SUBS
BGT
LDMFD
R0,#0
R3,[R2],#4
R0,R0,R3
R1,R1,#1
LOOP
R13!,{ R3,R15}
Subroutine
LISTADD
LOOP
Save R3and return addressin R14 on
stack, using R13 as the stack pointer.
RestoreR3 and load return address
into PC (R15).
Figure 3.10. Program of Figure 3.7 written as an ARM subroutine; parameters passed through registers.
18
LOOP
ADR
ADR
LDR
MOV
LDR
LDR
MLA
R1,AVEC
R2,BVEC
R3,N
R0,#0
R4,[R1],#4
R5,[R2],#4
R0,R4,R5,R0
SUBS
BNE
STR
R3,R3,#1
LOOP
R0,DOTPROD
R1 pointsto vectorA.
R2 points to vector B.
R3 is theloop counter.
R0 accumulatesthedot product.
Load A component.
Load B component.
Multiply components and
accumulateinto R0.
Decrementthecounter.
Branchback if not done.
Storedot product.
Figure 3.14. An ARM dot-product program.
19
Subroutine
INSERTION
LOOP
CMP
MOVEQ
MOVEQ
LDR
LDR
CMP
STRGT
MOV GT
MOV GT
MOV
LDR
CMP
STREQ
MOVEQ
LDR
CMP
MOVLT
BLT
STR
STR
MOV
RHEAD,#0
RHEAD,RNEWREC
PC,R14
R0,[RHEAD]
R1,[RNEWREC]
R0,R1
RHEAD,[RNEWREC,#4]
RHEAD,RNEWREC
PC,R14
RCURRENT,RHEAD
RNEXT,[RCURRENT,#4]
RNEXT,#0
RNEWREC,[RCURRENT,#4]
PC,R14
R0,[RNEXT]
R0,R1
RCURRENT,RNEXT
LOOP
RNEXT,[RNEWREC,#4]
RNEWREC,[RCURRENT,#4]
PC,R14
Check if list empty.
If empty, insert new
recordas head.
If not empty , check if
newrecord becomes
newhead,and
insert if yes.
If newrecord goes after
current head,
find where.
New record becomesnew tail.
Go further?
Yes,then loop back.
Otherwise,insert newrecord
betweencurrent and
next records.
Figure 3.16. An ARM subroutinefor inserting a newrecordinto a linked list.
20
Subroutine
DELETION
LOOP
LDR
CMP
LDREQ
MOVEQ
MOV
LDR
LDR
CMP
LDREQ
STREQ
MOVEQ
MOV
B
R0,[RHEAD]
R0,RIDNUM
RHEAD,[RHEAD,#4]
PC,R14
RCURRENT,RHEAD
RNEXT,[RCURRENT,#4]
R0,[RNEXT]
R0,RIDNUM
R0,[RNEXT,#4]
R0,[RCURRENT,#4]
PC,R14
RCURRENT,RNEXT
LOOP
Check if record to be
deletedis thehead.
If yes,delete
and return.
Otherwise,continue search.
Is nextrecordtheone
to be deleted?
If yes,delete
andreturn.
Otherwise,loop back
to continuesearch.
Figure 3.17. An ARM subroutine for deleting a record from a linked list.
21
T ABLE 3.1
ARM index addressing modes
Name
Assembler
W ith immediate of fset:
Pre-inde xed
Pre-inde xed
with writeback
[R n , #of fset]
EA = [R n ] + of fset
[R n , #of fset]!
EA = [R n ] + of fset;
R n  [R n ] + of fset
Post-inde x ed
[R n ], #of fset
EA = [R n ];
R n  [R n ] + of fset
W ith of fset magnitude
Pre-inde xed
syntax
in R m :
[R n ,  R m , shift]
Addr essing function
EA = [R n ]  [R m ] shifted
Pre-inde xed
with writeback
[R n ,  R m , shift]!
EA = [R n ]  [R m ] shifted;
R n  [R n ]  [R m ] shifted
Post-inde x ed
[R n ],  R m , shift
EA = [R n ];
R n  [R n ] 
Location
EA = Location
= [PC] + of fset
Relati ve
(Pre-inde xed with
immediate of fset)
[R m ] shifted
EA = ef fecti ve address
of fset = a signed number contained in the instruction
shift = direction #inte ger
where direction is LSL for left shift or LSR for right shift, and
inte ger is a 5-bit unsigned number specifying
the shift amount
 R m = the of fset magnitude in register R m can be added to or subtracted
contents of base re gister R n
from the
22
Figure B.6. ARM block transfer instructions.
23
31
28
23
Condition 1 0 1 K
0
Of f set
K=0 :Branch (B)
K=1 :Branch with Link (BL); store return address in register R14
Figure B.7. ARM Branch and Branch with Link instructions.
24
T ABLE B.1
Condition field encoding in ARM instructions
Condition
field
b31 . . . b28
Condition
suffix
Name
Condition code
test
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
EQ
NE
CS/HS
CC/LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Equal (zero)
Not equal (nonzero)
Carry set/Unsignedhigheror same
Carry clear/Unsignedlower
Min us (negative)
Plus (positive or zero)
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Signed greaterthan or equal
Signed less than
Signed greater than
Signed less than or equal
Alw ays
Not used
Z= 1
Z= 0
C= 1
C= 0
N = 1
N = 0
V = 1
V = 0
C Z = 0
C Z = 1
NV = 0
NV = 1
Z  (N  V) = 0
Z  (N  V) = 1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
25
TABLE B.4
ARM instructions for single word or byte transfer from/to memory
Mnemonic
(Name)
Instruction
bits
Operation
performed
B L
LDR
(Load word)
0 1
Rd  [EA]
LDRB
(Load byte)
1 1
Rd  [EA]
STR
(Store word)
0 0
EA  [Rd]
STRB
(Store byte)
1 0
EA  [Rd]
26