Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 11
Mesin Motorola 68000: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan implementasi instruksi
mesin untuk Arsitektur Komputer Motorola
( C4 ) ( No TIK : 5 )
2
Chapter 3.
Motorola
Instruction Set: I
3
LOOP
MOVE.L
N,D1
MOVEA.L
#NUM1,A2
CLR.L
ADD.W
SUBQ.L
BGT
MOVE.L
D0
(A2)+,D0
#1,D1
LOOP
D0,SUM
N contains n, the number of entries
to be added, and D1 is usedas
a counter that determineshow
many times to executethe loop.
A2 is usedas a pointer to the list entries.
It is initialized to NUM1, the address
of the first entry .
D0 is used to accumulate the sum.
Successiv
e numbers are added in D0.
Decrement the counter.
If [D1] 0, executethe loop again.
Store the sum in SUM.
Figure 3.25. A 68000 program for the addition program in Figure 2.16.
4
LOOP
MOVE.L
SUBQ.L
MOVEA.L
CLR.L
ADD.W
DBRA
MOVE.L
N,D1
#1,D1
#NUM1,A2
D0
(A2)+,D0
D1,LOOP
D0,SUM
Put n – 1 into the
counter register D1.
Loop back until [D1]= –1.
Figure 3.26. An alternative 68000 program for the program in Figure 3.25.
5
24
2 - 2
24
by te 2 - 2
24
by te 2 - 1
Figure 3.19. Map of addressable locations in the 68000.
6
1000
OP-code word
1002
Extension word
6
A1
100 = of f set
1102
1104
6 = index
1106
1108
Array
Operand
Figure 3.20. An example of 68000 full relative mode for the instruction ADD 100(PC,A1),D0.
7
Memory
address
label
Assemblerdirectives
C
A
B
Statemen
ts that
generatemachine
instructions
Assemblerdirective
Operation
EQU
ORG
DC.W
DC.W
ORG
MOVE
ADD
MOVE
END
Addressing
or data
information
$202200
$201150
639
– 215
$201200
A,D0
B,D0
D0,C
Figure 3.23. 68000 assembly language representation for the routine in Figure 3.22.
8
Appearance of loop in memory
Assembly language
v ersion of loop
[PC] = 1006 when branch address is computed
Branch address
= 1006- 6 = 1000
(b) Example of using a branch instruction in the loop of Figure 2.16
Figure 3.24.
68000 short-offset branch instructions.
9
TABLE C.1
Address field encoding for 68000
Addressfield
Mode
5
4
Register
3
2
1
0
Addressingmode
Mode
field
Registerfield
Data register direct
Addressregister direct
Addressregister indirect
Autoincrement
Autodecrement
Indexedbasic
Indexedfull
Absolute short
Absolute long
Relativebasic
Relative full
Immediateor statusregister
000
001
010
011
100
101
110
111
111
111
111
111
Register number
Register number
Register number
Register number
Register number
Register number
Register number
000
001
010
011
100
10
TABLE C.2
Differences from Motorola terminology
Terminologyused
in this book
Motorola terminology
Autoincrement
Auto decrement
Indexed basic
Indexed full
Relativebasic
Relativefull
Address register indirect with postincrement
Address register indirect with predecrement
Address register indirect with displacement
Address register indirect with index
Program counter with displacement
Program counter with index
11
TABLE C.3
Notation for Table C.4
Symbol
Meaning
s
d
An
Dn
Xn
PC
SP
SR
CCR
AAA
DDD
rrr
RRR
eeeeee
EEEEEE
MMM
CCCC
P. . . P
Q.. . Q
SS
Sourceoperand
Destination operand
Addressregister n
Data register n
An addressor data register, usedas an index register
Program counter
Stack pointer
Statusregister
Condition code flags in SR
Addressregister number
Data register number
Sourceregister number
Destinationregisternumber
Effective addressof the sourceoperand
Effective addressof the destinationoperand
Effective addressmode of destination
Specification for a condition code test
Displacement
Quick immediatedata
Size: 00  byte, 01  word, 10  long word (for most instructions)
01  byte, 11  word, 10  long word (for MOVE and
MOVEA instructions)
Trap vector number
Conditioncode flag state is undefined(meaningless)
Indexed basic addressingmode
Indexed full addressingmode
Relative basic addressingmode
Relative full addressingmode
VVVV
u
d(An)
d(An,Xi)
d(PC)
d(PC,Xi)
12
TABLE C.5
68000 branch instructions
Mnemonic
(Name)
Displacement
size
OP code
Operation
performed
BRA
(Branch
always)
8
0100 0000 PPPP PPPP
PC  [PC] + disp
16
011000000000 0000
PPPP PPPP PPPP PPPP
8
0110 CCCC PPPP PPPP
If cc is true, then
16
0110CCCC 0000 0000
PPPP PPPP PPPP PPPP
PC  [PC] + disp
8
0110 0001 PPPPPPPP
16
011000010000 0000
PPPP PPPP PPPP PPPP
SP  [SP] – 4;
[SP]  [PC];
PC  [PC] + disp
DBcc
(Decrement
and branch
conditionally)
16
0101CCCC 1100 1DDD
PPPP PPPP PPPP PPPP
DBRA
(Decrement
and branch)
The assem
bler interprets this instruction as DBF
(seethe DBcc entry).
Bcc
(Branch
conditionally)
BSR
(Branch to
subroutine)
If cc is false, then
Dn  [Dn] – 1;
If [Dn]  – 1, then
PC  [PC] + disp
13
T ABLE C.6
Condition codes for Bcc, DBcc and Scc instructions
Machine
code
CCCC
Condition
suffix
cc
Name
Test condition
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
T
F
HI
LS
CC
CS
NE
EQ
VC
VS
PL
MI
GE
LT
GT
LE
True
False
High
Low or same
Carryclear
Carry set
Not equal
Equal
Overflow clear
Overflow set
Plus
Minus
Greateror equal
Lessthan
Greaterthan
Lessor equal
Always true
Always false
C Z= 0
CZ= 1
C= 0
C= 1
Z = 0
Z = 1
V = 0
V = 1
N= 0
N= 1
N V = 0
N V = 1
Z  (N  V) = 0
Z  (N  V) = 1
T and F suffices cannot be usedin the Bcc instruction
14
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 12
Mesin Motorola 68000: II
15
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan implementasi instruksi
mesin untuk Arsitektur Komputer Motorola
( C4 ) ( No TIK : 5 )
16
Chapter 3.
Motorola
Instruction Set: II
17
MOVEA.L
#LOC,A1
READ
BTST.W
BEQ
MOVE.B
#3,INSTATUS
READ
DATAIN,(A1)
ECHO
BTST.W
BEQ
MOVE.B
#3,OUTSTATUS
ECHO
(A1),DATAOUT
CMPI.B
#CR,(A1)+
BNE
READ
Initialize pointer registerA1 to contain the
addressof the first location in memory
where the charactersare to be stored.
Wait for a characterto be entered
in the keyboard buffer DATAIN
Transferthecharacterfrom DATAIN into
the memory (this clearsSIN to 0).
Wait for thedisplay to becomeready.
Move the characterjust read to the output
buffer register (this clearsSOUT to 0).
Check if the character just read is CR
(carriagereturn). If it is not CR, then
branch back and read anothercharacter.
Also, increment thepointer to storethe
next character.
Figure 3.27. A 68000 program that reads a line of characters and displays it.
18
Calling program
Subroutin
e
LISTADD
LOOP
MOVEA.L
#NUM1,A2
MOVE.L
N,D1
BSR
LISTADD
MOVE.L
D0,SUM
next instruction
..
.
Put the addressNUM1 in A2.
Put the number of entries n in D1.
Call subroutine LIST ADD.
Store the sum in SUM.
SUBQ.L
CLR.L
ADD.W
DBRA
RTS
Adjust count to n
#1,D1
D0
(A2)+,D0
D1,LOOP
– 1.
Accumulatesum in D0.
Figure 3.28. Program of Figure 3.26 written as a 68000 subroutine; parameters passed through registers.
19
MOVEA.L
MOVE.B
LSL.B
MOVE.B
ANDI.B
OR.B
MOVE.B
#LOC,A0
(A0)+,D0
#4,D0
(A0),D1
#$F,D1
D0,D1
D1,PACKED
A0 points to data.
Load first byte into D0.
Shift left by 4 bit positions.
Load secondbyte into D1.
Clear high-order 4 bits to zero.
Concatenatethe digits.
Store the result.
Figure 3.32. Use of 68000 logic instructions in packing BCD digits.
20
LOOP
MOVEA.L
MOVEA.L
MOVE
SUBQ
CLR
MOVE
MULS
ADD
DBRA
MOVE
#AVEC,A1
#BVEC,A2
N,D0
#1,D0
D1
(A1)+,D2
(A2)+,D2
D2,D1
D0,LOOP
D1,DOTPROD
Addressof first vector.
Addressof secondvector.
Number of elements.
Adjust count to useDBRA.
Use D1 as accumulator.
Get element from vector A.
Multiply element from vector B.
Accumulate product.
Figure 3.33. A 68000 program for computing the dot product of two vectors.
21
Subroutine
INSERTION
HEAD
SEARCH
LOOP
INSERT
TAIL
CMPA.L
BGT
MOVEA.L
RTS
CMP.L
BGT
MOVE.L
MOVEA.L
RTS
MOVEA.L
MOVEA.L
CMPA.L
BEQ
CMP.L
BLT
MOVEA.L
BRA
MOVE.L
MOVE.L
RTS
#0,A0
HEAD
A1,A0
A0 is RHEAD.
(A0),(A1)
SEARCH
A0,4(A1)
A1,A0
CompareID of new record to head.
A0,A2
4(A2),A3
#0,A3
TAIL
(A3),(A1)
INSERT
A3,A2
LOOP
A2,4(A1)
A1,4(A2)
A2 is RCURRENT.
A3 is RNEXT.
A1 is RNEWREC.
New record becomeshead.
Go to next record.
Figure 3.35. A 68000 subroutine to insert a record in a linked list.
22
Subroutine
DELETION
SEARCH
LOOP
DELETE
CMP.L
BGT
MOVEA.L
RTS
MOVEA.L
MOVEA.L
CMP.L
BEQ
MOVEA.L
BRA
MOVE.L
MOVE.L
RTS
(A0),D1
SEARCH
4(A0),A0
D1 is RIDNUM.
A0,A2
4(A2),A3
(A3),D1
DELETE
A3,A2
LOOP
4(A3),D2
D2,4(A2)
A2 is RCURRENT.
A3 is RNEXT.
Delete headrecord.
D2 is RTEMP.
Figure 3.36. A 68000 subroutine to delete a record from a linked list.
23
T able 3.2
68000 addressing modes
Assem bler syn tax
Name
Immediate
Absolute Short
Absolute Long
Register
#V alue
V alue
V alue
Rn
Register Indirect
Autoincremen t
(An)
(An)+
Auto decremen t
– (An)
Indexed basic
Indexed full
Relativ e basic
Relativ e full
EA
V alue
BV alue
WV alue
An
Rn
S
=
=
=
=
=
=
=
WV alue(An)
BV alue(An,Rk.S)
WV alue(PC)
or Lab el
BV alue(PC,Rk.S)
or Lab el (Rk)
Addressing
function
Op erand = V alue
EA = Sign Extended WV alue
EA = V alue
EA = R n
that is, Op erand = [R n ]
EA = [A n ]
EA = [A n ];
Incremen t A n
Decremen t A n ;
EA = [A n ]
EA = WV alue + [A n ]
EA = BV alue + [A n ] +[R k ]
EA = WV alue + [PC]
EA = BV alue + [PC]
+ [R k ]
effectiv e address
a n um b er giv en either explicitly
or represen ted b y a lab el
an 8-bit V alue
a 16-bit V alue
an address register
an address or a data register
a size indicator:
W for sign-extended
16-bit w ord
and L for 32-bit long w ord
24