TABLE D.4
(Continued)
Mnemonic
(Name)
Size
Operands
dst
Operation
performed
src
HLT
(Halt)
CC flags
affected
S
Z
O
C
Halts execution until
resetor external
interrupt occurs
IDIV
(Signed
divide)
B,D
reg
mem
for B:
[AL]/[src];
AL  quotient;
AH  remainder
for D:
[EAX]/[src];
EAX  quotient;
EDX  remainder
?
?
?
?
IMUL
(Signed
multiplication)
B,D
reg
mem
(double-lengthproduct)
for B:
AX  [AL]  [src]
for D:
EDX,EAX  [EAX]
 [src]
?
?
x
x
reg
mem
(single-length product)
reg  [reg]  [src]
?
?
x
x
x
x
x
D
reg
reg
IN
(Isolated
input)
B,D
dst = AL
or EAX
src = imm8
or [DX]
AL or EAX  [src]
INC
(Increment)
B,D
reg
mem
dst  [dst] + 1
INT
(Software
interrupt)
D
imm8
Push EFLA GS;
Push EIP;
EIP  address
(determinedby imm8)
Table D.4 – page 3
TABLE D.4
(Continued)
Mnemonic
(Name)
Size
Operands
dst
IRET
(Return from
interrupt)
D
Operation
performed
src
Pop EIP;
Pop EFLA GS
CC flags
affected
S
Z
O
C
x
x
x
x
mem reg  EA of src
LEA
D
(Load effective
address)
reg
LOOP
(Loop)
D
target
ECX  [ECX] – 1;
If ( [ECX]  0 )
EIP  target
LOOPE
(Loop on
equal/zero)
D
target
ECX  [ECX] – 1;
If ( [ECX]  0
^ [Z]= 1 )
EIP
target
LOOPNE
(Loop on
not equal/
not zero)
D
target
ECX  [ECX] – 1;
If ( [ECX]  0
^ [Z] 1 )
EIP
target
MOV
(Move)
B,D
reg
reg
mem
reg
mem
reg
dst  [src]
mem
reg
imm
imm
MOVSX
(Sign extend
byte into
register)
B
reg
reg
reg
reg  sign extend [src]
mem
Table D.4 – page 4
T ABLE D.4
(Continued)
Mnemonic
(Name)
Size
MOVZX
(Zero extend
byte into
register)
B
MUL
(Unsigned
multiplication)
B,D
NEG
(Negate)
B,D
Operands
Operation
performed
CC flags
affected
dst
src
reg
reg
reg
mem
reg  zero extend [src]
reg
mem
reg
mem
NOP
(No operation)
S
Z
O
C
(double-length product)
for B:
AX  [AL]  [src]
for D:
EDX,EAX  [EAX]
 [src]
?
?
x
x
dst  2's-complement
[dst]
x
x
x
x
x
x
0
0
alias for:
XCHG
EAX,EAX
dst  [dst]
NOT
(Logical
complement)
B,D
reg
mem
OR
(Logical OR)
B,D
reg
reg
mem
reg
mem
OUT
(Isolated
output)
B,D
dst = imm8
or [DX]
src = AL
or EAX
reg
mem
reg
imm
imm
dst  [dst]  [src]
dst  [AL] or [EAX]
Table D.4 – page 5
TABLE D.4
(Continued)
Mnemonic
(Name)
Size
Operands
dst
Operation
performed
CC flags
affected
src
S
Z
O
C
dst  [[ESP]];
ESP  [ESP] + 4
POP
(Pop off
stack)
D
POPAD
(Pop off
stack into
all registers
except ESP)
D
PUSH
(Push onto
stack)
D
PUSHAD
(Push all
registers
onto stack)
D
RCL
(Rotate left
with C flag)
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.32b;
src operand is
rotation count
?
x
RCR
(Rotate right
with C flag)
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.32d;
src operand is
rotation count
?
x
RET
(Return from
subroutine)
reg
mem
Pop eight doublewords
off stack into
EDI, ESI, EBP, discard,
EBX, EDX, ECX, EAX;
ESP  [ESP] + 32
reg
mem
imm
ESP  [ESP] – 4;
[ESP]  [src]
Push contents of
EAX, ECX, EDX, EBX,
ESP, EBP, ESI, EDI
onto stack;
ESP  [ESP] – 32
EIP  [[ESP]];
ESP  [ESP] + 4
Table D.4 – page 6
TABLE D.4
(Continued)
Mnemonic
(Name)
Size
Operands
dst
src
Operation
performed
CC flags
affected
S
Z
O
C
ROL
(Rotate left)
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.32a;
src operand is
rotation count
?
x
ROR
(Rotate right)
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.32c;
src operand is
rotation count
?
x
SAL
(Shift
arithmetic
left)
sameas SHL
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.30a;
src operand is
shift count
x
x
?
x
SAR
(Shift
arithmetic
right)
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.30c;
src operand is
shift count
x
x
?
x
SBB
(Subtract
with borrow)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst] – [src]
– [CF]
x
x
x
x
SHL
(Shift
left)
sameas SAL
B,D
reg
reg
mem
mem
imm8
CL
imm8
CL
SeeFigure 2.30a;
src operand is
shift count
x
x
?
x
Table D.4 – page 7
TABLE D.4
(Continued)
Mnemonic
(Name)
SHR
(Shift
right)
Size
B,D
Operands
dst
src
reg
reg
mem
mem
imm8
CL
imm8
CL
Operation
performed
SeeFigure 2.30b;
src operandis
shift count
CC flags
affected
S
Z
O
C
x
x
?
x
CF  1
STC
(Set carry
flag)
1
IF  1
STI
(Set interrupt
flag)
SUB
(Subtract)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst] – [src]
x
x
x
x
TEST
(Test)
B,D
reg
mem
reg
mem
reg
reg
imm
imm
[dst] ^ [src];
set flagsbased
on result
x
x
0
0
XCHG
(Exchange)
B,D
reg
reg
reg
mem
[reg]  [src]
XOR
(Exclusive
OR)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst]  [src]
x
x
0
0
Table D.4 – page 8
T ABLE D.5
IA-32 conditionaljump instructions
Mnemonic
Condition
name
Conditioncode
test
JS
JNS
JE/JZ
JNE/JNZ
JO
JNO
JC/JB
JNC/JAE
JA
JBE
JGE
JL
JG
JLE
Sign (negative)
No sign (positive or zero)
Equal/Zero
Not equal/Not zero
Overflow
No overflow
Carry/Unsignedbelow
No carry/Unsignedabove or equal
Unsigned above
Unsigned below or equal
Signed greater than or equal
Signed less than
Signed greater than
Signed less than or equal
SF = 1
SF = 0
ZF = 1
ZF = 0
OF = 1
OF = 0
CF = 1
CF = 0
CF  ZF = 0
CF  ZF = 1
SF  OF = 0
SF  OF = 1
ZF  (SF  OF) = 0
ZF  (SF  OF) = 1