Pref ix
OP code
ModR/M
SIB
Displacement
Addressing mode
(a) General f ormat
7
6
Mod
5
4
3
2
Reg/OPcode
1
0
R/M
(b) ModR/M by te
7
6
Scale
5
4
3
Index
2
1
0
Base
(c) SIB by te
Figure D.1. IA-32 instruction format.
Immediate
# include < stdio.h>
void main(void)
{
long NUM1[5];
long SUM;
long N;
NUM1[0] =
NUM1[1] =
NUM1[2] =
NUM1[3] =
NUM1[4] =
SUM = 0;
N = 5;
17;
3;
 51;
242;
113;
asm{
STARTADD:
LEA
MOV
MOV
MOV
ADD
INC
DEC
JG
MOV
EBX,NUM1
ECX,N
EAX,0
EDI,0
EAX,[EBX + EDI*4]
EDI
ECX
STARTADD
SUM,EAX
}
printf ("The sum of the list valuesis %ld \ n", SUM );
}
Figure D.2. IA-32 Program in Figure 3.40a encapsulated in a C/C++ program.
Machine instructions
(hexadecimal)
Assemblylanguageinstructions
03
47
49
7F
STARTADD:
04
BB
ADD
INC
DEC
JG
F9
EAX,[EBX + EDI*4]
EDI
ECX
STARTADD
(a) Loop body encoding
OP code
ModR/M byte
SIB byte
03
00000011
04
00 000100
BB
10 111 011
ADD
(doubleword
(seeTable D.2)
(seeFigureD.1c )
(b) ADD instruction
OP code
Offset
7F
01111111
F9
111111001
JG
(short offset)
7
(c) JG instruction
Figure D.3. Encoding of the loop body in Figure D.2.
T ABLE D.1
Register field encoding
in IA-32 instructions
Reg/Base/Index*
field
00
00
01
01
10
10
11
11
0
1
0
1
0
1
0
1
Register
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
*ESP (100) cannot be used as an
index register.
TABLE D.2
IA-32 addressing modes selected by the ModR/M and SIB bytes
ModR/M
byte
Addressingmode
Mod
field
b7 b6
R/M
field
b2 b1 b0
0 0
Reg
Registerindirect
EA = [Reg]
0 1
Reg
Basewith 8-bit displacement
EA = [Reg]+ Disp8
1 0
Reg
Basewith 32-bit displacement
EA = [Reg]+ Disp32
1 1
Reg
Register
EA = Reg
Exceptions
0 0
1 0 1
Direct
EA = Disp32
0 0
1 0 0
Basewith index (usesSIB byte)
EA = [Base]+ [Index]  Scale
When Base= EBP the addressingmode is:
Index with 32-bit displacement
EA = [Index]  Scale+ Disp32
0 1
1 0 0
Basewith index and 8-bit displacement(usesSIB byte)
EA = [Base]+ [Index]  Scale+ Disp8
1 0
1 0 0
Basewith index and 32-bit displacemet(usesSIB byte)
EA = [Base]+ [Index]  Scale+ Disp32
TABLE D.3
Scale field encoding
in IA-32 SIB byte
Scale field
Scale
00
01
10
11
1
2
4
8
TABLE D.4
IA-32 instructions
Mnemonic
(Name)
Size
Operands
dst
src
Operation
performed
CC flags
affected
S
Z
O
C
ADC
(Add with
carry)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst] + [src] + [CF]
x
x
x
x
ADD
(Add)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst] + [src]
x
x
x
x
AND
(Logical
AND)
B,D
reg
reg
mem
reg
mem
reg
mem
reg
imm
imm
dst  [dst]
x
x
0
0
BT
(Bit test)
D
reg
reg
mem
mem
reg
imm8
reg
imm8
bit# = [src];
CF  bit# of [dst]
x
BTC
(Bit test and
complement
D
reg
reg
mem
mem
reg
imm8
reg
imm8
bit# = [src];
CF  bit# of [dst];
complementbit#
of [dst]
x
BTR
(Bit test
and reset)
D
reg
reg
mem
mem
reg
imm8
reg
imm8
bit# = [src];
CF  bit# of [dst];
clear bit# of [dst] to 0
x
^ [src]
Table D.4 – page 1
TABLE D.4
(Continued)
Mnemonic
(Name)
Size
Operands
dst
src
reg
imm8
reg
imm8
BTS
(Bit test
and set)
D
reg
reg
mem
mem
CALL
(Subroutine
call)
D
reg
mem
Operation
performed
CC flags
affected
S
Z
O
bit# = [src];
CF  bit# of [dst];
set bit# of [dst] to 1
C
x
ESP  [ESP] – 4;
[ESP]  [EIP];
EIP  EA of dst
CF  0
CLC
(Clear carry)
0
IF  0
CLI
(Clear int. flag)
CF  [CF]
CMC
(Compl.carry)
CMP
(Compare)
B,D
reg
reg
mem
reg
mem
DEC
(Decrement)
B,D
reg
mem
DIV
(Unsigned
divide)
B,D
reg
mem
reg
imm
imm
reg
mem
x
[dst]  [src]
x
x
x
dst  [dst] – 1
x
x
x
for B:
[AL]/[src];
AL  quotient;
AH  remainder
for D:
[EAX]/[src];
EAX  quotient;
EDX  remainder
?
?
?
x
?
Table D.4 – page 2