Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 19
External Memory: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menghubungkan konsep eksternal
memory dalam mendesain sistem
komputer ( C4 ) ( No TIK : 9 )
2
Chapter 5.
External Memory: I
3
SUM := 0
for j:= 0 to 9 do
SUM := SUM + A(0,j)
end
AVE := SUM / 10
for i:= 9 down to 0 do
A(0,i) := A(0,i) / AVE
end
Figure 5.19. Task for example in Section 5.5.3.
4
Contents of data cache after pass:
Block
position
0
j =1
j = 3
j =5
j = 7
j = 9
i = 6
i = 4
i = 2
i = 0
A(0,0) A(0,2) A(0,4) A(0,6) A(0,8) A(0,6) A(0,4) A(0,2) A(0,0)
1
2
3
4
A(0,1) A(0,3) A(0,5) A(0,7) A(0,9) A(0,7) A(0,5) A(0,3) A(0,1)
5
6
7
Figure 5.20. Contents of a direct-mapped data cache in Example 5.1.
5
Contents of data cache after pass:
Block
position
j = 7
j = 8
j = 9
i = 1
i = 0
0
A(0,0)
A(0,1)
A(0,8)
A(0,1)
A(0,8) A(0,8)
A(0,9) A(0,1)
A(0,0)
A(0,1)
A(0,2)
A(0,3)
A(0,2)
A(0,3)
A(0,2) A(0,2)
A(0,3) A(0,3)
A(0,2)
A(0,3)
A(0,4)
A(0,5)
A(0,4)
A(0,5)
A(0,4) A(0,4)
A(0,5) A(0,5)
A(0,4)
A(0,5)
A(0,6)
A(0,7)
A(0,6)
A(0,7)
A(0,6) A(0,6)
A(0,7) A(0,7)
A(0,6)
A(0,7)
1
2
3
4
5
6
7
Figure 5.21. Contents of an associative-mapped data cache in Example 5.1.
6
Contents of data cache after pass:
Set 0
j = 3
j = 7
j = 9 i = 4 i = 2
i = 0
A(0,0)
A(0,1)
A(0,2)
A(0,3)
A(0,4)
A(0,5)
A(0,6)
A(0,7)
A(0,8)
A(0,9)
A(0,6)
A(0,7)
A(0,0)
A(0,1)
A(0,2)
A(0,3)
A(0,4)
A(0,5)
A(0,6)
A(0,7)
A(0,4)
A(0,5)
A(0,2)
A(0,3)
Set 1
Figure 5.22. Contents of a set-associative-mapped data cache in
Example 5.1.
7
Block 1
Hi t = 0
tag
v
d
d
000BF2
v
d
d
Set
0
Block 2
=?
Block 3
Y es
d
Mi ss = 0
Hi t = 1
tag
v
d
tag
v
d
d
tag
v
d
d
tag
v
d
d
Block 0
Block 1
Set
63
Block 2
Block 3
d
Fi gure 5.23. Data cache organi zati on i n 68040 m i croprocessor.
8
Processing units
L1 instruction
cache
L1 data
cache
Bus interface unit
System bus
Cache bus
L2 cache
Main
memory
Input/Output
Figure 5.24. Caches and external connections in Pentium III
processor.
9
k bits
Module
ABR
DBR
m bits
Address in module
ABR
Module
0
DBR
MM address
ABR
DBR
Module
n- 1
Module
i
(a) Consecutive words in a module
m bits
k bits
Address in module
ABR
DBR
Module
0
ABR
Module
DBR
Module
i
MM address
ABR
DBR
Module
k
2 - 1
(b) Consecutive words in consecutive modules
Figure 5.25. Addressing multiple-module memory systems.
10
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 20
External Memory: II
11
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menghubungkan konsep eksternal
memory dalam mendesain sistem
komputer ( C4 ) ( No TIK : 9 )
12
Chapter 5.
External Memory: II
13
14
Virtual address from processor
Page table base register
Page table address
Virtual page number
Offset
+
PAGE TABLE
Control
bits
Page frame
in memory
Page frame
Offset
Physical address in main memory
Figure 5.27. Virtual-memory address translation.
15
Virtual address from processor
Virtual page number
Offset
TLB
Virtual page
number
No
Control
bits
Page frame
in memory
=?
Yes
Miss
Hit
Page frame
Offset
Physical address in main memory
Figure 5.28. Use of an associative-mapped TLB.
16
Sector 3, trackn
Sector 0, track 1
Sector 0, track 0
Figure 5.30. Organization of one surface of a disk.
17
Processor
Main memory
System bus
Disk controller
Disk drive
Disk drive
Figure 5.31. Disks connected to the system bus.
18
Aluminum
Pit
Acrylic
Label
Polycarbonate plastic
Land
(a) Cross-section
Pit
Land
Reflection
Reflection
No reflection
Source
Detector
Source
Source
Detector
Detector
(b) Transition from pit to land
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
(c) Stored binary pattern
Figure 5.32. Optical disk.
19
File
File
mark
File
mark
•
•
•
•
•
•
•
•
File gap
Record
Record
gap
Record
7 or 9
bits
Record
gap
Figure 5.33. Organization of data on magnetic tape.
20