An Ultra Low-Energy DAC for Successive
Approximation ADCs
Hande Vinayak Gopal and Maryam Shojaei Baghini, Senior Member, IEEE
Department of Electrical Engineering,
Indian Institute of Technology(IIT)-Bombay, Mumbai, India.
Email: [email protected], [email protected]
Abstract—An ultra low-energy successive approximation (SA)
Analog-to-Digital Converter (ADC) is presented. The proposed
ADC uses an energy-efficient unit capacitor array having a new
switching arrangement in DAC for passive charge re-distribution.
Reference levels are generated sequentially to get successive bits.
The proposed method is analyzed theoretically and compared
with other methods. Mathematical analysis shows that energy
dissipation per bit can be reduced to the minimum possible
normalized level, which is approximately 200 times lower than
reported theoretical values. Simulation results of the proposed
DAC in 90nm UMC MM CMOS process are also presented.
I. I NTRODUCTION
Increasing trend of sensing biomedical signals with electronic hand held devices or environmental sensor signals
with self-sustained sensor networks has given birth to a
new paradigm of data converters, i.e. energy efficient data
converters. Portable and wearable medical devices need to
collect data from patient in hospital environment or home
or even when she/he is roaming. ADC is an integral part
of these devices and hence its energy efficiency is desired.
Successive approximation (SA) ADC is the most suitable
architecture for biomedical applications due to its reasonably
medium speed, low power consumption, low complexity and
low area consumption, compared to other ADC architectures.
SA ADC with binary weighted capacitor array is widely-used
architecture. However the die size and energy consumption
drastically increases as number of bits increase. This scenario
motivates efforts towards new designs of SA ADC to reduce
its energy consumption and chip area.
Most often, DACs of conventional SA ADCs consist of
a binary weighted capacitor array [1],[3],[6]. The binary
weighted capacitor array operates in a tracking mode wherein
an input voltage is sampled onto one plate of a plurality of
capacitors in a binary weighted capacitor array. After sampling
in the converter mode, the plates of the capacitors which are
connected to the input voltage are selectively connected between ground and reference voltage. A comparator connected
to the other plate of the capacitors gives the corresponding
digital output. This conventional one step switching method
is highly energy inefficient as the capacitor switching wastes
a lot of energy by simply dumping stored charges to ground
[3]. Subsequently other energy efficient methods have been
Patent application for the proposed idea has been submitted to Intellectual
Ventures India.
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
proposed, such as two step switching method [3], capacitor
splitting method [4], charge sharing method [3] and junctionsplitting capacitor array method [5] have been reported to
enhance the usage of the energy.
Another major limitation of conventional SA ADC is that
the total area of the array rises exponentially with the resolution, i.e. 2n Aunit , where Aunit denotes area of a unit
capacitor. Similarly, power consumption of the converter,
which is proportional to Fclk .2n Aunit , also increases with n.
To overcome the inefficiency of conventional SA ADC
architectures, different alternatives have been proposed. In
some cases, the size of the capacitive array is reduced by
combining it with an interpolating resistive ladder which
solves part of the n-bit output word of the converter [8-9]. In
other approaches, the capacitor count is reduced by dividing
the capacitive array into two parts connected with a coupling
attenuation capacitor [7]. The extension of this approach is a
complete C-2C ladder [10].
Owing to inefficient usage of an energy and chip area
by a conventional SA ADC approach, we proposed the unit
capacitor DAC array architecture. There is no energy dissipation during the conversion process. The proposed scheme can
reduce the energy consumption and area usage of the capacitor
array to its fundamental lowest limit.
The rest of this paper is organized as follows. Section II,
explains the proposed unit capacitor DAC array method for SA
ADC. Section III discusses the limiting factors for linearity of
SA ADC. Section IV compares the proposed technique with
the previous SA ADC techniques along with simulation results
of the design in 90nm UMC MM CMOS process. Section V
briefly discusses about the future developments for proposed
method to increase the resolution. Finally conclusion is given
in section VI.
II. U NIT C APACITOR A RRAY M ETHOD
Block diagram of the proposed unit capacitor array SA
ADC is shown in Fig. 1. Initially sample and hold circuit
samples the input voltage. A unit capacitor array generates
reference voltage levels e.g. VREF /2, VREF /4, 3VREF /4,
etc. successively in alliance with steering signals of control
blocks. The comparator output sequentially indicates if the
sampled input voltage is greater or smaller than the sequence
reference voltage levels generated by unit capacitor array. A
control block is also arranged to latch digital output bits.
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Fig. 1.
Block Diagram of Unit Capacitor Array SA ADC
In contrast to the conventional capacitor array, the proposed
unit capacitor array generates digital Vout by passively generating reference levels and connecting them in series. Since
effectively no charge is dumped to ground existing charge is
utilized efficiently.
Fig. 3.
Switching Arrangement of a unit capacitor array
initially stored on C1 , gets equally distributed on C1
and C2 .
QC2 = QC1 = Qtotal /2
(3)
VX (1) = VY (1) = VREF /2
Fig. 2.
Only a small amount of time is needed for the charge
re-distribution, determined by the time constant of the
switch resistance and unit capacitance.
4) Phase IV is comparison and passive charge redistribution. At this phase switches S3 , S5 and S7 are
closed to perform passive charge re-distribution. As C2
and C3 are of the same size. Now, the charge on C3 is
Structural Diagram of Unit Capacitor Array
Fig. 2 shows detail structure of unit capacitor array for n=3.
A unit capacitor array comprises (4n + 1) switches and (n
+ 1) unit capacitors, where n is the resolution of SA ADC,
i.e. number of bits. Control block provides signals S0 to S12
which close and open corresponding switches S0 to S12 . Four
capacitors C1 to C4 are used and the conversion procedure is
described in Fig. 3 (a) to (f).
1) Reset phase is the first phase (Phase I) of conversion. In
this phase the whole unit capacitor array is discharged
or in other words is reset. The voltages across all unit
capacitors is zero and hence
VX (0) = VY (0) = VZ (0) = 0
(1)
2) Phase II is pre-charging phase. In this phase switch
arrangement is in such a way capacitor C1 is precharged to the reference voltage VREF . Therefore the
total charge stored on C1 is
Qtotal = C1 .VREF
(4)
QC3 = QC2 = Qtotal /4
(5)
VY (2) = VZ (2) = VREF /4
(6)
At the same time, generated reference voltage VX and
sampled input voltage are compared. This comparison
generates MSB bit b0 .
If held input voltage > VX then b0 =1;
If held input voltage < VX then b0 =0.
5) At Phase V, as shown in Fig. 3, next comparison takes
place depending on b0 and in accordance with the
control block. The reference level for comparison is
generated as,
VX (3) = b0 .VX (1) + VY (2)
(7)
The comparator compares the difference between newly
generated reference voltage VX and already sampled
input voltage. This comparison generates next bit b1 .
If held input voltage > VX then b1 =1;
If held input voltage < VX then b1 =0.
(2)
3) Phase III is passive charge re-distribution phase. In this
phase C1 and C2 are connected in series. Since C1 and
C2 are of the same size. Therefore charge on C2 is
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6) At Phase VI, the procedure repeats. Accordance with b0
and b1 reference level is generated i.e.
VX (4) = S0 .VX (1) + S1 .VY (2) + VZ (3)
(8)
After charge re-distribution phase charge on C2 will be
which sets Bit b2.
III. FACTORS L IMITING L INEARITY
QC2 (1) = (∆ + 1)C1.
To explore nonidealities associated with the unit capacitor
array DAC architecture, discussed in section III, two primary
sources of error are considered. These sources are clock feed
through voltage(Vcf ) and capacitor mismatch (Vmc ). Accordingly, for example, the first generated reference value will be
changed as shown in Fig. 4
VC1 (1) = VC2 (1) = VREF /2 + Verror
(12)
and voltage across C2 will be
VC2 (1) =
VREF
∆+2
(13)
where ∆ is ∆Cu/Cu.
Therefore the error voltage introduced because of mismatch is
(9)
where Verror constitutes Vcf and Vmc . In order to keep
the worst case conversion error less than the converter
resolution the following condition must be maintained:
max|V error| < VREF /2(n+1) for n bit resolution [2].
VREF
(∆ + 2)
Vmc =
∆.VREF
VREF
− VC2 (1) =
2
2(∆ + 2)
(14)
Since the proposed design uses unit capacitor array the mismatch is reduced drastically as compared to binary weighted
capacitor array.
IV. C OMPARISON AND S IMULATION R ESULTS
A. Clock feedthrough
The asymmetry introduced into the circuit by the nonlinear capacitances associated with the charge-sharing. MOS
transistor switch results in a net feedthrough error voltage
during re-distribution. With respect to the circuit in Fig. 4,
A proposed successive approximation ADC has been developed on the basis of theoretical analysis.
A. Comparison
Table I quantitatively compares the energy consumption of
different reported SA ADC architectures and the proposed
unit capacitor array method. All values in this table are
based on the rigorous mathematical analysis for n=10. Energy
2
consumption per n bits is normalized to Cu .VREF
. It indicates
the significant reduction in an energy consumption.
TABLE I
C OMPARISON OF N ORMALIZED E NERGY C ONSUMPTION PER N B ITS
Fig. 4.
Output
Code
Convn.
swt. [3]
0
100
200
300
400
500
600
700
800
900
1000
855
847
832
808
774
730
675
612
539
456
363
Charge Sharing between two capacitors
after application of a control voltage pulse to the gate of the
transistor the resulting capacitor voltages will be
VC1 (0) + VC2 (0)
+ Vcf
(10)
2
Magnitude of the error component is proportional to the
channel capacitance of the MOS transistor CO and inversely
proportional to the sum of the charge-sharing capacitors
(C1 + C2) [2]. Therefore allowable error constrains size of
MOS switches in relation to the charge-sharing capacitors.
This restriction, in turn, limits the magnitude of the charging
currents and thus determines conversion speed. In the proposed
design in this paper we have used minimum size complementary switches to reduce the clock feedthrough effect.
VC1 (1) = VC2 (1) =
Two
Step
swt. [3]
679
679
671
669
643
601
635
578
528
453
362
Capacitor
Splitting
swt. [4]
341
386
422
447
463
468
465
451
428
395
352
J-S
Capacitor
swt. [5]
1
91
162
213
244
256
249
222
175
108
22
Unit
Capacitor
array
1
1
1
1
1
1
1
1
1
1
1
Table II compares area of capacitor array in different SA
ADC architectures and the proposed unit capacitor array
architecture. As table II shows the proposed architecture in
this paper consumes less area of capacitor array, compared to
other capacitor arrays used in different SA ADCs.
TABLE II
C OMPARISON OF A REA C ONSUMPTION
B. Mismatches
To evaluate the error voltage due to capacitor mismatch in
Fig. 4, consider C1 is Cu i.e. unit capacitor and C2 is (Cu +
∆Cu). Consider capacitor C1 is fully charged to VREF before
passive charge re-distribution phase. Therefore the charge on
C2 is zero where it is on C1 is
QC1 (0) = C1.VREF
(11)
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DAC Architecture
Conventional Binary Weighted Cap. Array [3]
Capacitor Splitting [4]
Junction Splitting Cap. Array [5]
C-2C Ladder Based Cap. Array [10]
Unit Capacitor Array
Area Consumption
2n .Aunit
2n .Aunit
2n .Aunit
(3n − 1).Aunit
(n + 1).Aunit
B. Simulation Results
A unit capacitor array SA ADC architecture is designed in
UMC 90nm CMOS process and simulated by Spectre using
foundry models.
The switches used in the proposed architecture are realized
with minimum size complementary MOS transistors. Fig. 5
shows a worst case i.e. FF process corner, simulation results
of differential non linearity (DNL) and integral non linearity
(INL) are ±0.5LSB at 700KHz sampling frequency.
lations using 90nm UMC CMOS process, show that 6 bit resolution can also be achieved by C-2C ladder DAC at the expense
of ≈3 times increase in both area and energy consumption
as compare to proposed method. Parasitic capacitance on the
interconnect severely impedes C-2C ladder DAC’s linearity.
Simulations have been performed considering same values of
Cu, VREF , switch sizes and sampling frequency for both
proposed DAC and C-2C ladder based DAC.
Ultra low energy dissipation provides flexibility to increase
resolution of the proposed SA ADC. For example, in a hybrid
architecture first few MSB bits can be evaluated by active
charge re-distribution technique and remaining bits by the
proposed unit capacitor array method. As charge on the MSB
capacitors will be refreshed during active charge re-distribution
technique, it helps to improve the resolution as well as linearity
of the proposed SA ADC architecture.
VI. C ONCLUSION
Fig. 5.
In this paper we have presented a new unit capacitor array
DAC architecture and switching methodology for a SA ADC.
The energy inefficiency of the conventional architectures has
been eliminated in the new unit capacitor array technique.
The presented unit size capacitor array and passive charge
re-distribution method are used to generate reference voltage
levels. The generated reference voltage levels are successively
compared with sampled input voltage to get the digital bits. As
most of the energy consumed by capacitor array, the proposed
architecture shows an efficient usage of energy and area.
DNL and INL for n=4 @ 700KHz Sampling Frequency
R EFERENCES
Fig. 6. Mismatch analysis using Monte Carlo simulation of DAC output for
1111 input code @ 700KHz Sampling Frequency,VREF =0.9V
Statistical analysis of DAC output for 1111 input code is
performed using Monte Carlo simulation, considering mismatch among capacitors and complementary MOS switches.
The proposed architecture requires only (n+1) equal sized
capacitors to form a DAC. The result shows that the standard
deviation of the output is 2.31mV from its mean value i.e.
840.356mV.
As per theoretical analysis max|V error| for n=6 and n=7
is 7.8125mV and 3.90625mV, respectively [2]. The simulation
results of proposed unit capacitor array SA ADC @700KHz
sampling frequency shows that max|V error| for n=6 and
n=7 is 7.445mV and 8.5975mV, respectively. It indicates that
the achievable resolution of proposed SA ADC is 6 Bits for
700KHz sampling frequency.
Simulation results show that the energy consumed per 6
bit conversion by 6 bit DAC is 1pJoules for Cu=1pF and
VREF =1V @700KHz sampling frequency.
V. D ISCUSSION AND F UTURE D EVELOPMENT
C-2C ladder based architecture [10] is also one of the
promising option for low energy DAC applications. Our simu-
[1] James L. McCreary and Paul R. Gray,”AII-MOS Charge Redistribution
Analog-to-Digital Conversion Techniques Part I,” proc. of IEEE JSSC,
vol.10, no.6, pp. 371-379, December 1975.
[2] Recardo E. Suarez, Paul R. Gray and David A. Hodges,”AII-MOS Charge
Redistribution Analog-to-Digital Conversion Techniques Part II,” proc. of
IEEE JSSC, vol.10, no.6, pp. 379-385, December 1975.
[3] Brian P. Ginsburg and Anantha P. Chandrakasan, An Energy Efficient
Charge Recycling Approach for SAR Converter With Capacitive DAC,
Proc. of IEEE Int. Symp. on Circuits and Systems, vol.1, pp. 184-187,May
2005.
[4] Brian P. Ginsburg and Anantha P. Chandrakasan, 500-MS/s 5-bit ADC
in 65-nm CMOS With Split Capacitor Array DAC, IEEE J. Solid-State
Circuits IEEE Int. Conf. on Electronics, Circuits and Systems, vol. 42,no.
4, pp. 739-747, Apr.2007.
[5] Jeong-Sup Lee and In-Cheol Park,Capacitor Array Structure and Switch
Control for Energy-Efficient SAR Analog-to-Digital Converters, Proc. of
IEEE Int. Symp. on Circuits and Systems, pp. 236-239, May. 2008.
[6] Jan Craninckx and Geert Van der Plas,A 65fJ/Conversion-Step 0-to50MS/s 0- to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital
CMOS, IEEE ISSCC Dig. Tech. Papers, pp. 246-247, 2007.
[7] K. Abdelhalim, L. MacEachern, and S. Mahmoud, A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor
Applications, Proc. of IEEE IEEE Int. Symp. on Circuits and Systems,
pp.2351-2354,May 2007.
[8] K. Hadidi, V. S. Tso, and G. C. Temes, An 8-b 1.3-MHz successive
approximation A/D converter, IEEE J. Solid-State Circuit, vol. 25(6), pp.
880-885, Jun. 1990.
[9] J. Park, H.-J. Park, J.-W. Kim, S. Seo, and P. Chung, A 1mW 10-bit
500kSps SAR A/D Converter, Proc. of IEEE IEEE Int. Symp. on Circuits
and Systems , pp. V-581584, 2000.
[10] Y. Liao, and T. Lee, A 6-b 1.3Gs/s A/D Converter with C-2C SwitchCapacitor Technique, in Int. Symp. on VLSI Design, Automation and Test,
pp. 1-4, April 2006.
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