IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
627
Short Papers
A Table-Based Approach to Study the Impact of Process
Variations on FinFET Circuit Performance
Rajesh A. Thakker, Chaitanya Sathe,
Maryam Shojaei Baghini, Senior Member, IEEE, and
Mahesh B. Patil, Senior Member, IEEE
Abstract—This paper presents a novel table-based approach for
efficient statistical analysis of Finfield effect transistor circuits. The
proposed approach uses a new scheme for interpolation of look-up tables
(LUTs) with respect to process parameters. The effect of various process
parameters, viz., channel length, fin width, and effective oxide thickness is
studied for three circuits: buffer chain, static random access memory cell,
and high-gain low-voltage op-amp. Compared to mixed-mode (devicecircuit) simulation, the proposed LUT-based approach is shown to be
much faster, thus making it practically a feasible and attractive option for
variability analysis especially for emerging technologies where compact
models are not available for circuit simulation.
Index Terms—FinFET, look-up table, look-up table interpolation,
process variation study.
I. Introduction
The Finfield effect transistor (FinFET) device is emerging
as a strong candidate to replace planar bulk metal oxide
semiconductor field-effect transistors (MOSFETs) due to its
better gate control and reduced short-channel effects [1]. One
of the major concerns about the usefulness of the FinFET
technology—indeed, any novel technology—is the effect of
statistical variations [2]–[5] in process parameters on the
circuit/system performance [6]–[8]. For a novel technology,
predicting the effect of statistical variations is difficult because
accurate analytical models are either not available at all or
are not sufficiently mature. For FinFETs also, analytical models are under investigation [9]. Mixed-mode (device-circuit)
simulation has been used recently for predicting FinFET
circuit performance in the presence of statistical variations
[7], [8]. However, this approach is only useful for small
circuits because of the excessive amount of computation time it
requires. The look-up table (LUT) approach has been effective
in simulation of circuits with novel technologies (see [10]
and references therein). Technology computer-aided design
(TCAD) simulators are generally used to generate LUTs
for devices. Interpolation of table data for MOSFETs was
discussed in [11]; however, it is not suitable for studying
process variations.
Manuscript received February 13, 2009; revised May 28, 2009, October 27,
2009, and November 18, 2009. Current version published March 19, 2010.
This work was performed at the Center of Excellence for Nanoelectronics,
IIT Bombay, which is supported by the Ministry of Communications and
Information Technology, Govt. of India. This paper was recommended by
Associate Editor, F. N. Najm.
R. A. Thakker, M. S. Baghini, and M. B. Patil are with the Department of
Electrical Engineering, Indian Institute of Technology, Bombay 400 076, India
(e-mail: [email protected]; [email protected]; [email protected]).
C. Sathe was with the Department of Electrical Engineering, Indian Institute
of Technology, Bombay 400 076, India. He is now with the Department of
Electrical Engineering, University of Illinois, Urbana, IL 61801 USA (e-mail:
[email protected]).
Digital Object Identifier 10.1109/TCAD.2010.2042899
Extension of the LUT approach for studying statistical
variations requires generation of a large number of lookup tables, which would generally be impractical in terms of
CPU time. In this paper, we present an accurate interpolation
scheme which circumvents the previously mentioned situation
and enables the LUT approach, for the first time, to predict
circuit performance in the presence of statistical variations in
new technologies, such as FinFET.
II. Look-Up Table Technique
The LUT approach basically consists of I–V and Q–V
tables, and interpolation coefficients for the transistor. This
information is used to compute currents during circuit simulation as follows:
dQX
IX (VG , VD , VS , t) = IXDC (VG , VD , VS , t) +
dt
dQX ∂QX ∂VG ∂QX ∂VD ∂QX ∂VS
=
+
+
(1)
dt
∂VG ∂t
∂VD ∂t
∂VS ∂t
where X = G, D, S. Equation (1) is valid if the quasi–static
approximation holds [12], which is generally true for short–
channel devices. The terminal charges (Q) can be calculated
from C–V data. For the purpose of circuit simulation, a
good LUT scheme should not only interpolate the current
and charges at nontable points but also accurately compute
their slopes with respect to the terminal voltages. For accurate
interpolation in all three regimes (i.e., subthreshold, moderate
inversion, and strong inversion), the ID –VG template-based
LUT approach is used in this paper. This LUT approach is
recently proposed and was verified using FinFET circuits in
45 nm technology devices. The complete details of the ID –VG
template-based LUT approach can be found in [10]. This LUT
approach is implemented in the circuit simulation package
SEQUEL [13] and used in this paper.
III. LUT Interpolation Scheme and Validation
A. LUT Interpolation Scheme
The look-up table for a given transistor consists of the I–V
and Q–V data for that particular transistor. For studying the
effect of statistical variations on a given circuit, the following
approaches have been reported in the literature.
1) Extract model parameters for the “nominal” transistor,
allow the model parameters to vary (say, within ±5%)
preserving the correlation among model parameters,
perform circuit simulation, and record the quantities of
interest (such as amplifier gain and gate delay) [14].
2) Perform process simulations to generate transistors with
different values of process parameters and use mixedmode simulation to see the effect on the quantities of
interest.
For novel technologies, such as FinFETs, accurate models are
not available, and approach (1) is not feasible. Approach (2)
may be used; however, it would require an impractically large
c 2010 IEEE
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
not able to interpolate accurately in the subthreshold
region. The following approximation was found to be
accurate for all regions of operation:
log(ID ) = a + bp
Fig. 1. Interpolation of (a) ID and (b) QG , along process parameter p which
can be L, TFIN, or EOT.
(2)
where a and b are constants, to be obtained from the
table points [see Fig. 1(a)].
2) Terminal charges (QG or QD ): The variation of terminal
charges with respect to process parameters is generally
much smoother than that of the drain current. Therefore,
a simple cubic spline approach was found to be adequate
for interpolation of the terminal charges. Fig. 1(b) shows
interpolation of the terminal charge QG . The QG –p
(terminal charge versus process parameter) data is fitted
with cubic splines and QG for p = p0 is evaluated.
B. Validation
Fig. 2. (a) 3-D structure. (b) Cross-sectional diagram of FinFET used for
simulations.
simulation time for even moderately complex circuits. In view
of the above limitations of approaches (1) and (2), we use an
LUT-based approach as described by the following steps.
1) Generate LUTs for selected values (within ±3σ) of the
given process parameter [e.g., gate length L, thickness
of fin (TFIN), etc.], using mixed-mode simulation.
2) From the tables obtained in (i), generate a large number
of LUTs by interpolation.
3) Perform Monte Carlo circuit simulation using the LUTs
obtained in (ii) with the help of LUT-based simulator.
4) Postprocess the simulation results to get statistical information about the circuit performance.
A suitable procedure for accurate interpolation between
look-up tables is a key requirement for the above procedure
to work well. The problem of interpolation between look-up
tables may be stated as follows. Two tables of ID and terminal
charges (as functions of the bias voltages, VGS and VDS ) are
given. All process parameters for the two tables are assumed
to be identical except for the parameter p, which takes on the
values p1 and p2 for the two tables. For example, p1 and p2
may be two different values of the channel length (L). For a
0
0
given set of bias conditions, say VGS = VGS
and VDS = VDS
, we
would like to obtain the value of ID and terminal charges at an
intermediate value p0 of the process parameter, i.e., for p1 ≤
p0 ≤ p2 . We found the following method to work satisfactorily
for interpolation of ID and terminal charges, respectively.
1) Drain current (ID ): The drain current is found to be
very sensitive to all of the process parameters considered
in this paper. Linear interpolation was found to work
well in the strong inversion region; however, it gave
significant errors in the subthreshold region. Also, the
commonly used cubic spline interpolation scheme was
The FinFET structure used for validation of the interpolation
scheme is shown in Fig. 2. 45 nm FinFET technology with a
minimum gate length (L) of 20 nm is used. The SENTAURUS
TCAD simulator [15] is used to generate I–V and Q–V
data for the preparation of the LUTs. The TCAD simulator
parameters (such as mobility and doping densities) are first
calibrated to fit experimental data [16]. The nominal values
of the process parameters are: L = 20 nm, effective oxide
thickness (EOT) = 0.9 nm, fin width (T FIN ) = 6 nm, and fin
height (H FIN ) = 30 nm. The channel doping is 1 × 1015 cm−3
and the source/drain doping is 1 × 1020 cm−3 with an overlap
distance (LOV ) of 2 nm. The LUT interpolation scheme is
implemented for the study of process variations in L, TFIN,
and EOT. FinFET device/circuit performance was reported
to be most sensitive to variations in these three process
parameters [2], [8]. Further, variations in L, TFIN, and EOT
were also reported to be independent of each other [2], [8]. The
following 3σ variations of these process parameters reported
in [2] and [8] are considered in this paper: ±2 nm for L (±10
%), ±1 nm for TFIN (±16 %), and ±0.1 nm for EOT (±11%).
The I–V and Q–V data are generated for the following
process parameter values, and the corresponding LUTs are
referred to as “reference set of LUTs.”
1) L = 17, 19, 20, 21, and 23 nm (TFIN = 6 nm, EOT =
0.9 nm).
2) TFIN = 5, 5.5, 6, 6.5, and 7 nm (L = 20 nm, EOT =
0.9 nm).
3) EOT = 0.8, 0.85, 0.9, 0.95, and 1 nm (L = 20 nm, TFIN
= 6 nm).
For the validation of the interpolation approach, we generate
data at intermediate parameter values by: 1) using TCAD;
and 2) using the interpolation scheme described above, and
compare the two. Fig. 3(a) and (b), show the comparison
of the drain current for the process parameter L for the
subthreshold and strong inversion regimes, respectively. In all
cases, the comparison is shown for various values of VDS .
Excellent agreement between the actual data and interpolated
data is observed. It may be noted that logID varies almost
linearly with L, thus justifying the approximation given by (2).
The same behavior was observed with respect to other process
THAKKER et al.: A TABLE-BASED APPROACH TO STUDY THE IMPACT OF PROCESS VARIATIONS ON FINFET CIRCUIT PERFORMANCE
Fig. 3. Interpolation of ID along L at VDS = 25 mV, 0.5-V, and 1.2-V.
(a) VGS = 0-V. (b) VGS = 1.2-V. Filled circles are original data. Lines with
crosses are interpolated data. Unfilled circles are TCAD data generated at
intermediate process parameter values for validation.
parameters and moderate inversion regime as well. The interpolated values were also found to maintain the desired trend
with respect to VGS for all three process parameters.
Fig. 4(a) and (b) shows the comparison of Qg versus L
between interpolated and TCAD data in subthreshold and
strong inversions, respectively, and for two values of V DS . In
all cases, the interpolated and TCAD results are seen to match
very well. Similarly, the interpolation procedure was verified
for Qd and also with respect to other process parameters
(TFIN and EOT) and moderate inversion regime, and excellent
agreement between the interpolated charges and TCAD results
was observed in all cases.
In TCAD simulations, the grid discretization due to change
in process parameter values results in some numerical noise.
To minimize this noise to an acceptable level, the grid and
the number of grid points have been carefully chosen. The
smoothness of the currents and charges with respect to process
parameters (see Figs. 3 and 4) is a good practical indicator of
a properly designed grid.
IV. Impact of Process Variations on Circuit
Performance
For studying the impact of process variations on specific
circuits, the following steps are performed.
1) For each of the three process parameters considered here
(L, TFIN, and EOT), a reference set of five LUTs is
generated as described in Section III-B.
2) For each process parameter, a large number of additional
LUTs are generated using the LUT interpolation scheme
described in Section III. For example, 41 LUTs are
generated for channel lengths between L = 17 nm to
629
Fig. 4. Interpolation of Qg along L at VDS = 0.5-V and 1.2-V. (a) VGS =
0-V. (b) VGS = 1.2-V. Filled circles are original data. Lines with crosses are
interpolated data. Unfilled circles are TCAD data generated at intermediate
process parameter values for validation.
L = 23 nm with a spacing of 0.15 nm. Generating and
storing LUTs in advance is very beneficial in terms
of computational efficiency since the study of process
variations requires tens of thousands of runs for each
circuit.
For the study presented in this paper, 41 tables were
found to be sufficient. Additional tables were not seen
to make any noticeable change in the process variation
results (3σ and mean values) at the circuit level. An
odd value (41) is chosen so that the nominal value of
the process parameter falls at the center.
3) During a given run of circuit simulation for a given process parameter, each transistor in the circuit is randomly
assigned one of the pregenerated LUTs according to a
Gaussian distribution. Circuit simulation is performed,
and the performance parameters of interest are stored
for this run.
4) The procedure described in (3) is repeated for a large
number of runs, and statistics about the performance
measures are collected.
We now consider specific circuit examples and discuss the
impact of variations in process parameters on the performance
in each case. The nominal values of the process parameters
are: L = 20 nm (50 nm in op-amp circuit), EOT = 0.9 nm, and
TFIN = 6 nm. All simulations are performed on a computer
with a 3 GHz processor, 4 GB RAM and 1024 kb cache.
A. Buffer Chain
The buffer chain circuit, generally used for driving high
capacitive loads, is shown in Fig. 5(a). A step input signal
is applied to this circuit and the propagation delay (τpd )
corresponding to the rising edge of the input signal is taken
630
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
Fig. 5. (a) Buffer chain. (b) SRAM cell. (c) Three-stage op-amp circuits. The numbers in brackets show the number of fins for transistors and other component
values. The number of fins for all transistors in SRAM cell is 1.
TABLE I
Simulation Results of Process Variations Study for Buffer
Chain [Fig. 5(a)]. SRAM Cell [Fig. 5(b)]. Op-Amp Circuit [Fig. 5(c)]
Performance
Measure
L
TFIN
EOT
3σ
M
3σ
M
3σ
Buffer Chain [Fig. 5(a)]
τpd (ps)
22.52
1.52
22.57
0.8
22.56
0.34
SRAM Cell [Fig. 5(b)]
SNMR (mV)
140
19.5
140
14.8
140
13.8
SNMH (mV)
370
19.35
370
14.0
370
9.15
Op-Amp Circuit [Fig. 5(c)]
OV (mV)
0.007
0.864
0.005
3.46
0.005
1.35
Gain (dB)
104.5
1.14
104.3
2.98
104.5
2.06
PM (Deg.)
83.3deg 2.36deg 83.0deg 17.4deg 83.3deg 1.09deg
UGF (MHz)
141
5.8
143
36
141
5.9
M
‘M’ stands for mean, σ for standard deviation, OV for offset voltage, PM for
phase margin, UGF for unity gain frequency, SNMR for SNM in read and
SNMH for SNM in hold operations.
as the performance measure. 50 000 circuit simulations were
carried out for each process parameter. The corresponding
mean (denoted by M) and 3σ values for τpd are given in
Table I. It can be seen from the table that the spread in τpd is
maximum due to variations in L and least due to EOT.
For a single run of circuit simulation, the LUT circuit simulator has taken 0.2 s, whereas the mixed-mode SENTAURUS
mixed-mode simulation [15] has taken 46 min. The difference
in simulation time points to the advantage of using LUT
simulations for the process variation study. Clearly, it is not
practical to carry out any meaningful statistical analysis with
a mixed-mode device simulator, since the process variations
study requires tens of thousands of runs. On the other hand, the
LUT simulator can be used effectively, and the statistics can
be obtained in a reasonable time. For example, the study presented in Table I for the buffer chain circuit took about 15 h for
generating the reference sets of 15 LUTs (see Section III-B),
30 min for generating the 123 interpolated LUTs, and about
9 h for all circuit simulations for all three process parameters.
Thus, the total time taken for the entire procedure is 24 h
30 min for the process variations study of this circuit using the
LUT approach. For the same study, mixed-mode simulations
would have taken approximately 150 000 × 0.75 h. It may be
noted that once the LUTs are generated, they can be used for
studying process variations in other circuits as well. In that
sense, it is a one-time computational cost.
The independent variation of L, TFIN, and EOT was reported at the single transistor level in [2], and it was further
used for the process variations study in [8]. We verified the
same for the buffer chain circuit in this paper for extreme cases
(i.e., process corners) of process variations using mixed-mode
simulations. It was found that the error in the calculations of
τpd was not more that 0.31% between the two approaches:
1) when the variations in all process parameters considered
together; and 2) the variations in process parameters considered independently and cumulative effect obtained. The error
less than 0.31% for extreme cases of process variations shows
that the multiparameter interpolation scheme is not required
for the study of process variation effects at the circuit level
for L, TFIN, and EOT parameters.
B. SRAM Cell
The circuit for the static random access memory (SRAM)
cell, shown in Fig. 5(b), is simulated for the study of process variation effects on the static noise margin (SNM) at
VDD = 1 V. SNM was calculated using the graphical method
demonstrated in [17]. 50 000 circuit simulations were carried
out for each of the process parameters. The simulation results
are given in Table I. It can be seen from the table that the
spread in SNM (read and hold) is maximum due to variations
in L. It has taken approximately 4 h to generate the results
given in Table I for the SRAM cell. The LUTs generated for
the buffer chain circuit are used for this circuit as well.
C. High-Gain Three-Stage Op-Amp Circuit
The third circuit considered in this paper is a three-stage
high-gain low-voltage op-amp shown in Fig. 5(c). This op-amp
in planar complementary metal oxide semiconductor (CMOS)
technology has been reported in [18]. This op-map is designed
with FinFET devices (L = 50 nm, other process parameter
values are the same as those given in Section III-B) with the
help of automatic design platform developed by the authors
[19]. The designed op-amp, shown in Fig. 5(c), features the
following specifications at VDD = 1 V:
open loop gain = 104.5 dB, power dissipation = 66 µW, phase
margin = 83.35deg, unity gain frequency = 140 MHz, input offset voltage = 7.6 µV, and rise, fall slew rates = 671-V/µs and
292-V/µs, respectively.
The LUT interpolation and pregeneration of LUTs are
carried out using the same approach as discussed in Section III
RÁK AND CSEREY: MACROMODELING OF THE MEMRISTOR IN SPICE
631
devices (50 nm), the variations in TFIN are found to generate
maximum variations in the performance measures.
Acknowledgment
The authors wish to thank Synopsys, Inc. for providing
TCAD tools for this paper. They are also grateful to A. Sachid
for discussions regarding device structure.
References
Fig. 6. Simulation results of process variations study for op-amp circuit.
[Fig. 5(c)]: (a)–(c) input offset voltage and (d)–(f) voltage gain. ‘M’ stands
for mean.
but for a FinFET device with a nominal channel length of
50 nm. 25 000 circuit simulations are carried out for each
process parameter. Paired FinFET devices are assigned the
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V. Summary and Conclusion
A novel table-based platform is demonstrated for statistical
analysis of circuits in emerging technologies such as FinFET
where compact models for circuit simulations are not available. A new LUT interpolation scheme is proposed for the
accurate process variations study. Effects of process variations
on the performance of three different circuits in FinFET
technology are studied. It is observed that the variations in
L contribute the maximum variations in propagation delay of
the buffer chain circuit and SNM of the SRAM cell circuit.
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