CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
A MULTI-PURPOSE
MICROCOMPUTER SYSTEM
A graduate project submitted in partial satisfaction
of the requirements for the degree of
Master of Science in
Engineering
by
Sima Koosha
May 1985
The Project of Sima Koosha is approved:
Dr. Robert Burger
Professor Soleyman K. Shaolian
Dr. Mohammad R. Roosta
Committee Chairman
California State University, Northridge
ii
To my Parents who made it
all possible, and to·
Dr. Roosta who helped me a great
deal with my accomplishments.
iii
TABLE OF CONTENTS
DEDICATION . .
.
. iii
.
. vii
LIST OF FIGURES
ABSTRACT .
.
.
.
.
X
CHAPTER
I.·
II.
III.
INTRODUCTION . .
1.
Introduction .
1
2.
Objectives . .
2
4
MICROCOMPUTER ARCHITECTURE .
1.
Microcomputer Organization .
4
2.
·z-80 Microprocessor System .
7
. .
Clock and Interrupt Signals . . .
Reset Signal
. . . . . . . . .
Memory Unit . . . . . . .
. . .
1. Memory Map .
2. Addressing Memory . . . .
Read and Write Cycles . . . .
3.
11
Input/Output Organization
23
SYSTEM DESCRIPTION
1.
2.
3.
4.
1.
2.
3.
4.
5.
IV.
1
. .
. . . . . . . .
The 8255 PPI . . .
The LED Display .
The Keyboard
Expansion Capability
. .
. . . . .
Power Supply Section
OPERATIONAL PROCEDURES
1.
Introduction
iv
.
. . . .
.
. .
. . . .
. . . .
. . . .
. . . .
. . . .
11
13
15
15
16
20
23
29
33
37
39
41
41
CHAPTER
Page
. .
1. Execution Command . . . . .
2. Data Entry Command . . . .
3. Data.Display Command
. .
4. Location Counter Set Command
5. Multiplication Command . . .
6. Division Command . . . . .
SOFTWARE DEVELOPMENTS . . . .
. . . .
1. · Main ·Program Descript~on . . .
2. Routine Descriptions . . .
2.
~·
v.
Keyboard Command Description
1.
2.
3.
4.
5.
6.
7.
8.
9.
.
. .
.
.
.
.
· Initialization Subroutine
Keyboard Sample Routine
Get A Character Routine .
Keyboard Scanning Routine
Test Row Routine .
. .
Delay Routine .
. . .
Branch Subroutine .
Decode Command Routine
Command Execution Routine
. .
a.
b.
c.
.
41
.
.
41
43
43
44
45
45
.
47
. .
. .
. .
.
. .
. . . . . .
.
Start Execution Command
Routine
Set Data/Set Location
Counter Command Routine
Display Current Location
Command Routine
. . . . . . . .
. . . . . .
10. NMI Interrupt Handler . . . . .
11. LEDOUT Routine . . . . . . . .
12. BLINK Subroutine
. . .
13. BCD to Binary Conversion
Routine .
. . . . . . .
14. Binary to BCD Conversion
Routine . . . . . . . .
. . .
MISCELLANEOUS PROGRAMS . . . . . . . . . .
1. Diagnostic Program . . . . . . . .
•·
VI.
1.
2.
3.
4.
5.
Initialization
LED Digit Sequencing (TEST 0)
RAM Addresses and Data Test
(TEST 1)
. . . . . . . . . . .
Short RAM Memory Test . . .
NMI Interrupt Processing . . .
v
47
49
49
49
52
53
53
57
57
59
59
59
63
63
67
67
71
71
71
74
74
74
78
78
78
81
CHAPTER
a.
6.
7.
8.
VII.
Clock Frequency, NMI
(TEST 3) . . . . . . .
Output Lines Test (TEST 4)
82
Input Lines Test (TEST 5)
82
Keyboard Scan (TEST 6) . . . . 86
2.
Multiplication Program .
3.
Division Program .
CONCLUSION .
. . ..
. .
.
•
•
•
• 86
•
•
•
90
•
•
•
93
95
REFERENCES
APPENDIX
81
ASSEMBLY PROGRAM LISTINGS .
vi
96
LIST OF FIGURES
Figure
2-1
The Microcomputer System Block
Diagram . . . . • . . . • .
5
2-2
Z-80 Internal Architecture
8
3-1
CPU Clock . .
3-2
MC4024 External Control Determination
for Clock . . . . . . . . . . . .
. 12
3-3 (a)
Non-Maskable Interrupt
. 14
3-3(b}
MC4024 External Control Determination
for NMI . . .
. . . .
. 14
3-4
CPU Reset Operation .
. 17
3-5(a)
Memory Map of System
. 18
3-5(b)
Memory Map Table
3-6
The Memory System .
3-7
Z-80 Opcode Fetch .
. 22
3-8
Z-80 Write Cycle
. 24
3-9
I/0 Section Block Diagram
3-10
PPI Registers .
3-11
Z-80 RD Instruction Cycle .
3-12
The LED Display
3-13
LED Circuitry .
3-14
MC14511 Conversion
. 34
3-15
Keyboard Circuity . .
. 35
3-16
Keyboard Scan Example .
. 38
3-17
System Power Supply Schematic Diagram .
. 40
.
'
. 12
. 19
.
.
. 21
• • 26
.
.
•
•
•
•
•
• 27
.
.
.
.
.
. 27
•
•
• 30
30
vii
Figure
4-1
Operator Terminal
5-1
Main Program Flow Chart .
5-2
Initialization Routine Flow Chart . . . . . 50
5-3
Keyboard Sample Flow Chart
. 51
5-4
GETCHR·Subroutine Flow Chart
. 54
5-5
Keyboar.d Scanning Flow Chart
. 55
5-6
ROW Subroutine Flow Chart .
5-7
Branch Subroutine Flow Chart
5-8
Decode Command Routine Flow Chart .
5-9
Execution Command Routine Flow Chart
5-lO.a
SET Data Command Routine Flow Chart .
.
.
. 64
5-lO.b
SET Location Counter Command Routine
Flow ,Chart . . . . . . . . . . . .
.
.
. 65
5-11
• • 42
. 48
.
.
. 58
60
.
. 61
. 62
Display Location Command Routine Flow
Chart . . . . . . . . . . . . . . .
. 66
5-12
Interrupt Handler Routine Flow Chart
. 68
5-12.a
LEDOUT Routine Flow Chart .
• 69
5-12.b
BLINK Routine Flow Chart
5-13
BCDBIN Subroutine Flow Chart
• • 72
5-14
BINBCD Subroutine Flow Chart
•
• 73
6-1
System Diagnostic Flow Chart
•
• 75
6-2
Initialization Routine Flow Chart .
6-3
LED Digit Test Flow Chart .
6-4.a
RM1 Test Flow Chart
6-4 .b
Short RAM Test Flow Chart .
6-5
NMI Routine Flow Chart
viii
•
•
• 70
76
. 77
•
• 79
• 80
•
• 83
Figure
Page
6-6
Outline Wave Forms . .
84
6-7
Output Lines Test Flow Chart .
85
6-8
Input Lines Test Flow Chart
87
6-9
Keyboard Scan Test Flow Chart
88
6-10
Multiplication Procedure Flow Chart
89
6-11.
Division Procedure Flow Chart
91
6-12
System Schematic .
94
ix
ABSTRACT
A MULTI-PURPOSE.MICROCOMPUTER SYSTEM
by
Sima Koosha
Master of Science in Engineering
In this Project a Z-80 based Microcomputer System is
presented.
The
Sy~tem
is basically designed to execute
programs entered in their machine code through the keyboard.
It is also capable of being interfaced with out-
side world for other applications such as burglar alarm,
telephone dialer, frequency generator or else simply by
software modification.
X
CHAPTER I
INTRODUCTION
l.
Introduction
The digital computer has made a transition from
paraphernalia that required government funding to build
and use, to a circuit component that is ·used in hundreds
of applications.
The microprocessors are now used to per-
form a variety of sophisticated tasks.
chips
Microprocessor
are designed into mixers, radio tuners, microwave
ovens, and many other devices now.
The microprocessor has become a standard engineering
building block, jpst as flip-flops were standard components several years ago.
The appeal of a microprocessor
over discrete logic is that a microprocessor does not have
to be dedicated to performing a single defined task, it is
a general purpose device.
The same circuitry may be pro-
grammed to perform any number of functions.
The multi-purpose microcomputer system is also able
to be used for a number of applications if the software is
modified for the specified application.
The advantage of
this system over a comparable "hard-wired" piece of
equipment is that the latter cannot be charged except by
rewiring whereas the former may be easily changed by
rewriting the program.
As a consequence the system is
1
2
much more flexible and can be put to use for a variety of
applications.
The system presented in this paper is set up to be
used as a multi-purpose computer which executes programs
manually.
It is also provided with DIAGNOSTICS software
to self debug the system in case of any malfunction.
Some arithmetic routines are also burned into the
EPROM for basic arithmetic operations.
The system is designed to be easily capable of being
expanded and interfaced with other systems for different
applications.
2.
The
objectiv~
Objectives
of this project is to design a low
cost and high-speed microcomputer which permits the user
to construct his or her own assembly-language programs
and execute them.
The system is also a multi-purpose
microcomputer, capable of interfacing with outside world
for any other type of applications.
This is achieved by
an extensive use of software to implement all the
functions.
The microcomputer system provides a feedback to the
user in case of operator error also.
The system provides the following capabilities:
1) Input program
2) Execute program
3
3) Output the result
4) Detect errors
In addition to the aforementioned it provides the
following capabilities not commonly found in low cost
microcomputers:
1) Mult·iply numbers as entered by operator
2) Divide numbers as entered by operator
CHAPTER II
MICROCOMPUTER ARCHITECTURE
1.
Microcomputer Organization
In this section, the general theory behind the Z-80
based microcomputer is discussed.
As it is shown in
Fig. 2-1, the system consists of 8 blocks.
The CPU or
central processing unit is the main controlling component
of the system.
It fetches and executes instructions from
memory and also oversees all system functions.
The CPU operates at a constant rate called the clock
frequency.
Every action in the CPU is broken down into
increments of this clock frequency.
The Z-80 microcom-
pressor is capable of operating at a clock rate of· up to
4 MHZ.
The clock frequency chosen for this system is
1 MHZ to utilize a less expensive version of the Z-80 and
to provide a good design safety margin.
The block called
clock (Fig. 2-1) is the circuitry that generates the 1 MHZ
clock pulse.
The period of the clock is 1 microsecond (1 MS).
Every action taken in the CPU occurs in increments of
half the period.
Each instruction that the CPU executes
varies from 4 clock periods to over 20 clock periods,
therefore instructions may be anywhere from 4 microseconds to over 20 microseconds long.
4
5
Clock
H
---1
LED
Display
I
Output Lines
I/0
Section
(PPI)
CPU
I
Input Lines
I~
NMI
Interrupt
1-i
j
Keyboard
Memory
r;:-----i
I
I
I
I
I
EPROM
II
I
I
I
rI
I
I
'
I
RAM
I
~
I
I
I
I
~---
Fig. 2-1.
I
_!J
The Microcomputer System Block Diagram
6
The NMI interrupt block is used to signal the CPU
that another 1/100 of a second in the real world has
passed.
The 1 MHZ CPU clock cannot be used for this
function because the CPU cannot reasonably keep track of
how many clock cycles have elapsed.
The memory block of Fig .. 2-l is another major
component of the system.
Every computer has a memory to
store programs and data.
The memory block consists of two
types of memory:
EPROM and RAM.
The 2716 EPROM is used in this project.
(2K) memory locations, each 8-bits wide.
It has 2048
The CPU
retrieves data one byte at a time from the EPROM by sending out an address over 16 address lines.
At about the
same instant that' ·the CPU puts the EPROM address on the
address lines, it reads in the data from 8 data lines.
In
this system the EPROM holds both the computer program
broken up into 8-bit bytes and also some constant data.
The 6116 RAM is used in this system with the capacity
of 2K memory location each 8-bit wide.
The input/output or I/0 section of Fig. 2-1 allows
communication with outside world.
In this project the
outside world is connected by 24 lines from an 8255 PPI,
or programmable peripheral interface chip.
lines go to the LED display.
Eight of these
Another 3 lines are input
lines that come from the keyboard.
input lines from the outside world.
Another 5 lines are
These lines could be
7
connected to burglar alarm switches, fire sensors, etc.
The remaining 6 lines are output lines which are used to
send data from the system to outside world, possibly to
open doors, send audio signals to a speaker, etc.
The PPI is an I/0 interface that is addressed
similarly to a memory location.
The CPU can send one byte
to the PPI and the· PPI will then route it to the. appropriate set of lines to display LED data or to signal outside world.
The CPU may also read one byte of data repre-
senting the state of five input lines or a digit from the
keyboard.
2.
The Z-80
Z-80 Microprocessor System
mic~oprocessor
is an 8-bit microprocessor
that has been extremely popular for all types of designs
incorporating a general-purpose microprocessor.
It
requires a minimum amount of support circuitry, that is a
working microcomputer can be implemented using just a few
additional components with the Z-80.
This microprocessor
includes all of the 78 instructions of the 8080 and adds
quite a few more to provide about 158 total instruction
types.
In addition, the speed at which instructions can
be executed is about twice as fast as 8080.
The Z-80 architecture is shown in Fig. 2-2.
Thirteen
CPU and system control signals are sent to or generated in
the instruction decode and CPU control portion of the
microprocessor.
The data bus is eight bit wide.
The
8
Internal
Data Bus
...
L
ALU
,
....
I
"
~-
"
Instruction
Register
,,
Control
Signal
.
...._
""
r
8-Bit
Data Bu s
,.
~
...
'
,...
Data Bus
Control
..
CPU
Registers
---....System
,."
CPU
System
Control
Signal
Fig. 2-2.
r--7
Address
Bus
Control
.....
7
16-Bit
Add res s Bus
...., Internal Control
Z-80 Internal Architecture
9
address bus is 16 bits wide.
Normally the address bus
would specify an external memory address of 0 to 65535
(0 to 64K) since the Z-80 has a full complement of input/
output instructions and no memory-mapped input/output
would be required.
The main path for data within the CPU is an internal
data bus which connects the CPU registers, arithmetic
logic Unit (ALU), data bus control, and instruction
register.
The Z-80 has fourteen general-purpose 8-bit registers
designated A, B, C, D, E, H, and Land A', B', C', D', E',
H' and L'.
There is a flag register which is an 8-bit
register used to specify various CPU conditions that
occurred after
a~.arithmetic,
hav~
logical or other CPU
operations.
The Z-80 has 6 special-purpose registers available:
I, R, IX, IY, SP, and PC registers.
The SP and PC are
respectively stack pointer and program counter registers
each 16-bit long.
The index registers IX and IY are two
16-bit registers that permits indexed addressing in Z-80
programs.
The Interrupt Vector Register I is an 8-bit
register that can be loaded with 8 bits of data specifying
a memory address.
This address when combined with a
lower-order byte of address supplied by the interrupting
device, represent a memory address whose contents in turn
10
specify the beginning memory address of the software
interrupt handling routine for the device.
The last special-purpose register is the 7-bit
Memory Refresh register R.
When external memory is made
up of dynamic memories, the R register allows automatic
refreshment.
Ih this project registers I and R have not been used
since non-rnaskable interrupt and static memory have been
chosen~
CHAPTER III
SYSTEM DESCRIPTION
1.
Clock and Interrupt Signals
The clock input is a simple square-wave input that
appears as shown in Fig. 3-1.
wave is 1 MHZ.
and to
~ive
The frequency of the square
This frequency was chosen for convenience
enough tolerance for the type of clock cir-
cuitry chosen.
The clock circuit shown in the figure is
a multivibrator circuit contained in one-half of an MC4024
integrated circuit.
This chip produces a square wave out-
put dependent upon the value of the capacitor and resistor
attached to Pin 3, and 4 of the chip.
The circuit required
to produce 1 MHZ frequency is shown in Fig. 3-2.
Every instruction executed within the Z-80 is divided
into T cycles, which are essentially clock cycles.
Each
cycle is one microsecond long.
The NMI signal or non-maskable interrupt signal is
generated by the second half of the MC4024 chip.
This
signal is another square-wave signal that has a frequency
of about 100 HZ.
The NMI input causes a non-maskable
interrupt to occur every 1/100 of a second when the NMI
make a transition from high to low generating an interrupt
signal to CPU.
The effect of NMI interrupt is to cause
the CPU to stop execution of the current instruction and
jump to location 102 decimal (66 HEX).
11
Location 102 has
12
I
MHZ.
Fig. 3-1.
l
CPU Clock
t<, = 325
c lt --
c.=
Fig. 3-2.
32s -S=.32o
I
MC4024 External Control Determination
for Clock
13
(.l
been defined as the NMI interrupt location (certain other
locations lower than 102 are dedicated for other possible
interrupts which are not implemented in this project).
As the NMI interrupt is implemented by the CPU, the
contents of the program counter is pushed into the stack
and then the instruction at location 66H is executed.
The
routine at 66H must somehow save the status of system.
The easiest way to do this in here is s{mply to switch to
alternate set of registers by two exchange instructions.
Interrupt processing now proceeds for the NMI condition.
At the end of processing, two exchange instructions
restore the CPU registers and flags to their status at the
time of the interrupt.
Then a RETN instruction pops the ·
'
program counter from the stack and causes the CPU to
start execution of the next instruction.
Usually the NMI is used to handle a catastrophic
condition in a microcomputer system, such as a power
failure.
In this system, it is used to count every pulse
that occurs.
By calibrating the pulse rate, the real-
time clock could also be implemented.
The circuit required to produce 100 HZ frequency for
NMI signal is shown in Fig. 3-3(a) and 3-3(b).
2.
Reset Signal
The RESET signal is an active low input that is used
as master CPU reset.
This signal would be brought low
immediately after power up, or at any time when the
'
14
Z-t<t>
c..pu
Fig. 3-3(a).
Fig. 3-3 (b).
Non-Maskable Interrupt
Mc4024 External Control
Determination for NMI
15
microcomputer system was to be reset.
When the RESET is
brought low, the following actions will be taken:
1.
The interrupt enable flip-flop is disabled,
preventing system interrupts except for NMI.
2.
Register I is set to OOH.
3.
Register R is set OOH ..
4.
Int~rrupt
5.
The address bus goes to a high-impedence
mode 0 is set.
state.
6.
The data bus goes to a high-impedence state.
7.
All output-control signals go to the inactive
state.
The RESET signal, therefore, causes Z-80 to clear the
PC register and a~ter a short pause, start execution from
memory location 0.
An input like RESET is obviously
necessary to allow the CPU to start from a known point.
The circuitry required for the RESET signal is shown in
Fig. 3-4.
A momentary switch resets the CPU and starts
program execution at location 0.
3.
3.1
Memory Unit
Memory Map
One of the design criteria in this project has been
its reasonable cost.
To reduce the number of components
used, memory was limited to 2K EPROM (2716) and 2K RAM
(6116).
16
The memory map of this system is shown in Fig. 3-5(a).
The unused locations in the 65536 maximum memory size are
shown in shaded areas.
Location 0 to 2047 are the memory
locations of the 2716 EPROM chip.
Locations 2048 through
4095 are memory locations of 6116 RAM.
3.2
Addressing Memory
In order to recognize.between the RAM and the EPROM
while they are being addressed by the CPU, the table shown
in Fig. 3-5(b) is organized.
In this table the difference
between the accessible addresses for both the RAM and the
EPROM is shown.
It appears that address line A
is never
11
on one for an address in the EPROM area and always a one
for an address in,the RAM area.
line selects either RAM or EPROM.
Therefore A
address
11
This selection is
accomplished by connection A
to pin 20 of the ROM and A11
11
to pin 20 of the RAM.
Both pin 20's of the RAM and the ROM
are OE (Output Enable) lines.
There is also other requirements that need to be done
in order for CPU to make connection with the memory.
The
CS (Chip Select) lines, on both pin 18 of the RAM and the
ROM, should be connected to MREQ (Memory Request) of the
CPU.
The CPU sends this signal when need to talk to mem-
ory.
The CPU also sends a WR signal to the RAM when writ-
ing to RAM is desired.
Fig. 3-6.
The memory system is shown in
17
~
~--+----4·RE£f
(.1
2.-'6~
c. pu
1""~ O·i'.
R:
t...
=?
Fig. 3-4.
c
10
_L
R<...
Sc.L.o ...
J.:.
K
-==?
c. s
~~ ~
--L- :
'LI<
;l;l
CPU Reset Operation
.:lb
J-<.f
/vj
18
EPROM
RAM
Fig. 3-5(a).
Decimal
Location
Hex
Location
0
0
2047
07FF
2048
0800
4095
OFFF
65535
FFFF
Memory Map of System
Al5
Al4
Al3
Al2
All
AlO
Ag
AS
A7
A6
AS
A4
A3
A2
Al
AO
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
EPROM
~~~~-~7FF
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
RAM
~8~~-~FFF
Fig. 3-S(b).
Memory Map Table
I-'
1.0
""
20
3.3
Read and Write cycles
The sequence of read and write operations performed
by the system is helpful to understand the system operation.
Fig. 3-7 shows the read operation during the fetch
of the first one or two of the instruction bytes.
period is 1 microsecond long.
Each T
The f.irst action taken by
the CPU is to put. ·address onto the address bus lines
A15 -A 0 ·.
(The Ml signal indicates that this is the "opcode"
fetch) •
The CPU then causes MREQ and RD to go low, indi-
eating to external logic that a memory read is being made.
From this point on, the memory being addressed has about
1-1/2 T states to respond.
The memory responds as follows:
It knows by the MREQ
'
that the CPU wants to read or write one byte of data via
the data bus.
WR
If the memory is RAM, it knows by state of
signal whether a write or read is required.
If the
memory is ROM, then it is always read state.
In general case, if the chip is selected, the memory
chip looks at the address present on the address bus, and
then outputs data on the data bus.
At the end of Ml, the
CPU reads the data into an internal register for decoding.
Subsequent reads of remaining instruction bytes are
done in the same fashion, except that only three clock
cycles are used.
The "opcode" fetch of the first one or
two instruction bytes is longer to allow the refresh
21
DB
if
•
AB
-~6
A
20
11
-
OE
AB 10
,
·•
2716
EPROM
MREQ
L.[:::;.
18
CE
20
-
OE
DB
AR
8
10
,
6116
RAM
R
Fig. 3-6.
18
-
21
-
DB
8
cs
WE
The Memory System
.
8
22
M:~Ji )fs
Tl
T2
T3
T4
~
Address
Bus
~
Contents of Prog.
Counter put on
Address Bus
'
Data
Bus
Data
Fig. 3-7.
Z-80 Opcode Fetch
23
register (R) to be sent to system dynamic memories, if
the system has any.
Writes to memory are done only during the execution
portion of an instruction, so the "opcode" fetch is not a
consideration.
The write cycle starts off similar to read
cycle as shown in Fig. 3-8.
The address of the memory
location to be written into is put on the address bus.
Signal MREQ is activated.
Shortly after, the CPU outputs
the data to be written to memory onto the data bus.
At
this time the memory starts to actually do a read of the
specified location.
However, signal WR is brought low,
and the data is written into the specified memory location.
4.
Input/Output Organization
The interface between the Z-80 microprocessor and
8255 programmable peripheral interface (PPI) is discussed
in this section.
In a sense the PPI is like a small micro-
processor in itself.
It accepts commands from the Z-80
and handles the tasks of inputting and outputting data
from 24 I/0 lines.
The logic associated with the LED
display, keyboard, input lines and output lines is also
discussed here.
4.1
The 8255 PPI
Fig. 3-9 shows the block diagram of the I/0 unit.
The PPI acts as an intermediate buffer between the Z-80
24
'
M-=3)1-::
T2
Tl
.:~
~
Address
Bus
~
T3
.,.,
.
·~
CPU Outputs Address of
Memory Location to be
Written
,__
~
.
CPU Outputs Data to be
Written to Memory
Data
Bus
Fig. 3-8.
Z-80 Write Cycle
25
CPU and the outside display, keyboard, input lines, and
output lines.
The PPI consists of four registers similar to the
registers in the Z-80 CPU.
Each register is 8-bits wide.
Three of the registers connect to three sets of eight
input/output lines as shown in Fig. 3-10.
The CPU can read or write to each of the four
registers in the PPI by an RD (read) or WR (write)
instruction.
Executing an RD A,
(2) instruction, for
example, reads register 2 of the PPI into A.
The four registers are addressed by addresses of 00,
01, 10, and 11.
Two address lines come into the PPI, Al
and AO; and these two lines are all that are required to
'
hold the 2-bit address
to specify the PPI register
involved.
Any time an I/0 instruction (RD or WR) is exe-
cuted, the program must be talking only to the PPI and no
other device.
To differentiate between memory and I/0
communication the IORQ signal is connected to PPI (Pin 6).
The IORQ is a zero only when an RD or WR is executed.
The
direction of transmission is decoded by the PPI from the
WR and RD signals.
Fig. 3-11 shows the signals during an
RD instruction from the CPU signal viewpoint.
When an RD
is executed, the CPU first puts the address of the I/0
device on the address bus lines A7-AO.
The format of the
I/0 instruction specifies only an 8-bit I/0 address, so
the number of devices that may be addressed are 0 to 256.
26
LED
Buffer
PA 4 -PA
WR
LED Display
~
7
PA 0 -PA
H
3
4
LED
Driver
7
~
Output
Buffer
6
~
RD ..
IORQ
Z-80
CPU
Al
, Al
Ao
.. Ao
PB -PB
0
5
....
7
Out
8255
PPI
8
Data
'
Bu~'
PC -Pc 7
3
~
Input
Buffer
5
....
I:J
PC -Pc
0
2
)
AB
4
Keyboard
Buffer
4
Keyboard
Rows
3
Columns
Fig. 3-9.
I/0 Section Block Diagram
,,
'
27
M
Register· 0
H Register
To
Z-80
CPU
I
l
-f Register 2
l
.-{ Register 3
1-
Internal Control
~
·•
Fig. 3-10.
Address
Bus
l
To Outside World
t
PPI Registers
I/0 Address from RD
Instruction
Data
Bus
Data from I/O Device (PPI)
Fig. 3-11.
RD Instruction Fetch Cycle
28
In this project only four addresses are used:
0, 1, 2,
or 3.
Shortly after the address is put on the address bus
the CPU "brings down" the IORQ and RD lines to low.
The
PPI looks at the two address lines of Al and AO to determine which one of the four registers to be read.
puts the
contents.~f
It then
that register on the data bus.
In
the middle of Third T cycle, the CPU inputs the content of
the data bus into A.
The PPI is a general-purpose device.
It is meant to
be as versatile as possible in allowing a microcomputer
systems designer to build a microcomputer with a few parts
that can do variety of tasks.
several different' ·modes.
The PPI may be set up in
Mode 0 is "basic" Input/Output,
mode 1 is "strobed" Input/Output, and mode 2 is "bidirectional bus."
All three have their uses in various systems.
The "strobed" mode allows "handshaking" sequence between
PPI and other devices.
The "bidirectional" mode allows
each line to be used for transmitting data in two directions between PPI and other devices.
The mode used in
this system is the ,;basic Input/Output" mode or Mode 0.
In Mode 0, lines PA7-PAO can be set up to be all
inputs or all outputs, but not a mix.
Lines PB7-PBO can
be set up to be all inputs or all outputs.
Lines PC7-PCO
are further subdivided into two sets of four each and each
29
set can be either inputs or outputs.
In this project it
is chosen to have the following combinations:
PA7-PAO
PB7-PBO
PC7-PCO
All Outputs
All Outputs
All Inputs
Address 0
Address 1
Address 2
The first action that must be taken before performing
input or output operations with the 24 lines of the PPI is
to· prOgram the PP·I by sending out the proper control word
to PPI control register (register 3).
This control word
is stored in the control register and remains there as
long as power is applied to the PPI.
The control word for
mode 0 is 89H.
Having output the proper control word to the control
register of the PPI, the PPI is now ready to be used to
transmit data between the CPU and "outside world."
"outside world" is divided into four areas:
The
The LED dis-
play, the keyboard, input lines, and output lines.
4.2
The LED Display
The LED display used in the system is a garden
variety six-digit display.
of display are used.
In this project only 4 digits
Four decimal digits from 0 to 9999
can be displayed.
The LED display is shown in Fig. 3-12.
The LED
display used here is a type of display called a commoncathode type.
All segments of the four digits are con-
nected in parallel and a common set of seven lines, one
30
Fig. 3-12.
-
The LED Display (DL-6500)
7'131
,,
<.z.
......
_j
k.
_j
82.SS
FPt
OL- '5"oo
~
(. _d,
I
Fig. 3-13.
t
'
I
I
,.,..,~,
I
(
I
LED Circuitry
31
for each segment, come out of the chip on pins
12, 11, 3,
8 , 2 , 9 , and 7 .
The LED circuitry is shown in Fig. 3-13.
The four
lines labeled Cl, C2, C3 and C4 are connected to the cathodes of each of the digits.
When one of these lines is at
ground potential (0 volts) and at least one of the anode
lines a-g is at +5 volts, current flows through the diode,
which
t~en
No
emits a red light.
more than one cathode line can be at 0 volts at
one time, so that at any given time only one digit is displayed on the four-digit display in one position only.
By
rapidly alternating between one digit position and the
next, the display shows all four digits at one time.
Every 1/100 of a second, a new set of inputs at a-g and a
new cathode line is enabled.
played every 1/25 of a second.
All four digits are disTo the eye this multi-
plexed display appears to be a single display of four
digits.
Displaying any series of four digits on the LEDs,
then resolves down into rapidly switching inputs to the
LED display.
All that should be done with PPI is to
ensure that every 1/100 second a new cathode line (Cl, C2,
C3 or C4) is enabled in sequence and put out a new set of
the seven segment lines at the same time.
Switching the cathode lines is easy.
The four
cathode lines are driven by the inputs of the 7437 chip.
32
This chip is a high-current inverter, providing more
current drive capability.
To output a zero to one of the
cathode lines, one of the upper four bits in the first PPI
register must be a one and the rest zeros.
This can be
done by performing an output instruction to the first PPI
register (Address 0).
CPU
i~
zeros~
First of all,. the A register in the
loaded with the proper configuration of ones and
Next a write instruction is executed to send the
contents of A to the register in the PPI.
LD
Out
For example:
A, 23H
(O),A
outputs 3 to C3 and lights up 3rd digit.
In order to enable the seven lines going to the seven
segments of the
~isplay
with only four lines from the PPI,
the MC14511 chip is used.
The MC14511 gives capability to
use only four output lines to generate the proper sequence
of the LED segments.
The MC14511 takes four input/output from the 8255
lines, assumes they contain the binary equivalent of 0-9,
and converts the input digit to the proper sequence of LED
segments.
The table of conversion is shown in Fig. 3-14.
Note that the input values 1010, 1011, 1100, 1101, 1110
and 1111 are invalid inputs and produce no display at all.
In addition to translating from binary into segments, the
MC14511 provides additional drive current capability.
PPI by itself would not be able to meet the current
requirements of the LED display segment inputs.
The
33
The resistor network limits the current through the
LEDs.
This is necessary because the circuit has very low
resistance when a segment is enabled.
The resistors limit
the current to the proper value for adequate brightness.
4.3
The Keyboard
The keyboard of this system is very simple affair to
keep costs of the project low.
The keyboard and associated
circuit"ry is shown in Fig. 3-15.
connects a row with a column.
Pressing any key simply
When no key is pressed the
inputs to the PPI register 2 on lines PC2, PCl and PCO are
Vee or about +5 volts, logic ones.
When a key is pushed,
two lines are connected and the column line associated
with the key is connected to the row
lin~
associated with
the key.
The column line goes to one of three inputs in the
three lower bits of the PPI.
The column line reflects the
state of the connected row output from the 74LS05 chip.
If the output of the inverter for the row is a zero (0
volts), then the input to the PPI will be zero and if the
output is a one, the input to the PPI will be a one.
To
detect a key depression, then it can be stated that if the
key is pushed and the inverter output is a zero, then the
input to the PPI for the column associated with the key
will be zero.
If it is certain that only one inverter
output is zero at a time, then it can pinpoint the key by
its row (inverter number) and column (bit position).
34
Input Lines
to MC14511
D C B A
Output Lines
from ~1C14511
a
c d e
b
f
·g
0
0 0
0
0
1
1
1
l
1
1
0
1
0 0
0
1
0
1
1
0
0
0
0
2
0 0
1
0
1
1
0
1
l
0
1
3
0 0
l
1
1. 1
1 .1
0
0
1
4·
0 1
0
0
0
1
1
0
0
1
1
5
0 1
0
1
1
0
1
1
0
1
1
6
0 1
1
0
0
0
1
1
1
1
1
7
0 1
1
1
1
1
1
0
0
0
0
8
1 0
0
0
1
1
1
1
1
1
1
9
1 0
0
1
1
1
1
0
0
1
1
1 0
1
0
0
0
0
0
0
0
0
"
1 0
1
1
0
0
0
.o
0
0
0
II
1 1
0
0
0
0
0
0
0
0
0
II
1 1
0
1
0
0
0
0
0
0
0
II
1 1
1
0
0
0
0
0
0
0
0
"
1 1
1
l
0
0
0
0
0
0
0
Number
(None)
Fig. 3-14.
MC14511 Conversion
35
·•
55
..:·
R,;r
PI
A,l
A,l.
~
.
"!!. Ss
'( s.,
>,(
$<.
'<51
'( s,
f..i
s,
'( s..
'( 5.
~~
s ..
'(
A,~
'('Sl
ftz
P<·
Pr.l
I
Fig. 3-15.
Keyboard Circuitry
36
As is shown in Fig. 3-15, the rows of the keyboard
are address bus A , A , A , A .
14
12
15
13
By continually
sequencing A , A , A
and A
and observing the bits
15
14
13
12
PC 2 -Pc 0 , a key depression can be detected and the key number can be found by noting which of the bits is a zero and
which of the four row inverter outpu-ts was a one.
This process· is called Keyboard Scanning and is a
common _technique for detecting and decoding keyboards.
The scanning in this system is implemented by simultaneously enabling one of the A , A , A
or A
address
15
14
12
13
lines and reading in the state of PC2 or PCO.
If all
three low-order bits in the PPI third register are ones,
then no key has been pushed.
In this case, the next
address line is eriabled and a new row is read.
The key to the technique in this system is that the
RD (read) I/0 instruction puts the contents of the CPU A
register on address lines A -A at the same time that the
15 0
read is done of lines PC7-PCO.
By putting the proper value
in the upper four bits of the A register, one address line
of A , A , A
and A
is selected at the same time that
15
14
13
12
data is read in from PC2-PCO.
A
is shown in Fig. 3-16.
13
with 0010 0000.
The sequence for selecting
First the A register is loaded
This value will go into address lines
A -A , when the read is performed. Next an RD (read) is
15 8
performed of PPI register 2. During the time that the
address (2) goes out on address lines A7-AO the upper
37
eight address lines A -A hold 0010 0000 and A
is
15 8
13
enabled.
If any of keys 57, 58, or 59 is pressed, the
corresponding input bit will be a zero.
This sequence is
repeated rapidly for all four rows until a zero is found
to indicate a
~ey
depression.
The actual instructions
used are discussed further in Chapter 5 of this paper.
4.4
~xpansion
Capability {Output and Iriput Lines)
The system has six output, lines that are not
dedicated to any internal task.
They are general-purpose
lines used to provide an output of one or zero for the
outside world.
The six outputs can be used individually
to control six On/Off conditions such as relays
or lights.
~
These output lines from the six low-order bits of the PPI
register 2 are buffered by the inverters in the 74368 chip.
This chip provides higher current drive capability to
drive external devices.
The top five bit positions of the PPI register 3 are
used as input lines.
External world inputs of On/Off con-
ditions can be scanned rapidly to detect switch closure or
other applications.
As in the case of output lines, the
inputs are buffered by six inverters on the 74L504 chip.
The main purpose of these inverters is not for current
drive, but to prevent outside signals from destroying the
relatively expensive 8255.
38
LD
A, 20H
RD
A,
Select A
13
Read
KB Row A
13
(2)
A now contains:
6
7
IN1
IN 2
5
IN3
4
IN4
....
'\..
2
1
0
KB
Col.
1
KB
Col.
2
KB
Col.
3
3
-INS
State of Input Lines
Fig. 3-16.
./
J\,
Keyboard Scan Example
""'
39
5.
Power Supply
Fig. 3-17 shows the schematic of the power supply
for this system.
This is a Linear Power Supply, con-
sisting of a linear AC transformer that converts 115 V AC
input to 12 V AC output.
A full wave bridge rectifier
converts transformer AC output to DC and finally a 3
terminal voltage
to 5V.
~egulator
regulates the output voltage
The capacitors on the output are for noise reduc-
tion and smoothing purposes.
of driving 5V at 3 Amps.
This power supply is capable
The microcomputer system
nominally requires about 1 Amp.
.
'
40
0
.,.
'il ttl I~·"
Vo.c..
-'-Jf
T•o .... s.~.--.c.r
2 \o 3 R..,f·
Fig. 3-17.
System Power Supply Schematic Diagram
'
CHAPTER IV
OPERATIONAL PROCEDURES
1.
Introduction
This system is controlled through an operator
terminal which consists of the following:
display, reset switch.
is
sho~n
keyboard, LED
A picture of the operator terminal
in Fig. 4-1.
Upon power up the system initializes the registers
and the stack, and clears the display.
the scan mode, waiting for a command.
Then it goes into
The display is
initially set up for 4 digits, since the only possible
entries are commands with up to 5 BCD digits.
These com-
mands could be for entering the machine codes of a program,
executing a program, setting program counter to some
value, multiplying numbers, and dividing numbers.
These
commands are described next.
2.
2.1
Keyboard Command Description
Execution.Command
This command starts execution at location defined by
current location counter.
Typically all machine codes
will be entered by the Data Entry Command, then location
pointer will be reset to the beginning address of the
entered program, and an Execution Command will then start
executing the program.
41
42
m0
0
GJ. CD 0
t2J 0 GJ
~
0
Fig. 4-1.
~
Operator Terminal
43
The steps of this command are:
Keyboard/Display
2.2
Comments
1
0
Start execution at the
current location counter
2
#
Display the result and get
ready for next command
Data Entry Command
The Data E_ntry Command enters the data specified
with this command into the current location and then
increments the content of location counter.
These are the steps required for this command:
Step
Keyboard/Display
1
1
2
nnn
3
#
Comments
Enter at current location
counter
this data nnn
Zero out the display, get
ready for next command
The nnn data represents a 3 BCD digit number, which
is an 8 bit binary number.
Therefore only one byte of
data could be entered at any time.
This command is used to enter the machine-codes for
the operator's programs into the RAM only.
2.3
Data Display Command
This command displays the data at current location
and increments location counter by one.
steps should be taken for this command:
The following
44
Keyboard/Display
Comments
1
2
Increment current location
counter
2
#
Display the content of
previous location
Pressing "#" again displays next location.
Entering
"0100" followed by "2" for example, sets the current location counter to decimal 100 and then displays the contents
of location 100 (in the ROM area).
RAM locations may be examined.
Note that both ROM and
This command is useful for
operator to check his entered machine-codes into the RAM
locations.
2.4
Location Counter Set Command
The Set Command is used to set the location counter
to some location specified within the same command.
The
location counter points to the location to be displayed or
into which data (instruction) will be entered.
The steps
of the set command are:
Step
1
2
3
Keyboard/Display
3
nnnn
#
Comments
Set location counter
to this data nnnn
Zero out display and wait
for next command
The nnnn data represents the location of the program in
the RAM.
Therefore the limits of nnnn are 0 to 4095.
45
2.5
Multiplication Command
This command multiplies numbers entered by the
operator until the end of the sequence is reached.
The
steps of this command are:
Keyboard/Display
Comments
; get ready for
multiplication
1
4
2
nnn
#
number.nnn is multiplier
enter the number
4
*
clear the display, wait
for next number
5
nnn
; multiply by this multiplicand (nnn)
6
#
7
*
display the result
there are more numbers
to multiply
; get the next number
(go through step 4-6)
#
8
; end of the sequence;
zero out the display; wait
for next command
The multiplication routine is limited to 8-bit by
8-bit multiplication, since there are only 4 BCD digit
display available.
The nnn number represents an 8-bit
number again.
2.6
Division Command
The Division Command is for dividing numbers entered
by the operator through the keyboard until the sequence
is ended.
command:
The following steps are required for division
46
Step
Keyboard/Display
Comments
get ready for division
1
5
2
nnn
3
#
enter it
4
*
get ready for next number
4
nnn
5
#
divide out and display
the quotient
"6
0
display the remainder
7
#
; end of the sequence;
clear the display unit for
another command
nnn is dividend
get the divisor
The division steps could be modified for successive
multiplication in the same way as steps 6 and 7 of the
multiplication
co~and
routine.
CHAPTER V
SOFTWARE DEVELOPMENTS
1.
Main Program Description
This chapter describes the software techniques and
approach used in the development of the programming of
this microcomputer system ..
The Main Program is responsible for accepting data
and commands from the keyboard, executing commands and
controlling of display update through the INTR (Interrupt)
routine.
The flow chart of the main program is shown in
Fig. 5-l.
The first section is initialization routine.
This routine initializes the memory buffers, software
variables and system hardware.
a keyboard scanning mode.
the commands.
Then the system goes to
It stores data and recognizes
The command then is decoded and executed.
Once the result is obtained from the command execution,
the system is ready for another command.
The INTR (Interrupt) routine is running continuously
every 1/100 of a second.
display.
This routine is updating the
It is running independently of commands and
operations.
47
48
Initialization
Sample
Keyboard
Store Data in
Input
Buffer
y
N
Decode
Command
Execute
Command
Update
Display
Store Result
in LED
Buffer
Fig. 5-l.
Main Program Flow Chart
49
2.
2.1
Routine Descriptions
Initialization Subroutine
The primary subroutine in the ROM area is the
initialization subroutine INIT.
When INIT is called at
the start of main program, it initializes the 8255 PPI by
outputting an 89H.
This sets up the 8255 as 8 sets of
outputs (PA7-PAO), 8 sets of outputs
of inputs (PC7-PCO).
(P~7-PBO),
and 8 sets
The second thing the INIT does is
to move certain variables from the ROM to the RAM area
starting at PROGR or 824H.
In moving the variables, they
are initialized to initial conditions which are necessary.
Every time the INIT is called, this default sequence is
loaded into RAM . . The flow chart of this subroutine is
shown in Fig. 5-2.
2.2
Keyboard Sample Routine
Sample keyboard routine is a subroutine called INPUT
subroutine.
line.
This subroutine inputs a complete command
A command line is defined as a string of characters
making up a command and terminated by an "#" key.
As it
is shown in the flow chart of this subroutine, Fig. 5-3,
another routine is used to get a character from the keyboard (Get Character).
If the character is an END ("#"),
there will be a return from INPUT subroutine terminating
the input sequence.
"*" key (Back Space).
Otherwise the program checks for a
If a "*" is encountered then the
50
Init.
!nitialize Ports
Move
Initialization
Data to RAM
Fig. 5-2.
Initialization Routine
51
Input
Store Char.
in LEDBUF
(Display it)
Get a
Character
N
Replace
Character
By the Last
Char. Entered
y
Store Char
in Input
Buffer
Fig. 5-3.
Keyboard Sample Flow Chart
52
last digit entered through the keyboard is replaced by
the digit that operator enters next.
If it is not a "*"
or a ''#", then character will be stored in the INPUT buffer called INBUF and also stored in LEDBUF for display.
The number of characters entered is checked every time a
new character is stored.
If this count is less than or
equals 16, then the system looks for another character,
until the sequence is ended ("#").
In case of more than
16 characters, the system over writes the last digit
entered through the keyboard by the next entering digit,
which is the same idea as "*" keyboard command.
(The
system does not allow more than 16 digits in a string of
characters. )
2.3
Get a Character Routine
A subroutine called GETCHR replaces this routine.
GETCHR is truly a get character subroutine.
After a char-
acter is detected, GETCHR delays 10 milliseconds for key
release.
If it did not do this, it would appear that the
key was being pressed many times.
As it is shown in Fig. 5-4, there is a scan keyboard
routine which scans the keyboard for a character or likewise a key pressed.
this subroutine.
Also there is a debounce section in
In the debounce section, the system
makes sure that the key is back to a normal position which
is "not-pressed."
Then the Delay routine follows.
It
53
gives 10 ms to the system to get ready for another key
depression.
2.4
Keyboard Scanning Routine
This routine is called KEYSCN subroutine.
The KEYSCN
subroutine returns the value of the key that is being
pressed or -1 for "*" or "-2" for "#" key.
being pressed, the
As
z
If no key is
flag is set upon return.
it is shown in flow chart of Fig. 5-5, the value
of first row right hand key is stored, which is "3", then
the first row is enabled.
To check for key depression in
that row a routine called ROW is used.
If the key is not
found then the value of second row right hand key is
stored ("6") and .then a call to ROW routine is performed.
This follows in the same fashion until the key is found.
In case of last row, the value of right key is
assumed to be 3.
If the key pressed happens to be one of
these 3 last row keys, then values of -1, -2 and 0 are
assigned in order to "*", "#", and 0 keys.
2.5
Test Row Routine
The Test Row Routine is called ROW subroutine in the
system programs.
This subroutine takes a keyboard row
address of SOH (row 1), 40H (row 2), 20H (row 3) or lOH
(row 4), reads the keyboard row and searches for a specific column key which has been pressed.
If a key is
pressed, the initial values of 3, 6, 9 or 3 (which are
54
Get Chr
Scan
Keyboard
Save
Character
Debounce
The Key
Delay
10 ms.
Fig. 5-4.
GETCHR Subroutine Flow Chart
55
Key Sen
Enable
First Row
Save First
Right Hand
Key Value
Enable
Second
Row
Save First Right
Hand Key of Row
Fig. 5-5.
Keyboard Scanning Routine
56
Enable
Fourth
Row
Decrement
Key Value
By 2
'First Right Key
·value= 3
Set
Zero
Flag
Reset
Zero
Flag
Return
Fig.
5-5.
Continued
57
the values of the right hand key orr every row, considering
a value of 3 for an r'#")' is decremented to the proper
value for the key.
value becomes 0.
If no key is pressed the returned
The flow chart of this subroutine is
shown in Fig. 5-6.
2.6
Delay Routine
This subroutine could· create a
milliseconds where desired.
del~y
of up to 65535
This is done by executing a
timing loop of 1 msec. for any number of times required
depending upon the necessary delay.
Therefore the total delay is computed by number of
execution of·the loop (Count Number) multiply by 1 msec.
This Count Number. will be set in HL register pair.
2.7
Branch Subroutine
The major task of this subroutine is to sample
keyboard and decode command.
This is done by calling
INPUT subroutine which in turn will accept a command
string and determines whether it is a valid command or
not.
If a valid string of characters has been input,
then the BRANCH subroutine goes to Decode Command Routine.
After decoding command, there is a jump to the
location containing the execution of the decoded command.
The flow chart of BRANCH routine is shown in Fig. 5-7.
Since the INPUT subroutine is already described in
58
Input
Columns
Right Hand Key
Value -1 =
Key Value
Fig. 5-6.
Row Subroutine Flow Chart
59
Chapter V, Section 2.2, the next section will be spent
on Decode Command routine.
2.8
Decode Command Routine
In order to decode a command the first digit input
and a function table called MICRT (in the program) are
used.
The MICRT table consists of relative branches for
appropriate functions.
In. other words, ·every br.anch leads
to execution of one function.
Since every relative jump instruction is 2 bytes
long, the decode format is to multiply the value of first
digit input by 2 and then add this result to the beginning
address of the MICRT.
For example, for a "1" function,
since the beginning address of MICRT is "23EH', a jump to
2xl + 23EH
=
240H.
This is the location in MICRT that has
a jump to executing function "1" or setting data.
The
flow chart for this routine is shown in Fig. 5-8.
2.9
Command Execution Routine
After decoding a command, depending on the first
digit input, a function is executed.
Different functions
executions are discussed here.
a) Start Execution Command Routine
In this routine, the current location is saved and
a jump to that location is made to start execution of the
program.
Fig. 5-9 shows the flow chart.
60
Zero Out
Display
Get Number of
Chars.
N
Blink
Display
Decode
Command
Jump to
Execute
Command
Return
Fig. 5-7.
Branch Subroutine Flow Chart
61
Decode
Command
Get First
Digit of
Command
\.1
Get Address
of Function
Table
2(First Digit) +
Table Func.
Addr. = New
Table Func. Addr.
Jump to New
Table Function
Addr.
(
Fig. 5-8.
End of
Decode Com.
Decode Command Routine Flow Chart
62
Execution
Get
Current
Location
Jump to
this location
Bump
Location
Counter
Fig. 5-9.
Execution Command Routine
63
b) Set Data/Set Location Counter Command Routine
This routine sets current location to specified
data and then increments the location counter.
As shown
in Fig. 5-lO.a first the data has to be converted from BCD
to Binary.
This is achieved by a routine called BCDBIN.
A maximum of 8-bit is acceptable for this command.
In case of a· ·set Location Counter <;ommand a. two-byte
value is stored since the current location pointer could
have a·value up to 4095.
Therefore part of the Set Data
routine is used to execute Set Location Counter Command.
The one byte flag is set when "1" command or Set Data
Command is executed.
When Set Location Counter Command
is functioning, first the value of location counter is
put in the current location (itself), then the flag is
reset to be able to store the next byte of information.
The flow chart of Set Location Counter Command is shown
in Fig. 5-lO.b.
c) Display Current Location Command Routine
In this routine the system increments the
current location counter.
Next it gets the content of
previous location counter, converts it to BCD and display
it.
The flow chart of this routine is shown in Fig. 5-11.
64
Set One-Byte
Flag
Convert
Data
BCD-tBIN
y
Get
Current
Location
Store 8-Bit
Value
Blink
Display
Bump Location
Counter By
1
Fig. 5-lO.a.
Store Next
8-Bit Value
Set Data Command Routine
65
Set Location
Counter
Current
Location
Lo.cation
Counter
=
Reset One-Byte
Flag
Fig. 5-lO.b.
Set Location Counter Command
Routine
66
Get Current
Location
Get the Content
of it
Convert it
BIN.
BCD
Result in LEDBUF
(Display)
Call
Keyscn
Bump the
Location
Counter
Fig. 5-11.
The Display Location Command
Routine
p '
67
2.10
NMI
Interrupt Handler
The NMI (Non-Maskable Interrupt) is always active.
Every 1/100 second this routine is automatically entered
at location 66H (NMIHAN).
The NMI routine outputs the
next digit to the LED display.
When NHIHAN is entered the CPU registers are
swapped to keep·the total status of system at the time of
interrupt.
Then the LED display is updated through the
LEDOUT·routine and the last thing to do is swap back the
CPU registers and return from the interrupt subroutine.
The flow chart of NMI handler routine is shown in
Fig. 5-12.
2.11
LEDOUT
Rou~ine
The LEDOUT portion of NMI Interrupt Handler Updates
the LED display.
It simply takes the contents of the
LEDBUF and outputs one of the four digits every 1/100
second.
After 4/100 the entire display has been updated.
Another function that the LEDOUT routine performs is to
blink the display in case of an operator error.
If BLINV
(the flag for blinking) is on the display is zeroed for
36/100 out of 100/100 second.
display.
This appears as a blinking
The flow chart of this routine is shown in
Fig. 5-12.a.
LEDPOS is a variable that holds the LED
address, if for example the fourth LED is to light up the
LEDPOS should have lOH.
digits.
LEDNO or LED Digit # is order of
68
NMI HAN
Swap
Registers
Call LEDOUT
(Display)
Swap
Register
Return
Fig. 5-12.
Interrupt Handler Routine
69
Output to
Display
Get LED
Digit
Number
.. Get Led Buf
Start Address
Dec.remen t Digit
Number
Shift
LED Pos.
Point to
Current
Digit
Get Current
Digit
Get LED Pos
(LED Position
Address)
Merge Current
Digit with
LED Pos.
LED Pos = Initial
LED Pos Value
y
Zero Out
Display &
Blink
Return
Fig. 5-l2.a.
LEDOUT Routine Flow Chart
70
Blink
Set
Blink
Flag
Call Delay
(5 seconds)
Reset
Blink
Flag
Return
Fig. 5-12.b.
Blink Flow Chart
71
2.12
BLINK Subroutine
In order to notify the user of an input error, the
BLINK flag is set by this subroutine.
It causes the dis-
play to blink for 5 seconds and then it resets the flag to
stop blinking.
The flow chart of this routine is shown in
Fig. 5-12.b.
2.13
BCD to Binary Conversion Routine ·
This routine is called BCDBIN subroutine.
This
routine converts a string of bed digits, typically a
string of INBUF to a binary value.
Values of up to 65535
(or up to 5 bed digits) can be converted.
As it shows in the flow chart of Fig. 5-13, this
routine, the
conv~rsion
pencil conversion.
another.
routine emulates a paper and
The limit could vary from program to
For the purpose of this microcomputer a limit
of 256 decimal maximum value is chosen.
2.14
Binary to BCD Conversion Routine
This subroutine converts a binary value in HL to a
string of bed values, typically in the LEDBUF for display.
The flow chart of this routine is shown in Fig. 5-14.
72
Bump
Pointer
Get Number of
Characters
ST * 10 = BCD
Digit : : :; ST
Initialize
Subtotal
(ST = 0)
No. Char.·- 1
= No. Char.
Save
ST * 2
N
Get Limit
(Max. Value)
(ST*2) + (ST*8)
= ST * 10
Get Pointer
to First BCD
Digit
N
Clear
Carry
Set
Carry
Get BCD
Digit
Return
Fig. 5-13.
BCDBIN Subroutine Flow Chart
73
Assign.
Pointer
to Table
Bump
Digit
Binary Value Power of 10
= New Value
Set BCD Digit
=
-1
· Get
Power of
10 from
Table
y
Restore
Residue
y
Store
Digit in
LEDBUF
Bump
Pointer to
LEDBUF
Bump Table
Pointer
Fig. 5-14.
BINBCD Subroutine Flow Chart
CHAPTER VI
MISCELLANEOUS PROGRAMS
There are some miscellaneous programs stored in the
EPROM that show the system capabilities.
These programs
are as follows:
1.
Diagnostic Program
In this section a diagnostic program for this
microcomputer system is discussed.
The diagnostic program
is used to test the system and help to debug the system if
any failure occurs after power up.
The flow chart of this program is shown in Fig. 6.1.
In the following sections the details of each routine are
discussed.
1.1
Initialization
When power is turned on, execution of the micro-
computer diagnostic starts at location 0.
pointer and PPI are initialized.
The stack
The LED display, as a
result, is cleared to zero.
Next (SCOPE) , the diagnostic loops for 7*65536
counts
(~
10 seconds) for a clock frequency of 1 MHZ.
This time may be used to check the data and address outputs of Z-80 with an oscilloscope.
routine is shown in Fig. 6.2.
74
The flow chart of this
75
GStart
)
Diagnosti
~
.J;
Initialize
System
,J,
Sequence
LED Digits
+
·•
Test RAM
Data & Add.
•
Short RAH
Memory Test
~-
NMI/Clock
Frequency
Test
'
-~
Output
Lines
Test
J,
Input
Lines
Test
J,
Keyboard
Scan Test
I
Fig. 6-l.
System Diagnostic Flow Chart
76
Initialize
Initialize
Registers &
Stack PTR
Loop Here
For 10 Seconds
No
Fig. 6-2.
Initialize Routine
77
Set LEDPOS
to First
LED
Set Digit
Value to Zero
Output
Current
Value
Fig. 6-3.
LED Digit Test
78
1.2
LED Digit Sequencing (TEST 0)
The next section of the system diagnostic routine
sequences the LED digits from right to left, counting each
from 0 to 9.
Each digit is displayed for about 1 second.
Then the digit is incremented until it's 9.
The flow
chart of this routine is shown in Fig. 6.3.
This routine
tests all the LED digits.
1.3
RAM Addresses and Data Test (TEST 1)
In this case the diagnostic program performs a very
cursory check on 6116 RM1 memory operation.
First zeros
are stored in RAM memory location 802H and then read back.
If other than zero is read back, the diagnostic program
will enter an indefinite loop.
Next all ones are stored
in RAM memory location 802H and then read back.
If other
than ones are read back, the program will once again
enter an indefinite loop.
In either case, the effect of
the loop is to cause 1 to be displayed continuously on
the LED display indicating that one or more data lines
connecting the Z-80 to 6116 are bad or the 6li6 chip is
bad.
The flow chart of this routine is shown in Fig.
6-4.a.
1.4
Short
RM~
Memory Test (TEST 2)
The flow chart of Short RAM Memory Test is shown in
Fig. 6.4.b.
As shown, this test performs a check on all
locations of 6116 RAM memory from 802H to OFFFH.
Zeros
79
Store 0 in
First RAM
Location
Get Back
Contents of
First· RAM Loc.
Increment
it
Delay
Store -1 in
First RAM
Location
Get Back
Contents of it
Fig. 6-4.a.
The RAM Test Flow Chart
80
0
Short
RAM Test
Store -1
in the
RAM Loc.
Display
-"2"
Get First
RAM
Location
Get Stored
Value
N
Put 0 in
RAM Loc.
Get Stored
Value
Bump
RAM Loc.
ADDRESS
N
N
Fig. 6-4.b.
Short RAM Test
•
81
and ones are alternately stored in each location.
test is repeated for all RAM locations.
The
If other than
zeros or ones are read back, the program continuously
displays "2''.
1.5
The flow chart is shown in Fig. 6-4.b.
NMI Interrupt Processing
From the time the system is "powered up," NMI
interrupts occurs at a rate of (ideally) 100 tirnes per
second.
Each interrupt causes an automatic branch to
location 66H.
NMIHAN (161H).
The contents of 66H is a jump to location
This NMI Interrupt Processing Routine
increments the content of locations 800/801H, treated as
a 16-bit value.
These locations serve as a real-time-
clock count that ,counts from 0 to FFFFH (up to 65535 in
decimal) every 655.35 seconds.
The real-time-clock count is used for Test 3 of the
system diagnostic programs as a mean to determine delays.
Resetting the locations to 0 and then checking for a
count of 100, for example, would indicate that 1 second
has elapsed.
The action of the NMI exercise the top locations of
6116 RAM (for storage of return address) and the first
two bottom locations of RA.rvl:.
a) TEST 3:
Clock Frequency/NMI
This test in the system diagnostic is used to
calibrate the clock frequency of the system and NMI
82
frequency.
The time between the first display of 3 and
the blanking of 3 should be exactly 30 seconds.
The second part of this test checks for the NMI
frequency.
The time between the second disappearance of
3 and the appearance of 4 should be exactly 10 seconds.
If the system diagnostic "hangs" during this test, and
continually displays the second occurrence of the digit 3,
the NMI interrupt is not operative.
The flow chart of
this test routine is shown in Fig. 6-5.
1.6
Output Lines Test (TEST 4)
This test enables output lines OUTl through OUT6 for
1/2 second and then disables the lines for 1/2 second.
This action is repeated for 30 seconds.
output on all lines is shown in Fig. 6-6.
The resulting
The output of
any line may be checked with a voltmeter or an oscilloscope.
Cycling from 0 to 1 and back should occur at a
1-second rate for 30 seconds.
The flow chart of this
test routine is shown in Fig. 6-7.
1.7
Input Lines Test (TEST 5)
The system diagnostic test checks the state of input
lines INl through IN5.
seconds.
played.
All five lines are scanned for 30
If any line is low (ground), its number is disOne or more lines may be made low clipping a lead
from ground to the line.
All lines should be tested in
83
Display
"3"
30 Sec.
Delay
Clear
Display
10 Sec.
Delay
Display
"3"
Get
Current
RTC Count
Fig. 6-s.
NMI/Clock Frequency Test
84
Repeat for
30 seconds
-----)
I
Sec.--.,!
l
I
I
I
I
I
I
I
II
I
~ ON~OFF~
'
I
I
,,
Fig. 6-6.
I
I
Out Lines Waveform
85
Output
Lines
Set
Sec.=30
Display
"4 ·~:
Enable
All Output
Lines
Delay
~ Sec.
Disable
All Output
Lines
Delay
~ Sec.
·Decrement
Sec.
Fig. 6-7.
Output Lines Test
N
86
this fashion.
The flow chart of this test is shown in
Fig. 6-8.
1.8
Keyboard Scan (TEST 6)
The last function of the system diagnostic routine
is the keyboard scan test.
After a 10-second display of
"6", the diagnostic routine continuously scans the keyboard, looking for a key depression.
If a key
~s
found to
be depressed, its row and column number are displayed.
The test continues for 30 seconds.
The flow chart of
this routine is shown in Fig. 6-9.
2.
Multiplication Program
As it was discussed in Chapter IV, Section 5, a "-4".
command is used to enable multiplication function.
multiplier is carried with the command.
The
In this program,
as shown in Fig. 6-10, first the multiplier is converted
to binary then the system awaits for Multiplicand.
Multiplicand also is converted to binary.
The
After the
Multiplicand is ready, the multiplication takes place
using a shift and add method.
For successive multiplica-
tion, the operator has to enter two ''*".
This causes
the display to clear to zero and the system to wait for
the next number to be multiplied.
The process continues
until there is no more demand for multiplication; this is
indicated by pressing an "#" key.
The multiplication
procedure is included in the flow chart of Fig. 6-10.
87
Display
"5"
Delay
10 Sec.
Line Value
Delay
=
5
~ Sec.
N
Get Next
Line
·Get Line
Correspond to
Line Value
y
N
Line Value
= 0
Display
Line Value
Input Lines
Fig. 6-B.
The Input Lines Test
88
Display
N
"6"
Delay
10 Sec.
Output
Columns to
"LED Pos.
Set Row
Value = 4
Delay
1:2 Sec.
Get Row
Number
Get the
Row
Output Row
Number to
the Leds
1:2 Sec.
Delay
N
N
Clear
Display to 0
Decrement
Row Value
Fig. 6-9.
Keyboard Scan Test Flow Chart
89
Convert
Multiplier
BCD-BIN
Shift
Multiplier
(1 Bit Position)
N
Product =
Multiplicand +
Product
N
Blink
Display
Convert
Product
BIN _ _ __, BLD
Input
Multiplicand
End
Hult.
Fig.
6-10.
Multiplication Procedure
90
3.
Division Program
The division function is specified by a "5" command
followed by a dividend number.
Same as multiplication
program, first thing to do is converting both divisor
and dividend to binary.
Then using shift and subtract
method, the division is taking
place~
The quotient is
displayed and the· remainder is also displayed if. "0" key
is pressed.
For successive division the same steps follow as in
the multiplication program.
The division procedure is included in the flow
chart of Fig. 6-11.
91
Convert
Dividend
BCD
Dividend
- Quotient
Quotient
BIN
y
Dividend +
Quotient
Dividend
Input
String
(Division),
N
Shift Left
1 Bit
(Dividend)
Fig. 6-11.
Division Procedure
92
Convert and
Display
Quotient
Display
Remainder
Div.
Fig. 6-11.
Continued
CHAPTER VII
CONCLUSION
The system described in this paper was used as a
multi-purpose microcomputer by executing the machine
language programs.
However, the main idea of such design was to develop
a flexible microprocessor controlled system that could
easily be interfaced with other systems to accomplish
different applications.
This system could easily be modified as a home
control system to control different functions in the
house such as the, alarm, smoke detector, temperature
control system, etc.
93
.-,
Vt
'-h.
I
I J
·--,~£!.L,
I
I
.I
I
I
3t_
)ooPFf
I
I
Yz. . '" _
~:_ MC.'io2.'1~
--=5'+-1_ - _
J:
I
r--
3
II
1.,
~ 1
rr- L
Q
Z-8¢
j :
---.,
I
I
2.Z.oJL
I
I .
C.PU
:
-
I
t
IJ z.
n'AiMi
,.
II g
Mc.~o1.!JWI~----~
tflq
'I
I
I
'---1:':-r-~-:;:14
·~
y~ "'H"
.
V<.c.
l
...
~
r
_ol~
d
-~Vee
. . A,, _;:..... OE.
.).0-
-
.
. -
J.t. CE
O,.J.o~-o<.-;--.-, l
1'L
IS
~
--o
a,~
.:
..
-
q. ~-++t-r-r-r,T
I'
l
7 GvC:t~.:t~=+~;f-1r 1
-~
(wD
tt
-+- · ;:2 11 b · . ~u~-_-+-1-+++tn-n
to K.J:L
P6 ..
~
so
-OVTI
u~:.______
ouT z
'.!
•I ~.L__ _ _ _ _ _ 6~'[3
-4 74/ ~ ~~
llfliL__ _ _ _ _ o.,;' '1
/l.
I-'-'
O&JI 5
A
:zl
~
10
ptH. i<>
'"
f61
zH
'i
u
fiB
o' 1L
0
MRE~-
10
f'6 s
- peo
ovl'
.:
,,
'i((-~
h,
··
~
. r.J.
J
th
......
.
_L_
~
).2.
_j
I kA.
-
WI\ __:!l iN E
~-
,~
Cs
J
~"-----=1
5
l_________________
3
~--~~-------~~0 ~
t~__
_____
r--.~-==-------====- 1
t~~~-==-~=-=-~-_-:_-:_-_-:_-:_-:_-:_=-=-=-~~=-=-=--_I
t'j"9
--
j"-
F l"g . 6-12.
system Schematic
REFERENCES
1) Barden, Jr., William, The Z-80 Microcomputer Handbook,
Indianapolis, Indiana, Howard W. Sams & Co., Inc.,
1983.
2) Camp, R. C., Smag, T. A., and Triska, C. J.,
Microprocessor Systems Engineering, Portland, Oregon,
1979.
3) Gayler, D., W{nston, The Apple II Circuit Description,
Indianapolis, Indiana, Howard W. Sams & Co., Inc.,
198~.
4) Peatman, B., John, Microcomputer-Based Design, New
York, McGraw-Hill Book Company, 1977.
95
APPENDIX
96
97
PROGRAM LISTING
ORG 0
EPROM Loc. 0
; Jump to Program
1
!NIT
INPUT
GETCHR
KEYSCN
ROW
BCD BIN
BINBCD
DELAY
BLINK
BRANCH
DEFB
OC3H
Jump to Program
DEFW
0220H
At addre$s 22011
Sub-routine Vectors
;
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
!NITS
INPUTS
GETCHS
KEYSCNS
ROWS
BCDBIS
BINBCS
DELAYS
BLINKS
BRANCS
Initialization Sub-routine
Input SR
Get one KB Char. SR
Scan Keyboard SR
Scan ROW SR
Convert BCD to Binary SR
Convert Binary to BCD SR
Delay SR
Blink LEDS SR
Branch SR
*Initialization Program. Moves Initialization*
*Data from EPROM to RAM.
*
Entry: (HL) = Start of Program Data
*
*
*
(BC) = # of Bytes of !NIT Data
*
Call INIL
*
*
Exit:
Program Data Moved
*
*
!NITS EQU $
LD
A,89H
OUT
( 3), A
LD
DE,PROGRM
Set mode control word
for PPI
Setting mode 0, Sub-mode 3
, Start of program RAM (for
PNTR and MFLG)
Move program data
LDIR
LD
HL, INITD
Start of general variables
in ROM
LD
BC, INITL
Size of gener~l variables
LDIR
Move general variable
RET
; Restart 3811 Location for Patches
ORG 38H
RET
,, .
98
INITD
INITL
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFB
EQU
0
0
0
0
0
0
0
0
3
lOf!
0
0
0
0
0
0
0
0
0
0
0
0
0
$:_-INITD
Protect byte for LED
Protect byte for LED
Protect byte for LED
LED BUFFER (LEDBUF)
LEDBUF Digit 2
LEDBUF Digital 3
LEDBUF Digital 4
Disable
.
LED Digit # (LEDNO)
LED Address (LEDPOS)
Blink (BLINV)
Protect byte for input
Protect byte for input
Protect byte for input
Input Buffer (INRUF)
f:
of input CHRS (NOCl!R)
; Size of defaults
; Location of variables after relocation
LEDBUF
EQU
804H
LED NO
LEDPOS
BLINV
INBUF
NOCHR
PROGR
EQU
EQU
EQU
EQU
EQU
EQU
LEDBUF+4
LEDNO+l
LEDPOS+l
BLINV+4
INBUF+l6
NOCHR+l
*NMI Interrupt Handler.
Updates
*
*Display Next Digit Once each lflOO Second*
NMI HAN
ORG
66H
EQU
EX
EXX
AF,AF
Fixed NMI Location
$
Save A,F
Save other register
Code to MULTIPLEX LED Display
Four LED Digits in INBUF.
OUTPUT 1 of Four to LEOs
Every lflOO of second so after 4/100 second the entir0
display is updated
99
LED OUT
$
A,(LEDNO)
C,A
B,O
HL, LEDBUF
ADD HL,BC
LD B, (HL)
LD A , ( LED POS )
or tl
EQU
LD
LD
LD
LD
OUT (0), A
LD A, (LEDNO)
DEL A
AND 3
LD (LED NO) l A
LD A,(LEDPOS)
SLA A
JR NZ,LEDlO
LD A,lOH
LED 10
LED 20
Get Digit li
Now in C
Now in BC
LEDBUF
Point to Digit
Get current digit
LED postiion address
Merge )A has PA4-PA7
B has PAO-PA3
OUTPUT
Digit #
Bump Digit #
Modulo 4
Save Digit
LED Postiion Address
Align
Go if okay
Start over
or A
JR Z,LED20
LD A . ( HUNDS )
AND 40H
JR NZ,LED20
OUT ( 0): ~
Save position address
Is blink on?
Test
Go if no
Get lOOths
Get 64/100 this bit
Go if not 0
Turn off
EX AF,AF
EXX
RET
Switch A - F
Switch other regs.
RET from NMI Int.
LD ( LEDPOS ) , A
LD A, ( BLINV)
*Get INPUT Sub-routine.
Gets AN Input String of*
*Characters.
*
No Special Setup
*
Entry:
*
Input characters in INBUF
*
Exit:
*
(HL)
points to last character
*
*
(C) = # of characters input
*
*
INPt!TS
INPOS
EQU
$
LD HL,INBUF
LD C,O
Point to Input BUF
Initialize# of chars.
PUSH HL
PUSH BL
CALL GETCHR
POP BC
POP HL
CP OFEH
RET Z
CP OFFH
JR NZ, INPlO
LD A,C
Save pointer
Save count
GETCHR
Restore Count
Restore Pointer
Test for End (#)
Return if done
Test for BS
Go if not back space
Get #
Test for 0
OR A
100
Go if none input
Adjust count
Adjust pointer to LST
Go for next
JR Z, INPOS
·DEC C
DEC HL
JR INP05
INPlO
LD (IlL)., A
INC C
PUSH HL
PUSH BC. ·
LD DE, LEDBUF+3
LD B, 0
LD A,C
CP 4
JP M, INPll
LD A,4
Store character
Bump count
Save Pntr
Save count
LEDBUF destinati6n
Zero high order
Get count
Test for 1-3
Go if l-3
·1 or above
INPll
LD C,A
LDDR
POP BC
POP HL
INC HL
BIT 4,c
DEC HL
DEC C
JR INP05
Count or 4
Transfer for display
Restore count
Restore Pntr
Bump Pntr
Test counter for 16
Do not allow
More than 16
Continue
Gets one Keyboard Char.*
*GETCHRACTER Routine.
No
special
setup
*
Entry:
*
Call GETCHR
*
*
(A) = BCD Digit 0-9
*
*
Exit:
-1
for
"*
*
*
-2 for "#"
*
11
GETCHS
GETlO
EQU
$
Call KEYSCN
JR Z,GETlO
PUSH AF
GET 20
Call KEYSCN
JR NZ,GET20
LD HL,lO
Call DELAY
POP AF
RET
T('st for Char.
Go if none
Save character
Tc·st for Char.
Go if same Char.
10 Milisccond delay
Delay SR
Retrieve Char.
*Keyboard Scan.
Test for Key Press
*
*
Entry:
No special setup
*
*
Call KEYSCN
*
*
Exit:
Z Flag Set if no key else*
*
(A)=BLD Digit 0-9,
*
*
-l for "*"
*
-2 for "c"
*
*
101
KEYSCS
EQU
$
LD 8, 3
LD A,801!
Call ROW
JP NZ,KEYlO
LD 8,6.
LD A,40!1
Call ROW
JR NZ, ··KeylO
LD B, 0
LD A,20!1
Call ROW
JR N2,Key 10
LD B, 3
LD A, 1 0!1
Call ROW
JR Z,Key 20
SUB 2
JR Z,Key 10
BIT 7,A
JR NZ,KeylO
LD A,OFEH
KEY 10
LD B, OFF!!
BIT 7,B
JR Key30
KEY 20
XOR
KEY 30
RET
For "3" key
ROWl
Tl?St HOW
Go if none-zero
Tor "6" k<'Y
How 2
Test ROW 2
Go if none-zero
For "9" Key
Row :l
Test ROW 3
For "B.S" Key
Row 4
Test ROW 4
Go if no key pressed
NOll' -1 , 0, + l
Go if "0" Key
TEST sign
Go if minus
Set l
Dummy
Reset Zr?ro FlagReturn
A
*ROW Sub-routinP: Test specified KPyboard ROW*
*
Hight Hand BCD Va 1 u''
Entry: (B)
*
*
(A) = HOW Add.
*
*
Call ROW
*
(A) = BCD value or !\leY or z(>ro
*
Exit:
*
(B) - Destroyed
*
*
*Z-Flag is set if no key
*
ROWS
HOW 10
EQU
$
IN A, (2)
AND 7
XOR 7
G<'t HOW
Get 3 Column Bits
Active Low
RRCA
JR C,ROW 20
DEL B
OR A
JR N2,ROW10
XOR A
JR ROW30
Set Carry
Return if found
Adjust BCD Count
Test for DonP
Try At.;ain
0 for No Key
RPturn
102
ROW 20
LD A,B
OR A
HOW 30
RET
BLD Value
Set Zero Value or Non-Zero
*BCD
~inary Conversion Routine.
*
*Converts up to 5-digits to Binary (O-G5535)
*
*
Entrv::
(IX)
Pointer to First BI~ Digit*
.;
(B)
1i of Chars.
*
*
(DE)
Max. Value
*
*
(HL)
Binary Value
*
*
Exit:
Carry set if under 1 i mit , resut
*
*
if over or equal.
*
*
BCDBIS
BCDlO
EQU
S
PUSH DE
LD HL,O
ADD HL,HL
PUSH HL
ADD HL, IlL
ADD HL,HL
POP DE
ADD HL,DE
LD D,O
LDE,(IX')
INC IX
ADD HL,DE
DJNZ BLDlO
POP DE
PUSH IlL
OR
A
SBC HL, DE
POP IlL
RET
Save limit
Initialize Subtotal
Subtotal *2
Save ST*2
Subtotal *4
ST*8
Get ST*2
ST*lO
Zero MS Byte
Get BLD Digit
Bump Pointer
ADD in latest digit
Continue if not done
Get limit
Save va 1 uc•
ClPar Carry
*Binary
BCD Conversion
*
*Converts 16-bit Binary Valu(' to;, BCD Char.*
*
Entry:
(HL) = Binary Value
*
*
(IX) = Pointer to fluffc·r
*
*
Ex i t :
( F i v e BLD Di g i t s Un p a c k c• d i n
*
*
5 Bytes of flu.ffer)
*
*
(IX) Points to Next Available
*
BINBCS
BIN05
EQU
$
LD IY,flTABL
Table of Constants
LD B,OFFI!
LD E, (IY)
BIT 7,n
RET NZ
Initialize BCD Digit
Get power of 10
Test Sign Bit
H(•turn if done·
103
BIN 10
.INC B
OR A
SBL HL,DE
JR NC,I3IN10
ADD HL,DE
LD (IX),B
INC IX
INC IY
INC IY
JR BIN05
BTABL
DEFW 10000
DEFW
1000
DEFW
100
DEFW 10
DEFW
l
DEFW -1
Bump Count (Digit)
Clear Carry
Subtract Power
Continue if pos.
Restore Residtw
Hestore Digit
Bump Pointer
Bump Table Pointer
Past 2 bytes
*Delay Sub-routine.
Delays 1 MS * Count in HL*
*
Entry:
(HL) = Delay in Milliseconds
*
DELAYS
$
LD DE,-1
D<ecremr~nt
DELOS
LD 8,04AH
ADD HL,DE
RET NC
Fiangle Factor
Decrement HL Count
Return if Done
DELIO
DJNZ DELIO
NOP
NOP
JR DEL05
Inner delay
EQU
value
Wast<" Time
R<'t urn to OutPr Loop
*Sub-routine to Blink Display for 5 Sr>conds*
BLINKS
$
LD A,OFFH
LD (BLINV) ,A
LD HL, 5000
Call Dt•lay
XOR A
LD ( BLI NV) , A
RET
EQU
All on
for flag
Set blink flag
5 Second
Delay
0 to A
Reset blink flag
*Sub-routine to Branch Out to Functions
*
(I!L) - Pointer to H<•lat ivc· Branch TablP*
*
Entry:
*
(DE)= Min. ti for input, ti of last
*
valid function
*
*
By jump to branch tab]P aft.<·r valid
Exit:
*
*
input string
*
*
104
BRANCS
$
·EQU
PUSH HL
INC E
PUSH DE
Save pointer
Bump # of last func.
Save parameters
BR05
LD I!L,O
LD (LEDBUF),HL
LD (LEDBUF+2),11L
Zeroes
Zero LED Di~p
Four bytes total
BRIO
CALL INPUT
LD A,C
LD ( NOCHR) , A
POP DE
SUB D
BIT 7,A
JR NZ,BR15
SUB E
BIT 7,A
JR Z,BR15
POP DE
LDHL,(INBUF)
LD H,O
ADD HL, rfL
ADD HL,DE
JP (HL)
Input String
Get it input
Store it of chrs.
Get min., Last
Tf>c;t for Min.
Tee; t for LT Min.
Go if LT Min.
Actual largest
Test for Minus
Go if not in range
Restore BR table point0r
Get # to L
# now in HL
# Times 2
Table ADD + # Times 2
Jump out
BR15
PUSH DE
CALL BLINK
JR BROS
END
Save limits
Blink leds
Try again
ORG
220!!
Next
EQU
LD SP,
LD
LD
CALL
$
lOOOH
HL,PDATA
BC,PDATAS
!NIT
Initialize stack
Start of RAM Data
Siz(e of data
Initialize
MICR90
LD
LD
LD
LD
LD
JP
HL,O
( LEDBUF) , IlL
( LEDBUF+2) , IlL
HL,MICBT
DE,0005H
BRANCH
Zero IlL
Zero Left Digits
Zero Right Digits
Function Table Addr.
0-~!in., 0-5 Valid
Branch out
MICRT
JR
JR
JR
JR
JR
JP
~!ICROO
MICRlO
MICR20
MICR30
MULT40
DIV50
0
1
MICRO
2
3
4
5
EPHO~!
Area
start execution
set data
display data
set 1oc. counter
Multiplication
Division
(l
•
105
MICROO
START EXECUTION FROM CURRENT LOC.
m CROO
LD IlL, ( PNTH)
JP (HL)
MICRlO
Set Location to SpecifiPd Data
MICRlO
LD DE,256
XOR A
LD
(MFLG)", A
M~tximum
MICRll
LD
IX,lNBUF+l
LD A, (NO CI!R)
LD B,A
DEC B
CALL BCDBIN
JR C,MICR12
CALL BLINK
JR MICR90
Start of data
Get # of Chrs. Input
~love to B
Adjust for Function
Convert
Go if okay
Over limit-blink
Go for next func.
MICH12
LD
(;et current 1oc.
Jump out
for conversi
Zero flag
Set one byte
Get current location
Store value
Get 1/2 byte flag
Test
Go if l byte
Two bytes
Do not bump location
IX, (PNTR)
LD (IX),L
LD
OR
JR
LD
JH
MICR13
A,
2,MICR13
(IX+l),H
MICR,90
MICR25
Di sp l uy Curn:nt Location
LD HL, (PNTR)
LD A, (HL)
Ul
L, A
LD Jl,O
LD
IX,LEDI3UF-l
CALL
BINBCD
CALL KEYSCN
JR Z,MICR25
JR MICR13
MICR30
MICR30
Get current loc.
Bump by l
Store
Get next command
LD HL, (PNTR)
INC HL
(PNTR),!!L
LD
JR MICR90
MICR20
MICR20
(MFLG)
A
LD
LD
LD
LD
Ul
JR
Get current location
Now in L
Now in IlL
LED BUFFER
, Convert and Display
Test Key Push
Go if none
Go to updatC'
Set Location Counter
HL,PNTR
(PNTR), I!L
DE,lOOOII
A, 1
( MFLG), A
MICRJJ
DATA AREA
~lcation County Locn
To itself
RA~l + 1
One to A
Set two byte flag
Go to store
llll
106
PDATA
DEFW 0
DEF8 0
(PNTR)
(MFLG)
NEWPROG
CALL GETCHR
CP OFEH
Test for End
LOOP
JR NZ,LOOP
JP MICRO.
PDATA
EQU
PNTR
MFLG
If not loop
Else get ready for execution of another one
P DATA
Size
EQU
PROGR
Location of (PNTR)
EQU
PNTR + 2
Location of MFLG
$
MULT40
Multiplication Function
~IULT40
LD DE,256
LD IX,INBUF+l
LD A, ( NOC!!R)
LD 8, ,\
DEC 8
CALL BCDBIN
JR C,MULT41
CALL BL-INK
JP ~IICR90
Maximum
Start of data
Get #of Chars. Input
Move to 8
Adjust for function
Convert
Go if okay
Over limit-blink
Go for next func.
MULT4l
LOOP l
PUSH HL
CALL GETCIIR
CP OFFH
JR NZ,LOOPl
Save multiplier
Get a character
MULT42
LD HL,O
LD
( LEDBUF) , HL
LD (LEDBUF+2),HL
CALL INPUT
LD B,C
LD DE,256
LD IX, INBUF
CALL BLDBIN
JR C,MULT43
CALL BLINK
JP MULT42
Clear IlL
Zero left digits
Zero right digits
Input string
Get # of Char. into B
Maximum
Start of data
Convert
Go if okay
Over limit-blink
Go for next function
MULT43
EX
POP
LD
LD
LD
LD
DE,HL
HL
II,L
L,O
D,O
A,8
Is it
"*"
If not loop
Exchange DE and HL
Get multiplicand
Now multiplier in l!L
Multiplicand in DE
Intcration count
107
LOOP2
ADD !IL,IIL
JR NC,MULT44
ADD HL,DE
Shift left one
Go if no carry
Add multiplicand to partial
product
MULT44
DEC A
JR NZ,LOOP2
PUSH HL
LD IX,LEDBUF-1
CALL BINBCD
Decremen~ Iterations
Go if not 8 Iterations
Save Result
LED BUFFER
Convert
LOOP3
CALL GETC!IR
POP HL
CP OFEH
JP Z,MICR90
CP OFFH
JP Z,MULT41
CALL BLINK
JP MICR90
Get a character
Retrieve result
Is Char = "#"
If it is go for next command
Is
it"*"?
If so go for successive mult.
Else blink display
Go for next command
DIV50 - Division Function
DIV50
LD DE,256
LD IX, INBUF+l
LD A, (NOCHR)
LD B, A
DEL B
CALL BCDBIN
JR C,DIV51
CALL BLINK
JP MICR90
Maximum
Start of data
Get *of chars. input
~IOV(' to B
Adjust for function
Convert
Go if okay
Over limit-blink
Go for next function
DIV51
PUSH
Save dividend
LOOP4
CALL GETCHR
CP OFFH
JR NZ,LOOP4
Get a character
LD
HL,O
LD ( LEDBUF) , HL
LD (LEDBUF+2),HL
CALL INPUT
LD B,C
LD DE,256
LD IX, INBUF
CALL BCDBIN
JR C,DIV53
CALL BLINK
JP DIV52
Zero HL
Zero left digits
Zero right digits
Input string
Get # of Char. into B
Maximum
Start of data
Convert
Go if okay
Blink (over limit)
Go for next function
DIV52
HL
Is it"*"?
If so, go
108
DIV53
LD
B,L
C,O
POP HL
LD
D,8
Get Divisor
Divisor in BC
Retrieve dividend
Interation count
LOOP5
ADD HL,HL
XOR A
SBC HL,BC
INC HL
JR NC; DIV54
ADD HL,BC
RES O,L
Shift left one
Clear carry
Subtract
Set Q=l
Go if positive result
Restore
Reset Q bit to 0
DIV54
DEC D
JR NZ,LOOP5
PUSH HL
LD
H,O
LD
IX,LEDBUF-1
CALL BINBCD
CALL GETCHR
POP HL
CP
OOH
JR N2,LOOP7
LD
L,H
LD
H,O
LD
IX,LEDBUF-1
CALL BINBCD
count
Continue if not 8
Save result
Now quotient in HL
LED BUFFER
Convert data, display
Get a character
Retrieve result
18 Char. 0
If yes, go
Remainder in L
In HL now
LEDBUFFER
Convert, display
LOOP6
GO
CALL GETCHR
OFEH
CP
JP Z,MICR90
,Jp
LOOP6
Get a character
Is it "#"?
If not go
Jump to get a Char.
LOOJ>7
CP
JP
LD
LD
JP
OFFH
NZ,GO
H,O
DIV5l
Dec remt~n t
Is it "*"?
yes go
Quotient in HL Now
Go for successive division
I f
109
SYSTEM DIAGNOSTIC PROGRAM
Initialize stack and PPI
START
LD
LD
SP,lOOOII
A,. 89H
OUT
XOR
OUT
OUT
A
(0),
A
( l),
A
( 3),
Top of the RAM+l
Mode control WD
Set Mode 0, Sub-mode 3
Clear A
Reset Leds
Reset Output Lines
A
; Loop Here 10 Seconds for Scoping
SCOPE
SCPlO
SCP20
Outer loop count
Decrement = -1
Inner Loop Count
Decrement HL
Loop if not done
Outer loop
LD
LD
8, 7
DE, -1
LD
HL, -1
ADD HL, DE
JP
C, SCP20
DJNZ SCPlO
; Sequence LED digits right to left
LEDDGT
LED05
LD
OUT
LD
LD
LEDlO
A, 1011
( 0), A
HL, -1
8C, -1
ADD HL: 8C
C, LED10
JP
ADD . A, 1
LD
B,
AND
LP
LD
JP
AND
SLA
CP
JP
OFH
OAH
A,
A
8
NZ, LED05
OFOH
A
0
NZ, LED05
, Test 1:
RAMTST
RAMlO
Test RAM Addresses and Data
LD
A,
OUT
XOR
(0),
A
LD
(802H), A
A, ( 802H)
LD
CP
1111
A
0
JP
CPL
NZ,
LD
(80211), A
A, (802H)
LD
INC
0 to right-most digit
Output current value
For delay count
For delay decmnt
Deere count
Loop if not 64K
Bump digit value
Save
Get digit value
Output 0-97
Restore
Go if move
Get position field
Move to next position
At left-most ?
Go if no
RA~ll
0
For Test 1
Output to Leds
0 to A
Store 0 in first RAM
Get contents
Zero?
Loop here on error
to A
Store -1
Get contents
Test for all ones
-1
A
110
RAM20
LD
N2, RAM20
HL, -1
BC, -1
Loop here on error
For delay C.NT
}'or delay decrement
ADD
JP
IlL, BC
C, RAM30
Decrement count
Loop if not 64K
JP
LD
RAM30
; Test 2:
MEMTST
Memo~y
Test
For test 2
Bypass NMI· vector
A, 12ll
69H
LD
JR
'
Short RAM
NM Interrupt Vector
Go to process NMI
XOR
66H
NMIHAN
69H
( 0)' A
HL, 802H
B, 2048
A
Output to Leds
Start of RAM
Size of RAM working
0 to A
MEMlO
LD
LD
CP
(HL), A
A, ( HL)
0
Store all zeros
Get stored value
Is it zero?
MEM20
JP
CPL
N2, MEM20
LD
LD
( HL), A
A, (HL)
A
Loop here on error
to A
Store all ones
Get stored value
Is it -1?
ORG
JP
ORG
OUT
LD
LD
INC
MEM30
-1
JP
NZ, ~lEMJO
INC HL
DJNZ MEMlO
HL, -1
LD
LD
BC, -1
ADD
JP
IlL, BC
C, MEM40
; Test 3:
NMICLK
NMI/CLK Frequency Test
A, 13H
(0), A
HL, 30000
LD
CALL DELAY
XOR A
OUT (0), A
LD
HL, 10000
CALL DELAY
LD
HL, OFC38!1
(TIME), IlL
LD
A, 13H
LD
OUT (0), A
LD
OUT
Loop here on error
Bump pointer
Continue here for 2048
For delay CNT
For delay INC
For test 3
Output to leds
30 Seconds delay at 1 MHZ
0 to A
Clear leds
10 Second Delay
Finagle factor for 1
Initialize RTC CNT
Second part of Test 3
Output to }C'dS
111
NMI 10
LD
LD
IlL, (TIME)
A, L
OR
JP
XOR
OUT
!I
Get current RTC count
Low order byte
Merge high-order byte
Go if not 0
0 to A
Clear leds
10 Second delay
NZ, NMilO
A
( 0). A
LD
HL, 10000
CALL DELAY
. Test
OUTLN ·
LD
LD
OUT
OUTlO
4:
Output Lines .Test
30 Seconds for test
For Test 4
Output to Leds
B, 30
A, 14H
(0), A
All on
Output to lines
l/2 Second delay
Save BC
A, OFFH
(1). A
HL, 500
BC
DELAY
A
(1). A
HL, 500
LD
CALL DELAY
POP BC
DJNZ OUTlO '
LD
OUT
LD
PUSH
CALL
XOR
OUT
. Test
IN LINE
INL02
INL05
INLlO
5:
Input Lines
All off
1/2 Second delay
Restore BC
Go if not 30 seconds
1\~s
t
OUT
LD
CALL
LD
LD
A, 15H
( 0). A
HL, 10000
DELAY
HL, OF448!1
(TIME) , HL
For Test 5
Output to Leds
For 10 second delay
LD
LD
B, 081!
C, 5
INS Mask
In Digit
IN
AND
JP
LD
ADD
A,
LD
OUT
LD
PUSH
CALL
POP
DEC
SLA
JP
LD
OR
JP
(02H)
B
z, INLlO
A,
A,
104
c
( 0)' A
HL, 200
BC
DELAY
BC
c
B
NZ, INL05
A, (TIME +l)
A
M, INL02
Fin a glc• factor for 30 SPconds
Initialize RTC count
::
Input Lines
Get line 0
Go i r 0
For right-most Led
Merge Line #
Output 0 or #
1/5 Second delay
Save BC
Restor(! BC
Decn•m<en t Digit #
Align Mask
Go i1' not last
RTC sign
Test sign
Go for another pan
112
; Test 6: Keyboard Scan Test
KBSCN
ill
OUT
A, l6H
( 0), A
HL, 10000
LD
CALL DELAY
HL, . OF448H
LD
(TIME), HL
LD
KBSOS
LD
LD
KSBlO
LD
IN
AND
XOR
JP
ADD
OUT
XOR
OUT
DEC
SLA
JP
LD
OR
JP
Finagle factor for 30 seconds
Initialize RTC count
B, l'OH
C, 4
Row It mask
Row It count
A, B
A, (2)
Row t: mask
Read input lines
Process only KB
Active low lines
Go if no depress
For right Led
Output to Leds
l/S second delay
Save BC
7
7
Z,
KBS20
A, lOll
(0), A
HL, 200
LD
PUSH BC
CALL DELAY
LD
A, c
ADD A, lOH
OUT ( 0)' A
HL, 200
LD
CALL DELJ\.Y
POP BC
KBS20
For Test 6
Output to Leds
For 10 second delay
A
( 0)' A
c
B
N2, KBSlO
A, (TIME + l )
A
M, KBSOS
Get Row #
For right Led
Output to Leds
l/S second delay
Restore BC
0 to A
Clear Leds
Decrement Row CNT
Get next Row #
Go if not last row
Get sign of RTC CNT
Test sign
Go if not past 0
; Return to Beginning of Program
JP
START
: Delay Sub-routine.
DELAY
LD
DE, -l
DELOS
LD
ADD
RET
B, 04AH
HL, DE
NC
DELIO
DJNZ DELIO
DEC
IY
JP
DELOS
Delays l MS Count in HL
Decrement value
Finagle factor
Decrement HL count
Return if done
Inner delay
Waste time
Return to outer loop
113
NMI Interrupt Handler
NMIHAN
AF, AF'
.HL, (TIME)
INC HL
LD
(TIME), HL
EXX
EX
AF, AF'
RETN
Sav<~ Flags, A
Save other Regs.
Get time CNT
Bump by one
Store
R~store Regs.
Restore flags, A
Return from NMI
ORG 80011
First RAM
DEFW 0
RTC Count
EX
EXX
lJ)
TIME
END
Locatio~