CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
HYBRID COMPUTER INTERFACE
USING DUAL COPROCESSORS
A thesis submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Engineering
by
Mark Scott Hutchenreuther
August 1985
The Thesis of Mark Scott Hutchenreuther is approved:
California State University, Northridge
ii
TABLE OF CONTENTS
Page
List of Figures
v
Abstract . . . . .
vii
Chapter
1.
Historical and Technical Perspective
1
Computer History • . . . . . . . . .
1
Analog Computers • .
5
Digital Computers
8
Hybrid Computers . .
2.
Hybrid Computer Elements
Overview . . .
. 11
• • • 14
• .
ADC Specifications .
18
ADC Classifications
DAC Specifications .
. 14
• 20
• • • • 24
DAC Classifications
• 26
Microcomputers •
. 28
Analog Elements
•
iii
•
• 32
Page
3•
Hybrid Computer Inputs and Outputs
General
.
• • • • 33
. 35
Inputs .
Outputs
•
•
Scaling
4.
Evaluation of Potential Implementations
• • 39
• 39
Hardware Considerations
•
• 43
Software Considerations
• 59
Overall Memory Map .
. 62
. . .
Specifications and Anticipated Performance
Packaging
64
............... .
• • 64
Microcomputer Selection and Performance
• 66
Analog Component Selection . .
. 69
Converter Selection
72
Hardware Integration .
6.
• 36
. 37
Evaluation of Alternatives . .
5.
• 33
Applications
. . .
•
•
• 75
. 84
.
Appendixes
A.
Analog Coprocessor Addressable Components . . . 88
B.
Dual-Coprocessor Card Component Listing .
Bibliography • .
.
• .
.
. • .
iv
. .
. . • . . . .
. 91
. 94
LIST OF FIGURES
Figure
Page
1.
Spectrum of Automatic Computers
2.
True Hybrid Computers
.
.
. 15
3.
Parallel Hybrid Computer
.
.
. 16
4.
Quasi-Hybrid Computer .
5.
Dual-Coprocessor Hybrid Computer
6.
Dual-Coprocessor Block Diagram
7.
Input Converters and Bus
8.
Output Converters and Bus .
9.
Digital Coprocessor and Busses
10.
. . 12
.
. 16
.
. 41
. 44
• • 46
.
. 47
•
Analog Coprocessor to Digital
Coprocessor Interface • . .
• 48
• 50
11.
Analog Coprocessor Block Diagram
•
12.
Analog Coprocessor Integrator
Array and Analog Bus
• • 53
13.
Individual Integrator . . . . • .
.
14.
Analog Coprocessor Coefficient Array
. 56
15.
Analog Coprocessor Input and
Output Summing Array
• . .
. 58
.
• 52
. 55
16.
Analog Programming Techniques
.
. 61
17.
Memory Map
•
• 63
18.
Dual-Coprocessor Hybrid Expansion Card Cage . • 65
v
Figure
Page
19.
Input/Output Summing Array Chip .
20.
Integrator Array Chip . . .
21.
Order-Sliced Analog Processor .
22.
Integrator Array Chip with
Feed Forward Capability . . . . . . . . . . . 83
vi
.
. 78
• • • 79
81
ABSTRACT
A HYBRID COMPUTER INTERFACE
USING DUAL COPROCESSORS
by
Mark Scott Hutchenreuther
Master of Science in Engineering
Analog and hybrid computers have not yet benefitted
from the impact of microprocessors.
Combining a state-of-
the-art microprocessor with equally modern analog, digital,
and conversion components results in a compact versatile
hybrid computer.
Equal in power to room-sized first genera-
tion and rack-sized second generation hybrids, the proposed
dual-coprocessor hybrid computer fits in an expansion unit
for the IBM PC or PC-compatibles.
Like the large hybrid computers of the 1950s and 1960s,
either the analog or digital coprocessor can operate independently as an analog or digital computer.
Both can
operate simultaneously in parallel as well, with either the
digital coprocessor utilizing the analog for subroutines,
the analog utilizing the digital for repetitive operations,
vii
or both operating separately.
Programming and control of
both coprocessors is performed by the host computer using
the high-level language FORTH.
In the case of the digital
coprocessor, the host computer compiles the FORTH program
in the machine language of the coprocessor, which is then
stored in common RAM.
Programming of the analog coprocessor
is accomplished by using extensions of the FORTH language to
address latching buffers which control the digital ·coefficient potentiometers, analog switches for programming and
scaling, and input and output summing amplifiers.
Additional extensions of FORTH control the numeric data processor and provide mathematic functions such as sine, log,
cosine, and exponent for the digital coprocessor.
Numerous interfaces are provided both between the
coprocessors and host computer, and the coprocessors and the
physical world.
The purpose of the former is to enable the
host computer peripherals to be used by the hybrid for
display, storage, and printout.
The latter enables the
hybrid to interface either coprocessor to both analog and
digital inputs and outputs.
In addition, through various
interconnections using ADCs and DACs, the hybrid can operate
in bilateral mode, or in unilateral mode.
In the unilateral
mode, the analog coprocessor can precede the digital, or the
digital can precede the analog.
viii
CHAPTER l
Historical and Technical Perspective
Computer History
While the ancient Chinese abacus might be called the
first digital computer, and Pascal's adding machine could be
called the first analog computer, both were mere calculators.
The same can be said for the machines of Leibnitz,
Babbage, and Hollerith.
It was not until the 1930s that the
basis for modern computers was really developed.
The truly
seminal analog computer was the differential analyzer built
by Bush and Hazen at MIT in 1930.
In 1939, Aiken began work
on the IBM Automatic Sequence Controlled Calculator (ASCC)
or Mark I.
Completed in 1944, it was the first electro-
mechanical device, but it still was not a computer.
Even
the first all-electronic device, the Atanasoff-Berry
Computer or ABC of 1938 did not quite qualify as a computer.
Although the ABC had many elements of the modern electronic
computer, it never operated as a complete machine.
1
2
Nevertheless, it was legally declared the first electronic
computer.
1
The loser in the legal battle to determine which device
was the first electronic computer was the Electronic
Numerical Integrator And Computer (ENAIC) completed by
Mauchly and Eckert of the Moore School of Electrical
Engineering at the University of Pennsylvania in 1946.
2
ENIAC and her offspring, the Electronic Delay Storage
Automatic Calculator (EDSAC) of 1949 and the Electronic
Discrete Variable Automatic Computer (EDVAC) of 1951, are
considered early first-generation or pre-first-generation
computers.
Yet the true honor of being the first electronic
computer really goes to the British COLLOSUS of 1943,
perhaps even to the German Zuse Z3 of 1941,
4
3
and
which was not
known until well after World War II had destroyed it.
A second computer appeared in 1951, the UNIVersal
Automatic Computer (UNIVAC I).
Performing additions three
orders of magnitude faster than the Mark I at 282 microsec1
Joel Shu r kin , =E;::,;n:..;;gL.:i~n.:..:e~s::._.::.o=f--=t:.=.h:.::e::__:M:.:.:~:=.:·n:.=.d=-=-:_..:.A~H:::..:~=..:·s=-t=-o=r..l..y--=o=-=f~t==h=e
Digital Computer (New York: W. W. Norton & Company,
1984), pp. 284-289.
2
Shurkin, p. 285.
3
Shurkin, p. 296.
4
Anthony Ralston, ed., Encyclopaedia of Computer
Science and Engineering, 2nd ed.
(New York: Van Nostrand
Reinhold, 1983), p. 533.
3
onds,
5
UNIVAC I was the first commercially available com-
puter.
IBM developed their 701 Data Processing System in
1952 and entered commercial competition with their model 650
in 1953.
Between 1951 and 1958, the first generation of
electronic computers relied on vacuum tubes for their logic
circuits.
Transistors were used in some of the circuits of the
UNIVAC II developed in 1955, and were used exclusively in
TRADIC of Bell Laboratory in 1954, but it was not until 1958
that the second generation of computers began.
The IBM 7070
and 7090 of 1958 and their 1401 of 1959 put the transistorized computer into many businesses, because the cost
was so much less than that of the older vacuum tube models.
Computers such as the CDC 6600 of 1964 performed additions
in 300 nanoseconds, another three orders of magnitude faster
6
than the Mark I.
Introduction of the IBM 360 in 1964 ushered in a third
generation of computers.
Transistors were replaced by
integrated circuits as the logic elements.
Miniaturization
had also begun, with DEC introducing their PDP-5 minicom7
puter in 1963 and the PDP-8 in 1965.
Intel carried
miniaturization a step further with the introduction of
5
Phillip H. Enslow, Jr., ed., Multiprocessors and
Parallel Processing (New York: John Wiley, 1974), p. 3.
6
7
Enslow, p. 3.
Ralston, pp. 555-556.
4
their 4004 microprocessor in 1969, followed by the 8-bit
8008 and 8080 in 1972.
8
The minicomputer aided the development of smaller and
less expensive hybrid computers as well.
Development of
these powerful hybrid computers was bringing the analog and
digital factions back together.
Each faction was now
realizing that the other type of computer had advantages
over theirs, and that merging aspects of both types in
hybrid computers was beneficial.
Rapid developments were
taking place in the area of interfacing digital computers to
the analog world, particularly through design of smaller,
faster analog-to-digital and digital-to-analog converters.
Hybrid computation had brought the development of analog
computers out of the shadow of digital development.
The electronic computer was initially developed for the
military to perform tedious calculations and produce complex
printed artillery tables.
The ability of the digital com-
puter to handle large volumes of data led to post-war commercialization for application in business and industry.
The first non-military analog computer, or electronic
differential analyzer, was developed by the Reeves
Instrument Corporation in 1947 and served as the forerunner
9
of REAC.
Applications of the analog computer were more
8
9
ed.
Ralston, pp. 973-974.
Clarence L. Johnson, Analog Computer Techniques, 2nd
(New York: McGraw-Hill, 1963), p. 1.
p '
5
limited than those of the digital computer, yet by the
mid-1950s, several companies were marketing analog computers, including Boeing, Beckman, Electronic Associates,
Goo d year, an d M1. d - c entury. 10
.
Analog computers found w1de
application in the areas of research, simulation, and
education.
Analog computer evolution followed that of digital computers, from vacuum tubes, to transistors, and finally to
integrated circuits.
Each generation of analog computer
included more digital elements and the analog computer
evolved into more of a hybrid.
This digital control and
the advances in digital simulations led to the widespread
belief that analog computers and even analog/hybrid com11
puters were obsolete.
Digital and analog computer factions had evolved partly out of professional rivalry, but
primarily because an individual did not have time to keep
12
abreast of both rapidly developing fields.
Analog Computers
In spite of the professional prejudices espoused by the
two factions, both computer types were benefitting from the
10
Granino A. Korn and Theresa M. Korn, Electronic
Analog Computers, 2nd ed.
(New York: McGraw-Hill, 1956),
pp. 395-407.
11
Granino A. Korn and John V. Wait, Digital
Continuous-System Simulation, (Englewood Cliffs, NJ:
Prentice-Hall, 1978), p. 14.
12
George A. Bekey and Walter J. Karplus, Hybrid
Computation, (New York: John Wiley, 1968), p. 3.
6
advances in electronics and both had their advantages.
Attributes of each computer type are in most cases directly
related to the characteristics of the computers and became
the advantages and limitations espoused or attacked by the
13
two groups.
In the case of the analog computer:
1.
The greatest attribute of an analog computer
is that it treats dependent variables in continuous form.
2.
The speed of the machine is limited by the
bandwidth of the computing elements, not by the complexity
of the problem, thus these machines are fast, working in
real time.
3.
Operations such as addition, multiplication,
integration, and generation of non-linear functions can be
performed quite easily.
Conversely, the ability to handle
non-numerical information, to store information, to provide
extended time delays and to make logical decisions is very
limited.
4.
All computational elements operate simulta-
neously, hence the machines feature parallel operation.
5.
Programming techniques are based on electrical
analogs for physical systems.
Computer elements having
transfer characteristics analogous to the physical system
under study are merely substituted for the various physical
elements.
13
Bekey and Karplus, pp. 4-5.
7
6.
Analog hardware of the system under study can
be easily included in the computer simulation.
7.
The engineer can modify the system under study
directly, by adjusting coefficient settings on the computer.
A potential problem with this apparent ease in programming
is that to change the value of a single variable, several
coefficient potentiometers may require adjustment to
accomplish this program change.
8.
Accuracy of individual computer components,
a function of their quality, directly determines the
accuracy of the computer.
This accuracy, or component
14
tolerance, is typically 0.01% in the best machines.
This
can accumulate overall in the simulation to create a rather
great inaccuracy.
Nevertheless, the components that comprise an analog
computer have benefitted greatly from advancements in the
state of the art.
While no one has announced a miniature
modern analog computer recently, the op-amps and other elements have all benefitted from the revolution in integrated
circuits.
The same advances that have enabled entire digi-
tal computers to be built on a single integrated circuit
chip have been applied to the area of analog or linear circuits.
Designers are almost universally taking specific
applications of analog or hybrid computers and placing the
dedicated circuits on a single chip.
14
In one case a limited
Korn and Korn, Electronic Analog Computers, p. 158.
8
analog computer has been built on·one chip and is advertised
as such.
15
Perhaps the most common application of hybrid computers
has been in the area of signal processing.
Most manufac-
turers have devised three-chip systems, with a single digital processor chip interfaced with an analog-to-digital
front end and a digital-to-analog back end.
Again, one com-
pany has put all three major components onto a single
16
.
c h l.p.
Digital Computers
But integrated circuit technology had a far greater
impact in the digital circles.
For years, the primary
advantage of digital computers was in the ease of application to business and industry.
With integrated circuits
came miniaturization followed by integration, and the race
to get the most electronic architecture onto a single chip.
This led to TTL integrated circuit elements from individual
logic gates to counters, registers, and multiplexers.
When
the first individual components of computer systems appeared
on individual chips, such as the central processing units
and memories, a new race began in the area of application
and use of microcomputers in all sorts of commercial and
15 Forrest M. Mims, III, "The Computer Scientist:
Analog Computer Techniques for Digital Computers,"
Computers & Electronics, September 1984, p. 31.
16
Dave Bursky, "Technology Report," Electronic Design,
Vol. 32, No. 10, 17 May 1984, p. 103.
9
consumer devices and systems.
As entire microcomputers
became available on a single chip, this accelerated.
Now
the proponents of digital computers were applying the attributes of digital computers everywhere.
Whether it is a
large mainframe computer or a single-chip microcomputer, the
characteristics of a digital computer include the
following:
17
1.
All data, including the dependent variables,
are handled as discrete values or quantities.
2.
Speed of a digital machine is directly propor-
tional to the complexity of the problem.
The internal clock
has an effect on this, but problem comlexity is the ultimate
determinant of computing time.
3.
Arithmetic operations are basically limited to
addition and multiplication.
Integration and function
generation require numerical methods such as approximation
techniques.
These problems are somewhat overshadowed by the
ability of the digital machine to easily store and access
large amounts of numerical data, to operate in floating
point mode, to make logical decisions, to provide looped
time delays, and to handle all sorts of non-numerical
information.
4.
Digital computational elements must operate in
series, with a minimum of parallel sub-operations.
This
serial operation, a limiting feature of the universally
17
Bekey and Karplus, p. 5.
10
adopted von Neumann architecture, greatly impacts the
overall speed of the machine.
Various types of parallel
architecture are presently being advanced to dramatically
speed up the operation of digital computers.
5.
18
Programming techniques are purely mathematic.
The physical system under study must be reduced or expressed
as a series of equations, which may or may not correspond to
the elements of the system being simulated.
6.
Complex interfaces are necessary to connect
hardware from the system under study to the computer.
This
is not a disadvantage, but rather a method of applying the
digital computer to such areas as automatic testing.
7.
Data flow within the machine can be easily
altered or controlled based on the results of calculations.
..
In addition to the ability to automatically branch within
the program, the digital computer can perform reiterative
operations by automatically changing variables over a
prespecified range.
8.
Accuracy of the digital machine is a function
of the number of bits and the numerical technique selected
for the individual problem.
This great potential for
accuracy is perhaps the greatest advantage of the digital
computer, just as speed is the primary advantage of the
analog computer.
18
Carole Patton, "Technology Report: Advance Computer
Architectures," Electronic Design, Vol. 32, No. 9, 3 May
1984, pp. 175-194.
' '
11
Hybrid Computers
It was the idea of combining the accuracy of a digital
computer with the speed of an analog computer which led to
the development of large and sophisticated hybrid computers.
The spectrum of potential variations of hybrid computers is
shown in Figure 1.
19
The first hybrid computers, developed
in the mid-1950s, were as large as their digital counterparts and often larger depending on how much analog equipment was added to a normal digital computer.
Again,
miniaturization and integrated circuits aided the development of hybrid computers, primarily the development of
single-chip analog-to-digital and digital-to-analog converters.
It was this development that provided an easy means
of implementing the motivations for combining digital and
20
analog computers into a hybrid system:
1.
A primary concern was to combine the speed of
the analog computer with the accuracy of the digital.
2.
There was a strong need to use system hardware
in digital simulation, both in research and development and
in automatic testing.
3.
The flexibility of analog simulation could be
increased by using digital memory and control.
19
20
Bekey and Karplus, p. 7.
Bekey and Karplus, p. 13.
,,
'
Automatic Computers
--~;"'"''A~
L'"" '"'''D
~
Analog with
dtgttal concepts
A~alog
[
Predominantly Digital
7
with~--=-------.
/
DigJ
analog concepts
/
Digital with
analog hardware
w"ith di.gttaltype numerical
____t:_:_~iq~~s
[
~
/
[
Pure digttal
~----I Wtth analog-type
I
mterprettve roultnes
With analog type-
Analog with
---~
dtgttal hardware
Analog wtth dtgttal ~
computer
programmtng
- ---------------
--A~~j.;-g-;,~thdigital
[
logtc and
programming
J
--------------·--··.
[
···-----
Digital with analog
arithmetic elements
Analog with
dtgttal subunits
----···--·-----
[
.
-----Analog using
digttal computer
--~-:~e~~a.!.~:ks
Figure 1.
Digital using
analog equipment
as subroutine
Spectrum of Automatic Computers
1-'
N
13
4.
The speed of digital computation could be
increased by utilizing analog subroutines in place of
complex numerical techniques.
5.
It was possible to combine both continuous
analog input data and discrete digital data for processing
by the computer.
While the first motivation, that of combined analog
speed and digital accuracy, may have been the driving force
behind hybridization and the rapid development of hybrid
converters, it was probably a combination of the second and
third that really opened up the field of hybridization.
The
coupling of physical devices to the powerful digital memory
is perhaps most visibly manifested in the appearance of
video arcade games and home video games.
It is ironic that
the explosive development of microcomputers for video games
actually brought the hybrid microcomputer home to the consumer, as a digital computer with an analog joystick or
paddle.
This has resulted in a bootstrap effect, lowering
costs of hybrid devices and also has resulted in a new
explosion of development of many different types of hybrid
elements.
It might not be unreasonable to suggest that the
hybrid computer now reigns supreme, it just is no longer
called a hybrid computer.
CHAPTER 2
Hybrid Computer Elements
Overview
.
As s h own ~n
hybrid computers.
.
F~gure
2 , 21 there are three types o f
true
In the two unilateral schemes, infer-
mation flows in only one direction through an analog and
digital computer connected in series and interfaced with
appropriate converters.
The bilateral system allows infer-
mation to flow in either direction, and is really the same
as the first unilateral scheme with the analog loop closed.
If the bilateral machine is reoriented as shown in Figure 3,
a parallel hybrid computer is created.
A fourth scheme for a quasi-hybrid computer is depicted
in Figure 4, where the analog computer has been deleted and
the digital computer performs all the processing.
In the
spectrum of computers shown in Figure 1, this is merely a
pure digital computer, with input and output converters.
If
the analog converters are considered subroutines rather than
21
Bekey and Karplus, p. 13.
14
15
Digital
Digital
Inputs
,
~L
...
I
Computer
DAC
~
Analog
Inputs
Analog
Computer
a.
Analog
Inputs
Unilateral, Digital Preprocessing
___,.
Analog
DAC
Computer
I
~"
~
I
Digital
Inputs
,
b.
Analog
Outputs
•
~.lADC
Digital
Inputs
--+ Analog
Outputs
Digital
,
r
Computer
~
Digital
Outputs
Unilateral, Analog Preprocessing
Digital
ADC
Computer
Digital
Outputs
Analog
Computer
c.
Figure 2.
Bilateral
True Hybrid Computers
Analog
Inputs
Analog
Outputs
16
Digit al
Input s
,
~
,
~
..
..
I
Digital
I
Computer
,
·p
Di gital
Ou tputs
I
,.,
DAC
ADC
•
Analog
Analo g
Input s
Figure 3.
Parallel Hybrid Computer
-
Analog
Inputs
Digital
Inputs
...
,
I
An a log
Ou tputs
Computer
....
+
ADC
~"'
1lr
Digital
Computer
i
, .I
DAC
Figure 4.
r
Digital
Outputs
r
Analog
Outputs
Quasi-Hybrid Computer
17
peripheral devices, this variation could be termed digital
.
.
.
22
us1ng
ana 1 og equ1pment
as su b rout1ne.
In either case, the simple addition of an analog-to-digital
converter and a digital-to-analog converter on an expansion
card for a home microcomputer is the most popular and widely
available hybrid computer available today.
Regardless of which form of hybrid computer is used,
there are four basic elements in the system.
One of these
is the electronic components that collectively make up the
digital computer portion of the hybrid.
These are primarily
microcomputer chips, including the CPU, memory and ports,
and the various digital integrated circuits needed to connect these components and the converters.
A second element
is the electronics that collectively comprise the analog
computer, which in turn interfaces with the analog and digital converters.
The converters are of two types:
analog-
to-digital converters (ADCs) and digital-to-analog
converters (DACs).
The latter provides an analog signal to
an oscilloscope, analog X-Y recorder, or an appropriate cornposite signal for a video monitor.
The former takes an
analog signal and converts it to a digital signal that the
digital computer can process.
22
Bekey and Karplus, p. 9.
18
ADC Specifications
An analog-to-digital converter is a very sophisticated
and complex device.
Historically, this has always been the
weakest link in the hybrid computer.
A diversity of schemes
for conversion has evolved, an indication of the
frustration-spawned creativity which was applied to the
problem.
It is ironic that the more popular methods of
analog-to-digital conversion include a digital-to-analog
converter as an integral component.
In spite of the diver-
sity, there are certain specifications common to all analog.
. ' t a 1 conver t ers, 23 spec~'f'~cat~ons
t o- d ~g~
wh'~c h no d ou b t h ave
driven the diversity of converter schemes, in attempts to
better meet selected specifications.
Maximum allowable analog input voltage is a magnitude
and range, which is specified as unipolar or bipolar.
Both
aspects ultimately affect the resolution of the ADC, which
can be improved by increasing the number of output bits, and
reducing the maximum input magnitude.
Additional serial
analog circuitry can convert a unipolar ADC to a more versatile bipolar, but speed and accuracy are adversely
affected.
Total dynamic accuracy consists of the various dynamic
errors, the static digital errors, and the static analog
23
Herbert Taub and Donald Schilling, Digital
Integrated Electronics
(New York: McGraw-Hill, 1977),
p. 536.
19
errors.
24
Accuracy, or error specification, is generally
stated as a fraction of the least significant bit (LSB).
The LSB of 8-, 10-, 12-, 14-, and 16-bit converters
corresponds to 0.4, 0.1, 0.025, 0.006, and 0.0015 percent of
maximum input.
25
Since most converters have total dynamic
accuracies of plus or minus half a LSB, extremely high
accuracies can be obtained at even low resolutions.
Certain
significant contributing errors are usually also given, but
as a percentage of full scale reading.
There are many
methods of stating accuracy of ADCs, and unfortunately all
are used interchangeably in vendor literature.
Significant
contributors to inaccuracy are temperature stability,
linearity error, and digital quantization error.
Conversion time is one of the two most important specifications, along with accuracy.
This is a function of clock
frequency and converter type, with the latter having the
greatest impact.
All types of converters are ultimately
limited in conversion speed and frequency response by the
sampling theorem.
In order to avoid aliasing in the
reconstruction of a sinusoidal waveform, the sampling frequency must be more than twice the frequency of the input
waveform.
The period of the sampling frequency is the
minimum conversion time, which is modified as a function
24
H. Schmid, Electronic Analog/Digital Conversions
(New York: Van Nostrand Reinhold, 1970), pp. 485-496.
25
Dooley
Data Conversion Integrated Circuits, ed. Daniel J.
(New York:
IEEE Press, 1980), p. 36.
20
of converter type.
The many different classifications of
ADCs can be further grouped together as fast, very fast, and
ultra fast converters.
Moderately fast to fast converters
operate in the range of milliseconds, very fast converters
in the range of microseconds, and ultra fast converters in
nanoseconds.
Output formats that are compatible with microprocessors
are available, as are outputs for typical logic families.
Formats include binary, BCD, Gray code, and complementary
binary for unipolar operation.
For bipolar operation, for-
mats include sign magnitude, offset binary, 2's complement
and l's complement.
Output can be serial or parallel, but
only the latter is of interest in high speed interfacing to
microcomputers.
ADC Classifications
Analog-to-digital converters can be classified in many
ways, due to the sheer diversity of converter types.
26
Schmid
classifies ADCs as parallel-feedback, serialfeedback, indirect, high-speed high-accuracy, and ultra-high
speed.
Parallel-feedback types are the successive approxi-
mation, which is the most common, and the servo or tracking
converter.
Two types of serial-feedback converter are the
circulating and the charge-equalizing converters.
Indirect
converters include the ramp-comparison, pulse-rate or fre-
26
Schmid, pp. 233-263.
21
quency proportional to amplitude, and dual-slope integration
converters.
High speed converters are comparator and
cascade or propagation converters.
Loriferne
27
acknowledges such classifications as direct
or indirect, serial or parallel feedback, and pulse width or
frequency proportional to amplitude, but finally opts for
analog, logic, and speed groupings.
Analog types include
tracking, pulse-width modulation, dual-slope integrating,
counter or ramp, charge equalization, and voltage-tofrequency conversion.
Parallel and successive approximation
converters are logic types, and the cascade is the only very
high speed type he considers.
Accuracy must be considered with speed, and the role of
technology is to provide faster and more accurate ADCs.
As
a measure of this progress, and perhaps in an attempt to
better classify converters, Schmid suggests a speed-accuracy
28
product.
Although neither Schmid nor Loriferne quantitatively define their speed groupings, others have done
so.
Technology produces faster converters of a given type,
so grouping of converters by speed is relative, and subject
to change.
Typical speed ranges are listed below, with
appropriate converter types and current commercial examples.
27
Bernard Loriferne, Analog-to-Digital and Digital-toAnalog Conversion (London: Heyden, 1982), pp. 68-69.
28
Schmid, p. 328.
22
Any converter with a conversion time greater than 333
microseconds can be considered slow, 33 to 333 microseconds
is intermediate, and 3.3 to 33 microseconds is high speed or
fast.
29
The minimum conversion time for these ranges
corresponds to a conversion frequency of up to 300 kilohertz.
Integrating types of converters are the most widely
available commercial product in this grouping, and speed is
a function of resolution for these converters.
An 8-bit
integrating converter is considered fast at 0.3 milliseconds, while a comparable 16-bit converter could take as
30
A
long as 50 milliseconds to perform the same conversion.
conversion time of 250 milliseconds is not unreasonable for
31
a 16-bit converter.
A National Semiconductor
ADB1200/LF13300 is a commercially available example of a
12-bit dual-slope integrating converter with a conversion
32
time of 36 milliseconds.
The advantage of these converters is their great accuracy, at the obvious expense of considerable speed.
Also falling in this category are tracking
converters, which are not widely available, and the slower
successive approximation converters of higher resolutions.
29
Data Conversion Integrated Circuits, p. 36.
30
G. B. Clayton, Data Converters
Wiley, 1982), p. 79.
31
32
(New York:
Clayton, p. 79.
Linear Databook (Santa Clara, CA:
Semiconductor, 1982), Sec. 8, p. 4.
National
John
23
Slower successive approximation converters have conversion
times of 30 microseconds for 8 bits and up to 400 microseconds to 16 bits.
33
An ADC1210 has a conversion time of
34
only 26 microseconds for 12-bit resolution.
Very high speed converters have conversion times less
than 3.3 microseconds and greater than 330 nanoseconds,
corresponding to a conversion frequency range of 300 kHz to
35
3 MHz.
Many of the more common successive approximation
converters fall in this speed range, and the higher resolutions are breaking into this speed range.
Conversion times
for 8-bit resolution range from 0.8 to 30 microseconds,
36
which overlaps the high and very high speed ranges.
Considerable development is taking place with successive
approximation converters, primarily with 12- and 14-bit
resolutions.
Conversion times are 2-4 microseconds for
37
12-bit resolution,
and 50 microseconds for a 14-bit
38
converter with 16-bit resolution.
While the latter truly
belongs in the high speed grouping, relative to previous
33
34
35
36
Clayton, p. 78.
Linear Databook, Sec. 8, p. 4.
Data Conversion Integrated Circuits, p. 36.
Clayton, p. 78.
37 Frank Goodenough and Mike Riezenman, "New Products:
Analog," Electronic Design, Vol. 32, No. 14, 12 July 1984,
p. 234; p. 240.
38
Goodenough, "New Products: Analog," Electronic
Design, Vol. 32, No. 20, 4 October 1984, p. 292.
24
16-bit converters this is indeed very fast, by an order of
magnitude.
Ultra high speed converters have conversion times less
than 330 nanoseconds, or a conversion rate greater than 3
39
megahertz.
The most widely available commercial ultrafast converter is the parallel comparator or flash converter.
As with successive approximation converters, much
development is taking place in the area of flash conversion.
A 6-bit converter is available with a conversion time of
40
only 20 nanoseconds.
More typical are 8-bit versions with
41
200 nanosecond conversion times
and a 12-bit converter
42
that operates in only 500 nanoseconds.
As with successive
approximation converters, at the higher resolutions these
converters are divided between two ranges, in this case very
high speed and ultra high speed.
Again, the trend is
towards ultra high speed analog-to-digital converters of
high resolution.
DAC Specifications
Relative to the analog-to-digital converter, the
digital-to-analog converter is considerably simpler.
39
It is
Data Conversion Integrated Circuits, p. 36.
40
Goodenough, "Analog Circuits," Electronic Design,
Vol. 32, No. 3, 9 February 1984, p. 172.
41
Curtis Panasuk, "New Products: Analog," Electronic
Design, Vol. 32, No. 15, 26 July 1984, p. 312.
42
Goodenough, "Analog Circuits," Electronic Design,
Vol. 32, No. 2, 26 January 1984, p. 197.
" .
25
also somewhat of an optional component for the hybrid computer, since it is only necessary if an analog output is
desired for display on an oscilloscope, stripchart recorder,
analog X-Y recorder or if the output interfaces with hardware in the physical system.
As with the analog converter,
43
.
. .
1 converter h as severa 1 common spec~. f.~cat~ons.
t h e d ~g~ta
The number of input bits of the DAC determines the
number of output voltages or steps, and hence the resolution.
This can be expressed as the actual number of output
steps, as the percent of full scale for each step, or as a
voltage when considered with the output reference voltage.
As with ADCs, the accuracy of DACs is comprised of
several elements.
Temperature stability is a primary
contributer to inaccuracy as is output current drift.
The
effect of temperature on the resistor ladder has less impact
on the accuracy than might be expected.
Nonetheless,
linearity is a critical specification for DACs also.
The
simplicity of the converter, in comparison to the analog
converter, is an aid to accuracy as well.
The settling time parameter is comparable to conversion
speed for the ADC.
Unlike the ADC which provides an end-of-
conversion signal to the computer, the DAC provides no
timing feedback.
Conversion is assumed, but is fortunately
considerably faster than the ADC conversion time.
The out-
put will slew to a stable value well before the next conver-
43
Taub and Schilling, pp. 513-516.
26
sion begins, except in the case where a flash converter is
used as an input ADC.
In this case, the output DAC will be
slower than the input and a race could occur.
Settling time
is greater for the most significant bit than for the least,
but this really does not indicate it is a true function of
resolution.
DAC Classifications
Digital-to-analog converters are more universally categorized as parallel, serial and indirect.
Of these three
categories, both serial and indirect are considerably slower
than the parallel.
Parallel types include the weighted
resistor, the resistor ladder, the inverted ladder, the
. 1 .
.
d
mu 1 t1p
y1ng, 44 and the we1ghte
voltage. 45
Of the two weighted types, the weighted resistor is
simpler and faster than the weighted voltage DAC.
The major
disadvantage of the weighted resistor DAC is in the number
of
46
.
. h t1ng
.
res1stance
va 1 ues nee d e d f or t h e we1g
networ k .
the number of input bits increases, so does the number of
weighting resistances.
In an 8-bit converter, there is
already over two orders of magnitude difference in the
smallest and largest weighting resistors.
A 12-bit con-
verter would have a difference of over three orders of
44
45
46
Loriferne, p. 53.
Schmid, pp. 180-182.
Taub and Schilling, p. 497.
As
27
magnitude in the weighting resistors, which is impractical
from the standpoints of both fabrication and operation.
The primary advantage of the ladder network DAC is that
only two resistor values are needed for the R-2R network,
regardless of the number of input bits.
This greatly aids
in the manufacture of these devices and contributes to
greater accuracy.
By utilizing an inverted ladder network,
the voltage spikes and propagation delay can be eliminated,
47
.
. a f as t er set tl'~ng t~me.
.
resu 1 t~ng
~n
For high-speed digital-to-analog conversion multiplying
DACs are used.
The four-quadrant type is most common, where
a bipolar reference voltage is multiplied by a bipolar
48
binary number.
Although it appears this is more versatile, this particular design is slower than the high-speed
multiplying DAC.
The latter generally requires a separate
op amp, which greatly affects overall speed.
Regardless of the type of DAC, a more critical form of
classification is whether the DAC is voltage or current
output.
A voltage output DAC has a built-in op amp, which
reduces the complexity, may increase the overall conversion
speed, and reduces the versatility.
Current output DACs
require an external op amp to produce a voltage output,
which can be a major determinant in the overall conversion
time, but can result in greater versatility.
47
48
Loriferne, p. 49.
Loriferne, p. 53.
28
As with ADCs, DACs can also be classified by speed
range.
Ultra high speed DACs have settling times less than
100 nanoseconds, very high speed converters range between
100 nanoseconds and one microsecond, and low to high speed
devices have settling times greater than one microsecond.
49
A typical 4-quadrant multiplying 12-bit DAC will settle to
1/2 LSB in one microsecond in current mode.
50
Resistor
ladder DACs of similar resolution will settle to the same
accuracy in only 300 nanoseconds in current mode, or 2.5
51
microseconds in voltage mode.
Microcomputers
Of all the elements in the hybrid computer, the microcomputer itself is most likely the slowest, and the ultimate
determinator of overall speed.
This lack of overall speed
is not due so much to the computer clock frequency, but
rather to the number of clock cycles to perform each machine
instruction and the number of instructions needed to perform
a given operation.
The number of operations is a function
of the complexity of the problem programmed.
Hence, as
stated previously in the discussion of the advantages of
analog and digital computers, the speed of the digital computer is a direct function of the complexity of the problem
49
50
51
Data Conversion Integrated Circuits, p. 36.
Linear Databook, Sec. 8, p. 6.
Linear Databook, Sec. 8, p. 5.
29
or simulation which has been programmed.
In the case of a
hybrid computer, another determinator of speed is the data
bus width in bits.
Microcomputers are referred to as 8-, 16-, or 32-bit
machines, depending on the width of the internal data bus,
which usually corresponds to the length of the microprocessor registers as well.
The speed factor comes from the
resolution of the ADC and DAC relative to the data bus and
register width.
With an 8-bit machine, output of a 14-bit
ADC must be loaded into two 8-bit registers through an 8-bit
data bus in two consecutive load operations.
This process
will take roughly twice as long as loading in a single
operation with a 16-bit machine.
Similarly, a converter of
width greater than sixteen bits would require a 32-bit
machine for efficient operation.
While use of a bus smaller than the converters may slow
down the processing time, the operating speed might be partially regained by merely the increasing clock frequency
within the operating limits of the microprocessor.
This
tradeoff of frequency versus bus width is certainly viable,
however, with 16-bit microprocessor prices dropping and
clock frequencies increasing, it is perhaps more logical to
use the widest bus at the fastest speed that can be
afforded.
There are two other interesting possibilities for
increasing the throughput and decreasing processing times.
One is to utilize a numeric data processor, which is a
30
specialized coprocessor for performing floating point
operations up to one hundred times faster than the main
52
processor.
Additional speed can be gained by also adding
an I/0 processor to speed up that part of the processing.
The second method of increasing throughput is to use a
multi-processor chip, which may have four or more processors
53
performing specifid tasks in a pipelined architecture.
It is even feasible to combine these two methods for still
greater throughput, with minimal peripheral chips.
Other components of the microcomputer which are critical to efficient high-speed operation are memory devices,
input/output ports, and special-purpose bus-compatible
chips such as waveform generators.
The latter have value as
built-in audio frequency generators for sine, triangle, and
square waves and also variable duty cycle pulses.
Although
intended for use as sound generators in home computers, they
have equal value as signal generators within the audio frequency spectrum.
Memory devices include ROM or PROM for
storage of machine instructions and perhaps common subroutines or macros, and RAM for program and data storage.
Both
devices must have access times which are consistent with the
clock frequency, and it is this very problem that may ultimately determine and limit the maximum clock frequency.
52
Military Handbook
(Santa Clara, CA: National Semiconductor Corporation, 1984), Sec. 6, pp. 9-10.
53
Military Handbook, Sec. 6, pp. 11-13.
31
Input/output ports and buffers are needed only where
the selected ADCs and DACs are not microprocessor compatible, or where converters cannot be easily addressed and
operated directly.
An example of the latter is the use of a
16-bit converter with a 16-bit machine.
The start conver-
sion and end-of-conversion signals must be controlled by a
bidirectional port, apart from the converter input/output,
which may require a second port or buffer.
plays an important part in input/output.
Architecture
Considerations
include software versus hardware interrupt processing, and
whether the microprocessor utilizes memory-mapped
input/output or direct input/output via numbered ports.
While direct input/output is more efficient, since it uses
special instructions, it is not necessarily faster.
The selection of operating system or language can also
impact the operating speed of the microcomputer.
High-level
languages such as BASIC, Pascal, C, or FORTH simplify
programming and reduce the need for complex algorithms, but
they slow down program execution.
Conversely, the use of
assembly language and machine coding speeds up the execution, but programming is more difficult, and more complex
algorithms are required to perform even simple operations.
This tradeoff will be discussed in greater detail under the
topic of implementation.
32
Analog Elements
The analog computer portion of the hybrid computer is
the most variable component in the system, since it is a
direct function of the implementation selected.
At one
extreme, this may consist only of appropriate ADCs and DACs,
with all functions of the analog computer being performed by
the digital computer.
If extremely high resolution conver-
ters are used, the accuracy of this type of implementation
can actually exceed that of a typical true analog computer.
Combined with the great speed of a multi-task processor and
numeric coprocessor, the high speeds of the analog computer
could also be approached for relatively simple problems.
The opposite extreme is to incorporate numerous integrators,
amplifiers, and coefficient potentiometers as with a standard analog computer.
With the current state of the art,
considerably more digital hybridization of the analog computer can be achieved, and with fewer components in far less
space than had been accomplished in the late 1960s.
The
intermediate possibilities are as numerous and varied as the
tree in Figure 1 implies.
CHAPTER 3
Hybrid Computer Inputs and Outputs
General
Inputs and outputs of the hybrid computer may be digital as well as analog.
In a common bilateral hybrid shown
previously in Figure 2, the digital computer is provided
only digital inputs from the external world and provides
only digital outputs back to that world.
Similarly, the
analog computer receives only analog inputs from the external world and provides analog outputs back to the external
world.
Analog-to-digital and digital-to-analog converters
are used only to pass information between the two computers
within the hybrid system.
A more realistic and versatile approach to the bilateral hybrid computer system is the parallel hybrid shown in
Figure 3.
In addition to the features of the bilateral
hybrid, additional ADCs and DACs are added, so that analog
inputs can be processed directly by the digital computer.
The digital computer can then respond directly back to the
analog external system.
Similarly, digital inputs can be
applied directly to the analog computer, which can provide
33
34
digital outputs to the external system as well.
Each
computer can operate separately or together on a combination
of analog and digital inputs and provide a combination of
analog and digital outputs.
It is also possible to operate
this hybrid as either of the two unilateral hybrid schemes
also shown in Figure 2 by appropriate interconnection of the
two computers with ADCs and DACs.
One of the advantages of the analog or hybrid computer
is the ability to interface the computer directly to a
physical system.
Particularly in the area of testing and
evaluation, it is desirable to operate an individual component of a complex system, simulating the remainder of the
system with computers.
Although systems are becoming
increasingly digital, analog interfaces are still quite
common between individual components of the systems.
A
prime example is the analog signal that drives the control
surfaces in aircraft and missiles.
In fact it was the need
to interface actual missile autopilots to a full scale
simulation that led to the development of the first major
54
hybrid computer in the mid-1950s.
It is the very size and expense of aircraft and
missiles that makes computer simulation of these systems so
desirable.
Determination of frequency response of a system
is far easier and much less expensive with a computer simulation than with the actual system.
54
Bekey and Karplus, p. 15.
The same is true for
35
impulse response and power-of-time responses.
System error
and stability can be easily determined through simulation.
Inputs
To satisfy these simulation requirements, various
inputs are needed which are time-dependent voltage functions.
These input stimuli can be provided by oscillators,
waveform generators, pulse generators, ramp generators, and
so forth.
The basic requirement is that the output range of
the stimulus be compatible with the input range of the
hybrid computer system, either as a direct analog input to
an analog computer or as an input to an ADC.
The major use of a digital input in a hybrid computer
is for incrementing and decrementing in repetitive simulations.
This was one of the primary reasons that digital
sections were added to analog computers, which made them
pseudo-hybrid computers.
A second use of digital inputs is
as a second (or multiple) input, where the second input is
held constant while the primary input is varied.
Hence,
system response to a particular input stimulus for various
values of a second input can be determined.
If this digital
input is the output of a free-running counter, the resulting
random number can be used as a white noise input.
By synchronizing the digital input to the hybrid computer, several analog inputs can be generated with great
precision.
The synchronized counter can be used as a ramp
generator as an input stimulus.
Bit manipulation of a digi-
36
tal input can provide either a precise impulse input or an
ideal step input stimulus far better than an analog input.
Most conversion of analog inputs to digital inputs is
done by an analog-to-digital converter.
is converted to a binary number.
The input voltage
Two additional input con-
verters may be used, a frequency-to-voltage converter (FVC)
and a synchro-to-digital converter (SDC).
The former is an
intermediate device which can be used with· an ADC to derive
a digital signal from a variable frequency if desired.
The
latter is used to convert the output from a synchro to a
digital signal directly.
Both have value in interfacing a
hybrid computer to a physical system.
Outputs
At the output, where the computer may also have to
interface with the physical system, complementary converters
are also available.
Used in conjunction with a DAC, a
voltage-to-frequency converter (VFC) will convert a digital
signal to an output frequency.
To convert a digital signal
to a synchro output, the digital signal must first be converted to a resolver output using a digital-to-resolver converter (DRC).
The sine and cosine resolver output is then
converted to a synchro output with a reference and output
transformer.
A second use of the DRC is as a sine and
cosine input source for the analog computer.
The most common devices connected to the digital
outputs of hybrid computer systems for display purposes are
37
line printers and plotters.
Either overcomes the primary
disadvantage of analog plotters and stripchart recorders,
which is frequency response.
The discrete nature of the
output of a digital computer lends itself well to the task
of producing output response of very high frequency systems,
although this is not done in real time.
Devices that are commonly connected to the output of
analog computers, or the analog outputs of hybrid computers,
are oscilloscopes, stripchart recorders, and analog X-Y
plotters.
All of these devices operate in real time, pro-
viding a continuous recorded output from the analog/hybrid
computer.
The limitation of the stripchart recorders and
analog X-Y plotters is their ability to accurately record
only low frequency signals, although they do this much
better than digital devices which can add in a quantization
error in the process of discretely plotting data.
Only
oscilloscopes are able to display and record both low and
high frequency signals.
Scaling
Where the physical system is interfaced to the hybrid
computer input and/or output, interfacing is critical.
The
output voltage range of one device must be compatible with
the input voltage range of the other.
Digital computers,
and in general modern analog computers as well, are low
voltage devices.
Large input voltages must be scaled down
to a value the hybrid computer can work with, without
,, .
38
overdriving the inputs.
At the output, the output voltage
may need to be scaled up to interface with the physical
system at an appropriately high level.
Fortunately, op amps
are now available which will produce large output voltages
with a minimum of hardware.
Once the inputs are scaled down, and provisions are
made to scale the outputs back up, the digital computer can
easily process the problem.
However, it may still be
necessary to further magnitude scale the problem on the
analog computer so as not to overdrive the integrators and
amplifiers.
Generally, an indication is provided on an
analog computer to show when any of the integrators or
amplifiers are being overloaded and saturated.
Time or frequency scaling may also be required in the
case of the analog computer.
When this is done, usually by
changing the value of the feedback capacitors of the
integrators, the analog computer is also working in computer
time rather than real time.
Frequency or time scaling of
the problem for the digital computer is much easier, but
equally necessary.
CHAPTER 4
Evaluation of Potential Implementations
Evaluation of Alternatives
Several implementations of highly miniaturized hybrid
computers were considered.
The simplest of these is the
addition of an interface board containing ADCs and DACs to
an existing microcomputer.
Several versions of these
expansion boards are commercially available at the present
tirne.
55
The hardware merely interfaces the digital corn-
puter to the analog world, and suitable software is used to
perform analog operations. This is an inexpensive hybrid
implementation, potentially very accurate with suitable converters, but it is very limited and digitally slow.
This implementation can be digitally speeded up by
using one of the multiprocessors with a numeric
56
coprocessor.
To some extent, this is a totally digital
method of solving integral equations, which requires highspeed multiplication and which is traditionally in the
55
John Conway, "Real World Interfaces," Computers &
Electronics, September 1984, p. 58.
56
Product Guide,
(Santa Clara, CA:
p. 34.
39
Intel, 1983),
40
hybrid domain.
57
This is also well suited for solution of
differential equations using Runge-Kutta, and other classic
reiterative techniques.
Another means of speeding up this type of hybrid implementation is to incorporate an analog computer in the
design.
In the simplest sense, this produces a bilateral
hybrid computer, as shown previously in Figure 2.
With a
minimum of DACs and ADCs, this implementation can function
as either form of unilateral hybrid computer shown in the
same Figure.
Through extensive use of digitally gain-set op
amps and integrators and analog switches, the analog computer component can be programmed by the digital computer.
There is a loss of accuracy in the use of the analog computer, however, the gain in speed offsets this.
Either com-
puter could be operated independently of the other if
provisions are made to enable the coefficient potentiometers
and gains to be set manually, making this a scaled down
classic hybrid computer similar to the parallel hybrid
scheme shown in Figure 3.
Another implementation is quite similar to the parallel
hybrid with the addition of a digital coprocessor.
As shown
in Figure 5, the digital coprocessor functions as the digital computer and the host digital microcomputer is used only
as the programming and overall control element.
By using
the microcomputer to program both the digital and analog
57
Bekey and Karplus, pp. 422-424.
.
Digital
..
Inputs
Digital
Digital
... Outputs
Coprocessor
~
h
v
Host
Computer
·~
~
..
Analog
Coprocessor
Analog
Inputs
.•
P'
Analog
Outputs
---
Figure 5.
Dual-Coprocessor Hybrid Computer
,t:.
1-'
42
tal input can provide either a precise impulse input or an
ideal step input stimulus far better than an analog input.
Most conversion of analog inputs to digital inputs is
done by an analog-to-digital converter.
The input voltage
coprocessors, the programming can be done in a high level
language while the coprocessors operate in their·own efficient machine languages.
The peripherals associated with the host computer can
be utilized by the hybrid computer, and particularly by the
digital coprocessor.
The coprocessor need only store data
in common memory for the host computer to print on the line
printer.
This greatly simplifies the operation of the
coprocessor and speeds up the programming and program execution.
Similarly, the host computer can store and print con-
verted analog data from the analog coprocessor.
The stored
data can be saved on the host computer disk drive or
displayed on the video monitor as well as printed on the
line printer.
Another advantage of the dual coprocessor
implementation is the availability of the host computer for
parallel operations.
Of particular advantage is the possi-
bility of using the host computer to sample a particular
variable or variables and display, store or print the values
without disrupting or slowing down the operation of either
analog or digital coprocessor.
Since it is the digital coprocessor that interfaces
with the input ADC and output DAC, it is preferable to use a
16-bit or 32-bit coprocessor for speed and efficiency in
43
digital throughput.
Yet the hybrid computer can be
controlled and programmed by a host microcomputer with an
8-bit microprocessor.
Hence, the highly versatile parallel
bilateral hybrid coprocessor can be interfaced to any popular microcomputer system.
Hardware Considerations
Figure 6 is a block diagram of the proposed dual coprocessor implementation of the hybrid computer.
Several addi-
tional specialized converters are shown in dashed outlines
in the block diagram to indicate they are optional.
Individual components in the block diagram are discussed
below.
1.
places:
Analog-to-digital converters are used in four
as an analog input to the digital coprocessor, as a
digital output from the analog coprocessor, as an interface
between the integrator outputs of the analog coprocessor and
the digital coprocessor, and as a similar interface between
the integrator outputs of the analog coprocessor and the
host computer.
The ADCs that interface the analog copro-
cessor integrator outputs to the digital coprocessor and the
host computer are multiplexed from a set of sample and
holds.
Fast successive approximation converters can be used
for the host computer interface, but a flash converter may
be needed for the digital coprocessor interface for greater
speed in performing analog subroutines.
Similar flash con-
verters are more desirable at both the analog input to the
44
r-----,
r-----,
I
I
Host Computer
SDC
1- - - .
L ____ ..J
I
Interface
.,1
DRC
r--~r~l
I
1
'-----·J
.... ~
p
.,~...
Digital
Inputs
'
;
.
.J
;'
Digital
1--+-7"'~~ Outputs
Digital
Coprocessor
/'
ADC
ADC
Interface
DAC
DAC
Analog
,
Analog
Input
MUX
-
Coprocessor
Analog
Output
DEMUX
I
r - - ----,
I
FVC
I
L ____
I
I
.J
Figure 6.
Host Computer
Interface
~
r----1
I
I
VFC
I
I
~----.J
Dual-Coprocessor Block Diagram
45
digital coprocessor and the interface from analog coprocessor output to digital coprocessor input/output.
In
_general, all of the ADCs are bipolar with twos-complement
output coding and at least 12-bit resolution.
Figure 7
shows the arrangement of the various input converters, while
output converters are shown in Figure 8.
2.
places:
Digital-to-analog converters are used in three
as a digital input for the analog coprocessor, as
an analog output from the digital coprocessor, and for
interfacing between the digital coprocessor and analog
coprocessor.
save hardware.
The interface DAC can be a multiplexed type to
All of the DACs can be four-quadrant
multiplying with at least 12-bit resolution.
Of all the
DACs, the one which provides an analog output from the digital coprocessor is the most critical, both in speed and
resolution.
3.
The digital coprocessor is a 16-bit processor
for greater speed and efficiency in interfacing to the
12-bit converters.
As shown in Figure 9, the coprocessor
includes a minimum of dedicated ROM and PROM to hold both
common macros and subroutines.
Speed is further enhanced
through the use of a numeric data processor to handle
floating point mathematic operations.
The actual program is
stored in RAM which is also a part of the coprocessor.
Both
this program RAM and the data storage RAM are dual-port so
that the host computer can easily access this portion of
memory which is common to both microprocessors.
Operation
46
Synchro
Input
,..L ......
,
Digital
Inputs
,
/
..
Synchro-toDigital
Converter
/
Buffered
Latch
/
/
/
(PIA)
.
Analog-toDigital
Converter
Digital-toAnalog
Converter
.
Analog
Inputs
~
~
Analog
Input
Multiplexer
/
"
/
,
/_
,/
,"
,
~
,"
j
Data
Bus
Frequency-toFrequency
Input
Con trol
Bus
... Voltage
Converter
Address
Bus
Analog
Bus
Figure 7.
Input Converters and Bus
47
,
,
,
,/
,
/
I
Digital-toResolver
Converter
• Sin/Cos
Output
Buffered
Latch
..
(PIA)
Digital-toAnalog
Converter
/
/
/
Digital
Outputs
1-
Analog
!---+ Analog
Output
Outputs
Demultiplexer
_f
,
L_
/
t-
,/
L
,
Data
Bus
Contr ol
Bus
..
Address
Bus
Analog-toDigital
Converter
....
Voltage-toFrequency
Converter
__.. Frequency
Analo g
Bus
Figure 8.
Output Converters and Bus
Output
48
Numeric Data
Digital
Processor
Coprocessor
l
,
,
ROM
PROM
_,.
Host Computer
RAM
/
~
;
~
,v
l,-
I
I
/
Host Computer
/
,
Peripherals
L_
Buffer
,
Analog Coprocessor
Interface
/
Data Bus
Input/Output Converters
Control Bus
,
,
Address Bus
Figure 9.
Digital Coprocessor and Busses
I
49
of the coprocessor and numeric data processor is in machine
language which is compiled from the high-level language in
the host computer, assembled/cross-assembled to coprocessor
machine code, and stored in common RAM.
Data can be stored
in additional common RAM for retrieval by the host computer
for disk storage, screen display, or line printing.
4.
Much of the host computer to digital copro-
cessor interface is in the common RAM, whose dual ports
minimize contention.
The address and control bus are also
common between the three computers, which is not a problem
with the analog interface, but can be with the digital.
Hence, buffers are used on the common address and control
busses to enable the host computer and digital coprocessor
to operate simultaneously without interference.
5.
The interface between the analog coprocessor
and the digital coprocessor is minimal, as shown in Figure
10.
All that is really required is a DAC to interface the
digital coprocessor output to the analog coprocessor input,
and an ADC to interface the analog coprocessor output bus to
the digital coprocessor input.
The latter must be a
multiplexed ADC, since the actual output of the analog
coprocessor is a function of the complexity of the problem
which has been programmed.
An eight-bit sample and hold is
used in conjunction with the ADC to ensure that all integrator outputs are converted simultaneously.
Software in the
digital coprocessor takes care of the difference in polarity
of the alternating integrator outputs to eliminate the need
50
Digital Coprocessor
ADC
DAC
Multiplexer
Sample and Hold
,
.....
'---___;~
Analog
Inputs
Figure 10.
I
Analog
Coprocessor
Analog
f---+ Outputs
Analog Coprocessor to Digital
Coprocessor Interface
Q
•
51
for additional hardware.
A single output DAC is sufficient
for the interface from the digital coprocessor to the analog
coprocessor input, however, in addition to providing an
input to the lead integrator, the digital coprocessor can be
used to provide a second or multiple inputs to successive
integrator inputs.
Hence, the DAC must also be multiplexed.
It appears that there is some redundancy in the interface,
in that ADCs and DACs are already in place to interface the
digital and analog inputs and outputs for unilateral operation.
These converters are not sufficient to interface the
two coprocessors in the bilateral or parallel mode, and the
additional multiplexed converters described above are
necessary.
6.
A block diagram of the analog _coprocessor is
shown in Figure 11.
The primary block is the integrator
array and the associated analog bus, which is shown in
Figure 12.
Eight integrators are connected in series
without interstage inverters or coefficient potentiometers.
The output of each integrator is wired to the analog bus,
such that each stage is available as feedback to the lead
integrator, for summing as an output, and for interconnection to the digital coprocessor or host computer through
interfacing ADCs.
Integrators are interfaced to the host
computer individually and as a full set of eight.
As a set,
they are interfaced to the computer through an input set of
analog switches to perform a HOLD function, as in a typical
analog computer, and through a set of analog switches in the
(l
•
Input
Converters
Interface to
Digital Coprocessor
Analog Bus
Output
Convert·ers
Output
Coefficient
Integrator
Input
Coefficient
Array
Interface to Host Computer
Figure 11.
Analog Coprocessor Block Diagram
Ul
N
53
Analog Bus
vo 1
Vi
~~
~~
• • •
~~V
~'
J~
IC
1
~~/
IC
HOLD
RESET
8
Input Attenuation
Time Scaling
Initial Condition and Scaling Array
Data Bus
Control Bus
Address Bus
Figure 12.
I
,. /
,
~
,
L
Analog Coprocessor Integrator Array
and Analog Bus
54
initial condition setting circuitry to perform a RESET function.
The analog switches that control the integrator input
attenuation resistors and the frequency scaling feedback
capacitors are also controlled as a set of eight to enable
easy magnitude and frequency/time scaling of the problem
being programmed.
Individually, the integrators are inter-
faced to the host computer through a latched digital patentiometer to set initial conditions for each integrator to a
value between 0.00 and 19.99.
Figure 13 is a diagram of an
individual integrator showing various resistors, capacitors,
analog switches, and the initial condition potentiometer.
7.
Variable gain inverting and non-inverting
summers at the input to the lead integrator enable the
analog coprocessor to be programmed in classic Kelvin feed58
back technique.
Figure 14 shows a block diagram of the
input coefficient potentiometer array and a block diagram of
a typical potentiometer.
Potentiometers consist of a digi-
tal potentiometer with a setting range of 0.000 to
59
1.999
and a buffered latch. To prevent unnecessary
loading of the analog bus by unused coefficient patentiometers, analog switches and buffered latches can be used
at the input to the potentiometers.
An additional set of
58
Arthur Hausner, Analog and Analog/Hybrid Computer
Programming (Englewood Cliffs, NJ:
Prentice-Hall, 1971),
pp. 9-10
59
Data-Acquisition Databook 1984: Volume I,
Integrated Circuits (Norwood, MA: Analog Devices, 1984),
Sec . 9 , p • 17 7 •
R
vee
Digital
Potentiometer
Digital
Buffered Latch
Busses
>
v 01. 1
HOLD
Figure 13.
•
Output to
V . Analog Bus
01
and Next
Integrator
Individual Integrator
U1
U1
56
0
Vol
vo2
Analog Bus
Inputs
v.
J.n.]_
a.
--o
v2
Outputs to
Input
Summing Array
•
•
vo8
Other
Inputs
vl
•
0
0
v8
v.]_
Block Diagram, Input Coefficient Array
~
v.J.n
~
v out
Digital
Potentiometer
Digital
Busses
b.
-
Buffered Latch
Block Diagram, Typical Coefficient Pot
Figure 14. Analog Coprocessor
Coefficient Array
57
buffered latches is interfaced to the potentiometers to
enable the potentiometers to be set and read by the host
computer.
An array of programmable summers, shown in Figure
15, is used for programming and magnitude scaling at the
input, and a similar array is used at the output.
outpu t
f orma t
8.
.
~s
p h ase
The
. bl e. 60
var~a
The interface between the host computer and
analog coprocessor consists of a large number of output
ports to program the analog switches in the analog copracesser, and a few input ports to accept data input from the
analog output bus and the dedicated analog inputs and
outputs.
Either direct input/output or memory-mapped
·
I output ~s
· su~ta
· bl e. 61 Th e f ormer genera 11 y uses
~nput
parallel interface adapters (PIAs) and requires programming
of both the data direction registers and actual ports in the
62
PIAs.
The latter merely requires tri-state buffered
latches which appear as simple memory locations to the host
computer.
Memory-mapped input/output has some advantage
over the direct method in that data direction is fixed by
hardware and memory mapping provides more flexibility in the
address locations of the actual ports.
In the event an
60
Gene H. Hostetter, Clement J. Savant, Jr., and
Raymond T. Stefani, Design of Feedback Control Systems
(New York:
Holt, Rinehart and Winston, 1982), pp. 358-361.
61
Joseph J. Carr, Elements of Microcomputer
Interfacing (Reston, VA:
Reston Publishing Company, 1984),
pp. 99-100.
62
Carr, pp. 149-154.
vl
Inputs
v0
Output
v.1
Figure 15.
Analog Coprocessor Input and Output Summing Array
Ul
co
59
8-bit microprocessor is used in the host computer, direct
input/output has the additional disadvantage of being
somewhat limited by firmware to a fixed number of ports.
Software Considerations
Software for the coprocessor is assembly or machine
language.
Major repetitive operations such as integration
are handled as subroutines which are called from PROM firmware.
These subroutines make extensive use of the numeric
data processor in performing multiplications, divisions and
additions much faster than the coprocessor itself.
An
alternative method of performing integration and other
complex mathematic routines is to utilize the interfaces
with the analog coprocessor.
The complex calculations can
be programmed on the analog coprocessor and called as
subroutines by addressing the analog coprocessor from the
digital software.
There is some advantage to having com-
monality, or at least compatability, between the
microprocessor used in the coprocessor and that used in the
host computer.
Not only is there considerable software
efficiency, but the need for cross-assembly is eliminated.
The analog coprocessor is programmed by the host computer by loading latched analog switch arrays through buffered latches or PIAs.
feedback technique.
Programming is a modified Kelvin
Arrays of digital potentiometers are
used in lieu of ten-turn mechanical coefficient potentiometers and are set by programming the aforementioned
60
latches.
Inverters in the feedback paths and in the output
are minimized.
Additional analog switches are used to
select capacitor values for the integrators, for time and
magnitude scaling, for setting initial conditions, and for
performing HOLD and RESET operations.
By using the Kelvin
feedback technique for programming, the feedback path can be
simplified to one of an analog bus, which is accessible by
the analog coprocessor input, the analog coprocessor output,
the digital coprocessor, and the host microcomputer.
Figure
16 shows the traditional Kelvin feedback technique of analog
computer programming and the more modern phase-variable
technique for simulation diagrams, which is easily adaptable
to analog computer programming in general and to this implementation specifically.
Both the analog and digital coprocessors are programmed
by the host computer in a high-level language.
Suitable
languages include BASIC, Pascal, C, Ada, and FORTH.
Of
these, FORTH is considered the most feasible due its
63
. h erent expan d a b'l'
1n
1 1ty.
Any language can b e use d to
program the digital coprocessor with a suitable compiler,
assembler and cross-assembler if different main and coprocessors are used.
The analog coprocessor can be totally
programmed and monitored using POKE and PEEK in BASIC, and
similar statements in Pascal, C, Ada, and FORTH, since the
63
Thorn Hogan, Discover FORTH (Berkeley, CA:
McGraw-Hill, 1982), p. 6.
Osborne/
61
T(s)
=
y ( s)
2
-5s +4s-12
2
s 3 +6s +s+3
1
R ( s)
a. Phase Variable Simulation Diagram
-s
2
=
b + ~ _ R(s)
-s
a
a
a
R(s)
s
c/a
b. Kelvin Feedback Technique
Figure 16.
Analog Programming Techniques
0
62
buffered latches at each array of analog switches are
directly addressable.
The advantage of FORTH is that unique
statements can be created to program the switches more
directly and easily.
This can also be done in C with the
FUNCTION command, or in Pascal with a PROCEDURE, but not as
easily.
FORTH has the additional advantages of being more
compact t h an BASIC or P asca 1 , an d faster.
64
Overall Memory Map
Some of the memory interfacing has been shown in previous block diagrams.
Both the digital coprocessor and host
microcomputer have memory that is used only by each computer, and some memory that is accessible to both.
Common
memory assigned to the coprocessor is the program storage
RAM, and data storage RAM.
The host must be able to access
the former for programming, and the latter for peripheral
display and storage.
Thus this portion of the memory map of
the two processors must be common.
The program memory can
be common, but will not be accessed by the other processor.
Memory occupied by the analog coprocessor addresses needs
to be common to both the digital coprocessor and the host
computer for programming.
Figure 17 summarizes these
memory requirements for the overall system memory map.
Appendix A lists the addressable components in the two
coprocessors and the input/output converter arrays.
64
Leo Brodie, Starting FORTH (Englewood Cliffs, NJ:
Prentice-Hall, 1981), p. 4.
Spare Memory
Spare Memory
Unused
i
!
Common Data Storage RAM
Program RAM
Program RAM
Analog Coprocessor Latches, Coefficient Pots, and Analog Switches
(See Appendix A)
FORTH
Operating System
Host Computer
Operating System
Digital Coprocessor
Figure 17.
Unused
Analog Coprocessor
Memory Map
(j)
w
CHAPTER 5
Specifications and Anticipated Performance
Packaging
Versatility is one of the main features of the hybrid
computer implementation selected, however, the hardware
involved is considerable and presents a potential problem.
The IBM Personal Computer or one of the PC compatibles is
the host microcomputer targeted for the hybrid computer
expansion interface.
Room for a few circuit cards is
available in the IBM computer, but the need for an expansion
unit is anticipated, to provide room for additional circuit
cards.
As shown in Figure 18, major modules will be placed
on individual circuit cards.
four:
The minimum number of cards is
a digital coprocessor card, an analog coprocessor
card, an input converter card, and an output converter card.
Due to the large number of analog switches, coefficient
potentiometers, and buffered latches, two additional cards
may be required for the analog coprocessor input components
and output/interface components.
This will require wiring
the analog bus between the three analog coprocessor cards,
as well as the digital data, control, and address busses.
64
65
Host Microcomputer and Peripherals
Digital Coprocessor Card
Input Converters Card
Analog Coprocessor Input Card
*
Analog Coprocessor Card
i*
Analog Coprocessor Output Card
Output Converters Card
*
Analog Bus
Figure 18.
Dual-Coprocessor Hybrid
Expansion Card Cage
Q
'
66
The six-card implementation will almost certainly require
its own enclosure, however, it will make the hybrid computer
more compatible with the IBM PC compatibles.
The separate
enclosure can also contain power supplies for the digital
logic and the analog logic, which would benefit from a
higher voltage dual polarity power supply than the host computer would typically provide.
Although a typical computer
provides +12 vdc and -12 vdc, which is adequate for the converters reference voltages of +10 vdc and -10 vdc, the
operational amplifiers need at dual polarity supplies of at
least 18 volts, for 15-volt rails.
Microprocessor Selection and Performance
Whether the hybrid computer is contained within the
computer expansion slots or in a separate enclosure, it
interfaces to the host computer via the digital data,
control, and address busses.
As the host computer, the IBM
PC uses the Intel 8086 microprocessor, as does the compatible COMPAQ.
The related 8088 microprocessor is used in
the PCjr and the Heath and Zenith 100-series computers, and
the 80186 is used by the Tandy 2000.
All of these chips
share a common 16-bit bus structure, and can interface to a
common standalone version of this implementation of a hybrid
computer through the same data, control, and address busses.
Of the three related chips used by these computers, the
80186 is selected for its architecture, which includes all
of the functions of the key peripheral support chips on the
67
same chip as the microprocessor, and for its compatibility
with the 8086 and 8088.
This selection makes this hybrid
computer compatible with the widest selection of personal
computers likely to be encountered in industry, government,
and education.
In addition, FORTH has been implemented for
65
. d h'1g h - 1 eve 1
so the d es1re
t h e I BM P C an d compat1'bl es,
programming language is currently available.
An apparent
problem with FORTH is the lack of advanced mathematic functions, such as trigonometric functions, logarithms and exponentiation.
This is easily overcome by utilizing the 8087
66
numeric processor,
which is compatible with the 80186.
Addition of this coprocessor allows fast floating point
math to be performed in hardware, rather than software.
A lOOX increase in speed can be realized by this chip, with
a typical operation such as a 32-bit multiply taking only
67
12 microseconds.
This assumes the 80186 coprocessor and
its 8087 numeric processor are operating at the maximum
clock frequency of 8 MHz.
By using hardware rather than software to perform some
of the math, considerably less memory is needed for program
software.
The minimization of memory requirements for the
digital coprocessor is highly desireable.
Most or all of
65
Jonathan Amsterdam, 11 Computer Languages of the
Future, .. Popular Computing, September 1983, p. 150.
66
Memory Components Handbook,
Intel, 1983), Sec. 4, pp. 1-6.
67
Product Guide, p. 34.
(Santa Clara, CA:
68
the RAM is dual ported.
Single chip dual port RAM is
offered by several manufacturers, but it is very limited in
size.
For example, the Synertek SY2130 is only lK x
8-bits.
68
It is more reasonable to use the 64K x 1-bit
Intel 2164A with the related 8207 dynamic RAM controller and
8206 error correction unit, arranged for 64K x 16-bit dual
.
69
port operat1on.
This fast math processing greatly reduces the time
needed to perform complex programs which require frequent
repetitive multiplication and division.
Yet even with this
fast multiplication, a simple program will still be very
slow.
If an analog input is converted to a digital value,
multiplied by a constant, and reconverted to an analog
voltage output, it will still require a minimum time of 15
microseconds, and this ignores the basic input/output processing time.
This further assumes use of the 12-bit flash
analog-to-digital converter with 500 nanosecond conversion
time, and the weighted-ladder digital-to-analog converter
with a 2.5 microsecond settling time in voltage mode, which
were discussed earlier.
The corresponding sampling fre-
quency is about 67 kHz, which limits the maximum input frequency component to about 33 kHz.
This is adequate for
audio frequencies, but even a typical audio frequency appli-
68
Applications Information AN12:
SY2130/SY2131 1024
x 8 Dual Port RAM, (Santa Clara, CA:
Synertek, 1984), p. 1.
69
OEM Systems Handbook, (Santa Clara, CA:
1983), Sec. 3, pp. 70-130.
Intel,
69
cation would be more complicated than a simple multiplication.
Hence, even this high speed computer is relatively
slow for analog operations, although it is very accurate.
In all fairness to the digital computer, the processing can
be speeded up by running the input, computation, and output
in parallel.
The above example would only require 12 micro-
seconds to perform the operation, since the next input and
last output could be taking place during the multiplication,
but this is not a great increase in speed.
To operate at
high speed and high frequency, the analog portion of the
hybrid computer is needed.
With the analog computer, there
is a propagation time between input and output, but this is
merely delay time or phase shift, rather than a loss in
speed.
The digital computer stretches out the time response
of a system as a function of the program complexity, the
analog computer only causes a fixed propagation delay which
also varies as a function of program complexity.
Analog Component Selection
There is a loss of accuracy in the use of analog components, but the dramatic gain in speed outweighs this.
Operational amplifiers are capable of extremely high speed
operation, with accuracy a function of the components
selected.
This can be a problem when using the amplifiers
as integrators, where both external resistors and capacitors
must be used.
If 1% tolerances are specified for these com-
r .
70
ponents, considerable error can result when the tolerances
are accumulating through several stages of integration and
summing.
In contrast, a tolerance of 1% corresponds to a
converter of less than 8-bit resolution.
The analog switches used in this implementation have a
nominal resistance in the "on" position.
In the case of an
Analog Devices AD7510DI latched SPST switch, this is only
70
75 ohms,
which is generally negligible.
This low
resistance is far less than the input attenuating and magnitude scaling resistors of the integrators and
inverter/summers, and is also negligible in comparison to
the internal resistances of the Analog Devices AD7525 digi71
tally controlled potentiometer.
Even in the application
of switching the feedback capacitors, the resistance of the
analog switches will have less effect on accuracy than the
tolerance of the time-scaling capacitors.
Of all the components in the analog coprocessor, the
capacitors are the least accurate.
Typical values for the
feedback capacitors for analog computer integrators are 1,
0.1, and 0.01 microfarad.
These values are commonly avail-
able in 1% tolerance at a reasonable cost in either metal-
70
Data-Acquisition Databook 1984:
Vol. I, Sec. 16,
p. 13.
71 Data-Acquisition Databook 1984:
p. 177.
Vol. I, Sec. 9,
71
lized polystyrene or polypropylene.
72
It would appear that
polysulfone capacitors are somewhat superior,
73
but they are
not as widely available in even the 1% tolerance.
On the
other hand, both polystyrene and polypropylene types are also
available in 0.1% tolerance at greater cost.
74
Similarly, either metal film resistors or precision
wirewound resistors could be selected.
Of the two, the metal
film types have a somewhat higher reliability and would be a
75
.
b etter c h o~ce.
Either type is available in the value range
that is desired, and they are equally available in both 0.1
and 0.01% tolerances.
76
The final element in the analog coprocessor is the opamp, which has three different uses within the coprocessor.
Eight are used for integrators, ten are used as multiple
input and output summers and attenuators, and twenty-six are
used with the digital coefficient potentiometers.
In each
of these three cases, the amplifiers must have ·a high slew
rate, low drift, and high accuracy.
The integrators require
a higher gain than the summers, which are operating at a
72
Electronic Engineers Master Catalog 84-85 Vol. lA
(Garden City, NY:
Hearst Business Communications, 1984),
p. 1168; p. 1198.
73
Claude s. Lindquist, Active Network Design (Long
Beach, CA:
Steward & Sons, 1977), pp. 682-700.
74
75
76
EEM 84-85 Vol. lA, pp. 1052-1055.
Lindquist, pp. 649-667.
EEM 84-85 Vol. lA, pp. 1927-1994.
Q .
72
maximum gain of 10.
An Analog Devices type AD OP-37 is
selected for the integrator function because of its high
77
speed, low noise, and high gain.
The related AD OP-07 is
selected for the multiple input and output summers, and for
the digital potentiometers as we11.
78
While a high voltage
op amp would be beneficial as the final output for interfacing to the physical system, such as the Analog Devices
79
type 171,
additional power supplies with a very high
voltage output are required.
Additionally, both speed and
accuracy are compromised with the selection.
Converter Selection
The converters required at the input and output have
been partially discussed earlier.
The digital input, inter-
face, and output data busses are common, although they are
shown separately in the various figures.
Thus the digital
input and output ports can be one and the same, at the
expense of versatility.
Similarly, the ADC and DAC that
interface between the analog and digital coprocessors could
be combined with the output ADC and input DAC respectively,
but again with reduced versatility.
It is better to retain
the input DAC for interfacing to the analog coprocessor
77
Data Acguisition Databook 1984:
Vol. I, Sec. 4,
Data Acguisition Databook 1984:
Vol. I, Sec. 4,
Data Acguisition Databook 1984:
Vol. I, Sec. 4,
p. 143.
78
p. 129.
79
p. 21.
73
without multiplexing, as is done at the interface between
coprocessors.
Similarly, the output ADC is needed to apply
the final summed output to the digital coprocessor and host
computer, as well as the individual outputs from the analog
bus.
As was shown earlier, a flash converter is slow in comparison to the digital computer, faster than it need economically be.
Thus a simple successive approximation ADC can
be used at the analog input for digital conversion.
A typi81
80
cal 12-bit converter, such as the AD574
or ADC128o
is
suitable for this purpose.
This could also be used at the
analog to digital coprocessor interface with an eight chan82
nel multiplexer such as the AD7501
and eight sample and
83
holds such as the AD585.
This same ADC can be used at the
output for hardware commonality.
A common 12-bit DAC can be used at both the input and
output of the hybrid computer.
The difference in speed
between a weighted-resistor type and a four-quadrantmultiplying type is not that significant, hence, a
80
P· 55.
81
82
Data Acguisition Data book 1984:
Vol. I, Sec. 10,
Linear Databook, Sec. 8, p. 97.
Data Acguisition Databook 1984:
Vol. I, Sec. 16,
Data Acguisition Databook 1984:
Vol. I, Sec. 14,
P· 5.
83
p. 31.
74
voltage-output ladder converter such as the AD386o
selected.
84
is
At the interface, the reverse of the analog-to-
digital conversion can be realized, or an eight-channel DAC
can be used.
The former scheme is chosen, using the same
sample and hold and multiplexer for additional hardware commonality.
The remaining converters at the input and output are
optional.
These include the input synchro-to-digital con-
verter, the input frequency-to-voltage converter, the output
voltage-to-frequency converter, and the output digital-toresolver converter.
The last three devices are the most
useful, since frequency conversion is common, and the
sine/cosine output of the resolver converter is a useful
analog coprocessor input.
converter is the DRC1765,
A suitable digital-to-resolver
85
which is a 14-bit converter.
the input, a similar 14-bit combination synchro-to-digital
and resolver-to-digital converter such as the
SDC/RDC1740
86
is selected.
Hardware diversity is further
87
minimized by selecting the AD65o
combination voltage-tofrequency and frequency-to-voltage converter.
84
P· 9385
Data Acguisition Databook 1984:
Data Acguisition Databook 1984:
13.
P·
86 Data Acguisition Databook 1984:
p. 23.
87
Data Acguisition Databook 1984:
P· 15.
Vol. I, Sec. 9,
Vol. I, Sec. 13,
Vol. I, Sec. 13,
Vol. I, Sec. 111
At
75
Both the converters and potentiometers require a means
of addressing and switching.
Addressing is accomplished by
connecting the devices to the digital busses with
Am29845
88
8-bit non-inverting latches. All of the analog
89
switches are AD7510DI
dielectrically isolated quad SPST
switches.
A summary of the selected devices and the circuit cards
on which they are located is listed in Appendix B.
These
selections are based on versatility for the overall hybrid
computer, however, a secondary consideration has been the
minimization of hardware diversity.
Hardware Integration
The proposed analog coprocessor consists of a very
large number of discrete digital and analog chips of varying
degrees of integration.
These include forty-four op amp
chips, twenty-six digital potentiometer chips, thirty-four
analog switch chips and sixty-nine eight-bit buffered
latches.
There may be other assorted logic gates needed to
properly interface and operate the buffered latches with the
digital address bus, and numerous resistors and capacitors
are also required.
Due to the sheer number of chips, at
least 173 in the analog coprocessor, at least three circuit
88
MOS Microprocessors and Peripherals, (Sunnyvale, CA:
Advanced Micro Devices, 1984), Sec. 6, p. 14.
89 Data Acquisition Databook 1984:
p. 13.
Vol. I, Sec. 16,
76
cards will be required.
As shown in Appendix B, this still
results in a high chip count per circuit card for the input
summing array card, the integrator array card, and the
output array card.
This degree of integration corresponds roughly to that
of the central processing unit of the first minicomputers.
The advancing technology of integration eventually placed
the entire CPU on a single chip, which became the first
microprocessor.
Further improvements in integration added
the functions of several peripheral chips to that of the
microprocessor, culminating in the one-chip microcomputer or
mi.crocontroller.
In a parallel manner, integration in the analog field
led to one-chip operational amplifiers and then to chips
containing several amplifiers.
Integration has temporarily
digressed to a single amplifier on a chip, but all of the
components for digitally setting the gain of the amplifier
90
have been added in some cases.
Specialized communications
chips have then moved this concept forward by placing entire
complex analog and hybrid functions on a single chip or
91
group of chips.
But in spite of claims that a chip
92
contains an entire analog computer,
no one has actually
90
91
92
Goodenough, 12 July 1984, p. 234.
Bursky, p. 103.
Mims, September 1984, p. 31.
77
done so, or at least they have not gone beyond placing a
very few integrators on a single chip.
By taking advantage of the state of the art in integration, the entire proposed analog coprocessor could be built
with two basic chips.
The first chip would contain the
input or output digital coefficient potentiometers, the
summing amplifiers, and the various latches and analog
switches to program the input or output.
As shown in Figure
19, the entire ten-input input array or eight-input output
array could be placed on a single 40-pin DIP.
By doing
this, the architecture can be simplified greatly, utilizing
16-bit coefficient registers in conjunction with the digital
coefficient potentiometers and a 2-by-4 sign and magnitude
decoder.
With current LSI or VLSI technology, there should
be adequate physical space to accommodate these functions,
especially if they are integrated on a single die.
At the
very worst, half of the proposed input or output summing
array could be placed on the 40-pin DIP and two of the chips
would be cascaded to handle up to ten inputs.
In a similar manner, it would be possible to squeeze an
entire eight-integrator array onto another 40-pin DIP with
all the related initial condition digital potentiometers and
analog switches.
As shown in Figure 20, the architecture of
the integrator array chip is very similar to that of the
summing array chip.
The feedback capacitors would be the
most likely component to cause problems with physical space,
Q
•
7B
Digital Busses
Pot Sign/
Magnitude
Registers
v0
2 X 4
DEMUX
v10
a.
Pin 1
2
3
4
5
6
7
B
9
10
11
12
13
14
Internal Circuitry of Chip
DO
D1
D2
D3
D4
D5
D6
D7
DB
D9
D10
D11
D12
D13
b.
15
16
17
1B
19
20
21
22
23
24
25
26
27
2B
D14
D15
AO
A1
A2
A3
Vo
V1
V2
V3
V4
V5
V6
V7
29
30
31
32
33
34
35
36
37
3B
39
40
Pin Allocation for the Chip
Figure 19.
Input/Output Summing
Array Chip
VB
V9
V10
Vee
Vee
Vdd
Vss
R/W
spare
spare
spare
spare
{~
'
-79
Digital Busses
Vee
IC
Registers:
R
8 IC Pots
RESET
HOLD
Attenuation
Scaling
RESET
Scaling
C Array
v
v.
1n
Attenuation
R Array
a.
Pin 1
2
3
4
5
6
7
8
9
10
11
12
13
14
Internal Circuitry of Chip
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
b.
HOLD
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D14
D15
AO
A1
A2
A3
Vin
Vout1
Vout2
Vout3
Vout4
Vout5
Vout6
Vout7
29
30
31
32
33
34
35
36
37
38
39
40
Vout8
Vee
Vee
Vdd
vss
R/W
spare
spare
spare
spare
spare
spare
Pin Allocation for the Chip
Figure 20.
Integrator Array Chip
oi
80
and it would be advantageous to split the integrator array
in half and cascade two identical chips.
There is actually considerable advantage to placing
only one half of each array on the two chips and allowing
for cascading.
By designing the chips for cascading, it is
possible to easily create a very large analog coprocessor
with high orders of integration and many inputs.
This is
comparable to bit-slicing in a microprocessor, where the
number of data bits is the driving factor.
In the analog
coprocessor, the driving factor is the number of integrators, or order.
Hence, an analog coprocessor based on these
two highly integrated chips could be called an order-slice
analog processor.
Figure 21 is a representation of the pro-
posed eighth-order analog coprocessor implemented with these
cascaded input/output summing array and integrator array
chips.
Rather than the 173 chips that are required to
implement the analog coprocessor with discrete digital and
analog chips, only four input/output summing array and two
integrator array chips are needed, for a rather dramatic
reduction of 167 chips.
Another advantage of splitting the integrator array is
the availablility of pins for additional inputs.
There is
presently no provision for feed forward in the proposed
analog coprocessor.
This would require additional analog
switches and potentiometers to enable any input to be fed
forward to any integrator and appropriately attenuated.
A
constant second input can be applied to an integrator from
Output
Summing
Array
Chip
r--
v0
r-
vl
Input
Summing
Array
Chip
-
v.l
Integrator
Array
Chip
Integrator
Array
Chip
Output
Summing
Array
Chip
I
r--1
Input
Summing
Array
Chip
vn --
-~--
Figure 21.
Order-Sliced Analog Processor
00
I-'
82
the digital coprocessor interface with a software set gain,
but this is not feed forward.
Given pin availability and
physical space on the chip for the added registers and
potentiometers, true feed forward could be implemented.
As
shown in Figure 22, feed forward is limited to one added
input to each integrator, which can be attenuated with the
added potentiometer.
The primary application for the feed
forward is in the area of active filter design and
modelling.
83
Digital Busses
v cc
IC
Registers:
R
4 Input Pots
4 IC Pots
RESET
HOLD
RESET
Scaling
C Array
Attenuation
Scaling
Feed
Fwd
Input
voi
HOLD
v.ln.
]_
a.
Pin 1
2
3
4
5
6
7
8
9
10
11
12
13
14
Internal Circuitry of Chip
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Dll
Dl2
D13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
b.
Dl4
D15
AO
Al
A2
A3
A4
Vinl
Vin2
Vin3
Vin4
Voutl
Vout2
Vout3
29
30
31
32
33
34
35
36
37
38
39
40
Vout4
Vffl
Vff2
Vff3
Vff4
Vee (+15V)
Vee (-15V)
Vdd (+5V)
Vss
spare
spare
spare
Pin Allocation for the Chip
Figure 22.
Integrator Array Chip with
Feed Forward Capability
@
CHAPTER 6
Applications
An excellent application of the hybrid computer is in
education, particularly in a control systems laboratory.
The student has the choice of simulating control systems on
the analog coprocessor, or on the digital coprocessor.
The
latter has great value, since the main campus computer is
not needed for the simulation and printout.
Students can
actually perform experiments on the computer in the lab,
without waiting for a terminal or a time-shared line
printer.
The analog coprocessor has the same advantages as
the analog computer it replaces.
It is easier to program
than an analog computer, with less chance of error, yet it
provides the same real-time output to a storage oscilloscope
or stripchart recorder.
The student can actually see
something move in response to his stimulus.
Although the
only motion may be an oscilloscope trace or a recorder pen,
there is a sense of the physical response to the stimulus by
the hardware simulated.
Of course, actual hardware can be
interfaced to the hybrid computer to further augment the
learning experience.
84
•
85
A second application of the hybrid computer is in the
area of development and evaluation of hybrid hardware.
As
stated earlier, many complete hybrid systems are being built
on one or three chips.
In the case of the latter, the front
end and back end are analog-to-digital and digital-to-analog
converters with a digital processor as a third element.
Some of this is now becoming monolithic, and some is also
being done totally analog, as in complex active filters.
Much of the development and evaluation can be done by breadboarding, connecting various chips together into a functioning system and then converting this to a monolithic
device.
With capabilities in both the digital and analog
areas, and analog capabilities for eighth-order systems,
this hybrid computer is a valuable development tool.
Both of the first two applications utilize simulation,
which is an application unto itself.
Simulation is used in
hardware development, troubleshooting, modification or
upgrade, and training.
It is far less expensive, faster,
and easier to model a complex system on a computer and
adjust parameters than to attempt to do so with actual hardware.
Computer-aided design has made vast strides in the
past few years, both in the area of mechanics and
electronics.
In the case of the latter, several software
packages are available to create both analog and digital
circuits and provide output of anticipated time and frequency responses for analog circuits, and logic responses
for digital circuits.
The hybrid computer can be used to
Q .
86
further refine the design of complex analog circuits and
hybrid circuits, as well as mechanical or electro-mechanical
systems.
Automatic testing of systems and portions of systems
can also be performed by the hybrid computer.
As such, the
hybrid computer can be used as an article of automatic test
equipment, applying stimuli to a system through the analog
and digital outputs, and measuring the response through the
analog and digital inputs.
In the test environment, all
three variations of the hybrid computer have value:
the
bilateral variant, the unilateral variant with analog
preprocessing, and the unilateral variant with digital
preprocessing.
If the hybrid is to be used extensively as
an automatic tester, there is some advantage to replacing
the input ADC with an integrating type used in digital
multimeters.
An interesting aspect of utilizing the hybrid
computer as automatic test equipment is that no one really
makes a small automatic test system.
Most systems are quite
large, so this computer used as ATE might fill a niche.
A final application of the hybrid computer is related
somewhat to the first, in that it can be used for nothing
more that actual computation.
To some extent, this is of
value to the field of education, where students are seldom
exposed to the concept of an analog computer, and are taught
to believe that everything can be done better digitally.
It
is not until after graduation that students realize that the
world is analog, and it is often easier, faster and more
87
economical to perform certain operations and computations in
an analog sense.
The compactness of the computer enables it
to be moved into the classroom for demonstration of mathematic concepts in calculus and differential equation classes,
and for demonstration of engineering concepts in vibrations
and various electronics classes.
APPENDIX A
Analog Coprocessor Addressable Components
Coefficient Potentiometers
Analog Input from Input Converters
INPOT 0
Analog Input from Integrator 1 Output
IN POT 1
Analog Input from Integrator 2 Output
INPOT 2
Analog Input from Integrator 3 Output
INPOT 3
Analog Input from Integrator 4 Output
INPOT 4
Analog Input from Integrator 5 Output
IN POT 5
Analog Input from Integrator 6 Output
IN POT 6
Analog Input from Integrator 7 Output
INPOT 7
Analog Input from Integrator 8 Output
IN POT 8
Analog Input from Digital Coprocessor
IN POT 9
Initial Condition for Integrator 1
ICPOT 1
Initial Condition for Integrator 2
ICPOT 2
Initial Condition for Integrator 3
ICPOT 3
Initial Condition for Integrator 4
ICPOT 4
Initial Condition for Integrator 5
ICPOT 5
Initial Condition for Integrator 6
ICPOT 6
Initial Condition for Integrator 7
ICPOT 7
Initial Condition for Integrator 8
ICPOT 8
Analog Output from Integrator 1
OUTPOT 1
88
89
Analog Output from Integrator 2
OUTPOT 2
Analog Output from Integrator 3
OUT POT 3
Analog Output from Integrator 4
OUTPOT 4
Analog Output from Integrator 5
OUT POT 5
Analog Output from Integrator 6
OUT POT 6
Analog Output from Integrator 7
OUT POT 7
Analog Output from Integrator 8
OUTPOT 8
Analog Switches
Analog Input +10 Attenuation
INATT+lO
Analog Input -10 Attenuation
INATT-10
Analog Input +1 Attenuation
INATT+l
Analog Input -1 Attenuation
INATT-1
Analog Output +10 Attenuation
OUTATT+lO
Analog Output -10 Attenuation
OUTATT-10
Analog Output +1 Attenuation
OUTATT+l
Analog Output -1 Attenuation
OUTATT-1
Analog Coprocessor +10 Attenuation
ACATT+lO
Analog Coprocessor +1 Attenuation
ACATT+l
Analog Coprocessor +0.1 Attentuation
ACATT+.l
Analog Coprocessor +10 Scaling
ACSCL+lO
Analog Coprocessor +1 Scaling
ACSCL+l
Analog Coprocessor +0.1 Scaling
ACSCL+.l
Analog Coprocessor Hold
HOLD
Analog Coprocessor Reset
RESET
Analog Input to Analog Bus
AINBUS
Analog Input to Input ADC
AINADC
90
Input FVC Output to Analog Bus
FVCBUS
Input FVC Output to Input ADC
FVCADC
Input DAC to Analog Bus
INDACBUS
Analog Bus Output to Analog Output
BUS OUT
Analog Bus Output to Output ADC
BUSADC
Analog Bus Output to Output VFC
BUSVFC
Output DAC to Analog Output
DACOUT
Output DAC to Output VFC
DACVFC
Buffered Latches
Synchro/Resolver-to-Digital Converter
SRDCEN
Digital Inputs
DIEN
Input ADC
IADCEN
Input DAC
IDACEN
Digital-to-Resolver Converter
DRCEN
Digital Outputs
DOEN
Output ADC
OADCEN
Output DAC
ODACEN
Analog-to-Digital Sample & Hold
ADSH
Digital-to-Analog Sample & Hold
DASH
Analog-to-Digital Interface MUX
ADMUX
Digital-to-Analog Interface MUX
DAMUX
Interface DAC
CODAC
Interface ADC
COADC
APPENDIX B
Dual-Coprocessor Card Component Listing
Card 1:
Digital Coprocessor Card
Microprocessor
80186
Numeric Data Processor
8087
Dynamic RAM (64K x 1 bit)
2164A
Dynamic RAM Controller (for Dual-Port)
8207
Error Correction Unit
8206
ROM, PROM and/or EEPROM
Assorted logic chips and buffers
Card 2:
Input Converters Card
Synchro/Resolver-to-Digital Converter
SDC/RDC1740
Digital Input/Output Ports (8 bit)
8212
Analog-to-Digital Converter
AD574
Digital-to-Analog Converter
AD3860
Analog Input MUX (analog switches)
AD7510DI
Frequency-to-Voltage Converter
AD650
Coprocessor Interface DAC
AD3860
Coprocessor Interface 8-Channel MUX
AD7501
Coprocessor Interface Sample & Holds
AD585
Assorted Analog Switches and Buffered Latches
91
92
Card 3:
Analog Coprocessor Input Array
Digitally Controlled Potentiometers (10)
AD7525
Quad SPST Analog Switches (10)
For input selection
AD7510DI
8-Bit Non-Inverting Latches (25)
For input switching (5)
For potentiometers (20)
Am29845
Operational Amplifiers (15)
For input summing (5)
For potentiometers (10)
AD OP-07
Assorted resistors for op amp gain control.
Assorted logic chips for address bus interfacing.
Card 4:
Analog Coprocessor Integrator Array
Digitally Controlled Potentiometers (8)
AD7525
Quad SPST Analog Switches (16)
For RESET (2)
For HOLD (2)
For input attenuation (6)
For scaling (6)
AD7510DI
Operational Amplifiers (8)
For integrators
AD OP-37
Operational Amplifiers (8)
For potentiometers
AD OP-07
8-Bit Non-Inverting Latches (24)
For potentiometers (16)
For analog switches (8)
Arn29845
Assorted resistors and capacitors for op amps.
Assorted logic chips for address bus interfacing.
Card 5:
Analog Coprocessor Output Array
Digitally Controlled Potentiometers (8)
AD7525
Quad SPST Analog Switches (8)
For output switching
AD7510DI
8-Bit Non-Inverting Latches (20)
For potentiometers (16)
For output switching (4)
Arn29845
93
Operational Amplifiers (13)
For potentiometers (8)
For output summing (5)
AD OP-07
Assorted resistors for op amp gain control.
Assorted logic chips for address bus interfacing.
Card 6:
Output Converters Card
Digital-to-Resolver Converter
DRC1765
Digital Input/Output
8212
Digital-to-Analog Converter
AD3860
Analog Ouput MUX Analog Switches
AD7510DI
Analog-to-Digital Converter
AD574
Voltage-to-Frequency Converter
AD650
Coprocessor Interface ADC
AD574
Coprocessor Interface MUX
AD7501
Coprocessor Interface Sample & Holds
AD585
Assorted logic chips for address bus interfacing.
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