--------------------~--~-~~--~--------~
..
~-----------
- - --
-
----------------·------ .. ----------------·-------
CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
PERSONAL COMPUTER BASED
DIGITAL WAVEFORM GENERATOR
A graduate project submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Engineering
by
Ali Reza Angha
May 1987
···-···················-···························--·
The Graduate Project of Ali Reza Angha is approved:
California State University, Northridge
ii
To my parents
iii
TABLE OF CONTENTS
DEDICATION • . .
iii
LIST OF FIGURES
v
ABSTRACT
vii
CHAPTER
1
INTRODUCTION • • .
2
MODES OF OPERATION
3
4
1
. • • . .
3
2.1
Vector Entry and Manipulation .
3
2.2
Vector Down-loading and Board Set-up
3
2.3
Running Mode of DWG Board . . • . . .
7
THEORY OF OPERATION AND HARDWARE CONSIDERATIONS
3.1
Address Generation
3.2
Clock Generation
12
3.3
Waveform Generation (Channel) Circuitry . . .
16
3.4
Control Signal and Vector Address Generator .
20
3.5
Input/Output Buffering
20
3.6
Board Layout
21
AN EXAMPLE OF OPERATION
•...
8
8
23
REFERENCES . . • . . . . . . . .
26
APPENDICES
A
IBM PC Bus Specification .
27
B
Schematics
36
iv
LIST OF FIGURES
Figure
2-1
Sample Waveform Display. . . .
4
2-2
Application Software Flowchart
5
2-3
Vector Down-loading and Board Set-up Block Diagram
6
3-1
Data Path for Loading Channel Memories
9
3-2
Address Decoding and Memory Mapping . . .
10
3-3
Timing Register Bit Map and Its Associated States .
14
3-4
TRE Timing Relationship
15
3-5
Block Diagram of Waveform Generation Circuitry
18
3-6
Control Signal Timing • . . . . . . .
19
3-7
Truth Table of Output Enable Latch
22
4-1
Sample Waveform .
24
A-1
System t•1emory ~lap for 64/256K System Board
(Part 1 of 2) . . . . . . . . . . . . . . . . . . . 28
A-2
System Memory Map for 64/256K System Board
(Part 2 of 2) • . . . . . .
29
A-3
I/0 Channel Diagram . . · .
31
B-1
Address Decoding Circuit
37
B-2
Clock Generation Circuit
38
B-3
Vector Address and Timing Generation Circuit
39
B-4
Waveform Generation Circuit (Channel 0) .
40
B-5
Waveform Generation Circuit (Channel 1)
B-6
Waveform Generation Circuit (Channel 2) .
42
B-7
Waveform Generation Circuit (Channel
43
v
3) •
. . . . 41
LIST OF FIGURES (continued)
Figure
Page
B-8
Waveform Generation Circuit (Channel 4)
......
44
B-9
Waveform Generation Circuit (Channel 5)
..
45
.
46
..
...
47
B-10 Waveform Generation Circuit (Channel 6)
B-11
Waveform Generation Circuit (Channel 7)
B-12 Output Buffering Circuit
B-13
Input Buffering Circuit •
..
.
49
B-14 Channel Input Buffering (Part 1)
B-15
Channel Input Buffering (Part 2)
vi
48
50
.....
51
ABSTRACT
PERSONAL COMPUTER BASED
DIGITAL WAVEFORM GENERATOR
by
Ali Reza Angha
Master of Science in Engineering
This paper presents a complete description of a digital waveform
generator (DWG) board to be used in conjunction with an IBM PC/XT
compatible personal computer.
The personal computer is used as a
host to provide vector generation and initial set-up of the generator
board.
The digital waveform generator board itself contains the
circuitry capable of generating eight independent waveforms simultaneously (eight output channels).
Up to a maximum of six DWG
boards can be installed in each PC providing 48 independent output
channels.
The output rate is programmable and has a range from
0.01 Hz to 20 MHz.
Although the channels are all independent of .
each other, they are synchronized by the same system clock.
channel has a storage capability of 16K bits of timing data
vi;
Each
increments which can be scanned out repeatedly without any
disruption.
Timing data increments (bits) are scanned out at the
rate of the run time clock.
The run time clock can be obtained
either from an external source or from the on-board oscillator.
The user can select the source and change the rate of the run time
clock.
Application software on the user side, i.e., on the PC, will
allow creation, display, editing, storage and retrieval of vector
data on floppy disks, selection of run time clock source and data
output rate, down-loading vectors to DWG board, and starting and
interrupting the DWG board.
After the DWG board has been set up to
run, it will disconnect itself from the host (PC) and run independently until it is interrupted by the host.
viii
Chapter 1
INTRODUCTION
Digital waveform generators are
engineering environment,
whe~~"
.':!.~~~lly
used in an electrical
an engineer will either synchronize
or stimulate a circuit or parts of it by using the outputs of the
generator as the inputs of the circuit.
After applying the input
signal, the circuit can be observed for proper operation and
behavior.
the
It is important to have the flexibility of defining
timirrg_.A.n.Q~~h.C!P~.-QJ
the output from the waveform generator.
Usually, there is more than one output channel since most digital
circuits have several inputs which have to be specified and provided
simultaneously for correct operation and diagnosis.
In some board testers the use of programmable digital waveform
generators is very popular since it will provide a tool in realizing
a test vector and applying it to a circuit.
The degree of flexi-
bility of a generator in terms of output configuration is very
important in tester des.·ign.
Increased flexibility wil 1 make it
possible to test more types of circuitry in a more efficient manner.
Being able to determine the output rate within a wide range, specification of data increments for a lengthy output cycle, independence,
of output channels from each other, and repeatability of output
cycles are some characteristics of a configurable generator.
specifying an output cycle for the generator and repeating it
1
By
2
(\
continuously, a homogeneous and uninterrupted waveform will be
obtained.
The DWG board has been designed to conform to these
requirements so it can easily be integrated into a test system.
Since DWG has a modular architecture, there is no limit on the
number of channels that a test system can have.
'
Chapter 2
MODES OF OPERATION
2.1
Vector Entry and Manipulation
The user can define, edit, display, store and retrieve the
output channels• waveforms using application software on the PC
side.
The source of the system clock and its frequency (output
rate) can also be defined.
Application software can be written to
provide numerous tools, easing generation of output vectors.
For
example, scanning waveforms on the display can provide a good way
to compare them over a certain length of time.
Figure 2-1 shows a
sample of the display that could be provided by application software.
2.2
Vector Down-Loading and Board Set-Up
After output waveforms have been defined, they will be trans-
lated into vectors consisting of 8-bit words.
sent a timing increment.
Each bit will repre-
Each channel memory has 2K x 8 bits capac-
ity, providing 16K bits of output information.
Translated waveform
information is then written into 2048 addresses of its corresponding
channel memory on a DWG board.
After all channel data has been down-
loaded, output rate and clock source information (timing information)
will be sent to the DWG board.
Then set-up informaton is sent to the
board, disabling the high impedance state of the outputs and enabling
the board•s clock.
Figure 2-2 shows the sequence of these events.
block diagram in Figure 2-3 illustrates the relationship and interaction between the PC and DWG boards.
3
A
Timing Increment #
Channel .1
Channel 2
Channel 3
Channel 4
Channel 5
Output Rate:
1o
1
I
I_
I
I
I
I
I
I
I
I
,
I
I
I
I
1
I
I
2
3
I
4
I
I_
I_
I
I
I
I
I
I
I
I
I .
I
I
I
I
I
I
I
I
I
I
1.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
I
20 MHz
I eI
I
I
I
1
7
I
I
I
I
I
6 I
I
I
I
I
I
I
I
I
I
I
I_
I
5
_
I
_
Clock Source:
Figure 2-1.
I
I
I
I
I
I
I
I
I
9
I
I
I
I
I
I
i
I
I I II I II
I II I_ II I_
_
I u I
I
I
I
l_ I_
I
w
12
I 13
I_ I_
I
I
I
I
I_
I
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I
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I
I
II.
I
I
I_
I
I
I
I
I
I
I
I
I---
I
I
Internal
Sample Waveform Display
..p.
5
Yes
No
Translate data into
8-bi t words
Store (down-load) 8-bit words
in channel memory on DWG
board
Store timing data in the
timing register of DWG board
Enable outputs
Unmask board clock
Figure 2-2.
Application Software Flowcha1At
6
Host
IBM PC
Vector Entry
Software
,-
-- -
-
-
-
-
-
~r
-
Timing
"'Il
&
,.
Control
Registers
Address Decoding
... ~
-
-
-
lr
-
-
Channel
Memory
(8-bit wide)
-~~
&
Data Path Contr~
Circuitry
DWG Board
I
1-
Figure 2-3.
Down-loading and Board Set-up Block Diagram
7
2.3 Running Mode of DWG Board
After the board•s clock has been unmasked {enabled) it will
start to output data through its channels continuously.
For every
clock period it will ouput one bit of the data for each channel.
After it has scanned through the entire data {16K bits) it will
start from the first bit and repeat the entire process.
It will
continue to output independent of current activities on the PC
until it is interrupted by the PC.
When it is interrupted, its
outputs will go to high impedance and its clock will be disabled.
The state of the board will remain intact until it is enabled again
or the power is turned off.
Upon enabling the outputs and the
clock, it will continue from the state in which it was interrupted.
Therefore, there would be no loss of data upon interruption.
,,
CHAPTER 3
THEORY OF OPERATION AND HARDWARE CONSIDERATIONS
3.1
Address Generation
3.1.1 Theory of Operation
Waveform data is sent from the PC and is stored in the designated channel memory on the DWG board.
Channel memories have been
mapped on the PC bus so that data can be written directly into them.
Figure 3-1 shows the data path from PC to DWG board.
3.1.2 Hardware Considerations
In or9er to have 48 functional channels, 96K x 8 bits
(48 x 2K x 8 bits) memory map allocation within the PC bus is
needed.
Allocated space should not interfere with run time memory
used by the PC, thus making the PC and DWG board run independent of
each other.
Memory space from address of
allocated to channel memory.
D0~~~H
to E7FFFH was
This section of memory map in the
IBM-PC (refer to Appendix A) is reserved for expansion and control
which is not used by the main system itself.
Since there can be up to six DWG boards in a PC, each of them
should be selectable and one of their eight channels should also be
selectable.
Figure 3-2 shows bit mapping of the address decoding
scheme used.
By looking at the bit map, it can be seen that any
board or register can be selected only when A18 and A19 are both
high and A16 and A17 are complements of each other.
8
If 'E' were
'
9
I
.....
Data Bus
PC
Data
Buffering
and
Data
Channel
Memory
~1ultiplexing
Address Bus
I
I
I
•II"
·~
I
I
I
i
I
!
ii
I
I
i
Channel Write
Enable
1
Address Decoding
and
Channel Seiection
i
I
Fig. 3-1.
Data Path for Loading Channel
~1emories
(l
•
~-Channel
Channel Memory for Channel
47:
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Ag As A7
1
1
D~~l}H
E7FFFH
l
-
1
1
u
.....
0
1
1
0
J
0
0
l
'V"""
Board
Address
II A].g
I 11
I 11
1
1
1
1
0
1
•
0
1
0
1
0
1
Channel
Address
0
0
0
1
1
1
D~~~~H
From
0
1
to E7FFFH
A6 As A4
0
1
0
1
0
1
A3
A2
0
1
0
1
A1 A0
0 0
1 1
Channel Memory Address
A1s
Al7
A16
A1s
A14
1
1
1
1
1
1
0
0
0
0
1
1
1
·1
1
1
1
0
0
1
1
0
0
1
Board or Register
Select
Al3
A12
Au
0
0
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
0
1
0
Channel
Selected
I
1
1
1
I
0
I
0
0
0
0
0
1
0
1
1
1
0
1
Figure 3-2.
Board 0
Board 1
Board 2
Board 3
Board 4
Board 5
Output Enable Reg.
Timing Register
0
1
0
1
2
3
4
5
6
7
I
Address Decoding and Memory Mapping
I-'
0
11
the address enable function for the DWG board, it would have the
following relationship:
( 1)
By referring to address decoding circuitry (Appendix B,
Figure B-1), one can see the implementation of this decoding.
In
this figure, it can be seen that U22, which is a 3 x 8 decoder,
must be enabled before a board or register can be selected.
MEMWE
(memory write enable) signal goes low for a write operation and in
turn values of A12 through A19 will be sent to the DWG board.
In
order for U22 to be enabled its Gl input should be high and its G2A
and G2B should be low.
For Gl to be high, A19 must be high.
G2A
being low would mean A16 and A17 must be complements of each other.
The EX-NOR gate on the path of A18 to G2B serves as an inverter
(3 of 4 EX-OR/NOR gates in U7 have been used as inverters in order
to reduce the total number of parts).
This means the previously
discussed function E (formula (1)) must be true in order to enable
address selection of the board.
Six of the outputs of the 3 x 8 decoder (U22) which represent
the board selection are normally open and only the output representing the particular board in the system may be jumpered to BRD SLCT
(board select) 1 ine.
The uniqueness of the jumper installation
ensures that only one of the many boards in a system can be selected.
The other two outputs of the decoder are timing and output register
enables.
A14• A15 and A16 are the address bits selecting board or
register enables.
In order to enable address decoding of the DWG
12
board channels, the signal
signal is low
A~
1
MEM ADORS EN 1 must be low.
When this
through A11 will be passed on from PC bus to
channel memory address bus.
MH1 AOORS EN is the complement of the
CLK EN signal which is the content of the timing register•s eighth
bit.
By writing
into address
8~H
EC~~~H,
this bit can be set
and will result in enabling the board•s address decoding.
A second 3 x 8 decoder (U24) handles the channel selection.
Decoder enable lines Gland G2B are common with the previously discussed decoder (U22) and G2A is the output of U22.
Thus, not only
function E must be satisfied, but the board must also be selected in
order to enable the channel selection decoder.
decoder represent channel write enables.
Outputs of this
All• A12 and A13 represent
the bits selecting channel write enables.
After A11 through A19 have been set, a channel has been selected
and its 2K x 8 bit memory is accessed by setting
A~-Al~.
A~-Al~
are buffered and are tied to all of the channel memories on the OWG
board.
Since only one channel is selected at any given time, the
data present vdll be written into that channel• s memory.
When application softward is writing into channel memory, it
is selecting the board and the channel simultaneously by providing
a 20-bit address.
3.2 Clock Generation
3.2.1
Theory of Operation
Clock generation circuitry provides the system clock for out-
putting the channel data.
an external clock.
Its source can be either an internal or
If several OWG boards are used together, in order
13
to have synchronization, the system output clock (SOC) generated by
the master board will be shared by the other boards as an external
output clock (XOC) through jumper cables.
Output rate can also be
programmed by setting a value in the timing register.
The timing
register can also be initialized to mask or enable SOC.
By masking
SOC, all output activity is halted and outputs are frozen at the
1ast state.
3.2.2
Hardware Considerations
The system output clock (SOC) can be from an external input
clock, on-board oscillator or from another DWG board's (master
board) SOC.
Jumper configuration on P1 will determine whether SOC
comes via cable from another DWG board or is generated on the board
itself.
If SOC comes from the board itself, its source and frequency
is determined by the content of the timing register.
Figure 3-3
represents the bit map and different states of this register.
In
order to load this register, TRr (timing register enable) must go
from normal high to low and then high at the end of the write cycle
while the buffered data is present at its inputs (Figure 3-4). TRr
is generated by address decoding circuitry (Appendix B, Figure B-ll
when
EC~~~
is input as address.
As explained previously, before vectors are loaded into channel
memories, the system clock must be disabled.
address
EC~~~H•
By writing 80H into
CLK EN is set to high and 4 to 1 multiplexer (U41)
is disabled in order to mask the clock.
After all of the vector
data has been loaded into channel memories, source select bits (Q 1
and Q2 ) and frequency division factor bits (Q3 through Q7) are set
14
Address
Qg
Qs
-~ ~----------~--------~
Clock
Enable
(Low Active)
Qg Q7
Q6 Qs
Frequency Division Factor
Q4 Q3 Q2 Q1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
0
0
0
X
X
X
X
X
0
1
0
X
X
X
X
X
1
0
Ag A4 A2
A~
1
1
0 ,Al6
"'"
Value A
Figure 3-3.
t..__ _._.v
Clock
Source
Select
Result
System clock is disabled. soc is
high.
SOC is provided by external input
clock.
SOC is provided by on-board clock.
SOC = 20 MHZ
soc is half of on-board clock.
SOC = 10 MHz
soc is on-board clock divided by 2A.
SOC = 20 MHz/2A
Timing Register Bit Map and Its Associated States
15
Address - - - - - - '
·r1EMWE
Data -------'----'Data is latched at this time
TRE
Figure 3·4.
TRE Timing Relationship
16
to their designated values while Qs is set to 0 which will enable
the system clock.
Different combinations of clock source select bits (Q1 and Q2 )
will result in different sources of SOC.
Combination '00' (Q2Q1)
will select the input clock at J1 as SOC.
'01' will select the on-
board oscillator (20 MHz) and '10' will select the on-board oscillator divided by two (10 MHz) as the SOC.
Output of divide by 2n
counter (U42:74LS292) will be output as SOC when combination is '11'.
For this device, the division factor n must be greater than 2 and
less than 31.
Since a divide by two is not possible to obtain
through this device, it is obtained from a separate divide by two
counter made of aD-flip-flop.
Input of the divide by 2n counter
comes from the on-board oscillator.
Therefore, SOC can be selected
from an input clock, on-board oscillator or on-board oscillator
divided by m, where m can be from 2 to 231.
SOC is buffered and
sent to channel circuity and also to J2 for direct SOC output.
3.3 Waveform Generation (Channel) Circuitry
3.3.1
Theory of Operation
After vector information has been stored in channel memory, a
waveform can be generated.
In order to the data in channel memory
to be output as waveforms, data must be loaded in parallel (8 bits)
into a shift register and then shifted out serially.
By employing
two such registers and using them alternatively to load and shift
out data, a continuous output can be produced.
While one of the
·Shift registers is loading the current address data, the other shift
register will shift out the previous address data serially.
All of
17
the channels on the DWG board share the same vector address and
timing signals, that is to say, they are all at the same point
within their vectors relative to each other at any given time.
3.3.2 Hardware Considerations
When the channel memory write enable (for example,
channel
~)
( PD446).
WR~
for
is low, vector data can be loaded into channel RAM
At this instance, the output of the vector address gen-
eration circuitry (Appendix B, Figure B-3) is at high impedance
(disabled) since CLK EN is high.
This ensures the integrity of the
buffered address coming from PC since they are both connected to
the address pins of the channel RAMs (Appendix B, Figure B-4).
After the vector data has been loaded, CLK EN is set to low, thus
providing vector address generation outputs.
At this time the
RAM's write enable signal is set to high and RAM will be in the
read mode.
The vector address generated will fetch the data and put
it at outputs of the RAM.
This data is loaded into one of the two
parallel load shift registers (74LS1661) while the previous data is
shifted out of the other register.
A block diagram of the waveform
generation is presented in Figure 3-5.
Figure 3-6 shows the timing
relationship of waveform generation control signals.
State of the
signal BS will determine which shift register is being loaded and
which one is being shifted out.
A two-to-one multiplexer, 74LS157, will ensure that the output of
the shifting register will go to the output flip-flop, not the output
of the register which is being loaded.
Output flip-flop ensures con-
tinuity of waveform by latching its state for a clock (SOC) period.
-· . --·---r--
t>
..
Data
RAr,1
Parallel Load Shift
Register A
Shift/Load
J
>
A
r4UX
Parallel Load Shift
Register B
Data
F/F
2:1
f
,
..-
A
B
y
Outp ut
Q
'D
"'T
~
B
A/G
Shift/Load
.. ~
Address
BS
Vector Address
Generator
...._
,
-
ADRS
INCR
BS
Control Signal
(Timing) Generator
<
soc
-·-------~
Figure 3-5.
Block Diagram of ltJaveform Generation Circuitry
.._..
co
Sys tern
Output Clock
(SOC)
_flfLPLf4lj5l
~LI7
I~~-
I'L
!
Buffer Select
(BS)
Generated
Vector
Address
ADRS INCR
J<
-
J·--·
I
1
1
- X
I
I
>C
1··
I
Content of shift register A is
Content of shift register B is
~
shifted out while content of address: shifted out while content of address:
n is loaded into shift register B
n is loaded into shift register A
1
I
Figure 3-6.
Control Signal Timing
,__...
lD
20
3.4 Control Signal and Vector Address Generator
3.4.1 Theory of Operation
Buffer select (BS), address increment (ADRS !NCR) and vector
address (Figure 3-6) must be generated to ensure proper channel
output.
3.4.2
These signals are generated by binary counters.
Hardware Considerations
A simple binary counter, 74LS161 (Appendix B, Figure B-3, U2),
with SOC as its input clock will provide ADRS !NCR (divide by 4) and
BS (divide by 8).
A binary counter with tri-state output (74LS561A)
can be used as an address counter for scanning the RAM•s content.
Since RAM size is 2K x8, an address size of eleven bits is needed.
By connecting three of these counters (U44, U45 and U46) in series,
twelve bits will be available.
Since only eleven bits are needed,
the most significant bit is ignored.
When CLK EN is high, the output
of this counter goes to high impedance.
CLK EN at any time will
either enable the address coming from the PC bus or the one generated
by the counter.
3.5
3.5.1
Input/Output Buffering
Theory of Operation
Input data is buffered at two stages after it is received from
the PC data bus.
After the first stage of buffering, data is multi-
plexed and buffered for each channel.
buffers are tri-state buffers.
All of the input and output
The output buffer is enabled and
disabled according to the content of the output enable latch.
21
3.5.2
Hardware Considerations
The first stage of buffering is enabled by MEMWE from the PC
bus.
Buffered data is then supplied to eight channel buffers.
The
second stage of buffering is enabled for the channel whose memory
write enable signal (for example,
enabled at any given time.
WR~)
is low.
Only one channel is
The second stage of multiplexed buffering
will ensure mutual exlcusivity of the channels• data buses.
The output enable latch is aD-flip-flop which has been used
as an asynchronous latch (not dependent on a clock input).
Figure
·~~·
of this
3-7 shows the truth table of this latch.
Combination
table will not occur since both OE and TRE are outputs of the same
decoder (refer to address decoding section, Appendix B, Figure B-1).
Therefore, if TRE (timing register enable) goes low, the output
buffer is disabled and goes into a high impedance state.
OE (output
enable) should go low in order for the output buffer to be enabled.
After setting the timing register (TRE goes low) for the start of a
run, address
E8~~~H
(Figure 3-2) must be accessed (written to in
order to generate a low value for OE).
3.6 Board Layout
Since all channels should output at the same time without much
delay with respect to each other, it is important that they all
have the same path length for their outputs.
Therefore, great care
must be taken in laying out the board to ensure equal path length
for all channels.
In order to eliminate power line interference, for every two
chips one 0.01UF bypass capacitor should be used.
22
PRE
(Q[)
CLR
(TRt)
Q
Q
(DOT BRF EN)
*0
0
- ( uns tab 1e)
0
1
1
0
1
0
0
1
1
1
Q
lY (no change)
*This situation will not occur.
Figure 3-7.
Truth Table of Output Enable Latch
Chapter 4
AN EXAMPLE OF OPERATION
The waveform shown in Figure 4-1 is to be generated by channel
~of board~-
For simplicity, this waveform has a cycle which
spans over eight timing increments (i.e., it repeats after every
eight output clocks).
Timing increments of 12.5 ns means having an
SOC with 5 MHz frequency.
The following steps are taken in order
to obtain the waveform desired:
1.
After waveform creation and editing is done through the
application program, it is converted into 8-bit words to
form a vector of 2K x 8 bits.
Since this particular wave-
form repeats every eight timing increments, its vector is
made of 2048 words of value 67H.
2.
SOH is written into address
EC~~~H
in order to enable
the board's address decoding and mask the output clock.
3.
Vector is then loaded in channel
~·s
RAM.
For this
example, the vector value, 67H, is written into addresses
0~(8(8~wD~7FFH·
4.
The timing register's value is figured out by application
software as follows:
In order to obtain a 5 MHz output rate, a division
(divide by 4) of the on-board clock is required.
writing
~A
(refer to Figure 3-3) into address
23
By
EC0~(8H,
Timing increments
2
1
4
3
5
6
7
8
1
1
1
0
1
u
I
I
1
0
..
,
1
I
0
0
1
I
I
r
i
~
12.5 nx
<·
'
··--··-- 6 -··--- ...
7
.. ····--·--·--··X·.
Output Cycle
Figure 4-1.
.,..
.l
Sample Waveform
N
..j:::.
25
a frequency divider chip is selected to generated SOC,
the division value for this chip is set to 4 and the
output clock is enabled.
5.
A dummy value, for example,
EB~~~H
6.
~~H•
is written into address
in order to enable the output.
A word (represented by the generated vector address) of
channel
~
RAM is fetched and loaded into one of the shift
registers while the other register is shifting out its data.
After eight output clock cycles, these registers reverse
their roles.
This action continues and the whole address
spectrum of the RAM (2K) is scanned and its content has
been serially output.
address
buffer).
EC~~~H
This will repeat over an over until
is written into (disabling output
If a value greater than
8~H
is written into
this address, states of counter and registers will be
frozen, other their states continue to change.
REFERENCES
IBM PC Technical Manual. Boca Raton, Florida:
Machines Corp., 1983.
Memory Data Book.
1985.
TTL Data Book.
Mountain View, California:
Dallas, Texas:
International Business
NEC Electronics Inc.,
Texas Instruments Inc., 1984.
26
APPENDIX A
IBM PC Bus Specification
27
28
Start Address
Decimal
Fig. A-1.
Hex
0
16K
32K
48K
00000
04000
08000
64K
BOK
96K
112K
10000
14000
18000
lCOOO
128K
144K
160K
176K
20000
24000
28000
2COOO
192K
208K
224K
240K
30000
34000
38000
3COOO
256K
272K
288K
304K
40000
44000
48000
4COOO
320K
336K
352K
368K
50000
54000
58000
5COOO
384K
400K
416K
432K
60000
64000
68000
6COOO
448K
464K
480K
496K
70000
74000
78000
7COOO
512K
528K
544K
560K
80000
84000
88000
8COOO
576K
592K
608K
624K
90000
94000
98000
9COOO
Function
ocooo
64 to 256K Read/Write Memory
on System Board
Up to 384K Read/Write
Memory in 1/0 Channel
Up to 384K in 1/0 Channel
System Memory Map for 64/256K System Board (Part 1 of 2)
29
Start Address
Decimal
Hox
640K
656K
672K
688K
AOOOO
A4000
ABOOO
ACOOO
704K
80000
720K
84000
736K
88000
752K
BCOOO
768K
784K
C4000
128K Reserved
Monochrome
Color/Graphics
coooo
816K
caooo
ccooo
832K
848K
864K
880K
00000
04000
08000
OCOOO
896K
912K
928K
944K
EOOOO
E4000
EBOOO
ECOOO
960K
FOOOO
Re~erved
976K
992K
100BK
F4000
FBOOO
FCOOO
48K Base System ROM
BOOK
Fig. A-2.
Function
Fixed Disk Control
192K Read Only Memory
Expansion and Control
System Memory Map for 64/256K System Board (Part 2 of 2)
30
I/0 Channel
The I/0 channel is an extension of the 8088 microprocessor bus.
It is, however, demultiplexed, rcpowered, and enhanced by the
addition of interrupts and direct memory access (DMA) functions.
The 1/0 channel contains an 8-bit, bidirectional data bus, 20
address lines, 6 levels of interrupt, control lines for memory and
l/0 read or write, clock and timing lines, 3 channels of DMA
control lines, memory refresh timing control lines, a
channel-check line, and power and ground for the adapters. Four
voltage levels arc provided for l/0 cards: +5 Vdc, -5 Vdc, + 12
Vdc, and -12 Vdc. These functions are provided in a 62-pin
connector with 100-mil card tab spacing.
A ·ready' line is available on the I/0 channel to allow operation
with slow I/0 or memory devices. If the channel's ready line is
not activated by an addressed devi-ee, all processor-generated
memory read and write cycles take four 21 0-ns clock or 840-ns/
byte. All processor-generated I/0 read and write cycles require
live clocks for a cycle time of 1.05 ,us/byte. All DMA transfers
require live clocks for a cycle time of 1.05 ,us/byte. Refresh cycles
occur once every 72 clocks (approximately 15 ,us) and require
four clocks or approximately 7% of the bus bandwidth.
1/0 devices are addressed using l/0 mapped address space. The
channel is designed so that 512 l/0 device addresses are
available to the l/0 channel cards.
A ·channel check' line exists for reporting error conditions to the
processor. Activating this line results in a Non-Maskable Interrupt
(NMI) to the 8088 processor. Memory expansion options use this
line to report parity errors.
The 1/0 channel is repowered to provide sufficient drive to power
all live system unit expansion slots, assuming two low-power
Schottky loads per slot. The IBM l/0 adapters typically use only
one load.
The following pages describe the system board's I/0 channel.
31
Rear Panel
1\
Signal Name
~
GNO
Al-
+RESET ORV
f-
-
+5V
f-
-
+IRQ2
r-
-SVDC
f.-
Signal Name
~
-1/0 CH CK
+07
+06
·-
+DR02
f.-
-
-12V
f.-
-
Reserved
f.-
-
+01
+12V
r-
-
+DO
810
GNO
-MEMW
f.-
-MEMR
I-
-+----
+OS
+04
+03
---
102
+110 CH ROY
AlO
+AEN
-lOW
1-
-
-lOR
r-
-
-OACK3
1-
-
+A16
+ORQ3
f.-
-
+AlS
-
+A13
B20 A20
+All
-OACKl
1-
+ORQ1
1-
-OACKO
r-
CLOCK
+A19
+AlB
+A17
+A14
+A12
+IRQ7
1-
-
+AlO
+IRQ6
1-
+A9
+lAOS
-
+IRQ4
1-
+IRQ3
-DACK2
rr-
+TIC
I-
-
+ALE
1-
-
+5V
1-
-
+OSC
1-
-
+GNO
'---
\
Fig. A-3.
f- Bl
1/0 Channel Diagram
831
A31
+AS
+A7
-
--- +A6
+AS
+A4
+A3
+A2
-
----
•Al
•AO
'---
\
Comp onent Side
32
I /0 Channel Description
The following is a description of the IBM Personal Computer I/0
Channel. All lines arc TTL-compatible.
Signal
I/0 Description
osc
0
Oscillator: High-speed clock with a 70-ns
period ( 14.31818 MHz). It has a 50%
duty cycle.
CLK
0
System clock: It is a divide-by-three of the
oscillator and has a period of 210 ns ( 4. 77
MHz). The clock has a 33% duty cycle.
RESET DRY
0
This line is used to reset or initialize
system logic upon power-up or during a
low line voltage outage. This signal is
synchronized to the falling edge of clock
and is active high.
A0-A19
0
Address bits 0 to 19: These lines are used
to address memory and I/0 devices within
the system. The 20 address lines allow
access of up to 1 megabyte of memory. AO
is the least significant bit (LSB) and A 19 is
the most significant bit (MSB). These lines
are generated by either the processor or
DMA controller. They are active high.
DO-D7
I/0
Data Bits 0 to 7: These lines provide data
bus bits 0 to 7 for the processor, memory,
and 1/0 devices. DO is the least significant
bit (LSB) and D7 is the most significant bit
(MSB). These lines are active high.
33
Signal
I/0
Description
lOR
0
-I/0 Read Command: This command line
instructs an I/0 device to drive its data
onto the data bus. It may be driven by the
processor or the DMA controller.
This signal is active low.
0
-1/0 Write Command: This command line
instructs an I/0 device to read the data on
the data bus. It may be driven by the
processor or the DMA controller. This
signal is active low.
MEMR
0
Memory Read Command: This command
line instructs the memory to drive its data
onto the data bus. It may be driven by the
processor or the D MA controller. This
signal is active low.
MEMW
0
Memory Write Command: This command
line instructs the memory to store the data
present on the data bus. It may be driven
by the processor or the DMA controller.
This signal is active low.
DRQI-DRQ3
I
DMA Request I to 3: These lines are
asynchronous channel requests used by
peripheral devices to gain DMA service.
They are prioritized with DRQ3 being the
lowest and DRQ 1 being the highest. A
request is generated by bringing a DRQ
line to an active level (high). A DRQ line
must be held high until the corresponding
DACK line goes active.
DACKODACK3
0
-DMA Acknowledge 0 to 3: These lines
are used to acknowledge DMA requests
(DRQ 1-DRQ 3) and to refresh system
dynamic memory (DACKO). They are
active low.
34
Signal
1/0 Description
ALE
0
Address Latch Enable: This line is
provided by the 8288 Bus Controller and is
used on the system board to latch valid
addresses from the processor. It is
available to the I/0 channel as an indicator
of a valid processor address (when used
with AEN). Processor addresses are
latched with the failing edge of ALE.
l/0 CH CK
-I/0 Channel Check: This line provides
the processor with parity (error)
information on memory or devices in the
I/0 channel. When this signal is active
low, a parity error is indicated.
I/0 CH RDY
l/0 Channel Ready: This line, normally
high (ready), is pulled low (not ready) by a
memory or l/0 device to lengthen 110 or
memory cycles. It allows slower devices to
attach to the l/0 channel with a minimum
of difficulty. Any slow device using this
line should drive it low immediately upon
detecting a valid address and a read or
write command. This line should never be
held low longer than 10 clock cycles.
Machine cycles (l/0 or memory) arc
extended by an integral number of CLK
cycles (210 ns).
IRQ2-IRQ7
Interrupt Request 2 to 7: These lines are
used to signal the processor that an l/0
device requires attention. They are
prioritized with IRQ2 as the highest
priority and IRQ? as the lowest. An
Interrupt Request is generated by raising
an IRQ line (low to high) and holding. it
high until it is acknowledged hy the
processor (interrupt service 1outi,.e:.
35
Signal
I/0 Description
AEN
0
Address Enable: This line is use·d to
de-gate the processor and other devices
from the l/0 channel to allow DMA
transfers to take place. When this line is
active (high), the DMA controller has
control of the address bus, data bus, read
command lines (memory and l/0 ), and the
write command lines (memory and 1/0 ).
TIC
0
Terminal Count: This line provides a pulse
when the terminal count for any DMA
channel is reached. This signal is active
high.
The following voltages are available on the system board 1/0
channel:
+ 5 Vdc ±5%, located on 2 connector pins
-5 Vdc ±10%, located on I connector pin
+ 12 Vdc ±5%, located on I connector pin
-I 2 Vdc ±I 0%, located on I connector pin
GND (Ground), located on 3 connector pins
APPENDIX B
Schematics
36
37
C~ttYit'li.l
VJ
>------A~
Me~or!i-
>---'~~,._, A:
Address
A'
14
z
\.)1
UZ4
rr-~--
WR¢
n----- WRI
1/i
o.:.=;...._- Wfi
n-:.=--WE
uz
[")--o:o--ro
r')-'l:~-W"RS
j
I
I
n--'----Wi,
t:J.-'--m
BRD SLC.T
7
Ai;
4 n-.:..:....-a-
5 u-:-.:...-..o
>----a~_,._;~-------t-t--11 A
>--!.._~...;.;-• -----++-.;;;.;Z B
c. o-:._o
74 \..Sl"~B 7
~
7
Rigure B-1.
Address Decoding Circuit
o-:.=--o
38
l1
V.!
l"'yut
Clock
1.! LS
1.:>-'-·
7_
___,
U-41
U-47
Pt
~ ~;rTL f-!.,'T--------+--"'1~1. 4: I
•5V---l:!N
O!ic..
~- --~ •c t tClftla
.. 1,
5 ~.
L--.:.t' 13
t'\UX I'(
1
soc
r l
xoc
1'1
7'!~1.5'~
~Eij
G A
z
U!
If
14-
soc
u~s
U-42.
"
.....±. >Clll!
n
s
~
7
Q
7-4LS2!Z
ce
>-nll'Z
CliO
C!i.E'DCSA
11 "(
2
[l't
IS"
I
10
J2
U43
IS
&
2 9
7a 6G so.
lc
s
tt
&D 70
1
D'? _ _--.~ps
61> SO
&i1
til rG
<4o'D 3D
20 It>
74 LS374
II .
2
sa
~Q ~
t-4 13
s
r
-1
3
D' G --------~
D'5-------'
D' ~ ---------~
L;...; _ _ _ _ _ _ __,
..-...'-z
c'z ------------~
D'l-------------~
~¢------------~
Figure B-2.
Clock Generation Circuit
soc
To (\,Anne \'6 . RAMs- A.tJress BaAs
--'
(
U46
b
RCO
n
CLK EtJ _
'~
\1
BS
_j______ j_ _ _ _ ____,
ADR~
1?5
INCR
12.
U2.
II
~
74 LS \C. I A
Qc
2
soc
Figure B-3.
Vector Address and Timing Generation Circuit
w
U)
40
soc
Figure B-4.
Waveform Generation Circuit (Channel 0)
41
soc
U4
Figure B-5.
UG
Waveform Generation Circuit (Channel 1)
42
U4
Figure B-6.
U6
Waveform Generation Circuit (Channel 2)
43
Figure B-7.
Waveform Generation Circuit (Channel 3)
44
soc
U25
.,
US
Figure B-8.
UG
Waveform Generation Circuit (Channel 4)
45
US
Figure B-9.
UG
Waveform Generation Circuit (Channel 5)
46
,, .
US
Figure B-10.
UG
Waveform Generation Circuit (Channel 6)
47
SOC-
U35
7
SH ....
IS
mc5-,
v. It• [
"
QID~
Figure B-11.
l~aveform
+SV
Generation Circuit (Channel 7)
48
OE
U48 r---'1:~--.
R
74L':!7'i Gr-::8~;;.._,;~__:;::..:__._;......1
1'!
Figure B-12.
Output Buffering Circuit
49
U23
I)¢
1)1 4!
!Jb
I
D'i
I
I
'D2 6!
I
d-4
t{2
·12
1)'3
1)4_11_
e
1)'4
DSJ3!
7
l)'S
I
I
I
1)3Bi
M£MWE
I;
I
;
I
l)G 151
5 u'G
"07 17
-
I
191
Figure B-13.
Input Buffering Circuit
"1"'~7
v•
50
U2.7
U28
>-.....:.'Z::....l)' 0'3
WR(Z --.:..-~
->----"9~ '\) 11-4
v.;o
U29
>--",IZ::...-1:>'33
>---"9~ tl' 2~
WE.......,.-.:-~
>--=9~ t)'
:>--......!.7~1)'2~
>---'5~1/26
>-~Tf27
Figure B-14.
Channel Input Buffering (Part 1)
.3-"
51
uso
"'>-~t>~¢
'">-...:.l:..-t)'S~
'>-...!'1 ;~ 1141
"'>-~:":-'D'S \
'>---_:.;1'1:.....
'>---.....!;12!:.._
W"R4·--.:....--r---
1)'J\2
'>---....:.1 "~.:- D's Z
t/"f ~
").-....:.12:,_
t>'53
'>--'9'- \) ,-1-'i
'>-----"9~ 'D'S 4
'>-~7:_ 'D' 4!)
'>--~7- t)SS
!>'4G
~~t>'Sb
'>-~1)'47
'>-~"D'57
'>-.....:S"~
191
ChanY1e~
USI
5
U52
-:>-.....!.'I.:...' 1)'
'>--..:!:'1 '~:..... i)b
z
b3
'>---...!:12:..,_1>,
WR 6 --1-~---;:,....J
'>--'9'-'P,tA
5
71
'>-...::l'~::.....\)'72
'>-....:.12=- D'73
WRT----!..~~
"'>--'9'-1) '74
"'>--.....!..7:_ 1)'b
"'>--.....!.'7:_
"'>--'S"!-1)' 66
~--"-"0'7&
..__...__ T),b7
"">-~D'77
Ch.ttvme \ 7
Figure B-15.
Channel Input Buffering (Part 2)
1)'75'
.