CA-LIFORNIA STATE UNIVERSITY, NORTHRIDGE
MICROPROCESSOR BASED DATA ACQUISITION SYSTEM
A project submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Electrical Engin.eering
by
Chin-Wain Chang
May 1985
The Graduate Project of Chang,
Chin~wain
is approved:
(G~rald Davis)
California State University, Northridge
ii
Q
TABLE OF CONTENTS
PAGE
vii
ABSTRACT
Chapter 1
INTRODUCTION
1
Chapter 2
INTERFACE CIRCUIT BOARD
4
2-1
HARDWARE STRUCTURE
4
2-1-1
Z-80 MICROPROCESSOR
4
2-1-2
ROM (READ ONLY MEMORY)
4
2-1-3
RAM (RANDOM ACCESS MEMORY)
6
2-1-4
I/0 PORT
6
2-1-5
US ART
6
2-1-6
A/D CONVERTER
7
2-2
CONTROL PROGRAM
10
2-3
DEBUGGING SYSTEM
10
Chapter 3
13
DATA TRANSFER
3-1
RS-232 BUS
13
3-2
INTEL 8251
15
3-2~1
COMMUNICATION FORMAT
17
3-2-2
THE RATE OF DATA TRANSFER
19
3-2-3
INTEL 8251 CIRCUITRY
19
3-2-3-1
RECEIVER
19
3-2-3-2
TRANSMITTER
21
3-2-3-3
MODEM COMTROL
22
3-2-3-4
I/0 CONTROL
22
3-2-3-5
I/0 BUFFER
23
I
3-2-4
8251 MODE SELECTION
iii
23
'
3-3
INS 8250
24
3-3-1
I/0 BUFFER OF INS 8250
24
3-3-2
OPERATION SEQUENCE
34
DATA TRANSFER IN THIS DATA ACQUISITION
3-4
SYSTEM
- Chapter 4
Chapter 5
34
3-4-1
HANDSHAKING
34
3-4-2
OPERATION OF INS 8250
35
3-4-3
OPERATION OF INTEL 8251
35
OPERTING RPOCEDURE
38
CONCLUSIONS AND DISCUSSIONS
42
5-1
AN ALARM SYSTEM
42
5-2
ANALOG DATA RECODER
42
BIBLIOGRAPHY
43
APPENDIX
A
SCHEMATIC OF INTERFACE CIRCUIT
44
B
CONTROL PROGRAM ON IBM-PC
48
C
CONTROL PROGRAM ON INTERFACE.CIRCUIT
56
iv
LIST OF FIGURE
PAGE
Fig
1-1
Block diagram of the system
2-1
Block diagram of the interface circuit
3
board
5
2-2
Block diagram of ADC0801
8
2-3
The flowchart of the control program
3-1
25-pin O-shell connector
14
3-2
connector pin assignments
14
3'-3
Signal levels of
3-4
Signal converter
16
3-5
Asynchronous and synchronous format
18
3-6
INTEL 8251 functional block diagram
20
3-7
The flowchart of INTEL 8251
RS~232
bus
.11
16
initializatiori
25
3-8
The format of the mode instruction
26
3-9
The format of the command instruction
27
3-10
The format of the status register
3-11
The format of the interrupt
identification register
3-12
27
29
The format of the interrupt enable
register
29
3-13
The format of the line control register
30
3-14
The format of the line status register
30
3-15
The format of the modem control register 31
3-16
The format of the· rwdem status register
v
31
'3-17
3-18
4-1
The flowchart of INS 8250 intialization
33
The flowchart of the data transfer
36
The flowchart of the system operating
procedure
39
4-2
Screen display for analog signal
41
4-3
Screen display for digital signal
41
vi
ABSTRACT
MICRO-PROCESSOR BASED DATA ACQUISITION SYSTEM
by
Chang, Chin-Wain
The purpose of this project is to.design and implement a microprocessor based data acquisition system. The
system has- the capability to fetch either analog or
digital signals, store .them in memory, then display them
at a later time. Data in memory can also be processed
prior to display. The system includes three parts:
1. An interface circuit board. It is essentially a microprocessor based subsys'cem.
The function of it is to
control the acquisition data including analog-todigital conversions for analog signals.
vii
2 . IBI'1 Personal Computer.
The fetched data are trans-
fared to an IBM PC and displayed on the screen. The
computer can also be programmed to processed the data
stored in memory prior to display.
3. RS-232 Bus.
Data transfer between IBM PC and the
interface circuit is through a RS-232 Bus.
This system was designed with two applications in
mind. First, it is used as a analog· signal recorder.
Second, it is used- as an alarm system. Hardware has been
designed and software-needed to operate the system was
developed. Photo transistor and dip switch-are used to
generate analog and digital signals to test the system.
Test results indicated the system operated as designed.
The system performances are summarized as follows:
1) One analog channei
A. Voltage range: 0-5 Volt
B. Max. sampling rate: 4 times per second
2) Eight digital channel
A. Logic level: 0-0.85 volt for logic
for logic
11
"O", 2-12 volt
1 11 •
B. Max. sampling rate: 4 times per second
viii
CHAPTER 1
INTRODUCTION
It is .oftel"l.!l=?-~s~~l:"_¥__~_<::) r~c~?_;:9- anolog signals and
d~g~:t:~-<!~!a__!_n rea_~
time. These dat:a g9n}?_e analyzec:l at
a later time. The analcig si9nals
transducers or sensors that
gener~lly
produc~-output
come from
voltages
which varied (usually linearly)as input parameter such as
pressure, temperature or current changed. The digital
data might come from counting manufactured items on a
conveyor. These data have been used for many purpose.
For .instance, in a factory, products must be manufactured
at a certain range of temperature and pressure. A monit:or
..
and control system can be desinged to keep the pressure
and .temperature in this certain range. In this application, an acquisition system is needed to· measure· the
current temperature and pressure and then check the data
if they are within the allowable· range. Once the s:ystem
finds that the.parameters are outside of the allowable
range, it will issue control signals to the control
equipments to bring the temperature and pressure· back to
the allowable ranges. These operations
~};~__p_§?;JQ.l.=:_!t!~d --~!!..~-­
an ~:':l.~~!!lat:_§~.-~Cl.EE.!=.~C::.t:.~~-~-~~-~X-~~~.!ll-~
This project. is__t:-'?_~~-~~9.~---~!!~.-~l:ll:LJ~E:Ifient §_!:l._g_h_ __c;___Qata _
_acquisition
S¥~_1:._~!_1\·
~£le
system
-~as
one analog data
channel and eJght digital data channels. The number of
channels is expandable, requiring only a minor additions
1
,,
of hardware and software modification.
The system consists of three main parts.:
1) An interface circuit board. It is a microprocessor
based subsystem, _c:::Qnsisting of an Z-80 microprocessor,
an A/D converter, an USART (Universal Synchronous/
Asynchronous Receiver/Transmitter), an output port, an
input port, lK-byte RAMs and 2K-byte ROMs. _The
function of this part is to fetch data, to perform A/D
-=-~=-~=,_."~-""''"'"'~~~,-7>=~-·-·<~..~--~K--~~~><~'-~--=-------
conversion if needed, and to. send the data to an IBM
Personal Computer.
2) IBM Personal Computer. The data fetched from ·interface
circuit board are send to this computer to be
processed. Software w~~---d~~-~-~.c?_E~_?___~_«? . ~~~~¥~.~--!~~ data
and
di~lay
the results.
------------.·~-------~··
3) RS-232.Bus. Data transfer between· interface circuit and
IBM-PC is through a RS-232 bus. The· data transfered is
in asynchronous format.
____Th~-_.!?_~sic block diagram of this system is
show~
as___!_!g --~=-~­
The interface circuit ,including hardware structure and
control program, is pres~_l!!_~~--!~--~~~l?!:~E.-~ Method used
for transferring data between interface circuit and IBMPC is disscussed
in .Chapter 3.
The system software for
..
....
---------~
~----~~-----~-M•L.__.,.., ~~,-~~.·---~·..-o.w<••>-·~
the IBM-PC wtLl l?§..~!:ai;._~~J:!!.._9!!.~:et~_:;:__ i_· K~E.9-J.:l:x.L_ in
Chapter 5, the ·-- conclusions and discussions are stated •
. ---· --
-
, .... ,
------~-- -----~--~---~-·-------------------~--~---~~-~-~-----~----.-~~~~_,.._,_
'
3
An a log
In put
Dl'gital
In1put
,' Interface
Circuit
"'"'-
RS-232
',
IBM-PC
',
Fig 1-1
Block diagram of the system
Chapter 2
INTERFACE CIRCUIT BOARD
2-1 HARDWARE STRUCTURE
The function of this interface. circuit is to fetch
either analog signals through an A/D converter or digital
data through an input port and then transfer the data to
IBM-PC. This.interface circuit consists of a Z-80 microprocessor, 2K-byte ROMs; 1K-·byte RAMs, an A/D converter
and an INTEL 8251 communication chip. The block diagram
of the interface circuit is shown in Fig 2-1.
2-1-1 Z-80 MICROPROCESSOR
The Z-80 is a single chip, N-.c=;hannel Silicon CPU
produced by Zilog. The important features of Z-80 are:
l) 158 instructions, 10 addressing modes.
2) 17 internal registers.
3) Three modes of fast interrupts plus a nonmaskable
interrupt.
4) Directly interfaces to standard statio or dynamic
memories.
5) 1.0 micro-second instruction execution·speed.
6) Single 5 Vdc supply and single phase 5 Volt clock.
7) All pins are TTL compatible.
8) Built-in dynamic RAM refresh circuitry.
2-1-2 ROM (READ ONLY MEMORY)
The control program is stored in a 2716 ROM which is
4
Di gital
In put
1--1--
I/
An a log
In!pUt
.!::::: 8212
"'.
'
7
A/D
~
"
~
7
IQ_ata Bus
2716
':;'PROM
Input
Port ...
'"'
~
~ 1-
'
~ddr.
,,'
~
r-
1-
,;
8251 ~t:
To :];BH-PC ~SART
.r
."'.
"<=
;
1-
'
1-
~"
8218 I'
~
...--<(utpu i\
II
=>ort
'
Bus
1--
1---1
2114
t
.
.
.
0;::
-
~
RA£-1
Z-80
.1--
f.--
1--
...
I--
"""
~Hero-
processor
Control
Bus
7
.;(£
'
Fig 2-1
Block diagram of the interface circuit board
U1
6
a programmable and erasable read only memory (EPROM) . The
2716, with its single 5 Vdc supply and with an access
time of 350 ns, is ideal for use with the high
performance +5 Vdc microprocessor such as Z-80 and INTEL
8085. The capacity of the 2716 is 2048 bytes. The 2716
can be programed using single pulse level programming
technique.
2-1-3 RAM (RANDOM ACCESS MEMORY)
In this interface circuit, 2114 RAM's are used as
data memory. The 2114 is directly TTL compatible in all
respect: input, output, and a single +5 Vdc supply. The
capacity of 2i14 is 1024x4. So, two of them has been used
to form 1024x8 memory.
2·-1-4 I/0 PORT
The I/O port used here is 8212, which consists of an
8-bit latch with 3-state output buffer along with control
and device select logic. Also included is a service
request flip-flop for the generation of interrupt request
to the microprocessor.
2-1-5 USART
INTEL 8251 is a serial communication chip with
several different operation modes which can be select by
setting certain registers. The INTEL 8251 will be
discussed in detail in next chapter.
7
2-1-6 A/D CONVERTER
The A/D converter
used in this project is ADC0801.
It is an 8-bit, successive approximation A/D converter
which uses a modified potentionmetric ladder. The
converter appeared to the processor as memory location or
I/O port, hence no interfacing logic is required. The
important features of ADC0801 are:
1) Conversion time of less than 100 microseconds.
2) Differential analog voltage inputs.
3) Interface compatible with many
micropro~essors.
4) TTL input and output compitable.
5) On chip clock generator.
•
6) 0-5 Volt analog voltage input range.
7) No zero-adjust required.
The block diagram of ADC0801 is shown in Fig 2-2.
Conversion is started by having CS and WR simultaneously
low. This sets the start flip-flop and reset the 8-bit
shift register, the interrupt flip-flop and input a "1"
to ~he D flip-flop, DFF1, which is at the input end of
the 8-bit shift register. Internal clock signals then
transfer this
11
1 11 to the Q output of DFF1. The AND gate,
G1, combine this
11
1 11 output with a clock signal to
provide a res~t signal to the start flip-flop. If the set
signal is no longer present, the start flip-flop is reset
and the 8-bit shift register then can·have a
"1" shifted
into it's least significant position. This starts the
8
READ
CLK
START
CLK
~=~F/F
D
DFFl
Q
CLK B
D
UCCESSIVE
LADDER t:::::::;:::;:::=J APPROX.
AND
REGISTER
ECODER
~ND LATCH
R~-""4
8-BIT
SHIFT
REG.
Q
D.
CLK A--+---o DFF 2
DIGITAL
OUTPUT
INTR
Fig 2-2
Block diagram of ADC0801
9
0
conversion process. After the
11
_1 11 is shifted through the
8-bit shift register, which·complets the SAR-operation,
it appears as the input to. the DFF2. As. soon as this
11
1 11
is output from the shift register, the AND gate, G2,
cause the new digital word transfer to the 3-state output
latch. When DFF2 is subsequently clocked, the Q output
makes a high-to-low transition which causes the interrupt
flip-flop to set. An inverting buffer then supplies the
INTR output signal. When data is to be read, the
combination of the
cs
and RD being low will cause the
interrupt flip-flop to be reset and the 3-state output
latches will be enabled to provide an 8-bit digital
output.
In this project, the
cs
pin of ADS0801 tight to A4.
So, the address of it is 10. The
proc~dure
to control the
A/D conversion is as follow: First, output an arbitrary
data to it that will cause both CS and WR to be low. The
conversion process starts. Second, either wait for a
period of time of equal to or greater than 100 microsecond
or wait for the interrupt from ADS0801 indicating the
conversion process is completed. Third, read the data from
ADS0801. The control program is as follow:
L1:
OUT (10),A
;OUTPUT AN ABITRARY DATA TO ADS0801
LD L,10H
;200-MICROSECOND PAUSE
DEC L
JR NZ,L1
'
10
IN A, ( 01)
;READ DATA FROM ADS0801
The detailed schematic of the interface circuit is shown
in Appendix A.
2-2 CONTROL PROGRAM
The control program was written to be resided in
Z-80 to control the operations of the interface circuit.
The flowchart of this control program is shown as Fig 2-3.
The initialization block includes USART initialization and
set stack pointer. The data transfer block will be
discussed in chapter 3. The program listing of this
control program is- in Appendix B.
2-3 DEBUBBING SYSTEM
The interface circuit was debugged with a FLUKE
9010A Microsystem troubleshooter which is a portable
service instrument for testing and troubleshooting
microprocessor based- equipment. The 9010A provides the
following features:
1) Keyboard selection of "function" and "operation" modes.
2) 32-character display for presentation of test result,
operator message, and prompts.
3) Single-keystroke validation of electrical integrity of
microprocessor bus.
4) Learn function for mapping UUT (unit under test)
address space and identifying RAH, RON:, and
r;o.
5) Comprehensive, functional testing of RAM, ROH, and I/0.
11
Reset
Initialization .
Fetch two
data
Transfer
two data
to
IBJI.~-PC
Fig 2-3
The flowchart of
the control program
Stop
12
6) Nine troubleshooting functions for troubleshooting on
or off the bus.
7) On-line programming for development of system test and
fault isolation program.
~)
Consistent prompts and defaults for
~asy-selection
of
operations.
9) Detail error message for locating UUT failures.
10} Dual-function stimulus/response probe for generating
bus synchronized pulses or gathering signatures,
counting events, and detecting logic level.
11} Hexadecimal keyboard for data entry.
12} Sixteen 32-bit internal registers for storage and
manipulation of data.
13} Optional interface pods for interfacing with the
following microp-rocessors: 8080, 8085, Z80, 6800, 6502
14) UUT emulation for execution of UUT program.
15} Rear-panel scope trigger output that is synchronized
to UUT microprocessor bus events. -
Chapter 3
DATA TRANSFER
In this project, the data transfer between the IBMPC and the interface circuit board is through a RS-232
bus. In the interface circuit board, a USART (INTEL
8251) is used as serial communication port. In the IBH-PC
there is a INS 8250 which is also used as a serial
communication port.
3-1 RS-232 BUS
RS-232 Bus is a standard serial data communication
link developed by the Electronic Industries Association
(EIA) . RS-232 bus specifies voltage levels of the
contr~l and data signals exchanged ~etween an signal
converter and a communication port, such as INTEL 8251 and
INS 8250, Essentially, RS-232 Bus is a 25 lines cable and
a 25-pin O-shell connector on each side of the.cable. Fig
3-1 shows the
25~pin D~shell
connector and Fig 3-2 shows
the connector pin assignment ..
The signal converter is a serial interface. Which
contains data and control signals as list below.
Pin 2
Transmitted data
Pin 3
Received data
Pin 4
Request to send
Pin 5
Clear to send
Pin 6
Data set ready
13 .
..;.
--
-14
1
13
. {. ............ ·t
0\ ••••.•••.•••
14
Fig 3-1
,o
25
25-pin D-shell connector
Pin
..,
"
/
~
.,!'
'
/
"
./
'
NC
Transmitted data
Receive data
Request to send
Clear to send
Data set ready
S1anal around
Received line sianal detector
+Transmit current loop data
NC
-Transmit current loop data
NC
NC
NC
NC
NC
NC
+Receive current loop data
NC
Data Jcerminal ready
NC
Rinq detector
NC
NC
-Receive current loop return
Fig· 3-2
1
2
3
4
,.....
6
....
~
s
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
/
,
.......
..
',
',
.,,
Connector pin assignments
15
Pin 7
Signal ground
Pin 8
Carrier Detect
Pin 20
Data terminal ready
Pin 22
Ring detector
The signal converter converts the signals from TTL
levels to EIA voltage levels. The signals are sampled
and generated by the communication chip. These signals
can then be sensed by the system software to determine
the states of the interface or peripheral devices. The
signal will be considered in the "marking" condition when
the voltage on the signal converter measured at the
interface point, is more negative than -3 Vdc. The signal
will be consi<;ier in the "spacing" c'ondition when the
voltage is more positive than +3 Vdc. The region between
+3 Vdc and -3 Vdc is defined as transition region. The
voltage that is more negative than -15 Vdc or more than
+15 Vdc will also be considerd an invalid level. As shown
in Fig 3-3.
During the transmission of data, the "markipg"
condition will be used to denote the binary state
11
1 11 and
the "spacing" condition will be used to denote the binary
-state
11
0 11 • Two chips, 1488 and.1489, are used as the
shown in Fig 3-4.
3-2 INTEL 8251
INTEL 8251 is a Universal Synchronous/Asynchronous
16
Invalid levels
+lS.vdc
On function
+3 Vdc
0 Vdc
Invalid levels
-3 Vdc
On function
-15 Vdc
Invalid levels
Fig 3-3
Signal levels of RS-232 bus
-12v
RS-232
1\r---- input
To
8251
Fig 3-4
Signal converter
,,
'
17
Receiver/Transmitter which is capable of operating with
a wide variety of serial communication formats. INTEL
8251 can be used to interface a microprocessor to a broad
spectrum of peripherals, as well as to a serial communication channels.
3-2-1 COMMUNCAITION FORMAT
There are two types of communication formats,
synchronous and asynchronous. These formats are similar
in that they both require framing information to be added
to the data to enable proper detection of the character
at the receiving end. The major difference between the
two formats· is that the asynchronous format reqires
framing information to be added to each character, while
the synchronous format adds framing information to blocks
of data. Since synchronous format is more efficient than
the asynchronous format but requires more complex in
decoding, it is typically found on high-speed data links,
while the asynchronous format is used on lower speed
lines.
The asynchronous format starts with the basic data
bits to be transmitted and adds a "START" bit in the
front of them and one or more "STOP" bits behind them as
they a-re transmitted. The START bit is a logical zero, or
SPACE. The STOP bit is logical one, or "MARK".
In the synchronous format, instead of adding bits to
each character, group characters into records and adds
18
framing characters are generally known as SYN characters
and are used by the receiver to determine where the
chatacter boundaries are in a string of bits.
An example of the synchronous and asynchronous
formats is shown on Fig 3-5. The synchronous format shown
requires two SYN characters at the start of the message.
The asynchronous format requires a START bit preceeding
each chatacter and a single STOP Bit following it.
llllllllli1111U1
Data
.
QJl,.. [b!l[
SYN
Char#2
SYN
Char#l
Synchronous
r
. Stop
__ j I I l I I I I I I I I I I I I I I I I
d';; \. oai:; ..-// \ ' - Dat; ..-/ S~rt
Start bit
Stop bit
Asynchronous
Fig 3-5 Asynchronous and synchronous format
bit
19
3-2-2 THE RATE OF DATA TRANSFER
In order to transmit data over a single line, the
rate of data transfer must be specified. For serial data
communication, the rate at which data is transfered is
determined by the baud rate. The baud rate is defined as
the number of bits, persecond being transfered over a
single line.
3-2-3 INTEL 8251 CIRCUITRY
A block diagram of 8251 is shown in Fig 3-6. The
8251 consists of five major sections which_communicate
with each other on an interna-l data bus. The five
sections are the receiver, transmitter, modems control
readjwrite control and I/O buffer. The I/O buffer has
three subsections: the status buffer,the datajcommand
buffer, and the receive data buffer. In this project
asynchronous format was used.
3-2-3-1 RECEIVER
The receiver accepts serial data on the RxD pin and
converts it to parallel data ·according to the appropriate format. When the 8251 is in the asynchronous
mode and it is ready to a·ccept a character, it look for a
low level on the RxD line. When it sees the low· level, it
ass~mes
that it is a START bit and enables an internal
20
../''~
External data bus
'
I
L_
1'\.
'
1
Status
buff_er
~
Receive
laata buffer
'-I
""""
..,v
.
.,.~'""'-"'
Xnlit data/
cmd buffer
I/O buffer
/ I'
_.....
Reset
Clk
C/D
'
.~
...
..
...
)
RD
Read/write
' control
,
logic
'·
~
'
'
/
'l'ransmi ttelr
~
)
i.,;
I'
I--
DTR
DSR
RT8
C'l'S
~
'
,'
Modem
control
/
.......
-
........
Fig 3-6
~..
~
/
"
',
'
··~
y
{-.
', TXRDY
·•
~
Receiver
~
,
TXE
TX'C
RXRDY
SYNDET
~
\
,;
!/
I'
INTEL 8251 functional block diagram
P~D
21
counter. At a count equivalent to one-half·of a· bit time,
the RxD line is sampled again. If the line is still low,
a valid start bit has been received and the 8251 proceeds
to assemble the chatacter. If the RxD line is high when
it is sampled, then either a noise pulse has occured on
the line or the receiver has become enabled in the middle
of the transmission of the chatacter. In either case, the
receiver aborts its operation and prepare itself to
accept a new chatacter. After the successful reception of
a START bit, the 8251 clocks in the data, parity and STOP
bits, and then transfers the data on the internal data
bus to the receive data register. The RxRDY signal is
asserted to indicate that a character is available.
Before the receiver is operated, it must be enable by the
RXE hit(D2) of the command ins-truction. If this bit is
not set, the receiver will not assert the RxRDY.bit.
3-2-2-2 TRANSMITTER
The transmitter accepts parallel data from the
processor, adds the appropriate framing information,
serializes it, and transmits it on the TxD pin. In the
asynchronous mode, the transmitter always adds a START
bit. Depending on how the unit is programmed, it alse
adds an optional even or odd parity bit, and either 1, 1
and 1/2, or 2 STOP bits. The transmission is inhib:l.ted
until TxE and CTS input are asserted.
- ----
..........
22
Q
3-2-3-3 MODEM CONTROL
The modem control section provides for the
generation of RTS and reception of CTS. In addition, a
general purpose output and a general purpose input are
provided. The output is labeled DTR and.the input is
labeled DSR. DTR can be asserted by setting bit 2 of the
command instruction. DSR can be sensed as bit 7 of the
s~atus
register. DTR-is normally assigned to the modem,
indicating that the terminal is ready to communicate. And
DSR is a signal from the modem, indicting that it is
ready for communications.
3-2-3-4 I/0 CONTROL
..
The Read/Write Control Logic decodes control signals
on the microprocessor control bus into signals which
gates data on and off the USART's internal bus and
control the extenal I/O bus (DBO-DB7)·. The truth table
for those operation is as follow:
CE
C/D
READ
WRITE
Function
0
0
0
1
CPU ,READS DATA FROM USART
0
1
0
1
CPU READS STATUS FROM USART
0
0
1
0
CPU WRITES DATA TO USART
0
1
1
0
CPU WRITES COMMAND TO USART
1
X
X
X
USART BUS FLOATING
In this project, CE and C/D are directly connect to
address bus A3 and A2, the I/O control can be performed
•
23
with following Z-80 instruction:
IN A,(08)
;CPU READS DATA FROM USART
IN A,(OC)
;CPU READS STATUS FROM USART
OUT (08),A
;CPU WRITES DATA TO USART
OUT (OC),A
;CPU WRITES COMMAND TO USART
3-2-3-5 I/0 BUFFER
The I/O buffer contains the STATUS buffer, the
RECEIVE DATA buffer and the XMIT DATA/CMD buffer. Note
that although there are two registers which stores data
for transfer to the CPU (STATUS and
RECEIV~
DATA), there
is only one register which stores data being transferred
to the USART. The sharing of the input register for both
transmit data and commands makes it -important to ensure
that the USART does not have data stored in this register
before sending a command to the device. The TxRDY signal
can be monitered to accomplish this.
3-2-4 8251 MODE SELECTION
The USART is capable of operating in a number of
modes. These operating mode are selected via a series of
control output to the USART. These mode control output
must occure between the time the USART is reset and the
time it is utilized for data transfer. Since the USART
needs this information to structure its internal logic it
is essential to complete the initialization before any
attempt is made at data transfer.
~
----
............
24
Fig 3-7 is the flowchart of the initialization
process. The format of the mode instruction is shown in
Fig 3-8. The format of the c9mmand instruction is shown
in Fig 3-9. Notice that DTR, RTS are directly related to
the modem control output pins DTR snd RTS. Fig 3-10 is
the format of the status register. Notice that DSR,
SYNDET, TxE, RxRDY, and TxRDY are the same definitions as
those pins with the same name.
3-3 INS 8250
INS 8250 is an asynchronous only communication
ch~p.
\
..
Its structure and function are almost the same as INTEL
8251 operated in asynchronous mode except the I/O buffer .
. .
In INS 8250, there are 10 registers including Data Buffer
Divisor, Latch, Int&rrupt Control Register, Modem Control
Register, Modem Status Register, Line Control Register,
Line Status Register.
3-3-1 I/0 BUFFER OF INS 8250
The functions and formats of these registers are as
follow:
1) Received Buffer Register. Its an 8-bit register which
contains the received character.
2) Transmitter Holding Register. Its also an 8-bit
register which contains the character to be serially
transmitted.
3) Divisor Latch LSB. The INS 8250 contains a programmable
25
Software
Initialization
Load Mode
Instruction
Load
SYN characto
Load Command
Instruction
Fig 3-7
Flowchart of INTEL 8251 initialization
~
-·--- .........
26
Baud rate factor
...__~
OO=SYN mode
Ol=ASYN 1
lO=ASYN 16
ll=ASYN 64
Character length
'------~
...___ _ _ _ _ _ _~
00=5 bits
01=6bits
10=7 bits
11=8bits
Parity control
)(.O=No parity
Ol=Odd parity
ll::=Even parity
Framing control
.Yes
OO=Not valid
01=1 stop bit
10=1.5 stop bits
11=2 stop bits
SYN control
L---------------------~ XO=Internal SYN
Xl=External SYN
OX=Double SYN char
~=Single SYN char
Fig 3-8
The format of the mode instruction
27
Request to send
Fig 3-9
The format of the command instruction
D7
D6 DS D4 D3 D2 Dl DO
DSR SYN FE OE PE 'I')(E RX T)(
DET
RDY RDY
I
F
,'
Receive ready
,'
Transmit empty
',
Parity error
'
Overrun error
,.'
Framing error
,
SYN detect
/
_.....
~
r
Fig 3-10
Transmit ready
Data set ready
The format of the status register
28
baud generator that is capable of taking the clock
input (In IBM-PC, the frequency of clock input is
1.8432 MHz} and dividing it by any divisor from 1 to
65535. Two 8-bit latch stores the divisor in a 16-bit
binary format. This register stores the least
significant 8 bits. of the divisor.
4} Divisor Latch MSB. It stores the most significant 8
bits of the divisor.
5} Interrupt Identification Register. The INS 8250 has an
on-chip interrupt capability that allows to
interfac~
to all the popular microprocessor. In order to provide
minimum software overhead during data character
transfers, the INS 8250 prioritiza$ interrupt into
four levels:
Priority 1
receirver line status
Priority 2
received data ready
Priority 3
transmitter holding register empty
Priority 4
modem status
Information indicating that a prioritized interrupt is
pending and the type of prioritized interrupt is store
in the interrupt identification register. The format
of this register is as Fig 3-11.
6) Interrupt Enable Register. This register enables the
four types of interrupt of the INS 8250. The format
of this register is as Fig 3-12.
7) Line Control Register. The mode of qommunication can
..,..----
"""""""'.
29
ID7ID6ID5ID4ID3ID2 Dll DOl
=0 if interrupt pending
Interrupt type
_......
/
=00 Receiver line status
=01 Received data available
=10 Transmitter holding
Register empty
=11 Modem control
,
...... =0
', =0
_..... 0
,
', =0
,'
Fig 3-11
0
The format of the interrupt identification reg.
1D 7 1D 61 D 51 D 4 1D31 D21 D11 Dol
I
I
,
.....
1 Enable interrupt 10
,.
...... 1 Enable interrupt 01
)
1 Enable interrupt 11
,........=1
......
,
0
/
...
0
,......
0
Enable interrupt 00
,..' =0
Fig 3-12
The format of the interrupt enable register
30
ID7ID6ID5ID41 D3ID2ID1 DOl
,c haracter length control
= 00
= 01
= 10
\= 11
......
7
s top
5-bit
6-bit
7-bit
8-bit
bit control
=0 one stop bit
=1 one and~half stop bits
7'
if character length is 5
two stop bits if character
le~gth is 6,7,or 8
\
......
/
Parity enable
.... Even parity select
/
'/
Stick parity
·'7 Set break
'
Divisor latch acess bit
/
Fig 3-13
The format of the line control register
ID71 D6l D5l D41 D31 D21 Dll Dol
Data ready
I
I
;
Overrun error
Parity error
'/
Framing error
Break
"'
interrupt
holding
,' Transmitter
register empty
.... TXshift register empty
I'
'
/
Fig 3-14
=0
The format of the line status register
31
Data terminal ready
~--~~Request
to send
Outl which is a useroutput
~--------~designated
~--------~~Out2
Loop which is a loopback
'-----------------+feature for diagnostic
testirig Of the INS8250
~----------------~=0
~------------------~=0
~----------------------~=0
Fig 3-15
The format of the modem control register
Delta clear to send
~-----YDelta
data set ready
"------~'railing
edge ring indicator
...__________;:~Delta R Line signal detect
'-----..,.---------4- Clear
to send
'-------------~Data
set ready
~--------------------~Ring
indicator
'----------.:....-....---------+Receive line signal detect
Fig 3-16
The format of the modem status register
32
be selected through setting this register. The format
of this register is shown in Fig 3-13.
8) Line status Register. It provides status information
on the processor concerning the data transfer. The
format of this register is shown in Fig 3-14.
9) Modem Control Register. It controls the interface with
the modem or data set. The format of this register is
shown in Fig 3-15.
10) Modem status Register. It provides the current _·state
of the control lines from the modem. The format of it
is shown in Fig 3-16.
The address of these registers in .IBM-PC is shown in
Fig 3-17.
ADDRESS
REGISTER SELECTION
DLAB STATE
2F8
TX BUFFER
DLAB=O
2F8
RX BUFFER
DLAB=O
2F8
DIVISOR LATCH LSB
DLAB=1
2F9.
DIVISOR LATCH MSB
DLAB=1
2F9
INTERRUPT ENABLE REG.
2FA
INTERUPT IDENT. REG.
2FB
LINE CONTROL REG.
2FC
MODEM CONTROL REG.
2FD
LINE STATUS REG.
2FE
MODEM STATUS REG.
Fig 3-17
Address of registers in INS 8250
----33
~
"
Load Line
Control
Register
DLAB=l
'II
Load
Divider Latch
(lower byte)
... ll
Load
Divider Latch
(higher byte)
..
'
II
Load Line
Control
Register
(se·t mode)
' II
Load
Interrupt
Znable
R~::gister
t
l
Fig 3-18
The flowchart of
INS 8250 initialization
- 34
3-3~2
OPERATION SEQUENCE
Befor performing any data transfer, INS 8250 needs
to be initialized. The initialization procedure is shown
in the flowchart in Fig 3-18.
3-4 DATA TRANSFER IN
D~TA
ACQUISITION SYSTEM
In this data acquisition system, asynchronous format
was used. One START bit and two STOP bits are added into
every 8-bit data. The data is transfered at the rate
of 1200 BAUD.
3-4-1 HANDSHAKING
Data are transfered from interface circuit to IBM-PC.
IBM-PC acts as a receiver and the interface circuit acts
as a transmitter. Before the data transmission can start,
procedures are needed to verify that the two devices are
ready for data transmission. The procedures for validating
the availability and operability of the devices is called
hankshaking.· The hankshaking can
be made
through the modem
control of RS-232 bus. The circuit is validated through
following procedures: First, IBM-PC send a DTR (notice
that DTR is defined as state transient, from high to low
or low to high, not as a stable state) to interface
circuit. Once the interface circuit senses D~R~ it will
transmit a data to IBM-PC. The above procedure is done by
programming INTEL 8251 in interface circuit and INS 8250
35
in IBM-PC. Fig 3-19 is the flowchart of the initialization, handshaking and data transfer procedure.
3-4-2 OPERATION OF INS 8250
The program listing of the operation of INS 8250 is
in Appendix
c which is written in BASIC. Statements 85-97
is the initialization for INS 8250 and statements 30003200 are the data transfer prodedure. statements 86-88
are used to set the divider such that the transmission
baud rate will be 1200. Statement 89 is to set the
operation mode, 8-bit character and two stop bits.
statement 90 is to disable the interrupts. Statement 97
is to send out "Data Terminal Not Ready". Statements 30653070 are used to check if the data.is received. If the
data is received, read it in and store as variable Vl.
Statement 3100 is to change the state of DTR before
receive next data. Statements 3165-3170 are used to do
the same thing as statement 3065-3070 and are used to
acquire two data at a time and process the data, then
display them.
3-4-3 OPERATION OF INTEL 8251
The INTEL 8250 in the interface circuit is
respoDsible for transmitting two fetched data to·IBM-PC
each t;i.me. The operations of INTEL 8251 are controlled by
a program executed in Z-80. The program listing is shown
in Appendix B. The INTEL 8251 initialization procedure is
36
INTEL 8251
INS8250
Initialization
Initialization
( _ _ _ _ _ _
Sent DTR
Yes
/
/
/
I
/
/
/
'rransmi t
data
/
---·--7
Read data
No
Fig 3-19
The flowchart of the data transfer
il
'
3·7
more complicated, including software reset, mode setting,
transmiting enable. In between these procedures some
pauses and dummy read are necessary. After the data is
fetched from-outside world, 8251 start to check if DTR is
issued from IBM-PC. Once it sense ·DTR, it transmits one
8-bit data to IBM-PC. After two data are transmitted, the
interface circuit starts to fetch another two data.
CHAPTER 4
OPERATING PROCEDURE
This system was designed easy to use. Instructions
displayed on the moniter screen of the IBM-PC are
available for the user to follow. All procedures are
controlled by a BASIC program executing in IBM-PC. The
flowchart of the operating procedure is shown Fig 4-1. The
procedures are as follow:
1) Boot IBM-PC with DOS 2.1 or 2.0.
2) Type PROJECT to execute the program name PROJECT.
3) A brief introduction about this data acquisition
system will appear on the screen. Press any key, that
will continue the next step.
4) On the moniter screen, it will ask the user to enter
the operation mode, entering A or D.
5) Then, it will ask the user to enter the acquisition
time interval between data. Due to the
on~line
operations, the scquisition time interval can not be
too small. The limitation on this is 1/4 second.
6) The instruction PLEASE PRESS THE RESET BUTTON OF
INTERFACE CIRCUIT BOARD will appear
on-~creen.
After
the user does that, press any key to continue.
7) Now, the system will start to fetch data and to
display the fetched data on the screen. If the mode
selected is analog, the screen will be as Fig 4-2. If
38
39
Start
Display the
Fig 4-1
introduction
The flowchart of the
of this system
system operating
procedure
operation mode
Receive the
data from
page number
interface CK
Display one
Display the
data on the
monitor screen
previous
page
40
the mode you select is digital, The screen display is
shown in Fig 4-3.
8) If the user wants to examine the previous data or
terminate the operation, enter @. The system is
designed to trace back previous 180 data for digital
mode and 300 data for analog mode.
9) Once the user enter @, the screen will display YOU
WANT TO EXAMIUE PREVIOUS
Dl'~TA
OR TO TERMINATE THE
OPERATION right after the current page is completed.
If the user enters T, the operation will be terminated.
If the user enters E, the system will do as next step.
10) The user will be asked DO YOU WANT TO EXAMINE THE
LAST ONE, TWO, OR THREE.PAGE. Entering 1, 2, or 3,
that page will be displayed on the screen. In the
analog operation mode, it is need to press SPACE BAR
once to retrieve one data.
11) After that, on the bottom of the Screen, it appears
DO YOU WANT TO EXAMINE
OTHER.DATA~
If the user enters
Y, it will go back to 10) • If the user enters N, it
will go to 12).
12) The user will be asked YOU WANT TO CONTINUE DATA
FETCHING OR TO TERMINATE THE
OPER1'~TION.
If the user
enters T, the operation uill be terminated. If the
user enters C, it will start again to fetch data and
display the fetched data on the screen.
41
page
.
no.~
12
value of~ 168
current
data
1 0
1 0
5
OL-------~------~------+-------+-------+
20
40
60
80
Fig 4-2 Screen display for an~log signal
page
no.~
15
CH 1 0000000000001111110000000000000000000
CH 2 0000000111111111111111000000000000000
CH 3 1111111111111111111111111111111111111
CH 4 0000000000000000000000000000000000000
CH 5 0101010101010101010101010101010101010
CH 6 1111111111111111111000000000000000000
CH 7 000000111100011100000011110~000111111
Ci:I 8 1110000000011000000111000000000000111
Fig 4-3
Screen display for digital signal
·CHAPTER 5
CONCLUSION AND DISCUSSIONS
The Data Acquisition System v1as implemented and
tested by sending binary data with a dip switch and
analog data with a
pho~o
transistor. The test results
show that the system operated as designed. The system is
applied to two applications, first, an alarm system.
second, analog data recoder.
5-l AN ALARM SYSTEM
An alarm system .was implemented to accept signals
from devices such as pressure sensor, smoke se_nsor, or
light sensor, The system produces an alarm when the
signals are outside of the safety range.
The program SECURE is executed in IBM-PC. IF the
outputs from one or more of the sensors indicate ·out-of
range condition, the.IBM-PC will beep and the message
about the affected sensor or sensors will be displayed on
the screen. The beeping stops when the key @ is pressed.
Dip switch is used to generate out-of range conditions to
verify that the alarm system t.-lorked as designed.
5-2 ANALOG DATA RECORDER
This system
wa~
designed to receive analog signals.
Signals were digitized and stored up to 180 points in the
memory. A photo transistor was used to generate analog
signals to show that the system worked as designed.
42
43
@
BIBLIOGRAPHY
[1]
stou~,
David F.
Microprocessor Application Handbook,
New York; Mcgraw-Hill Book Company, 1980
[2] Coffron, James
w.
and Long, Willian E.
Practical
Interfacing Technique for Microprocessor System,
Englewood Cliffs, N.J.; Prentice-Hill Inc. 1982
[3] Z-80 microprocessor Handbook, Zilog 1977
[4] Microsystem Components Handbook - Volume II, Intel
1984
[5] Memory components Handbook, Intel 1984
[6] Hot Ideas in CMOS, Intersil Inc. 1983
[7] The TTL Data Book for Design Engineers, Texas
Instrument Inc. 1979
[8] 9010A Microsystem Troubleshooter User's Manual,
[9] IBM-PC Technique manuul, IBM Corp. 1982
[10] Disk Operating System, IBM Corp. 1982
[11] IBM-PC BASIC, IBM Corp. 1982
'
44
APPENDIX A
SCHEMATIC OF INTERFACE CIRCUIT
Ofl'tw Df
+~
Vee
2MHt
Vs>
D
-16
A~~AI~
INT
+tY'"
/4&A
:4
K
i.-80
~~
T416 I
L.P
f
N~1l
CLI<.
+5V
:2.
ck ~4161
RD
21
t-- ---t
-
'------------ --~> C.\<1
SCHE£-.i.ll..TIC OF CPU AND CLOCK GENERATOR
45
~A IS
All
I
MERE\
!8
s
+5V
1'
Pt;C&
6 AI
::,.
*' IH
3 ~ 2114- fol
4i
!
2
Ita
1
'----I Ai>
i
A5 (I) J.ju3 /:l
7/o4-
; t=r
I
IJA.
II
D~
A1
B I.a.
(l;
1
.~
P3
4
3
:z.
I
1
r
4•
3
.:l
~..,
fo
At
!t5 21IG
19 A?
ftJO
~~ DE:
HER&.
A+ (2) I/o3 112 P6
Ar
,- ,.., -
06 116
0., l'f
~~
%fol
2flf.rjo2 /3 vt
~t
Ot it_
:u A'd
14- P4
I
IT
: /6
~· 15 A8
04 14
ltb
Iff
TJQ
J..g
t ticf> -cs
I
01 ~
O:J. II
03 /3
/'13
WE
Al,.i
;·
01> ~
/fl.
2.3
WP..,
6
1:2.1
:r AI
6
t>J
16 1ft
N6
15
114-
£»
fo+ II
/J?
v:~
jto
SCHEHATIC OF ROM AND·RAM'S
18
ce
..
/:l.
4-
-
_..
46
+sv
DSI
CLR
D~
5TS
SCHEMATIC OF INPUT AND OUTPUT PORTS
+sv
47
A2--_..~
CL/( ----1-...=:::.t
IOP.P
-
'l.OW~ ------~
l.lfr
-E-----4
At
ADC. ozo I
SCHEMATIC OF A/D CONVERTER AND USART
CONTROL PROGRAM ON IBM-PC
APPENDIX B
10 REM
SOFTWARE FOR DATA ACQUISITION SYSTEM DESIGN BY VINCENT CHANG *****
****~
41
CU3
4~.?
f<E-...r' CiFF
43 BK$=SPACE$(60l
::50 L..OC(i TE 4 !I 2'7
52 COL.DI~ 0, ?
53 REM ******** DISPLAY INFORMATION *********
F'Fd NT
DATA ACQUIsITION SYSTEI"1
~i4
:56
II
COL.OF-~
II
7 !I 0
60 LOCATE 7,5
c!5
70
PR I I\IT TH I E.l SYSTEM IS VINCENT CHANG'S GFU~DLHHE F'F:O.J ECT. CH(-)1',!(3 IS ,:.") GRADUf:)TE
PRINT ''STUDENT IN DEPARTMENT OF ELECTRICAL ENGINEERING~ CALIFORNIA STATE UNIV
11
11
E~ns:rr·t,"
r:Jo PF< :r I\IT
85
86
87
88
"''mFTHr-::: :r Dt3E"
~~1\!D THE rmv I SDI~ Is DF:.
F:.. t.JUNG .. "
REM ***** INS 8250 INITIALIZATION ********
OUT t:H~::.F--8 !I ~<HElO
OUT ~-:l·f3F·r~, ~~H60
OUT ~<H:::;F--9, ~d-10
89 OUT
~>i 1:=;F~Fl
90 OUT
95 FOR
~d···I~SF9, ~d-·10
I~l
:1 i>H/
TO
SOO:I~I:NEXT
17
~7
D!...JT ~:<H::::;I::C:, 0
1 c". :1 I.._!:J L:: f.:: TE i. l , .;:!
1 :J. o r::·r:: Tr·rr "TI···J I!::.>
n.~~T~~
r~CC:H.n..:;
:r T rON
SY~"3TJ:::r·1
11:'::! F'Fili\!T ~~~~~!'U~UJG OR DlGIT?L Dr1TA.
IT
[JL.J._l]\J..) I NEi II
:1. :1.7 F'li I ~H II I 1\iST!~UCT I 01'-IS. II
1 :?0 L.DCI~1 TF::: :? l :1 l
12!:; PRINT II F'RESS ANY KEY TO CONTINUE II
130 X$=INF'UT$(1)
150 CL.S
:r: ~:;
<:::(1F't'\BU:::
·u
i:
ETCH
IS VEFi:Y Et:·1SY TO USE.
f.~ND
PF<DCr::ss
E I THEF: II
F'LEASE F'OLLOW
THE F
""'
00
4
c
1. bC L..UC:(1 rE: 4 ~ :?7
164 COLClf::
0~7
165 REM ****** SELECT OPERATION MODE *******
166 PFi:INT
167
COUJ~-::.:
DfH:C; ACClUJSTIDI\l SYSTE/"1
II
11
7 !' 0
1 7 0 L.. DC?YT t~ 7 ~' ~::_:;
T \(f:• ~~;
l/:? .HJF'I.JT "F·u;:::A?iSE E)ELEC>T THE Df-YTA T10DE (A/D)
175 IF TYF$< >"(-") 11 Ai'm TYF'$< >" D 11 THEN LOC(HE 8, 5: F'R I !\IT "I N\/AL I D SELECT I ON,
II ;
PLEASE
REENTER'':BEEP:BEEP:BEEP:GOSUB SOOO:LOCATE 7,5:PRINT BKS:LOCATE 8,5:PRINT BKS:GOT
0 170
180 LOCf.-HE 9, 5
182 I 1\lPUT II PLE(-~SE SELECT THE SAI1PL I NG PER I OD (SEC. ) II :. SP
184 LOCATE ,10~5
186 INPUT "IS TH~::~ SAMPLING F'ERIODE RIGHT? (Y/N) ";SF:$
187 IF SR$< >11 Y 11 THEN LOCATE 9~ 5: PF:II\IT BKS: LOCATE 10~ 5~ PRINT 81<$: GOTO 180
200 IF TYF'$= II{~ II THEI'·l IF SF'>. 1 THEN NMN= ( 390*!3P) -"40 ELSE NMN= 1
210 IF SP>.35 THEN NMN=C390*SP>-132 ELSE NMN=l
230 LOC?\TE 16 !• !:i
:z:::;s COLOR 0 ~ 7
:::?40 F'F\ I NT
Pl.... EASE
II
:24:5 CDL_Oh 7
F'l.JSH F:ESET BUTTON
IN THE
I NTEF:FlC;CE
c 1 RCUI T
~.0
II
"
·,
2~'.;0
LOC:':YTE 2l :• l
260 F'F:INT "PF:::Ef3S ANY I<EY TO CONTINUE"
270 X$:=:JNF'LJT$C1)
299 REM
RECEIVE TWO DATA FROM INTERFACE
9 9 0 F\ EM ·t! ·>(··¥.··I(··~· >t ·¥:· '*· D I ::; PL t1 Y D (:.:, T A ~· ·!!- i<' .,.. ·* ·li· ~· "'·
****
CIRCUIT
****
1000 DIM RDA(3, 100)
1050 IF' TYF'$::: 0
GDTO 6000
II
II
11 00 SCREEN :."Z
.1120 ~:::EY OFF
1150 PGE=O:FLAR=O
1200 F'GE ::::PGE + 1
1300 F'GE1::::PGE
1500 GOSUB 2250
,.t:>o
1.0
4
4
1700 FOR J=O TO 100
1717 GOSUB 3000
1720 RDA<FLAR,Jl=INPT
1 T::::o :~ 1 "<?4+ <J -~6)
1750 Yi=176-<RDA(FLAR,J)*120/256)
l Ti'O C I PCI...E ( "J\ 1. , Y .t :• :• i.
1780 LCiCf.HE !;.:) :• 70
1790 PH I hiT I NPT;
1792 IS!f;==UWEY'$
179:3 IF I 8$== "t~" GOTO l!-000
NEXT J
1795
1800
1900
2000
2250
2400
2450
2500
2510
2520
2530
2550
2560
FLAR=<FLAR+1) MOD 3
CLS:GOTO 1200
REM ~***** DISPLAY FORMAT ********
C:LS
LINE <24~176>-<624,176)
LINE <24,48)-(24,176)
FOR I•l TO 5
IY=32+<1*24l
LINE
C22,IY)-<26,IY>
NEXT I
FOR I=l TO 5
IX=24+(120*l)
2570 !... I l'.lF
(I X!' 175:1
-··IT
y' !. 7~' :·
2580 NEXT I
2600
2610
2620
2630
26i\-O
2650
2651
2652
FOR 1=0 TO 5
IYY=22-(l*3)
LOCATE IYY~l
Il=I*50:PRINT II
1\JEXT I
FOR I==l TO 4
IXX=2+(15*Il:III=I*20:LOCATE 24, IXX:PRINT III;
NEXT I
L11
0
.,
4
:2 /:-:, ~5 :3 L_ C) C~ t:1·r E ::; :1
26~.51.1·
;: ()
F'P I NT F'GE 1 ,
2700 I::::E:Tt.JG:i'-1
2990 REM ******* DATA TRANSFER **********
:·sooo BF=i
3002 OUT &H3FC,BF
3063 REM ******* CHECK DATA READY BIT ***********
3065 V1=INP<&H3FD>
3070 A=V1 AND 1:IF A=O GOTO 3065
3080 V2=INP<&H3F8)
3100 BF=<BF+l) MOD 2
3102 OUT &H3FC,BF
3163 REM ******* CHECK DATA READY BIT ***********
3165 V1=INP<&H3FDl
3170 A=Vl AND l:IF A=O GOTO 3165
3180 V4=INPC&H3F8)
:3190 IF TYP$:::::"0" THEI·-...1 INPT=VLJ· ELSE INPT=:V23200 FOR NN=l TO NMN:NN=NN:NEXT NN:RETURN
3990 REM ****** RETRIVE DATA *******
4000 CLS:FOR M=J+l TO lOO:RDA<FLAR,M)=O:NEXT M
400 :l LOCiHE 5 ~ 5
"\'CJU \.A):'':!··rr· ·ro FX{)Iv1INE PF~:EVIOLJ:3 Df.:H(l m~: TU :_::;::ri'v'E TI·IE ::;.;·:sTEt1
11
THEN GOTO ·1-200
'-1-030 LOCATE 6" 5
4(1~:2 PRINT II I 1\1\!AI._D ~)~~~LECTI ON,
PLEASE F:EENTEF:"
,10:>1- BE:EF' ~BEEF
LJ·O•+O (30t:>L.JB :=.;ooo
LJOO::::'
INF'LJT
<E/i_) "; D(:fi
4020 IF CJ:::$::::" E" THEN GDTO 1.1-100 ELSE IF Cl($:=" 1._
40~5!)
LOCPtTE
~.5 ~ ~:'i
LJ-0:'!5 i='Fo: I NT Ell<$
40~57 PI::: I NT BK$:
L~ObO (30TU 4000
41.00 LOCATE 7~5
4105 I NF'UT "YOU llJANT TO EXAM THE LAST F'{4GE OF: LAST TWO OR LAST THREE? ( 1 /2/3) "; N
U1
1-'
i
4:,:~:~::'.;
F·F:: :r l\i
r
I!
t3CJUDBYE
II
4230 LOCATE 24,5
F'F:: I r"n
PU::.?-"ibE TuF::N DFT THE F'OWER.
T!·-I:Cii'·JI< ':'CJU:
4300 GOSUB 5000:GDTO 4230
4990 REM ****** DISPLAY DIGITAL DATA *******
5000 FOR I=l TO lOOO:K=I+l:NEXT !:RETURN
5500'FOR 1:1 TD 8
4~·:~50
5510
II
II,
Il=(I*2)+3:I2=12+J
5520 LOCATE I1,I2
5530 AA=INPT AND 2A(I-1)
554·0 IF A(-,:::(1 THEN PRINT
5550 NEXT I
5600 RETUF~N
~000 I<EY OFF
"0"
ELSE
PRINT "1"
~~01 0 F'GE==O: FLAF:==O
6020 DIM RDD (3~60)
6050 CI_S
6055 PGE=PGE+1:PGE1=PGE
6060 LOCATE
2~70
6065 PFn NT PGE l ;
6070 COLOF; 0, 7
6100 FOR I=l TO B:Il=(I*2)+3
6110 LOCATE 11,5
L·1:-~o
FF(INT '
1
c;li' 1''
1
1
'
6130 NEXT I
. 6J 50 CUUJF:: 7:10
6200 FOR J=O TO 59
6210 GOSUB :3000
6220 RDD!FLAR~Jl=INPT
6T~:o GUSUB 5500
6240 I St~:== I Nl<EY$
6245 IF IS$==''1~" GOTO 7000
6250 NEXT J
Vl
I'V
u
4110 PN=<FLAR+<1-NU)) MOD 3
4115 PGE1=PGE-NU+1
4·1 :?O
+
1 12~;
~3C!'~:EEN 2
(3D SUB 2250
4130 FOR J=O TO 100
4131 X1=24+(J*6>:Y1=176-(RDA<PN,J)*120/256)
4132 CIRCLE <Xl~Yl>,l
4133 LOCATE 5,70
4134 PRINT RDA<PN,Jl;
4135 I<Y·li~ I N~<EY$
4136 IF I<Y$="" GOTD 4135
1.~137
1\IEXT ..J
4140 LOCATE 25,5
4145 INPUT "DO YOU WANT TO EXAM t=.)NY OTHEF: PAGE <Y /N) "; TT$
41~;o IF TT$::="Y" THE!\1 CL.S:GOTO 4100 ELSE IF TT$:::::"1\l" THEI\l GOTO 4170
41. 60 BEE:P: BEEP
4162 LOCATE 25,5
4165 F'R I NT B~<$;
4 1.6 7 f30TO 4. l.L~O
4170 CU:3
4l/2 LOC(~TE 5, 5
4173 INPUT ''YOU WANT TO CONTINUE TO FETCH DATA OR LEAVE THE SYSTEM
.q 180 IF CCt;.;;o" C
THE::!·i c::;CJTC~• 12,)•.) Ei_SE l r: CC$==' L. '' THEN GOTO 4200
(C/U II; CC$
;I
4185 l...DC?HE 6, '::)
4186 F'R I 1\JT
II
}I\I\H1LD SELECT I ON' F'LEASE RE::t::NTEF: II~
4 :l t-38 BEt::F': BEEr=·
4190 GOSUB 5000
·'!·191 LOCATE 5,5
4193 PRINT BKS:F'RINT BKS
4195 GOTO 4170
4200 CLS:SCREEN 0
4220 LOCATE 10,35
U'l
w
6300 FLAR=(FLAR+l) MOD 3
6400 CLS:GOTO 6055
PE::t~i !" ;.c!<:·1i·1H<t· !:;:ETFU 'v'E DI Ell ·rAL D~iTf-: * i'!·~ ·"-*"""·-l!'·
7000 CLS:FOR M=J+l TO 60:RDDCFLAR,M)=O:NEXT M
b'?90
-:.;·010 LDCr1T.E 5,::;
701."5 INF.UT "'{\Jl...J itJ{'-\1\H TD E:X(ii"1II\IE PF:E>JIOUH D(HPr OF: TO i.. .E~WE TI···IE
7020 IF C!<.$="E" THEN (30TO 7100 ELSE IF cr:·:<t;="L.'' THEN GOTO 4200
7030 L.OC{iTE 6, 5
7032 PRINT "INVALD SELECTION,
7035 BEEP:BEEF'
7040
70::iO
7055
7060
7100
PLE?'~SE
SYSTEM <ElL)"; D<S
REENTER"
GOSUB 5000
LOCATE 5, 5
PRINT BKS:PRINT BK$
GCJTO 7000
LOCtYrE 7 ~ 5
71i)5 INPUT. "YOU W?iNT TO EXAM THE
LAST
PP~GE
OR LA!:n HJO OF: LAST THF;:EE? ( 1/2/3) "; N
u
7110 PN=<FLAR+(l-NU)) MOD 3
7115 PGE1=PGE-NU+1
7120 CLS
7121 LOCATE 2,70
.7123 F'F: I l:l"f PGE 1 ;
7125 COLOR 0,7
7130 FOR
I~l
TO 8
7131 I 1= ( I*2) ·+·::;
7132 LOC(:lTE ll, 5
71~~;3
F'RINT
II
CH" I
1111
7:1.34 NEXT I
71.:::::5 COL. OF: 7, 0
7136 FOR J=O TO 59
7137 INPT=RDD<F'N,J):GOSUB 5500
7138 NEXT J
7140 LOCATE 25,5
(Jl
~
7145
7150
7 160
7162
7.1 tA
li\IF'UT "DO vou l'JAI">.il TO E.XAt-'1 (~NY O"THF::F: F'i~GE (Y/1\l) II; "fT$
IF TT$~--="Y" THEN CL.S:GCJTO 71.00 ELSE IF TT$=="N" THEl'-J GOTO 7170
BE::E:F': BEE:F'
LOCATE 25,5
PP I r,rr Bl·=~-:t;;
71<~)6
l::J[i"f[l
]J.l]-0
7170 'C!.... S
7172 L..DCP1TE 5 ~ 5
7174 I!\IF'U"T "YOU wt'1NT TO COI""HINUE TO
7180 IF CC$=="C" THEN GOTO 6050 ELSE
718~5 l._OCATE 6,5
7186 PH IN T II I NVf"~LD SELECT I ON' PLEASE
7188 BEEF':BEEF'
71 90 GOf.3UB 5000
719:2 LDCATE 5,5
7194 PRINT BK$:F'RINT BK$
7195 C30TO 7170
7500 FOR I=1 TO 8
7510 Il=(I*2)+3
7520 I 2·~"' 12+J
7530 LOCATE .I1,I2
7540 AA=RDD(F'N,J) AND 2A(l-1)
7::.)50 IF AA==O THEN PRINT "0 II ELSE PF: I
FETCH DATA OR LEAVE THE SYSTEM
IF CC$= 11 L" THEI'l GOTO 4200
t=;:EENTER II
NT
II
(C/U ";CC$
;
1 11
V1
V1
CONTROL PROGRAM ON INTERFACE CIRCUIT
APPENDIX C
::.~. !_:_:j t) 0
t~ v
II
~
ZB0 C F: (~:! ~:~ E ,,1 ~::~ S [ f-·1 ni... E: r:~
r:: r-~ T f~ T F~ t~ • t"' F ·i
I:•f,T(;Tnr~ ,. UPJ
:;: 1'·-i? UT
F I .'... C r·-i h i""'i E::
DUT F' UT F I L. F N(', i'i E:~
Ol 00
()2
0()
1 ()
0()
DF'T
IF'T
r·,v
!...! ~::; ·;· :0
oc
OD 00
00
u~;T
()6 00
IN 1)
CF 00
f·i~JDC
000()
21 00 OI<
~;T(',F;T
00() :.·~:;
~::- <;.:-
0004
~~E:
0000
()()() (:·
OOOD
~~· C' ·:; t'i
oooc
()()r)[
0() 1 C·
0012
-"
j -v
'-.} ~} .._:)
~
001~5
001 ~?
0019
001B
OOlC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
DRG
0()
r~: ~:-; () c::
D.·.;: OC
't·,••<t
,r.. r·•.
-... ..·
3[ 0-4
r. 3 oc
···-c
:::·c
,
I
2[1
20 FD
3E CF
D3 OC
2E FF
2D
20 FD
L2
~
t·,_/I: C::DN'v'EF~TEF:
: !...::::;AF:T f.lt,Tt•,
~
OCH
i. Uf:){',F:T COMt·lAND
06H
:INTERRUPT VECTER
CFH
OOOOH
HL. Of.{OOH
; :::; :::: T :::: T (', C i<; F' 0 I NT E:: n
::; ! ,, : ; :...
(;. OOH
U!JT
(Uf::T')
(lJ~3T) .t~,
;: u.::. r .~ ,. {. 'i
l..J ''j"
I y·,
,b, .
(JUT
( u~:.~ ·r· ) \' r=·~
DEC
:)•~H
:::[:"'I
1"1
!.. . .'.• '
:u::;hi:T INTTIAL.IZr1TIDN
~:f~
•... .'.,'
I
.,
..... J.
:
O!.:Tf>UT PDnT
t, INPUT F'OF:T
01H
02H
10H
08H
LD
DUT
~~;
\,
:... ·..•
L. I:
L..D
')LF:r;:::oN 3 .oob
,I__
'·'I
I
·,
...'F:
N:Z.~L1
L..:O
A.MODE
U!...!T
(U~:T).tJ
LD
DEC
L ,. F r~ H
c..
JF:
NZ.L.2
: ;.> (·, :...~ .::: i:;~
:SET USART OPERATION MODE
: F' r'l U:; [ .
.I
I
lJ1
0'1
57
@
--~--------
----· --
--
·-·
------
-
...
----
-----------
z
0
H
r<
N<
.-.
,__,
Hl__.i<C
.ot£: ;:::.
H
!->HLC
~-·
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z<r:
HZ
LLU
(f";
!-
Hl;J
~LL
:----l
>--!
}--
tr)
_..J ::J
~
_.;_
-..!
<C .. _.. _J
__;
:._.:
r. . ~
r...~
__ j
z
.;t_- _j _J
G: ,-._
:c
M
0
~~-
z c
.. !,-.. w.....
!-H
P.I
}- c:
•
< :;.
<C
Z_ P
:--: _j
!f.! ;-
r..~ •
:JLJ
.._ .. LL
.-J -1 ::~ <C
r-
~
0
u
Q
!-
:::tr:z
Z P. -· >=: LLi ::C Z
__ 0
_j ;:::,. - ; H
H
0
-j
OJ
::
0
)--:
l!.l
I
u
t-l~!
..-:t
__j
-·
!.:"") '-' :::;
,...,... -·-j
.. ,-·
:-;
~-
:. .:_: r.: :: w o. (:: .:.
~-=-:: ,__: c-.l c-.;. c-~
:...!~
-·
-~·
.-
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··-··
:,_)
::::!
~..(
Li"~:
Li_
.;
ir;
l.J._
_J
C'; L:J
CD ~ -:--: ('.~
..-.. 0
0 0 .....,.
;T: LLi ~ ::::: ;I(
~: c.~ ~--
i..L!
c--~ ~!
w r..;
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r.r:: i::C o.
.....
~
r...._ r·l~;
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.
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.--;
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L
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w ;::::: c:: ;:c:
cJ t)
_j
c) ---··.
;__;
u_ ~ ;.~~; ........
r--~ ~ ~ ~-.:.:
c-~
:·
cc
, __. --· "-:·::: r··...
<:
.~
u_
:.::-
r·-
-
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--
:..~
..... '
.
.c:.C
L
::=:: <::: co r.::: co
;. -: c r--~ i"· ~ -:-~
r..:~: ;.~~:
;
:··. (}-. :.:::::: ;__: '·' r, -~ <::; ~-=
' ..-::r- ·'
~ -::.;-~ :r·~ ~... -~
·.:
-~ r-~ t'".i !"') r<; r<.:
·J
'r• .
---. () r·-. ::::; 0 Co 0 C• ,-,
C:: .._,
.... c:.: C': r.:; ::::: r.":'.: C:: (") C; C.: .. _. C; 0
:::.::::_ .,_,
r-.
, __. r-. c::
.---. ,_,. .......
c,
:.,_)
c::
C;
C.:
_(;:
C;
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0
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c·:
0
C:::-,:
:.:J
'•,.•'
0
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58
.:::~
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C·~ S:::C
C= C"·~
-.:::: ~::::
7-f
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C;
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w;::c
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1.:
L.:...!
LC .
C:: c.:
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C"'.: C:
C'; ()
L:J C·-!
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C.: C'·.! :=::t
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OC)C;C~
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C.:
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