CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
A DATALINK INTERFACE FOR A
GUIDANCE SYSTEM
A project submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Engineering
by
Donald J. Ruffing
May, 1982
The Project of Donald J. Ruffing is approved:
r. Laurence
s.
g
n
California State University, Northridge
ii
To my wife, Michelle, for her unlimited patience.
iii
TABLE OF CONTENTS
. . . . . . . . . . . . ... . . . . .. . . .............•..
LIST OF FIGURES .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
ABSTRACT . . . . . .. . . .. . . . . . . . . . . . . . . . . . . .. . . .. .. . .. . . . . .
ACKNOWLEDGEMENT
iii
vi
vii
Chapter
I.
II.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
1. System Overview. . . . . .. . . . . . . . . . . . . . . . .. . . ..
2. Inertial-Navigation Unit (INU)
External Interface .. . . . . . . . . . . . . .. . .. .. .
DATALINK MODULE INTERFACE .. . . . . . . . . . . . . . . . . . . .
1. INU Interface . . . . . . . . . . . . . . . . . . . .. . . . . .. .
INTRODUCTION
~
2.
III.
. .. .. . .. . ... . . .. . . . . ... .
MICROPROCESS STRUCTURE
lo
Program lviemory ••••
2.
Data r.-1emory
3.
4.
IV.
Datalink Module Internal Interface
1
1
2
4
4
4
9
••••••••••••••
9
••.•••••••.•••••••••••••••••
10
o ••••• o
•• o
.... . . . . . . .... . . .... .......
Test and Interrupt Inputs .. . . . . . .. . . .. . .. .
DESIGN
. . ... . . .... .. .. . .. .. . . . . . . ...
TOD Interface . . . .. . ... . . . . . . . . . .. . . . . . . . . .
BIT . . . . . . . . . . . . . .. . . . . . .. ·- .. .. . . . . . . . . . . . .
Downlink Interface . . . . .... . . . . . . . . . . . . . . . .
Uplink Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Structure
~
11
13
HARD~lARE
14
1.
14
2.
3.
4.
iv
14
18
19
Page
Chapter
v.
. . .. . . . . . . . . . .. . . . .. . •· . . . . . .
1. Overview . . . . .. . . . .. . . . . .. . . . . . . . . . . . . . . . . . .
Initialization and BIT . .. . . . . . . . . . . . . . . ..
2.
3. DMA Routine . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . .
Downlink Routine . . . . . . . . . . . . . . . . . . . . . . . . .
4.
5 .. Uplink Routine . . . . . . . . . . . . . .. . . . . . . . . . .. . .
MECHANICAL . . . . . . . . . . . .. .. . . . . . . . . . . . . . .. .. . . .
1. Mechanical .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . ..
TESTING . . . . ... . . . . .. . . .. . . . . . . . . . . . . . .. . . . . . . .
1. Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
SUMMARY . . . . . . . . . . . . . . . . . ... . . . . . . . ... . . . . .. . . .
SOFTWARE STRUCTURE
~
~
VI.
VII.
VIII.
1.
REFERENCES
APPENDIX A
APPENDIX B
Summary .•.............•..••.........•.•.••
.... .. . . .. . . . . . . .. . . . . . ... .. . . .. . . ·- .. .... ..
SOFTWARE FLOWCHARTS . . . .. . . . . . . . . . . .. . .. .
SOFTWARE LISTINGS . . . . . . . . . . . . . . . . . . . . . . .
v
24
24
24
27
28
33
35
35
38
38
40
40
41
42
49
LIST OF FIGURES
Chapter II.
2.1
2.2
2.3
INU Structure •••.•••.
Datalink Structure
I/O Assignments
.....
. . .. . . . . .. .
3
7
8
Chapter III.
3.1
Memory
~laps
................................ .
12
..... . ... . .... . .. ....
. .. .
.
.. . . ..
.
.
.
. ... . .
..
.
.
.
.
..
.
.
.
.
.
.. . .. ..
. . . ..
.-
15
16
17
20
21
23
..
25
26
30
31
Chapter IV.
TOD Timing Diagram
TOD Hardware Interface
BIT Timing Diagram
Downlink Interface
Uplink Timing ·Uplink Interface
4.1
4.2
4.3
4.4
4.5
4.6
Chapter
5.1
5.2
5.3
5.4
.-
v.
..... ... . .... . ..
Uplink Flowcharts
Downlink Flov1charts
LC4516 Memory Map
Downlink Frame Cycle Flow
Chapter VI.
6.1
6.2
Power Dissipation
Assembly Drawing
....... . .. . . . . .. ... .... ........
vi
36
37
ABSTRACT
A DATALINK INTERFACE FOR A
GUIDANCE SYSTEM
by
Donald J. Ruffing
Master of Science in Engineering
In this project, a microprocessor based datalink
interface for an Inertial Guidance System is presented.
Work pertaining to this project is associated with a system
done at the Litton Guidance/Control Systems Division in
Woodland Hills, California.
The purpose of the datalink
interface is to process information between the Guidance
System and an aircraft Central Processing System.
The interface is designed around the Intel 8039
Microprocessor.
The project consists of a time of day
interface, built in test functions, uplink interface and a
downlink interface.
The downlink and uplink sections will control the
flow of information to and from the Central Processing
System.
Both interfaces are serial interfaces with the
vii
downlink running at a continuous 50 KHz and the uplink
running at a gated 5 KHz.
The time of day interface is
also serial and is used for synchronization purposes.
The
built in test functions are used to verify proper operation
of the downlink and uplink interfaces.
This report con-
tains the detail design of the hardware and software
structure of the datalink interface.
viii
CHAPTER I
INTRODUCTION
I.l
System Overview
The purpose of an airborne Inertial Navigation
System is to provide the aircraft with position and velocity information as well as attitude and heading references.
The most significant feature of an inertial system is that
it performs these functions without the need for any external inputs.
Gyroscopes and accelerometers are employed to
sense any rotational or linear motion, respectively.
The
linear velocities are integrated to derive position information.
A problem inherent in an inertial system is that
being self-contained, errors tend to build up and, over
time, significantly affect the accuracy of the system.
To
overcome this, the inertial system frequently interfaces
with an external update source such as a radio navigation
network like LORAN or a Doppler radar system which provides
an external ground velocity reference.
Because the iner-
tial system drifts in a bounded mathematically predictable
manner, update corrections can be filtered to provide
smooth and accurate position and velocity information.
1
2
This project deals with a particularly complex update interface between an inertial system and a ground
based tracking station.
In this application, the high
accuracy required of the inertial position and velocity
information necessitated the design of an interface that
would synchronize both airborne and ground tracking systerns.
The interface was also required to provide a con-
tinuous stream of synchronous data to onboard users.
The interface system was designed to be used in an
Inertial Navigation System developed by Litton Guidance
and Control Systems Division of Woodland Hills, California.
I.2
Inertial Navigation Unit (INU)
External Interface
All communication with systems external to the
Inertial Navigation Unit is accomplished via
t~e
aircraft's
Central Processing System {CPS) bus and controlled by the
interface module referred to as the Datalink Module (see
Figure 2.1).
Output data from the Datalink Module is
sent out the CPS bus for both the ground station and the
on-board users.
Input data from the ground station and
Time of Day (TOD) time-synching information is received
by the Datalink Module via the CPS bus.
The Datalink Module is independent from the other
INU modules.
It communicates to the INU Central Processing
Unit (CPU) via the internal INU bus which is controlled by
the I/0 Gontroller Module.
following four functions:
As such it performs the
receives and processes uplink
3
data, transmits downlink data, receives TOD information
and performs Built-in-Test checks.
These functions are
controlled by an Intel 8039 microprocessor except for the
TOD interface which is handled by hardware.
The uplink data is received as a gated burst of
serial data.
This data is processed by the Datalink Module
and stored in the INU Main Memory, then the CPU is notified
of its presence.
The downlink data is read from the INU Main Memory
and transmitted in a continuous serial stream to the CPS.
The TOD data is received as a gated burst of serial
data.
The data is stored in registers where it can be
accessed by the CPU to time tag downlink data, enabling
synchronization with systems external to the INU.
The BIT circuitry exercises and verifies operation
of the uplink and downlink circuitry.
CHAPTER II
DATALINK MODULE INTERFACE
II.l
INU Interface
The datalink interface is located on one of the
ten I/O assemblies of the INU.
The datalink communicates
to the LC4516 CPU which is a Litton built computer designed for the Inertial Navigation application.
Internal
communication to the LC4516 is over a 16 bit I/O data bus.
The data bus is used as an I/O Select for the datalink's
Time of Day interface.
This is the standard form of com-
munication from an I/0 device to the LC4516.
The reference
designation used for the Time of Day interface is I/O
SELECT~~.
The uplink and downlink interfaces, however,
utilize the data bus in a direct memory access capability.
This mode of operation is required because of the required
speed the datalink must operate at.
assigned the name DEV REQ 2.
The datalink has been
Figure 2.1 shows a block
diagram of the INU structure.
II.2
Datalink Module Internal Interface
Communication internal to the Datalink module is
controlled by the Intel 8039 microprocessor.
The 8039
microprocessor was chosen as the datalink's CPU because
4
--·----..--- - ....
...........
r-i
I/0
CONTROLLER
MODULE
~-~
.
,.,.._,~----·-·
- --...-.............,_....... .... ,... __._".........................-
..., . .......
CPU CONTROL LINES
...,.
.........,
LC4516
DATA
BUS
DATA
BUFFER
MODULE
DATAL INK
MODULE
,AIRCRAFT
CPS
.
..]___~
INU
SUPPORT
MODULES
16 BIT DATA BUS
INU STRUCTURE
~--------·--------------·------------------------------------------J
Figure 2.1
INU Structure
t.Jl
6
it is specifically designed for high speed controller
applications.
The 8039 processor contains the following functions
in a single 40 pin package:
8-Bit CPU, 128 by 8 RAM Data
Memory, 27 I/O Lines and a 8-Bit Timer/Event Counter.
A
2.5 microsecond cycle time and a repertoire of over 90
instructions.
Each of the instructions consists of either
one or two cycles, making the single chip 8039 equal in
performance to most presently available multi-chip processors.
The 8039 provides an instruction set which allows
the user to directly set and reset individual lines within
its I/0 ports as well as test individual bits within the
accumulator.
A large variety of branch and table look-up
instructions makes this processor very efficient in implementing standard logic functions.
has been given to code efficiency.
Also, special attention
Over 70% of the
instructions are a single byte long and all others are
only two bytes long.
Thus many functions requiring up to
4K bytes in other processors can be compressed into 2K
equivalent bytes using the 8039 processor.
The uplink channel interfaces with the 8039 using
the processor's data bus.
Communication to the LC4516 is
done through the data bus as well as Port 1 to provide the
16 bit interface capability.
Port 2 provides the I/O
assignments as well as the upper address bits to the
memory.
Port 2.
Figure 2.3 lists the I/O assignments decoded from
r - - -..
UPLINK CLOCK
UPLINK DATA
-·~-·
1--
UPLINK
-INTER. - FACE
l
. - EPROM
1--
1--
BIT
LOGIC
8039
CPU
I-.
-
I
~DDRESS 1--
LATCH
16 BIT
DATA
LATCH
DMA
DECODE
LC4516
DATA BUS
!
fl-6 BIT
1--
TOD DATA
TOD GATE
1
1-
1--
TOD CLOCK
TOD
INTERFACE
LC4516
CONTROL
LINES
~---
~-r-
I
~o-ONTROT
...........
DOWNLINK
....-- INTERFACE
'-
-·
DOWNLINK
CLOCK
DOWNLINK
DATA
1 -...__LOGIC
.
Figure 2.2
Datalink Structure
"
8
Input
Strobe
Purpose
Input
Strobe
Purpose
lYO
Frame Syncing
2YO
Loads DMA Data
lYl
Uplink 1st Half
2Yl
Loads DMA Address
1Y2
Uplink 2nd Half
2Y2
Uplink
1Y3
Uplink Reset
2Y3
BIT Strobe
Figure 2.3
Acknowledg~
I/.0 Assignments
The interrupt capability of the 8039 is used to
accommodate the downlink channel.
During normal operation
the downlink will interrupt the 8039 every 330 microseconds
to request another data word to be sent to the CPS.
Because of this fast interrupt rate, the 8039 is operated
at 6.0 MHz to provide the 2.5 microsecond cycle time.
At
this rate no software duty cycle problems are encountered.
Figure 2.2 shows the structure of the datalink module.
CHAPTER III
MICROPROCESS STRUCTURE
III.l
Program Memory
Program memory consists of 2048 words eight bits
wide which are addressed by the program counter.
The pro-
gram is stored in an erasable EPROM and is accessed by the
8039 by its 8-bit bus.
There are three locations in
Program Memory of special importance.
Location 0:
Activating the reset line of the
processor causes the first instruction
to be fetched from location 0.
Location 3:
Activating the interrupt line of the
processor (if interrupt is enabled)
causes a jump to subroutine at
location 3.
Location 7:
A timer/counter
inter~upt
resulting
from timer/counter overflow (if
enabled) causes a jump to subroutine
at location 7.
Therefore, the first instruction to be executed
after initialization is stored in location 0.
The first
word of an external interrupt service subroutine is
9
10
stored in location 3 and the first word of a timer/counter
service routine is stored in location 7.
Program memory
can be used to store constants as well as program
instruc~
tions.
III.2
Data Memory
Data memory of the 8039 microprocessor is organized
as 128 words 8-bits wide.
All locations are indirectly
addressable through either of two RAM Pointer Registers
which reside at address 0 and 1 of the register array.
In
addition, the first 8 locations (0-7) of the array are
designated as working registers and are directly addressable by several instructions.
Since these registers are
more easily addressed, they are usually used to store
frequently accessed intermediate results.
By executing a Register Bank Switch instruction RAM
locations 24-31 are designated as the working registers in
place of location 0-7 and are then directly addressable.
This second bank of working registers is reserved for use
during the downlink interrupt service routine.
This bank
switching allows the registers of Bank 0 used in the main
uplink program to be instantly "saved" by a bank switch.
Since the two RAM Pointer Registers RO and Rl are a part
of the working register array, bank switching effectively
creates two more pointer registers (RO' and Rl') which
can be used with RO and Rl to easily access up to four
separate working areas in RAM at one time.
11
RAM locations 8 through 23 contain the program
counter stack.
An interrupt or Call to a subroutine causes
the contents of the program counter to be stored in one of
the 8 register pairs on the Program Counter Stack.
The
pair to be used is determined by a 3-bit stack pointer
which is part of the Program Status Word (PSW).
The stack
pointer when initialized to 000 points to RAM locations 8
and 9.
The first subroutine jump or interrupt results in
the program counter contents being transferred to locations
8 and 9 of the RAM array.
The stack pointer is then incre-
mented by one to point to locations 10 and 11 in anticipation of another Call.
Nesting of subroutines within
subroutines can continue up to 8 times without overflowing
the stack.
The Program Memory and Data Memory Maps are
shown in Figure 3.1.
III.3
Port Structure
Ports 1 and 2 are each 8 bits wide and have identi-
cal characteristics.
Data written to these ports is
statically latched and remains unchanged until rewritten.
As input ports these lines are non-latching, i.e., inputs
must be present until read by an input instruction.
The lines of ports 1 and 2 are called guasibidirectional because of a special output circuit structure which
allows each line to serve as an input, an output, or both
even though outputs are statically latched.
This struc-
ture allows input and output on the same pin and also
2047
<:
128
I
USEH RAM
t
32
. r- OPERA'l'IONAL '
31
PROGRAM
7
-
WCA'l'ION 7-TIMER
r-
INmRRUP'l' VECIORS
PIUiHAM ~liRE
WCATION 3-EX'l'ERNAL
3
0
~
'-
ADD HESS
24
23
tl
7
INl'EHHUPT VEX::'IORS
P~
HERE
RFSE.'l' VECIORS
Pla3RJ\M HERE
0
~
BANK 1 W:)RKING
RF.GI S'I'EHS
-~-------
HO'
I
DIRECTLY ADDRESSABLE \VIIEN BANK 1
IS SELEX..'l'ED
(
I ADDRESSED INDIR&.'"'I'LY
'lliiWQI Rl oa: RO or
8 LE.\1EL S'l'ACK
BANK 0 OORKING
RffiiSTERS
-------Rl
-- - RO- - - -·
PROGRAM MEMORY MAP
(R0 1 or Rl')
'DIHECI'LY ADDRESSI
ABLE WilEN BANK 0
IS SELEX::l'ED
DATA MEMORY MAP
Figua:e 3.1
.Memory Maps
I-'
N
13
allows a mix of input lines and output lines on the same
port.
The quasibidirectional port in combination with the
ANL and ORL logical instructions provide an efficient means
for handling single line inputs and outputs within the 8039
processor.
The bus is also an 8-bit port which is a true bidirectional port with associated input and output strobes.
If the bidirectional feature is not needed, the bus can
serve as either a statically latched output port or nonlatching input port.
Input and output lines on this port
cannot be mixed however.
III.4
Test and Interrupt Inputs
Three piris serve as inputs and are testable with the
conditional jump instructions.
These are TO, Tl and INT.
These pins allow inputs to cause program branches without
the necessity to load an input port into the accumulattir.
CHAPTER IV
HARmvARE DESIGN
IV.l
TOD Interface
The Datalink will accept a TOD interface.
This
interface consists of 16 data bits transmitted serially
at a 2.5 Megabit rate.
An Update Time Gate is provided
during the data transfer.
The gating signal is high
beginning l/2 clock period before data transfer begins and
remains high until data transfer is complete.
Figure 4.1
shows the TOD timing interface.
The Datalink accepts the above 16 data bits and
latches them until the INU computer requests the data.
To
accomplish this task, two 8 bit serial to parallel chips
and two octal latches were utilized.
The INU computer re-
quests the latched TOD data by an I/O Select Discrete
available from its I/O interface.
Figure 4.2 shows the
block diagram of the TOD interface.
IV.2
BIT
The BIT circuitry checks the uplink and downlink
channels for proper orientation.
This is achieved by
having the datalink write a 16 bit test word into the main
memory of the INU via DMA.
The datalink will then read
14
15
Update Time Gate
)
l
TOD Clock
TOD Data
Figure 4.1
TOD Timing Diagram
the test word (again using DMA) into the downlink channel.
During BIT the logic will be set to direct the downlink
channel into the uplink channel, therefore the test word
will become available at the uplink port of the datalink.
If the test word and uplink word just received match the
uplink and downlink, interfaces are operating correctly.
If the two words do not match, a failure has been detected
and the datalink will inform the INU via DMA.
informs the necessary I/0.
done only at turn-on.
The INU then
This test is a one shot test
Figure 4.3 shows the timing diagram
for the BIT.
The datalink initiates the BIT by outputing a
strobe on 2Y3.
Thi~·
strobe is sent by the 8039 and is
used to activate the BIT flip-flop.
During the next
shift/load pulse, the discrete BIT becomes active and
directs the uplink multiplexers to use the downlink
channel.
At this time, the 8039 waits until all 16 bits
of the test word have been latched.
When the test word is
available, the 8039 then compares the word to the
word it wrote into the INU's memory.
o~iginal
The 8039 then sets
TOD CLOCK
TOD DATA
TOD GATE
8-BIT
CLOCK
BUFFER
LINE
DATA
RECEIVGATE
ERS
8-BIT
TRISTATE
LATCH
I
',
LC4516
16 BIT
DATA BUS
I
f-
a~BIT
~
BUFFER
8-BIT
TRISTATE
LATCH
I
'
,y
I
I/0 SELECT
LC4516
READ
STROBE
I/0
DECODE
LOGIC
Figure 4.2
TOD Hardware Interface
I-'
0)
Downlink Clock
Strobe 2Y3
Shift/Load Pulse
JUlJll~ ~u-·i_h_JlJl_
u
u·
l
?~
BIT Discrete
l
;t
Downlink Data
){)()<]
0
I
1
Figure 4.3
0
J
·u
{
L_l
~
~ 1 [XS< 'X<S<,'')('
BIT Timing Diagram
1-'
--.]
18
the required pass/fail flags.
BIT is then turned off by
having the datalink send another strobe out on 2Y3.
If a
failure was detected, the datalink will still attempt to
continue with normal operation.
It is the responsibility
of the INU to either turn the datalink off or to inform
the required I/0 of a datalink failure.
IV.3
Downlink Interface
A downlink channel is provided to supply the CPS
with aircraft position, altitude, velocity, time data, and
standard navigation data.
The purpose of this data is to
augment Kalman filtering at the CPS and to provide
steering/synchronization information, INU status, time
tags, command echo and various ancillary navigation data
for use at the CPS.
Downlink data is:transmitted as a continuous succession of frames.
There will be five frames with fifty-six
17 Bit words per frame.
These frames are transmitted at a
rate of 52.5 frames per second and a bit rate of 50 KBPS.
Bit and frame timing are achieved by synchronizing the output data signals to the 50 KHz clock signal supplied to the
INU from the CPS.
The downlink design is responsible for maintaining
the 50 KBPS data output with no gaps to insure synchronization.
Also since all the words in the frame have been
set, the downlink must keep track of what information is
being sent out to insure proper data exchange.
19
As shown in Figure 4.4, the downlink interface
interrupts the 8039 CPU to request a new downlink word.
This interrupt is transmitted at every downlink word,
therefore it will come every 340 microseconds.
The format
for each word is 16 bits of data followed by the parity
bit.
Parity is defined as odd parity and is generated by
two 8-bit parity generators provided in the hardware.
At
the time of the interrupt, the 8039 CPU must issue a DMA
request to the LC4516.
The LC4516 then sends the next
16 bit downlink word to the downlink interface.
This word
is then latched, parity is determined, and then the word
is sent out serially through line drivers.
IV.4
Uplink Interface
An uplink data channel is provided to interface
with the CPS.
The uplink message formats will consist of
a continuous stream of 128 bit messages.
accompanied by a 5 KBPS gated clock.
messages can be sent via the
uplin~
Each message is
Six different
channel.
Figure 4.5
shows the timing for the uplink interface.
Data transmitted to the datalink by this channel
is verified within the datalink by a comparison of double
messages sent from the CPS.
This means that any 128 bit
message that is transmitted up to the datalink will be
followed by the exact same message in the succeeding
frame.
The datalink is responsible for determining if
there is a failure and informing the CPS of any failure
20
I
I
DMA
·cONTROL
LOGIC
8039
..:;,.
"""'
F
LC4 516 DMA
CON TROL LINES
CPU
DMA
READ
ACK
-
~
INI'ERRUP£.
rDOWNLINK (
COUNTER j
..:.I S/L PULSE
PARITY
jGENERATOR
8-BIT i
I
LC4516
16 BIT
DA'I'A
BUS
·-
~
!
LATCHJ
DMA
'>READ
1
ACK
I
h
I
~
;----
-
I
8-BIT
LATCH
J
I
PARITY
GENERATOR
8-BIT
1-- PARALLEL
~
TO
SE~2AL
S/L PULSE
-
CPS
DO';VNLINK
CLOCK
1
LINE
RECEIVER
J
8-BIT
PARALLEL
TO
1' - - SERIAL
'--
_I.e_
JI DRIVER
LINE
Figure 4.4
Downlink Interface
J
----7
CPS
omvNLHlK
. DATA
21
Clock-SKBPS
!!!IIIII
1111111
111111111
I Frame
Data
L-----1
Figure 4.5
Uplink Timing
by the downlink interface.
Parity codes are also provided with each uplink
message.
After the datalink has verified the double
message comparison, the parity is verified to insure the
message as formatted and transmitted contains no errors.
If both of these tests are valid, the datalink must then
DMA to the main memory of the INU, the uplink data and
alert the INU that valid uplink data is available.
The uplink channel flags the 8039 CPU when a message
is sent by the CPS by using the TO and Tl input pins available on the 8039.
Testing the TO input pin will inform the
8039 if a message is being sent up.
If TO is set, the 8039
will begin execution of the main uplink program.
If TO is
not set, the 8039 will continue to loop and check TO.
The
input pin Tl is set by a flip-flop in the uplink hardware
every 16 bits.
At the 16th bit of the uplink serial data,
the 8039 inputs 16 bits of latched uplink data.
Once the
data is brought into the processor, the Tl flip-flop is
reset and the 8039 waits for the next 16 bits of data to
come in.
After Tl has been set 8 times, all 128 bits of
the uplink message have been stored and the uplink
22
processing begins.
Figure 4.6 shows the block diagram of
the uplink interface.
SERIAL
TO
PARALLEL · - IC
8-BIT
TRISTATE
LATCH
I
8-BIT
TRISTATE
LATCH
SERIAL
TO
PARALLEL
IC
1--
BUS
:--
8039
CPU
Tl
TO
,,
UPLINK DATA
UPLINK CLOCK
r--
LINE
RECEIVERS
4 BIT
COUNTER
Figure 4.6
Uplink Interface
N
w
CHAPTER V
SOFTWARE STRUCTURE
V.l
Overview
Figures 5.1 and 5.2 show the general flowchart out-
line of the datalink program.
Detailed flowcharts are
located in Appendix A and the datalink listing is located
in Appendix B.
Similar to the hardware structure, the
software can be broken up into the Initialization and BIT
routines, the DMA routines, and the downlink and uplink
routines.
V.2
Initialization and BIT
During initialization, the program loads the required
constants into the interrupt register bank RBl and the uplink program register bank RBO.
The routine also sets the
required constants in the data memory.
A software flag FO
is also cleared during initialization.
This flag is checked
during the DMA routine to determine whether a DMA Read or
DMA Write was requested.
with the BIT program.
The processor then proceeds on
The BIT routine begins by setting
up a DMA Write to the LC4516.
This consists of writing a
16-bit test pattern of 0101010101010101 into the LC4516
memory location 56376 •
8
The routine then requests a DMA
24
RESEr UPLINK erRS
Figure 5.1
Uplink Flowchart
N
lJl
y
INITIALIZE <..'TR
I sn~o
SYNC Pl.iLSE
[
~
Y
·---
~:~moc=
~/
L45l6CPU
N
t'igure 5. 2
Downlink Flowchart
N
0'\
27
Read from the same memory location.
This action loads the
test pattern into the downlink hardware buffers.
A strobe
defined as 2Y3 is then issued by the program to initiate
the hardware BIT functions.
A delay routine is then execut-
ed to give the hardware time to begin serially shifting the
test pattern into the uplink channel.
During this time the
program verifies the input pin Tl is set.
If it is set,
the program waits for the input pin TO to be set which
indicates all 16 bits have been latched.
If Tl was not
set, this implies a hardware failure since a clock should
have been present during this time.
The failure flag is
then set in a data memory location.
If no failure was
registered, the program verifies the test pattern is identical to the one it sent to the LC4516.
If the patterns do
not match, the same failure flag is set in data memory.
BIT is then turned off by issuing another strobe on 2Y3.
The uplink flag TO is then reset, the downlink interrupt is
enabled and the program begins execution of the main uplink
program.
V.3
DMA Routine
This routine provides the main line of communication
between the datalink and the LC4516.
A block of memory in
the LC4516 has been allocated for use by the datalink.
This block begins at location 56000
long.
and is 256 locations
8
The low order 8 bits of the DMA address therefore
must be set for every DMA.
The high order 8 bits are
28
never altered and are set in the hardware.
This routine
is only used in a subroutine fashion.
When called the routine sets Port 2
the write discrete is cleared.
to
0 to verify
The program then checks
flag FO to determine whether a DMA Write or Read has been
requested.
If a write was requested, 16 bits of data from
registers R6 and R7 are loaded into the hardware data
registers and the write discrete in Port 2 is set.
If FO
was not set, the program loops over the loading of the data
register section.
The 8-bit address is then loaded into
the hardware latch and a DMA is requested by sending a
strobe out on Port 2 to activate the DEV REQ #2 signal to
the LC4516.
FO and Port 2, except for the write discrete,
are then cleared and the subroutine returns to the main
program.
The reason for not clearing the write discrete
is because the LC4516 may delay in acknowledging the DMA
request.
If this occurs and the discrete was cleared, a
DMA Write request would be issued as a read request.
V.4
Downlink Routine
The downlink routine is responsible for three main
functions.
First it must keep track of what frame it is
sending to the CPS.
This will determine the location in
the LC4516 memory it has to request a DMA Read.
Secondly
the routine pulls the uplink flag word to see if an uplink
message has been sent to the datalink.
If one has, it has
the task of sending the entire message, plus status flags,
29
to the LC4516 via DMA.
Thirdly all communication to the
LC4516 is controlled by the downlink.
This involves pack-
ing various status words with software flags and sending
the words to the LC4516 at the correct times.
As stated previously, there are five frames of data
that are sent to the CPS.
The first 44 words are common
to each frame and the last 12 words contain various data
depending on the frame number.
Because of this format, the
following memory map shown in Figure 5.3 was formed in the
LC4516 memory.
The memory allocation is broken up into two identical
buffers labeled Buffer A and Buffer B.
The reason for
having two buffers is the requirement that each frame contains data that is correlated and time tagged.
The LC4516
will therefore be loading one buffer with information
while the datalink will be sending the other buffer down to
the CPS.
This flow of frame cycles is shown in Figure 5.4.
As shown on the figure, the datalink must inhibit the
LC4516 from loading the next buffer just before the crossover into the next frame.
This is required to prevent any
overlap of "fresh" and "old" data generated in the INU.
A
status word sent by the downlink informs the LC4516 when to
inhibit loading.
The status word also tells the LC4516
what buffer it should be loading to maintain synchronization.
The downlink routine is executed once an interrupt
occurs.
Its first task is to save the accumulator and
30
LC4516 Hemory
Location (Base 8)
Purpose
56000
56200~
56053
56054
56254 (~~-- Not used
First 44 words of all frames
56253~
56057
56060
56257
56073
56074
56273
56274
56077
56100
56300~
Last 12 words of frame 1
56260~·
~
+-r-- Not
used
56277<._j
Last 12 words of frame 2
56313~
56113
56114
56314
56117
56120
56317 ~
56320 ~Last 12 words of frame 3
56133
56134
56333
56334
56137
56140
56340
56153
56154
56354
56157
56160
56357
56360
56157
56174
56175
56176
56177
56373 ~
56374 V,
56375 ~
56376 ( j
56377 ~
BUFFER A
<t-r- Not
~
~Not
used
used
56337~
T-- Last
56353~
~
~
12 words of frame 4
Not used
.
T-
Last 12 words of frame 5
Not used
·Software status words
BUFFER B
Figure 5.3
LC4516 Memory Map
Downlink
Frame Cycle
I
Frame 4-- Frame 5
.II'
.lj\
~ame_l
I'
I\
( Frame 2
.li\
I'
l_~E_ame_}_l
.lr"o
I
~
Frame 4
I 1\.
IFrame
/'
5
Ji'
Datalink Flags LC4516
To Inhibit Loading
LC4516 Loads Buffer A
LC4516 Loads Buffer B
""'
Datalink Reads Buffer
(Outputs Frame 1)
A
Datalink Reads Buffer
(Outputs Frame 2}
B
Datalink Reads Buffer
(Outputs Frame 3)
A
-----
Figure 5.4
I
I'
------
Downlink Frame Cycle Flow
w
I-'
32
switch to Register Bank 1 so it will not disturb the
uplink routine.
The routine then generates a DMA request
to output the next downlink word.
by the downlink address counter.
This word is determined
At this point, several
decisions are executed to find out where the downlink is
at in the five frames.
If the routine is not at a critical
point, it simply increments the downlink address counter,
restores the necessary locations and exits the routine.
If a critical point is reached, there are five possible
routines that can be executed.
If the downlink address counter is on the 44th word,
this counter is changed to match the next location as
listed previously in LC4516 Memory Map.
A decision is
also made to determine if we are in frame 1.
This is re-
quired because the uplink message is echoed back to the
CPS for BIT purposes.
Since the uplink message is always
sent to Buffer B, the downlink address counter may be
modified to output the next 12 downlink words from Buffer
B.
This does not affect the loading of the buffers by the
LC4516 since these locations are never-written into by the
LC4516.
The next critical path occurs at the end of a frame.
At the end of frame 1, the downlink address counter must
point back to the proper buffer since it may have been
modified due to the requirement of echoing back the uplink
data.
The routine also sends a status word to the LC4516
to inform it what buffer it should be loading next.
33
The third critical point occurs at the start of any
frame.
At this point, a sync pulse is sent out on Port 2.
This pulse is used for hardware synchronization for testing
the datalink assembly.
The next critical point occurs when an uplink message is ready to be sent to the LC4516.
For an uplink
message to be sent, the uplink program must have set the
uplink flag which insures all eight words are present and
the status of the words is known.
This routine then begins
to transmit the message to the-LC4516 through the use of
direct memory access.
After all nine words are sent (8
data words and 1 status word) the routine informs the LC4516
whether the uplink message was valid.
The last critical path occurs when the address counter reaches the 43rd word of any frame.
When this point is
reached, the datalink sends a frame sync word to the LC4516.
This frame sync word contains the frame number and an alternating barker code which provides synchronization for the
CPS.
V.S
Uplink Routine
The uplink routine is responsible for bringing in all
uplink messages, performing the required BIT and then informing the downlink routine that a message is present.
This routine is continually checking for a message by
monitoring the processor input flags TO and Tl.
Once a
message is sensed, it verifies all 128 bits are sent and
34
checks to verify the data was not all zeroes.
If any of
these conditions are present, the routine resets all
necessary counters and flags used for uplink processing.
It then ignores the data and begins checking for another
message.
When a full non-zero 128 bit message is received,
the routine verifies the next message is identical to the
message it just received.
This is required since the CPS
will transmit all messages twice in successive messages.
Depending on the outcome of this comparison, a status bit
is set in the uplink status word.
If the comparison was
valid, parity is then determined on the message.
The CPS
has also determined the parity and has set the 128th bit of
the message to indicate even parity.
If the parity com-
parison is identical, a valid uplink message was received
and the uplink routine sets the parity status bit in the
uplink status word.
The uplink then stores the eight up-
link words and one status word in the data memory of the
8039 and sets a valid uplink flag which is picked up by the
downlink routine at the proper time.
CHAPTER VI
MECHANICAL
VI.l
Mechanical
The datalink module was designed to be installed in
one of the spare input/output slots of the guidance system.
This requirement implied the design must be implemented on
a general purpose printed circuit (PC) board designed
uniquely for the guidance system.
This PC board is a
fiberglass board with an aluminum core which is used for
heatsinking and stress purposes.
The PC board is 5 by 6
inches and can handle up to sixty 14 or 16 pin flatpack
chips.
In the datalink design, flatpack as well as dual-in-
line chips were used.
provided on the board.
Etch for power and ground is also
Figure 6.2 shows the layout of the
datalink module and the chips utilized.
The EPROM was
placed on a socket to allow for easy removal when the
operating software was altered during integration phases.
This type of PC board requires no more than 8 watts
of dissipated power per board.
Figure 6.1 lists the chips
used with their typical power dissipation.
The total
number of 7.06 watts is well within the acceptable limits.
35
COMPONENT
QTY
54LS113
54LS175
54LS161
5450
54LS164
54LS374
54LS123
54LS04
54LS03
54LS10
54LS08
8039
54LS139
82S191
54180
54166
9615
9614
54LSOO
4
1
2
1
2
11
1
5
1
1
1
1
1
1
2
2
3
1
1
POWER DISSIPATION
10
55
93
14
80
175
60
2
2
2
4.25
1500
34
875
170
360
250
250
2
TOTAL IC DISSIPATION
mvJ/FF
mvJ
mw
mW/gate
mW
mW
rnw
rnW/gate
rnW/gate
rnW/gate
rnW/gate
rn\lil
rnw
rnW
rnvv
rnvJ
rnw
rnW
rnW/gate
80
55
186
28
160
1925
60
60
6
6
17
1500
34
875
340
720
750
250
8
mw
mvJ
mw
mw
rnW
rnw
rnw
mW
rn~v
rnw
rn~v
rnw
rnw
rnW
rnw
rn~v
rnW
rnw
rnw
TOTAL POWER DISSIPATION 7.06 WATTS
Figure 6.1
Power Dissipation
w
"'
.,.,
37
~
C!JL!J
I~
~--~
I ~I
~
~
~
I JlJ'TO .,
en
•;
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~,
J
1o·t
g
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I
L:..J
CHAPTER VII
TESTING
VII.l
Testing
Since the datalink module is a unique design, a
tester had to be designed to verify the datalink's operation.
The tester basically had to emulate the functions
of the CPS since this is the only system (outside the INU}
the datalink communicates with.
The tester performs three main functions.
First,
the tester must capture and display any word in any of the
five downlink frame cycles.
For this function, the opera-
tor must insert the frame number and the number of the
word in the frame.
The data is then displayed in a LED
display and refreshed continually.
The second function of
the tester is that it must be capable of sending uplink
messages to the datalink.
Again, the operator must enter
the uplink data through the keypad.
Once the data is
entered, the entire message will be displayed on the LED
display.
The operator then has the option of rejecting or
accepting the message.
Once the message is accepted, the
data is sent to the datalink module in the uplink message
format.
The last function calls for the tester sending
the TOD interface signals.
These interface signals contain
38
39
a predetermined message that is continually sent to the
datalink assembly.
In all three functions it is up to the operator to
verify proper operation.
The datalink tester just performs
the operator's wishes and in no way verifies the resulting
actions were done properly.
CHAPTER VIII
SUMMARY
VIII.l
Summary
The datalink module was designed, built and tested
at the Litton Guidance/Control Systems Division in Woodland
Hills, California.
The datalink module met all initial
requirements and was integrated successfully into an
inertial guidance system.
Extensive testing of the guidance
system in a flight test environment is currently under way.
Preliminary flight test results have shown the datalink
design concept functional and sound.
The module is now
being evaluated for productionization with minor hardware
modifications.
40
REFERENCES
1.
MCS-4~,
2.
TTL Databook, 1979
1979
MCS-48 Users Manual.
Corporation, 1979.
USA:
Intel
TTL Databook. USA: National
Semiconductor Corporation, 1979.
41
APPENDIX A
SOFTWARE FLOWCHARTS
42
SE'£
SE'r
SET
SE'I'
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,.
SE'l'
SET
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SE'£
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SE'l'
SE'I'
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HO TO 00111
I
Hl '1'0 BOll
R2 TO 09H
R3 '1'0 02llJ
H6 TO FFH
I
~~~~-~~r.·~~-~l-.Vnl wA
I
I
/
LIN!\
-......
N
vV
It
N
1
H30
M31
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M43
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'1'0
'I'O
'£0
'1'0
TO
'1'0
'£0
TO
'1'0
OOH
OOH
ril-lAVAILABLE
UPLINK 1\Dlill ISI
SO GO
00111
2lll
GEi' l'l'
20H
1011
3011
02H
OOH
-I
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!
[SEr Rl ·ro 21H I
1----
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0
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LA'l'Cli '£0 BY
SE1'l'ING 2Y2
~
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JUMP 'lU ~lAIN
UPLINK Pl~RN1
~~N~--~----------~
~
~ur~~
SE:r FAIL FLAG
BI'£ 4 IN M61
----·--·w
"""
44
D~1A
CLEAR PORT 2
R
__
MOVE DATA MSH TO Pl ...
SET WRITE DISCREI'E
AT PORT 2
CLR P2 EXCEPT
FOR l!ffi!TE DISCRETE
COMPARE HSH
'1'0 HSII OF
FHANE 1
7
Clll:X::K B4 'IO SEE
IF IJ\S'l' UPLINK
\'lAS USED
00 HA'I'CH SO SE'I'
B4 OF M60 .AND
CLR B6
OF MSO
.t:>Ul
3
.JL.<"
FHN·~>
-~··JP~E
.-
CHECK PARITY
OF ENTIRE
FRAME
SE'f WOHD CTR
BACK 'I'O 7
>INI'I'IA'l'E UPLINK
JW! AOR POIN'l'ER
sE." ..,:., ern
J
P.ACK 'l.D 7
w,_, _ _ ,.., _ _
I
[
DECRElviBN~
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..:::J
[_
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...
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UPL[NK GIECK )
"""
0'1
SINCE '11lliHE \i!\S
NO UPLINI\ DA'rA
y
5
Il-IA Fil\G WOrm
'10 4516 '1\1 INDICATE VALID DA'l'A
3
)
( 4
,!:>.
-....]
G)
GEl' '11 IE FRAME
SYNC 1-Dlill (HSH)
SEND Ol!'l' A
l!lu~MAHE SYNC
PULSE VIA POffi' 2
S.E.T Tilli MSI3 Or~
'!HE D. L. ADDHESS
'1'0 "1" SO IT WILL
BE ECHOED BliCK
,j::.
co
APPENDIX B
SOFTWARE LISTING
49
50
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l•hj'J ·~F.:t), ll•)tE!H
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l·ltY·l Ri, li21H
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tj(•.:.H (5
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1131
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10-'11:14
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, THIS IS fHE BIT SEC.f!O:•N •JF THE PROGI':t'tl'l. IT lHLL WRITE r'<
TEST W(oF.J• T•:O 1-ltHN I-IEI·I(oF·',' THEil fi 1-HLL REAL• THE ~lOR!i Bfi(
IT !~ILL fH!:N SENC' fHE 1-JOH, •)IJ T THE C•Ot-JNLl Nk CHHNNEL FIN[•
52
LO:tO:.
·::OUF:O:E STAT£1'1EU r
OBJ
lo:O::<
. BF:rtl•~ IT 811.:1: IN THP(II_hjH THE UPLIIJV CHt1NI·IEL.
. BE [•o)NE o)IJL'•' t1T TIJHJ (oi-J.
J. J.o:•
1.11
11.2
E:UlLT fN TEST
1•:010:
THIS fEST t·
112
!JA
, SETUP [•1'111
11'3
•JIEE 8(2(.
t:u)..J(t E:Et1t1
•)(t•J.2 E•Ft1t1
•on)-4·1 '34 ::::
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,
t)(t49
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O:n:t•IF EE4t1
t)(t51 EE:01
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ll~
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11:3
119
1..2•:i
1..21
1..22
1..2.:
1..24
125
1.215
1•1(1'•/ R·L 11.2CH
l·l(t\•' p.;... I! TESHl[,
1•10'.,' Ri'. I! TESft.l[•
, LOt1C• TEST l·KIP(• fl(,[.•F.'ESS
, L•)t1[, [•r'!Tft HSB
, LOt1[, (.•ftTr1 L::.s
O:.t1LL [•(tl•lt1
CPL F•:•
CALL (.o(ol•lt1
, WRITE
1·1ov 11.. lHWu'T'.::.
•:OIJ TL P.2, ft
I·IOV: : •~F.:€1, H
NOV ft, lt05H
1.2 i (•ELH'T' :
I·I•W f<·.:;. II•NAH
1.2::. [JELt1'•' 1. [J.JrJ.: F.·.:: .. [•ELH'•' 1
[.o£(. H
12::"
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1-'-'''
t·IOV f1, II fl.J(t'T' .2
El
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1.:2
NOV:·: o!'RO .. ft
E:
, REriu
.. rtHTBIT
. STr'!F.:T (;ELA'T' •)F .2. 5 MSEC.
, CLEt1R (oUT THE UPLINk LATCH Tt3
E4
(II~~·=·
.:;:.;.~H-
E5 l·Jt'tfT.
t.:.::
t:i(t')E'
.2.:10
Ei
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I:U:f.:-(1
:t=t
E::-<
•:00.::1
8(1
1'101/:-: H.• ·~R•:O
o:PL t1
::PL H.· IITESHJ[•
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1·~:
144
I·K•V t't .. it0:•NE'•'2
OIJTL P2.. H
145
H•jV: : t1, •!oPt)
Ht:>
CPL t1
Hi
14>0:
: :RL t1, lHESTWu
14::"
JN.2 Ft1L f.l
15•:0 8! TOFF . NOV t'f, lt(•o.;H
151 [•ELI1'•'.2. I·IOV F:t;, 110(:3H
15.2 C•ELt1'r'.:.. [•.m-.:: i':t., (,ELt1'T'.:;
15:.
vEC Ft
.m: C•ELt1Y2
!54
I·IOV t'!, IHI~OY3.
!55
O:•U TL P .~, ft
1515
15;'
~IOV: : •!F.:t;t, t1
HOI/ t1. iHWOY 2
158
o)IJTL P2 .. t1
159
r·rov:.; •.!'!<'.:•, t=t
lt.t.J
EN !
lbl
JI'IP (.HE•:!(
1.;.::
t:'n)5H ..J0::2.·1
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•.:.'•~.::~ %84
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·:·~2 .24(113
14•)
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14.2
.JNT! FftL f4
JNT•:t l~ftfT
. I.IFL!Nh CLOO< STOP, Tl=>:t
.t~t1fT FOP UFLHII< ~IO!<:IJ
I'I•JV 11.. ltONE'•'l
•)IJ FL P2, r'!
. !NPU r IJPU m.~ NSH
o:.uu:r;
, IS !T THE TEST 140Ru
. LNPIJ f IJPL I Nl. SECONu HALF
• 11[•[•
THE I:OELt1Y FOR THE BIT
, TUF.:t·J O:•FF BIT
Ht1S STOPPEr
53
LOC
t~>-J>:N B~Et>
o'.II)Bt;
F•J
•)•)8i" 4.li0
lftt89
SOURCE STATEMENT
OBJ
~
•:JUSA oHiO
lti:
1ti4 FHL.f4.
MOV RI3.11RE6bi
165
1156
110Y A, o;Re
lei
~~)II •~Rt),
:L.;a
l.69
:Lie
JHP BlTt)FF
; SET BIT FAIL RbL B4
ORL A, itiaH
fl
iii
17.2
17Z CHECK:
174
JTI3 tJPLINI<
, IF UPLINK RIJ'r' •:JO TO UPLINk:
,I.Jf1..!Nt, 15 REAIJY IF TO IS HIGH
:L7c
JTi CHECI--:
, IF Cl.OCI-: 15 ON LOOP TILl. UPLINK REMIJY
177
178
I'IOV A, FLHtil
JB5 CHECK
, SET FLi10 B5 IF COUNTER Ht1S
li9
ORL fl, 1113.2t)H
~1011 FLMGL tl
JTe UPLINk:
1".011 A, Rt:>
:<RL H. II•J7H
175
010.2 5bOO
8104 FF
•.U05 B.200
•Hl:ii 43.29
0189 t1F
.:lii)A .l61Z
l:liOC FE
l:liw r:.ze7
189
18:1
18.2
i8.l
184
O:L•3f' c.;oo ·
185
180
187
188
JZCHECk:
Oili .24iU
189
JNP CLRCTR
BEEt~
, WHS UPLINk: COMPLETE BEFORE CLOCk: STOP
;TEST WORIJ COl~TER
, IF A FULL FRAME WttS NOT
, RECEIVE[), CLEAR WORIJ COUNTF.R fiNCo
,SENIJ A NESSttGE ERROR TO
, t>OWNLINK
, FULL FRAME GO TO OCVCLE.
l.9t)
Oiil FF
.-.u4 •s:r:.F
>3ii6 t1F
o3lli .2Z.29
•Jii9 HS
•liiH .::A
19:1 ;
PROCESS UPLINK loiORC>
19.2
193 UPL INk: : 1'1011 fl, FLi1Ui
ANL H. ltOOFH
, CLR CLOCk: STOPPEti FLAG
19-1
~lOY FLHGLA
19'5
NOV H. lHWOY.2
i~
19(
11011 RJ., fl
OUTL P.2, A
:.1.98
tliiB 9o3
199
.200
NOV..: @R9,A
o)ilCI r;..::ei'
.29:1
OiiF 913.2fl
13i.2i aa
OL2.2 Zi'
:<RL A. li07H
JNZ FRAME
29.l
-eu.c FE
t.ti.2Z c.;;fi:L
.2132
.204
.2e5
NOli tf,Rb
, TEST WORto COUNTER
HOY;.; H. .;RQ
CPL A
JZ CLRCTR
, INPUT HSH
1101/ Re, ltf<EGbe
NOll H. @Rt3
J84 CU~CTR
.CHECk: IF LAST UPLINk: WAS USEC>
, S!-:IP THIS UPLINK IF LAST ONE
; WAS NOT USEC>
HO'I H. FLAG.1
; WHICH FRAI'IC IS IT'?
.213b
I:)J25 B$.SC
0!27 FO
.:l:WEI 9.2A:.L
~at
.2tl8
2139
219
131.2ft FF
o3i.2B 72l9
1312CI 89
.2ii FRAI'IE :
.d.2
J83. (.QMPI'lR
MOll'..: ;'1,~0
;STORE UPLINk: IJMTA IN~
USE Ri t1S POINTER
; !iSH.
e:L.2E r"li
tli2F :.1.9
ou9
.2Z:Le
CLR ONCE
54
ISIS- I I IKS-48.-'I.IP I -·H 1·111( F.0:1 t1SSEH8LER,
L•j(.
(IE;.]
•)1.::.2 HB
•.H.:: .::11
•:il.::4 ~:o
•)1.::5
.21:3
2-f
•:::JEB 51
.n.:.c :;..,;s1
•H:E L:.
.O•l:F .2:1(1
•H41 118
(ti-12 311
•011-J:. ;3(1
•:•144 .;.,.(11·~5 51
o)l.j.; 9t552
•H-18 19
o:l:l•4 9 E:8:1
•)i-18 F(t
•)i.JC ·E4•)
•)L~E
t18
•H4F 249.?.
5
t·IOV R:., t1
oJUTL P ,2, t1
2.L9
t·IOV:·: 11, •!oRO
l•hjl/
t.tl:--:: 19
•H:i .2..J~2
•H:.r1
PAGE
S(•UF:CE STHTENEIH
SEO
Hi
•H:::< .::o
V2. •:1
·~F:.L,
· LSH.
ti
INC F:l
JI'IP SETUP
..::24
2.25 CCII'IPt1F'
t·IOV:·: H.·
.22i
CPL t1
.2.2:?.
2.2::.2:0
.2:1
r1NL fi, •!sRi
.m.: Ft1L r 1
INC R1
HOI/ 11, ltONE'r'i
NOV p::;,ti
2:..2
.22.:.
·~P~:•
.l'fSH
OUTL P.2,ti
I·IOV:·: ti, •!F'O
CPL ti
r1NL H.- •!oR!
JU.Z: FFILT2
INC Ri
HOV F:O, i!REG50
NOV H, ~~R(t
ORL ti, lt4i':tH
.2:8
2·40
.241
242
24:
t·IOV
. COI'!PtiFE NEH IJPLINf, ~IOF<:IJ TO
. rHE PF:EV I (IIJS FF:fti'IE
•~F:O,
.L$H
, l·IOF:IJS OF FF:ftNE1&.2 t·lft TCH
, SET F:5(~>.8t;;o
rt
JNP SETIJP
<~44
•HSl 19
.2·15 FFtLTl.
INC Pi
.. No !·lATCH HSH OF UPLINI<;
t·IOV RO, ltF:El:j51)
I·IOV H, •!oR(I
FtNL A, IWBFH
t·IOV •!oRO, t1
t•t;jV RO, ltREG.;•J
NOV ti, 1!'RO
OPL t1, ltit)H
t·IOV 1!'RO,A
, riO HATCH LSH OF UPLitlk:
.24.;:
•H52
•HS4
•)155
•:115(
1)158
01511
•H58
•115v
•H5E
8::::.1
F•)
s:eF
11(1
BB:C
F•)
4:10
118
24111
.2·fi FFtLT.2.
.248
.2·B
.2';;0
.251
.252
.25:
.254
.255
.2515
.25(
258
.:59
.2150
.:::.;1
JNP CLRCTR
, PARIT'T'
· THfS IS All UPUNL PARIT',.' CHECL THE Pt1RITY IS
· Ct1LCULt1TE(• l~HEIJ THE fl.IO I'IAT(HIN!l FF:t'ti·!ES OF
, UPLlllf. vt1Tt1 HHVE 8EE11 RECIEVE£• tiNIJ l'!!iTCHEt•.
21'5.2
2!5:.
•)1.:,(1 8Ct::1F
•)16.2 88:0
2t55
·I'IOV R(t,
·:•it.·~ F•)
.;;.;.:;
I·IOV Fi, •i'R•::i
.~.;-!
PFiR IT'l : I'ICII/ R4, ltt)FH
~2•3H
•H.:-5 C8
2t5i BUNCH:
C•E•: RO
•:..Loo IJ(t
2t58
::RL t1, \!IR(t
•)1t;;(
1)1159
(ti.;t1
•:.1158
EC>55
2>59
IJJNZ R·~, BUNCH
HH
.278
f·IO'v' R.2, A
4(
[•11
.271
2.?2.
.• F.:5€1 '·· B...::=(•,. R.;!ih84=iJ
St~HP
ft
:':RL t1, R2
55
IS IS-II t·ICS-48,-'IJP l-41 NACPO ASSEI·IBLER, \12. 1::i
L0C
OBJ
iH6C
0:•16[.•
•H6E
016F
•)iiO
•.Hil
J:)ii2
•Hi:
t)l{..J
t111
E-,.
E-,.
SE(!
SOURCE STHTEI'IENT
.2i..J
2i5
--
E•r=t
.2i~
11ft
Ei
[•11
.:.i ..
.:;..(
F.284
NCtl/ R2, ft
PL r=t
I<'L A
. ; :P.L 11, R.2
NOV R.2. A
RL ft
:-:RL A, R2
CPL 11
J8{' FHLE
"')"':-'"':"
..:...& -·
...
27"8
.2i9
280
.::::31.
...:::=;.::
•:•1(.:; 8821.
l:tli::: FO
•3179
•Hi8
•HiC
(JliE
•HiF
•H:::l
1)1:3.2
·ECO
Aft
. Pt1R I T'r' WHS GOOIJ .
, SET R5•}•.86 ~ 8{) R6•:h84 & 85:.
.28:
.2:::-1
285
2:::.:;
e::::c
.2:3(
2:::8
FO
.::::::9
r'tl)
.2·h1l
.291
.292
4 7_.,.,-,
PAGE
t·IOV F.'t}. lti'~EG50
11,t!'RO
ojF'L 11, lh:H:.13H
NOV •!ti':O,r=t
NOV Rtot, IIREO:ir5tt
t·IO'v' A,t:!'R•::i
(ti':L t't,lEOH
NOV •l'Rt), tt
JI·IP CLRCTR
~IOV
.29t)
292-
•::d8..J 8::::1.
tjl:O;~::: FO
t)l::<i s:.;F
1)1~:9 thl
01.:311 8:3:..:.
t)!:.::c. FO
tjl.SIJ ·ClO
(tl:::F 1113
t)l9(1 .2-ltU
•H9.2
t)i9:.
1)!95
(ti9t5
(t19t:
•)1::'11
•:H:?B
FE
9t5ft8
FF
i26t!t
·C08
r'tF
69.21
Ol9[.o 8E•3<
Oi9F 24i~t(f
2:::04 FALT:.
295
t·IOV Rtot, ltl'£t:j50
NO'·/ A,•!F.:O
.2:.~t5
t1NL
tof(tl/
I·IOV
fof(tiJ
ORL
fo!O'v'
JNP
~
..::,.-
.C::...-i
29:3
299
200
:.01
:.02
:.o:
:u-t
:.os
:.o.;
2(t(
.:o8
.:(•9
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:H
s:.F;
.::.1.:-
r'tF
89.2..1.
.2-I.Cttt
:18
:.1.9
.:.20
•Hr18
CE
(tlt10:. .;:..J(JI)
:it:
.:a
'
•,
~.
:2:
, I 5 FRAt·IE Cot·IPLETE?
, IF FRAt·IE 2 CHECK PARITY.
; SET FLff61,
B:
' !NIT POINTER FOR UPLINK RAM
• t=tC•E•RESS.
:u:
..::l-1
:.15
NO I/. 11,Rt5
.JN:: WCCTR
NOV A, FLft(il
JB.: PFtR IT't'
•:tF<:L 11,#08H
fo!OV FLftC.L 11
HOV Rl, #21H
fo!OIJ Rti,llft('H
Jt·IP CHECK
:.1.2
•HAi
•)lA:
0111-1
t)lr'tt£
•:tlr'ti
(tl.r19
BE•3i
FF
SETUP:
A,#{'FH
•!oRO, 11
RO, IIF<'ECst50
11 .• •!oRO
t't,ltiOH
•!tRO,A
CLRCTR
C.LF.~C TP.
NOll
t·IOV
FtNL
NOV
fo!OV
JNP
l"t5,1t8{'H
A,FLFtG!
11, UOFiH
FLAG1,11
Ri.· lt21H
CHECI,
.. CLEt=tR WORIJ COUNTER
, C.LR FF.~ANE FLF!G BZ
~R.;:.
INCC.TR: IJEC p.;
JNP CHEO.~
..::.<:4
:.25
(1.213o:i
:.2..:;
---
..;...c:,,·
o)P(i 2t3tiH
.• ,jooDCuJOOLtOOOOOOOOOC•OOOOOOOOOOOOOOOO
56
ISIS- I I
LOC.
NCS-48/UF' I -41 t·IAC.PO ASSENBLER,
OBJ
. THIS IS THE ut1TA LHih: INTH:P.UPT ROUTINE
:..29
.::.(J
.::1
o::o.2CU A[•
0.202 F8
a:t.2(t_:. B8:.E
•:12>)5 AO
(t.,:(tt:
·~.2(t(
u'5
95
•)2f•8 543;3
•Z•.20H F•.:
•).2(•8 5:.i'F
•:0.20(1 [0:~.28
~_::o,;::o;:oF C.t54C
•::0211 C.E
(t21.2 FE
•:•21: c.,;,;c.
•)215 FC
02lo5 .s:i'F
•:0218 u:O(I
0.21i1 .:.,;:;..;
(1210: lC
•:021u 88.:C
0.21F F•:O
(t2.2(1 9.2EA
~:;.2.22 S::OFE
•:i,~24 Ae
•)225 FC
13.2.21'5 51i'F
..:12.2!3 c..:.;::A
•)22Ft CJ5fit5
(t.22C. C5
,322[1 FB
IZ•.2.2E ZA
0.22F B81E
•)211 Fe
(12.2.2 A8
€t.2:: Fu
(123.4 .28
.:•.2:.5 9:.
(t.22.,; 0:::4i;)C
PAGE
SOURCE STATEI·IEHT
SEll
(t.201it .28
V2. 0
. IT lHLL ST!iRT t1T LOCATION .2o:::n:::•H ANu TAI<ES
, HF'PRO:·:. 20:::4 l·JOR[.S. THIS ~:OUTINE WILL
, HLSO COIH~:OL THE I)NA SUBROUTINE
HIT .
:-;cH A,RO
I·IOV R5 .. A
~IOV
.3.:::.8
A,
_,STORE POUlTER R(1 IN R5
~·o
~10\1
RO.IIREGt5.2
t·IOV •f<Ro). t1
:.48 SELP.B:l. SEL RB1
.:41
CPL FO
14.2
CALL u0Nt1
NOV A,R4
.:44
t1NL A, !lONES
:AS
::PL A,it28H
vONE44
.:41:5
[.'Eo.: R>5
:.4<
:48
NOV A,R.;
.:49
J: EII[•Ff.<'li
NOV t'f,R4
.:51
t1NL A, !lONES
:-:RL A, ltoOH
15.2
JZ C•OS','NC
:4:
..r:
. STORE NA HI t1CC IN Ro5.2
.SWITCH REG
; SET FO:::o TO t1 ONE FOR t1 REflto
, [•0 THE NE::T C.Ot-IA
· CHEC¥ FOR (.Ot·IPLETION OF 44 I.JOR[IS
. IS THE FRANE uONE
, IF R4=:<0o.::ni:O•)(uiJoj THEN SEN!:> THE S't'NC PULSE
:5:.
:54 HICF<EG. me 1':4
:.55 UPC•I·IA. NOV 1':0, IIREGoO
l·h)V 11 .. ·~R•)
184
[.ot·IAO~;
:.58 CLP.FLG. t'tNL· A,#OFEH
t·IOV . •!<RO, A
IIOuOI'IA: t·IOV A,R4
HNL fi,IIONES
:-:RL.: t1,#2AH
"- S','NC
IHN:
SEL RB0
NOV A, R:3.
OUTL P2,A
NO'.J RO,IIREGo52
NOV A, •!<R0
3.~8
}159
NOV RO,A
NOV H.• RS
.:<o
r
.:71
:.72
L•OS'.-'NC.
. HIO:REt·IENT THE l'lt1IN COUNTER
.. IS FLt1C. 4 SET. UPLINK SETS FLftG 4 l·iHEN I
.• F:EC.EI 'v'Eu 8 UPLIN~.: ~101':[•5
· CLEt1R [•I'IA 0~- FLAG 0 BECAUSE THE UF'LH-It'~ H
.• VAUu uftTfi AT THE ENv OF FRANE 5
. l.JE fti':E AT THE 43Rv f..lOR[• 50 LETS SEl-l[; IJP
, S't'NC. WOR[) TO THE 4516 NEHORY
;RESTORE PORT 2
; RESTORE THE ACC
. RESTORE THE F'OINTER Re
Rl)
~iCH
A,
RETR
JNP
c.os•,·m;
.• t1[•[,Ev FOR PAGE AuuRESSING
~~·.,
:it
~7'8
.;&9
;:sa
lSi
.;s2
, THIS IS rHE [•t·IA F:OUT rNE. IT ~1s:::u
• ',.'!)1_1 HAVE THE I:Ot1TA LSH IN R6 f!Nv
· [•t1Tt1 I·ISH IN R7. IT 11LSO ASSUI'IES
. HfiVE THE r1C.•L•PESS lU R4. FLAG Fi)
· fHE REF![• OR ~iRITE NOvE WITH F0=1
, NEAN Hl>i A WRITE NOvE.
57
ISIS-II HO:S-4>::/UF'I-·H t·IAO:.F:O ASSEI·IBLEF:,
LOC
OBJ
•)2:.8 9H(I(I
•32.:11 Bt;42
•.:1.2:.c FF
,::.~:.r,.
~-9
•32:E
(1240
•3241
(1.242
(1244
(1245
8A4.:0:t
FE
SEO
.;::::.
C.•Oi'lft.
:.81:)
:.:37
3.88
90
2-89
:?.ft10
FC
98
}9(1 PEAC•:
:.91
1.92
(t.24r5 8H8~t
•:•.24:3 9A4(t
392
294
.:12411 85
•3248 81
395
ANL P2, #ZEF'O
.JF0 REftC•
NOV A, R7
OUTL PL ft
OF~L P2, lt*•:JH
Joli)'yl Ft,Rt;
NOV:-: ·~Rft, ft
ORL P2, #fl.lO'T'1
NOV fl, F:4
~IOV>; r~F:1.:t.. ft
ORL P2, lti·IAS~·I•7
fiNL P2, lt4(1H
CLR F.-:J
RET
•.:l2t;O FC
1)20::1 4~8(1
•:t2~:. r'tC.
•:•.20::4 44l(.o
•::t.2t.i FC
•)2t5i
4Z81~t
40(1 v0NE44: INC R.:
401
I'IOV Ft, ltfo!AS~:v7
402
FtNL A,R4
NOV R4,Ft
4•E
~IOV ft, R3.
4•::•4
405
SWAP Ft
4•3t;
ORL r't,R4
40:Ir
1'101/ R-+,r't
4(18
I•IOV p.,;, #(ICH
-l(t9
NOV F:O, ltPEG6•)
410
I·IOV H.. I~R(1
411
NOV P5,Ft
·H2
CPL r't
JB.: ·UP(.oi'IA
414
J8.2 '[•(!50
I·IOV Ft .• R4
415
41t;
ORL Ft, lti·IASH) r
I·IOV R4,t1
417
41:3
JI'IP UPvi'IA
I'IOV Ft, P4
419 v7ISi:O:
4213
OPL t1,ltNHSI<vr
41.:
421
•.::t.2o9 AC
•)26Ft 441[1
42.2
42:.:
424
425
42b
427 ENvFF'I·t: NOV R•3, #REGt>J..
~~26E FB
026F [.•313Z
~::1.2(1 9t;8€t
(12{3. Fe
428
429
410
43,1
13279 FtC
.:l2<A C8
13.218 FO
.
~.,
~.:...
4.::.::
414
415
416
417
; SET AC•vRESS REG
C.I·IA
·' WIT
·' CLEfiR P2 E:\C.EPT FOR THE WRITE viSCRETE
.: NASI< I)(
·SET
~·:.
so
R4 WILL CONTAIN
xooooeee
POINTER
; I·IOVE r'tC•vRESS TO R4
; SET J':t; TO COUNT THE LFtST 1.2 WOF:vS OF THE
. SET RO TO POINT TO THE FLAG WORv Roe
, t·IOVE FLFtGS TO THE ACC
.. SAVE Rt5•) IN R5
; AF:E WE IN FF:ANE 1 ~EC=•3i
.• WHICH l·lAY [•0 l·lE SET [.o( OF THE AC,vPESS PO.
; l~E ·HAC• TO SEll[• UP THE UPL!Nr~ WORvS
TH'
.. ECHO 15 FROI·I BUFFEP 2 so SET (.o( TO t1 i
so
so
; WE C• Iv NOT HAVE AN'T' UPLINK WORvS
ECHO
. 8UFFEF: 13
SET [.•( TO t1 0.
, '"**I·IE~l CHAN1::.E. ECHO FtLL THE TINE .:OR w
so
NOV R4,A
JI·IP UPvi'IA
•3.21'5C 881[1
1-3274 .:..-i"
•32i5 5.:eo
(1277 43.:8
• SET Pi TO C.•ftTFt NSH
• SET ~lRITE C.•ISCRETE
; I·IOV C.•tHFt LSH TO ACC
.: LOfl[• C•ATA IN OUTPUT REG
; SET C.ECOC.•ER FOR 2Yi
THIS IS THE CONPLETEC• 44 ROUTINE
. ~lE WILL NOW F'~EINITIALIZE THE
, t't[•vRESS POINTER R4
299
':).25E 52t5t5
·'SET P2 TO 81)1iKI01)130
·' CHEC~.. FOF; REftC• OR WRITE
·'
.198
·::•24(. 18
(t.24[.o .z:.:::o
<:124F 5C
(125(1 tiC
•)251 FB
..:).252 4<
•)25.: 4C
':)254 r'tC
,:,.255 BE1X
sj.25f B8:C
1)259 F•3
·::•.2511 r't[.o
•).258 ~(
(1.0:::50:. 721[•
PAGE
SOURCE STFITEI·IENT
:.84
385
1915
:.97
1/2.13
f'IOV A,RJ
::RL ft, #01H
.iN: BUFF?
i·!OV Ft •• t1RO
CPL A
t1NL M, #t·IASI<C.?
ORL A, ih338H
NOV !<: +.· 11
vEC 9.1)
NOV Ft, @RO
·' rHIS F':OUTINE IS THE FRAI·IE C.ONPLETE
.. ROUT HIE. THIS WILL PESET R4 AN(.o TELL
.. BOB WHftT BUFFER TO LOAv NE:'\T
; R3.=•3€u)000ii ~ IF ::.u l·lE ARE AT THE ENIJ OF
; l FtN(.o t·JUST RESTORE ()? ANv CLEAR FLAGS .2
; RESET
~"' BACK TO X(iiiiOii
·'SAVE POINTER IN R4
; C.LEAR FLAGS 2 ANC,. 1
58
ISIS-II l·h:S---!.3.-'UPI-·H 1'111CRO 1155EI'IBLEF':, V.l. 13
LOC
O::•B.J
s.:F:::<:•2;-"E HI)
(t.2iF 18
,_:t.2E:O FO
(1.281 A[.o
(1.2{C
(1.282
•Z128:
(t.2:35
1).286
tj.288
-·
~..,.
53.80
2v
52 iF
4v
•3.289 A0
(t.28H AF
1),2:=:8 BCFF
•::i.28[• 5438
•).28F FF
0.298 .S.i
(t.29l 5.:18€1
€t29~.. 11C
f1.294 FB
(1.2~5 53. iF
•.::•.29( c.zo7
(t-2•?9 9r5A2
•).298 8Bt•.2
029V C8
'329E Fi1
0.29F 43.1)9
•3.2Hi 110
(1.211.2 E:EFF
0.2114 442C
(t2A!5 Fa
(t.2H7 AF
·~•.2Ft8
.;;;z:E
•).21111 158
1)2118 118
~2HC F.;,
•32Ft[• 2F
·~1.2r'!E
H8
•32AF FC
02E:8 F2BC
tj28.2 8C8l3
(t284 BE 58
•::•2815 543.8
1).288 BC.2A
1328A 442C
028C BCOI)
O.:t.2BE BE27
•32CO 5438
(1.2C2 BCAA
•32(.4 442C
(t2Ct5 FC
•:l.2C7 AV
•32CS 89Bt:l
SEC!
PAGE
SGUI':CE STATENENT
11, lWF2H
NOV •!'F:O,A
44i3
INC F:O
. R•1 IS PO li-lTING AT Ro51
441 BUFF~·: NOV A.~RO
44.2
1·1011 RS,A
_. t:OI'IPLEI·IEN T I)( FO THE STATUS WORv
44:CPL A
444
AI-lL Ft, #NASI<vr
445
:.<CH A, RS
4415
11NL ft,#ONES
44(
; R5 CONTAINS CO~IPLENENTEv i{00001)80
Of':L A, R5
448
f'IOV •!oRfl, A
443
t·IOV R7,A
45ft TELBOB: NOV 1":4, #NASI<
; tiCoC•RESS OF 45115 STATUS I·IORv
; SEIIv THE 451>5 THE STiiTUS wo;;·c.
451
CALL [•ONA
, , f'IO'./E PO II-ITER E:ACY TO R4 8 l CO!-IPLE~IENT I NG
452
NOV A,Ri
,OF THE STATUS ~~o~<:v TO l•it11<E IT ;,;cua0o11ee
452
CPL A
454
ANL f1,#NASI<:v7
455
I·IOV R4.i1
4515
; P3=<.:0ii:tf10iii? IF so WE ARE AT THE ENv OF
NOV A.. R3.
;FRANE 5
457
11NL 11, 1101-IES
458
i<F:L 11,#07H
459
JNZ RESTRt5
460
; RESET R2. BAO.: TO t10il3
NOV R3., #•32H
;SET vNA 01< FLAG
461
vEC Rl)
415.2
NOV A,oioR0
; SET THE vNA 01< FLAGS .;FLAGS e ANt> l)
4153.
ORL Ft,#l)9
464
NOV •!'R•3, ft
465 F:ESTF:S. ~IOV Rt5,#0FFH
4t)!5
JNP Rm
46(
THIS IS THE S'r'NC l·lOR[J ROUTINE. IT WILL
41:)8
, C•ETERNINE WHAT S't'NC l~ORv TO LOAv IN THE
, NEAT FRAI·IE.
4159
4(0 S'r'NC.
NOV A, R•3
4(1
NO'./ R?,A
472
NOV Ft, #S'r'NCWv-•).2H ,PUT THE t·ISH OF THE S'r'tlC l·JOR[J TOGETHER
4-f1[,v H.• 1'::.
; ~lORC•S LOCATEv !N C•FtTA r·tENOR'r' AT
'"'
4(4
_, S'r'NCJ.Jv <:LOC 4€JH TO 44H)
t·IOV Re,Ft
4(5
I•!OV A.~Re
4-; 1'10\IE THE I~ORv INTO Ri FOR THE [JNA OPERAT
XCH ft, R7
''='
4i7
1'10\1 RI3,A
4(8
1'10\1 A, R4
479
JBi ~lORvi
;uNit SYNC WORL• l HHO BUFFER A
480
NOV R4,J1080H
NO'./ RC:,J1Ct58H
481
482
CALL IJOI'IA
NOV R4,#2AH
; SET R4 BACI<:
483
484
JNP RTN
; uNft SYNC J.IOI':u 2 HHO BUFFER 8
485 WORv1: 1-10'./ R4,#2ERO
481:)
l·IOV Rt5,#1327H
48(
CALL vOI·IA
; SET R4 BFtCI<:
NOV R4,#0AAH
488
489
Jt-IP RTN
490 vOl~Rv9: I·IOV A, R4
, SFtVE R4 IN RS
491
NOV RS,A
40::.)
t·IOV R1, #•380H
; RESET f':i TO 101113000
·E8
AI~L
·F<=~
~~
1
59
IS IS- I I NCS-4;3/UP I -41 NACRO ASSEI'IBLER,
LOC
OBJ
(t.2(.ft BAOft
493
494
•:•.2Cv
•ot.2CF
(1.2[•1
•).2!:0.2
1).::[.•4
Jj.2[rt5
(t2[J8
t32!ir1
1).2[.•(
o2vE
02!iF
0.2El
o.;:E:
•32E4
0.2E5
02Et5
8:33F
802J.
1.7
B2vc
BEFF
BFFF
BC.FE
5·E:3
8E:3C
FO
495
496
497
498
499
5th)
5•)1
5i)2
503
504
52(.(.
s.as
43•)4
50!)
507
508
A0
F!i
AC
BEFF
(t2E:3 442C
5~:::•9
510
5li
10
SOURCE STATE~IENT
SEO
•:•.2(.C FO
PAI:lE
V2. 0
NOV R2, #(tHH
t·IOV f1, •l'R•3
NOV Rtot .. lEFH
NOV •!oRO, #.21H
CPL A
J85 ENvULI,
1·1011 Rt5 .. #OFFH
I'ICtV R< .. !WFFH
NOV R4, l*OFEH
CALL [•t)I·IA
EN[•IJU< : NOV R•:i, ltREGoO
t·IOV A, i.!RI:i
ANL Ff,ltOCCH
ORL Ft .• lt•)4H
1'1011 @RI), A
I'IOV A,RS
1·101/ R4, A
NOV Rt.>,#I'IASI<:
JI·IP RTN
;RESET R2 TO 006010i0
, F~O POINTING AT R60
; SET R64 E:ACI< TO .13
; !iO l·lE HAVE GOO[• [.•FfTA:> BS=O UIPLIES GOOV
; SET J:oFtTA LSH TO ii1HH1
; SET C•ATFt I'ISH TO iiliiii1
.• SET LOC .56.3.76•:0C.TAU TO r1LL ONES TO INIJI
.• THFtT '·/ALI[.• UPLIN~: [lATA IS AVAILABLE
;GET THE STATUS WOR!i
, CLEr1R FLAGS 1), L 4 ANV 5
; SET FLAG 2
.. t·IOVE FLftG 140RJ:o SACK
51.2
sn
514
515
•:•2Ef1
•32EB
•J2Ev
0.2EE
f•.2EF
0.2FJ.
ft2F2
27
51!) J:oi'IAOK:
1225
Cft
FA
Ct5C.t5
FC
517
t=tv
518
519
52~)
521
522
(t2.FJ. 883F
t)2F5 F€1
•32Ft.> ft8
(t.2Fi' F•3
•).2F8
•32F9
ft.2FA
tt.2F8
0.2FC
•::J.2Ft•
tj.2FE
t'tF
18
Fft
AE
F9
FIC
'54:;.8
.;.:.oo J.9
.:;:.oJ. J.8
0262 F8
.:;:...::~:. 883F
.;.:es
At3
•Ettt5 F!i
03•3< AC
03.•38 BEFF
03.011 442C
•33-t:,C 9ACF
•3sf•E 80
t:EGF 441C
USER S'r'NSOLS
5.24
525
52!)
527
528
529
5:1)
s.:a
53..2
53.4
5:?.5
.J,(
5-53.8
519
540
541
542
54]
544
545
546
A
NOOONA
R"'
A, R.2
JZ [.ooJWR!i9
NOV l'f, R4
NOV R5.t=t
I·IOV RO, lEFH
NOV. A, t!'Rt3
NOV· RO, 11
I·IOV A, @R•3
NOV R7,A
INC Re
I·IOV A, @Rt3
I·IOV Rt5,A
NOV A,RJ.
NOV R4, A
CHLL !iONft
INC Ri
INC Re
I·IOV A,R0
NOV RO, lt:.FH
NOV •!Re, r~
~IOV A, R5
NOV R4,11
I'IOV Rt.>,#NASI<:
JNP RTN
!iOS'.-'NI( : ANL P2,#t3CFH
I·IOVX A,@R0
JNP INCREG
CPL
JBO
C.EC
NOV
ENIJ
...
;
;
..
;
THIS IS THE UF'Ll t ~~-: ' [•I· IA ROUT INE. ~lHEN
ALL THE FLAGS ARE SET 14E WILL E:EGIN TO
C•t·IA UP ALL THE UPLINI< C•ATA-9 ~JOR!iS.
CHECK TO SEE IF THE t•t·IA 01<.: FLAG IS SET
; IF R2=0 THEN WE HAVE SENT ALL THE UPLINI
; WOF:[,5 AN[• NOW vlE HAVE TO TELL THE 4516 I
_; THE vATA WAS GOOIJ
; SAVE R4 IN RS
;SET R0 TO POINT AT Rt54
; SET R0 TO UPLINk: J:oATA Avt:oRESS POINTER
; NOV vATA
~ISH
TO .R7
; ~lOVE iJATA LSH TO Rt)
; NOVE A!i!iRESS LSH TO R4
; INC C•I·IA AviJRESS POINTER
, INC I·IEI·IOR'r' POINTER ANv I·ICII/E IT BACK TO
; RESTORE R4
; SEI-ID THE S'r'~lC PULSE
60
PAGE
ISIS-I I NCS-48/UPI-·H !·IACI':O ASSEI'IBLER, 112. 0
BITOFF .cu:•<o
C.•ELri'r' 0•014F
C•OS'lNK o:oc
FLFtt:ll l::u~u.)('
IJO[Jt)I•IA t•.:::.25
REC.so 0021
3 1T 1NC
02fto
UP[-'f'IH 10•.21[.•
BUFF~·
(t.;::3~1
I:OELA'r':L (nZs5!
[J()i~f<:[,::; 8.2Cr5
FRAI·IE 81.211
ONES
OOiF
REG6•3 oo:c
SW-K~Jv •3•34(1
UPLINk 0112
11SSEI·I8L '-r' COI-IPLETE,
NO ERRORS
BUNCH
v£LAY2
ENC•FI':I•I
WCCTf':
01-JE'•'O
I':Eo:ioi
TELBOE:
WHIT
•3165
(nt172
(1.2i.C
(t1A8
(1€1tt(t
(n3:v
1).288
OOSA
CHECK
[,ELA'r'1ENvUU<
INCF:E•::.
Ot-IE'r'1
REGo.2
TESHlv
140Rvi
1)1()0
•010{4
•3.2[.•C
021C
0•310
€nEE
I)I)HH
02BC
CLRCTR
L•I·IAOI<.:
FFIL Ti
!NIT
ONE'r'.2
:<:ESTRo
TWO'r'(l
ZERO
13222
13238
13152
0.21)13
fi,:Ge
~?e2Ft2
CLRFLG
[JOI·IA
FALT.2
INT
ONEYJ
RTN
06(•0
Tl~O'r'i
130113
•.HAl
62Ei1
0151
00:1(1
tn:::1.20
8€11~113
022C