CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
MICROPROCESSOR CONTROLLED
DATA ACQUISITION SYSTEM
A graduate project submitted in partial satisfaction of
the requirements for the degree of Master of Science in
Engineering
by
James Edward Rollinson
Hay, 1982
The Graduate Project of James Edward Rollinson
is approved:
fr'"avid Schwartz
California State University, Northridge
ii
TABLE OF CONTENTS
CHAPTER
I .
Page
SCOPE. • . . . . . • . • . . • . . . . . • • . . . . . . • . • • . . • . . • . . • • • • .
System Design ...••••
Breadboard model.
Hardware ••
Software.
. ...
. ..
1
1
.1
1
1
Hardware Considerations •..•••
Physical packages .•.....•.
Commercial block diagram •..
Controlling logic •.•.••.•
Critical timing requirements.
Interface between microcomputer and
terminal •...•.•••••.
3
3
3
3
5
. . . . . . . . . . . . . .. . . . . . .
Software Considerations .•••••
Programming language level.
Simple operating system ..•••
5
5
5
5
7
7
9
Iviemory Slze . . . . . . . . . . . . . . . . . . . • . . .
1'-Iicrocoinputer provided programs ••
ivl.emo ry map •••.••••••••••••••••••
II. CIRCUIT DESIGN .........•....•..•.••....•.•..••••
10
Input JYiul tip lexer . . . . . . . . . • . . . . . .
Number and type of inputs .•...
Number and type of components.
Circuit design •.....••••
Ir~ut socket ..•••.•••.•.
Selection of components.
Input expansion.
10
10
10
10
10
12
12
Input Arr~lifier ••..•...••••••
Instrumentation amplifier ..
Programmable gain ....•.•.••
Instrumentation amplifier selection ..
Amplifier gains ..•.•••
External connections •.
12
12
13
13
13
14
Sample and Ho 1 d • ••••.•••••••••••••••.•••••
Selection
of sample and hold amplifier ..
•:
Selection of the hold capacitor ••••.••..
15
15
15
..
iii
CB.APTER
II.
Page
Analog-to-Digital Converter ••••.•••••••••••••
Conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolution of digital result •••••••.•••••••
Component selection •••.•••.••...•..•••••••..
Converter references •••..•.•..•••.....•.•.•
15
15
15
16
16
Logic Control and Timing •.•.•••••.•..•..••••.
Input/output decoding •••••••••••.•.••••••••
\VI"i te da~te. enables . . . . . . . . . . . . . . . . . . . . . . . . . .
Read data enables . . . . . . . . . . . . . . . . . ,. . . . . . . . .
Signal buffers .•••...•.•••.••••..•.••••••• _.
External register ..•.•••.•••.••.••.•••••• ~.
Clock input for the converter ••.•••••••••••
Address decoding mechanization ..•••••.•••••
Address decoding improvements •..••••.••••••
19
16
17
17
19
19
19
.. 21
21
High Voltage Protection •••.••.•.... ~ ...•••.••
Input voltage limitation •..•••••.•.•..•••••
21
21
Digital-to-Analog Converters .•••••••••.••••••
Separate from data acquisition system •••.••
Desired qualities •••••••••.••...•.•••.•••••
Device selection ..••••••.•.••••••••••••••••
23
23
23
23
Pov1er Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requirements ..•.•.•....•.•••••..•••••••••••
Voltage Regulator Circuits .••...••.•••.••.•
GI··ounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
25
II I. SQI'i'T\'JARE • •••••••••••••••••••••••••••••••••••••••
26
Iviaj or Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .... , ..
26
System initialization ........•.............
Data acquisition .•.........••....••.•.•....
26
26
27
Data displa-:;,r ................................. .
System Initialization Process ••••••.•...•.•••
P~cogram procedure ....................... " ..... .
User defined parameters •••..••..•••.•...•••
Messages and responses ••••••.•.••.•.....•..
T·lenory location of system parameters .••••.•
Softvvare implementation for messages ....•••
Softv1are implementation for responses ••••••
Hexadecime.l responses •••...•••••.••••.•.•••
Message subroutines .•••••.••••.••...•.••.••
Halt until the user is ready to proceed •••.
Data(rAcquisi tion by Interrupt Request •••••.••
Interrupt prograrn procedure •••••••.•••••.••
Input ~an1pling . . . . . . . . . . . . . . . . . . . . . . . ...... .
iv
27
27
30
31
33
34
34
35
37
41
42
42
43
CHAPTER
III.
Page
Display of Interrupt Requested Data •••.••••••
Data display process.......................
Binary-to-BCD conversion ••••...••••••••••••
Stored data processing ••.•.•••.•••••••••••• _
ASCII coded output characters ..••••••••••••
Transmission of outputs....................
47
47
48
50
55
55
Data Acquisition and Display by Software
Generated Data .•..•......•..•.•••..•••.••••
Timing procedure ••••.••••••••••••.•••••••••
Input sampling procedure ••.••••••••••••••••
58
58
59
IV. RESULTS AND COI'\fCLUSION ••.•.•••••.•• :·... • • • • • • • • •
63
Results of the Hardware Design ...•.•••.••.•••
Malog gairi................................
Analog-to-digital conversion .•.••••••••••••
Common mode rejection •••.••••••••••••.•••••
Dynarnic resrJonse. . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-analog conversion •.••••••.••••••
63
64
64
65
65
63
Results of the Software Programs ..•••••••..•.
Sampling rates for multiples of 100
microseconds •..•.•.•..•••••••.••.•••••• ~.
Sampling rates for multiples of 10
milliseconds ••....•••••••.••••..••.••••••
Sampling rates for multiples of 1 second ...
Data display messages......................
67
67
68
~···········
68
.A.. I-11\.RD\VARE SCHEij1ATIC •. ...... , ••••••••••• _. • • • • • • • • • •
70
Input rnul tip lexer circuit.. . • • . • . . . • • • • • • • . . •
Input amplifier, sample and hold circuit,
and the high voltage protection circuit ••••
Analog-to-digital converter and the external
71
Conclusion . . . . . . . . . . . . . . . . . . . . . . .
66
66
APPENDIX
72
register.....................................
73
Address decoding aDd the data enables .•••••••
Logic control ••••.•.••.••.•.•.••••.•••..•••••
Data bus latches and buffers.................
References for the analog-to-digital conver·ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-analog converter circ~its •••.•.••.
74
75
B. ASSEl\lBLY LANGUAGE PROGRAJ\.1. • . . • . • • • • • • • • • • . • . • • • •
v
76
77
78
79
APPENDIX
c.
Page
. ..............•.......•.•... . . ... ...
Hardware calibration •••.••••••••• . . . . . .... .
CALIBRATION.
Software calibration ••.••••.•.••.
Zero offset calibration example ••••••
Calibration of the digital-to-analog
......
......
G·LOSSARY • ••.••••••••••••••••••••
Vi
e
97
97
98
98
convertel""'S • •..•..•..•.•• ·.•
D.
97
•
•
. ... . .. .. .. ..
99
LIST OF TABLES
Table
Page
1. Pin List for Analog Input ChaDnels ••.•••.•••••••.
13
~········
14
3. Input Voltage Ranges for Analog Components ..•••••
23
4. Binary-Coded-Decimal Equivalences ••••. ~········~·
30
5. Printed Messages •••••••••••••••••••••••.•••••••••
31
6. Gain Selection •••.•••••••••.•••••.•••.•.••••.•••.
32
7. Zero Page Address Registers •.•.•••••••••.••••••••
34
8. Look-up Table for Encoded Gain Values .•••.••.••••
39
9. Decoded Addresses .....•.••••.•••..••••.•..••••.••
45
10. Look-up Table for Decoded Gains..................
54
11. Measured Amplifier Gains •••••••.•.•.•.•.••••••..•
63
12. I-'Ieasured Amplifier Zero Offsets..................
64
13. Digital Output Specifications •...••••.•••••..•.•.
65
2. Gain Truth Table . . . . . . . . . . . . . . . . . . . . . . . .
14. Digital-to-Analog Converter Transfer Characteristics . . . . . . . . . . .
0
••••••••••••••
Vii
e................
66
LIST OF FIGURES
Figure
Pa.ge
o&........ . . . . . . . . . . .
8
2. Three Input Configurations •••••••••••••••.•••.•••
11
3. \vri te Data Bus Enables. • • • • • • • • • • • • • • • • • • • • • • • • • .
18
1.
4.
Blocl~
Ree~d
Diagram .. . _.. , . . . . . . . . . .
Data
Enables· •.••••••.•• ·-·...............
20
5. Start Conversion Pulse ••••••.••••••••••.•••••••••
22
BLlS
Flovr Chart of the Subroutine
READ • ••••••••••••••.
36
7. Flow Chart of the Interrupt Request Programs .••••
43
8. FlO'A' Chart of the Subroutine COI""JVER • •••••••••••••
44
9. Flow Chart of the Program PROCES • •••••••.•. • •. • • •
L1'7
'I
10. FloH Chart of the Subroutine BII,IBCD ...••.•••••..•
49
11. Flow Chart of the Subroutj_ne
. . . . . . . . . . . . . . ·• •
51
12. F'lm'r Chart of the Subroutine OlTTPUT . ...............
57
6.
viii
Gl\~G •
LIST OF PHOTOGRAPHS
Plate
Page
1. Layout of the Total System ..••.•... ·;.. . • . • . • • • • • .
2
2. Layout of the Hardware Components................
4
3. Close-up of the Hardware.........................
6
·..
ix
_
...
ABSTRACT
MICROPROCESSOR CONTROLLED
DATA ACQUISITION SYSTEM
by
James Edward Rollinson
Master of Science in Engineering
The data acquisition system built for this project
is intended to be used in engineering laboratory experiments which require a record of time dependent data in
the form of analog voltages.
The system is controlled by
a microcomputer and is capable of accommodating a v;ide
range of applications without hardware adjustments.
The
project is comprised of a circuit design and software
programs.
A breadboard model of the circuit was built to prove
the hardware design.
The circuit consists of m1 analog
and a digital subsystem.
The analog subsystem provides
the input signal path and the signal gain.
The digital
subsystem conyerts the analog voltages into digital logic
levels and provides the control signals.
X
The software programs are used to prove the system
design.
The programs, which are stored in the micro-
computer's memory, are divided into three functions.
First, the $ystem is initialized by the user for a specific application from a series of software generated
questions.
Next, the analog inputs are sampled, converted
into digital values, and stored in the microcomputer's
memory.
Finally, the data is displayed as digital volt-
ages .
...
Xi
CI-I.APTER I
SCOPE
1.
Breadboard model.--
System Design
The intent of the project is to
build a breadboard model of a complete microprocessor
controlled data acquisition system.
The implementation
of this task is separated into the hardware design and the
software programs.
Hardware.-selected.
A popular microcomputer and bus were
A physical layout of the total system is shown
in Plate 1.
1.
The KIH1 by MOS Technology, Inc. was chosen as
the microcomputer.
The Kir-11 is used by colleges and
universities as a teaching tool.
2.
The hardware design uses the S-100 bus.
Since the
S-100 bus is not standardized, the KDII1 must be connected
to a KIM/S-100 Bus Interface manufactured by Forethought
Products, or a custom-made substitute.
Software.--
The software programs were written in
6502 assembly language.
Ivlajor requirements for system
operation are:
1.
Adaptable for a large range of applications.
2.
Completely controlled by software.
3.
Easily operated by an inexperienced user.
1
2
Ct--1
0
3
2.
Hardware Considerations
Physical packages.--
All hardware fits on one univer-
sal S-100 pre-drilled board.
1024 by 8 PRQI.1 1 s.
The program is stored in two
The input data is stored in any avail-
able conb_guous RAI',1.
A physical layout of the hardware
components is shown in Plate 2 and Plate 3.
Commercial block diagram.--
The hardware design
utilizes the basic block diagram used in commercially
available complete modular data acquisition systems.
Typical block diagrams include dual 8-channel multiplexers,
instrumentation amplifiers, sample and hold circuits, and
analog-to-digital converters.
The block diagram differs-
from the commercially available block diagrams by including
the controlling logic.
See Figure 1 for the block diagram.
Controlling logic.--
Functions controlled by the
microprocessor are as follows:
1.
Set the mode flip-flop for single-ended inputs
and reset it for the differential pair inputs.
2.
Store the value to the multiplexer and analog
switch to select inputs for the next channel to be sampled.
3.
Store the encoded value to the programmable gain
amplifier for the next channel to be sampled.
4.
Set the sample and hold flip-flop for sample mode
and reset it for the hold mode.
5.
Create the start conversion pulse and the output
enable strobe for the
6.
ana~og-to-digital
converter.
Create the output enable strobe for the signals
4
5
which indicate a saturated input and which enable the data
acquisition process to begin.
Critical timing reouirements.--
The hardware has 100
microseconds to accomplish to following:
1.
Reset the sample and hold flip-flop.
2.
Store in RM·1 the previous converted value from the
analog-to-digital converter's latch.
3.
Create the start conversion pulse for the analog-
to-digital converter.
4.
Store the value for the next inputs and gain into
a latch.
5.
Wait for the analog-to-digital converter to
complete the conversion.
6.
Set the sample and hold flip-flop.
Interface between microcomputer
and terminal.---
The
microcomputer provides a 20 milliampere current loop.
Also, the microcomputer determines the baud rate of the
terminal.
3.
Software Considerations
Programming language level.--
Assembly language
programming was necessary to achieve a high sampling rate.
An assembler/editor was used during software development . .!/
Simple operating system.--
The program was made
complex in order that the operating system remain simple.
1.
User controlled parameters are entered into RAM
_!/Peter Jennings, Micro-ADE for the 6502, Micro-Ware Ltd.,
Toronto'· Ontario, Canada, 1977, pp. 5-56.
6
(!)
.c:
+-'
<i-1
0
§'
I
(!)
rJJ
0
r-1
0
7
locations.
2.
Inputs by the user are one of the following:
yes or no,
3.
Options for each parameter are displayed.
(1)
(2) a decimal value, or (3) a hexadecimal value.
The correct number of characters is required
before the data is entered.
to entering data.
Inputs can be corrected prior
A carriage return is
re~uired
to enter
an input.
4.
An illegal input causes the request for informa-
tion to be repeated.
The requested information may be more
than the immediate line.
5.
After the user controlled parameters have been
entered, the program waits for an input response to start
the data acquisition process.
6.
Upon completion of the data acquisition process,
a new message is displayed.
7.
The program waits for an input response to display
the data taken for the first channel.
This step is repeat-
ed until all channels have been displayed.
The data is
displayed as decimal values.
8.
The data acquisition process can be repeated with-
out redefining the parameters.
Memory size.--
The standard low cost PROIV! has 1024
memory storage locations.
Two of these devices were
required for program memory, look-up tables, and strings
of characters.
Zero page RAI>1 locations are provided by
the microcomp1.;'ter.
Jl'iicrocomputer provided programs.--
The microcomputer
8
ANALOG
INPUTS
!e
~a
STARTCON -H
A~
t
~
8
7'
ANALOG
MUX
8-BIT
LATCH
DIGITAL8,
,
TO-ANALOG
CONVERT-
~
~
f.R
j·
~
3,
"7
ANALOG
SWITCHE.S
6- &IT
LATCH
..e..
,
s
8
~
-1-
8
4
'\IN7
ANALOG
OUTPUT
~
_L
U)
:>
.
...
8-SIT
LAT<.H
en
AMPLIFtR
--
DIGITALTO-ANALOG
CONVERT-
ER
4
INSTRUMENTATION
8
~
0
~
.J
cc
z
I
5AMPL.E/
HOLD
0
t-
u
~
uJ
a:
,
OVER
VOLTAGE
PROTECTION
At~AlOG-TO-
DIGITAL
CONVERTER
0
f
cO
LOGIC
OV£~FLOW
~
CONTROL
-
.....
1
...,_~
8
_f'IO
-r
,
ADORE;~
DECODING
~
t-•
~
3.
VOLTAGE
REHRENC£5
•
J.
MIC.ROC.OMPUT E R
ADDRESS SUS
EIGI·IT LS8'S
Figure 1. Block Diagram
8
9
contains programs for two-way ASCII coded data transfer
between the microcomputer and a terminal.
The monitor
program is called at the completion of a task for user
convenience.
Nlemory map.--
The assignment of memory locations is
the following:
1.
Hemory locations $0000 through $01FF are used by
the microcomputer and the program.
2.
Nemory locations $0200 through $16FF are available
for data storage.
3.
Nlemory locations $1700 through $1FFF are used by
the microcomputer.
4.
l1emory locations $2000 through $7FFF are available
for data storage.
5.
Memory locations $8000 through $83FF contain the
program.
6.
I>iemory locations $8400 through $EFFF are available
for data storage.
7.
Memory locations $FOOO through $FFFF are used by
the microcomputer and the program.
CHAPTER II
CIRCUIT DESIGN
Input Multiplexer
1.
Number and
~
of innuts.--
A commercial standard of
16 single-ended inputs or 8 differential pair inputs was
chosen as a requirement.
Number and type of components.--
To minimize internal
resistc;mces, cross-talk, and board space, the smallest possible number of components is desired.
A sixteen input,
two output, analog multiplexer plus a quad analog switch
will best perform this function.
Circuit design.--
Three combinations of analog input
pairs to the instrumentation amplifier are possible.
three possible combinations are shmm in Figure 2.
The
The
lower three bits of the channel (a four-bit number) select
one-of-eight input pairs Xa_ and Xb to be .19-resent at Da and
Db, respectively.
The most significant bit of the channel
enables 81 for channels less than eight and enables S4 for
channels equal to or greater than eight.
For the differen-
tial pair mode, the programs allow only channels that are
less than eight.
The mode flip-flop enables S3 for single-
ended inputs and S2 for differential pair inputs.
Input socket.--
The 16 possible analog inputs plus
r
the digital signal STARTCON-H are brought onto the board by
10
11
Xo
Xa
Do
Sl
ANALOG
MUX
-=-
Db
)(b
8
S3
GND
IN 5TRtJM£NTATION
AMPLI Fl ER
54-
5
ANALOG
5WlTGH
3
SINGLE· ENDED
MODE: CHANNELS 0 TO 7
8
Xb
$3
Db~~----~----~--~
54
9
6ND
3
SINGLE- ENDED MODE: CHANNELS 8 TO f
Xa
Xb
e
8
DIFFERENTIAL PAIR MODE
Fi~ure
2.
Three Input Configurations
12
a 40-line ribbon cable that is plugged into a 40-pin dualin-line socket.
Each analog signal has been separated from
adjacent signals by a wire connected to ground.
A list
that references the pin numbers to the input channels is
shown in T.s;_ble 1.
to ground.
Pin numbers 21 to 40 have been connected
Pin number 1 is connected to the signal
STARTCON-H.
Selection of components.--
Analog multiplexers and
analog switches are not widely available.
uters have a large minimum order charge.
Many distribThe selection
of the DG507CJ and LF13331 were based upon their low cost
and availability to the unit buyer.
Inout expansion.--
Capability of expanding to twice
as many inputs is provided in the circuit by an enable
input to the analog multiplexer.
be required.
Additional hardware would
In addition to another 16-input multiplexer,
separate enables for latching the channnel and gain would
be required.
The latch function of the programmable gain
instrumentation amplifier would be utilized.
The software
requirement of 100 microseconds per cycle would require
a faster analog-to-digital converter.
2.
Input Araplifier
Instrumentation amolifier.--
Since the input to this
stage is a differential pair, the amplifier must have a
high common mode rejection ratio and a high input impedance.
t
Instrumentation amplifiers are suitable for high common
13
Table 1.
Pin
( 1)
Singleended
(2)
5
6
7
8
0
1
2
3
4
5
6
7
9
10
11
12
Pin List for Analog Input Channels
Differential
Pairs
(3)
0(+)
0(-)
1(+)
1(-)
2(+)
2(-)
3(+)
3(-)
Signal
Name
(4)
Pin
(1)
S1a
S1b
S2a
S2b
S3a
S3b
S4a
S4b
13
14
15
16
17
18
19
20
Singleended
( 21
8·
9
A
B
'v"'
D
E
F
Differential
Pairs
(3)
Signal
Name
(4)
4( +)
4(-)
5(+)
5(-)
6(+)
6(-)
7(+)
7 (-)
S5a
S5b
S6a
S6b
S7a
S7b
S8a
S8b
mode rejection ratio applications.
Programmable gain.--
A single package that includes
the feedback resistor trimmed for each gain selection
greatly reduces (1) offset between gain selections, (2)
number of components, and (3) size of subsystem.
Instrumentation amplifier selection.--
The Burr-Brovm
3606A instrumentation amplifier was the least expensive
amplifier available (November 1978).
minimum order charge.
The cost exceeded the
The estimated delivery time was six
weeks, but the actual delivery time was ten months.
Amplifier gains.--
The instrumentation amplifier has
two independent gain stages.
The differential gain of the
first stage is determined by the digital inputs at D2 and
D3.
The linear gain of the second stage is determined by
the digital inputs at DO and D1.
The output of the first
stage at J1 iq connected to the input of the second stage
at J2.
The noise at the output of the second stage was
14
excessive for first stage gains of256.
not used in the software programming.
These gains were
The gain truth table
is shovm in Table 2.
External connections.--
The 3606A was externally
connected as recommended in the device specifications.
1.
Digital common and analog common were tied to
ground.
2.
Output references R1 and R2 were tied to ground.
3.
No gain setting resistor was placed between the
optional external gain pins.
4.
The feedback loop of the second gain stage was
closed by connecting the output to the three sense pins S1,
S2, and S3.
5.
The input latch was tied to +5 volts to enable the
digital input from the channel/gain latch to select the
gain.
6.
used.
The first order low pass filter option was not
The low pass filter would affect signal tracking
performance.
Table 2.
Digital
Inputs
D3 D2
( 1)
0
0
0
1
1
0
1
1
Gain Truth Table
Gain
at
J1
(2)
1
4
32
256
Digital
Inputs
D1 DO
(3)
0
0
0
1
1
0
1
1
Gain
at
J2
(4)
1
2
4
4
15
7.
The power supplies were decoupled with tantalum
capacitors.
3.
Sample and Hold
Selection of sample and hold amplifier.--
Many sample
and hold amplifiers are subject to large. minimum order
charges.
The LF398 was selected for its low cost and
availability to the unit buyer.
Selection of the hold capacitor·.--
Sample and hold
circuits require a hold capacitor with a low hysteresis.
The value of the hold capacitor is based on the acquisition
time and the output droop rate.
For this application, the
value of the hold capacitor was not critical.
The 1000
picofarad polystyrene capacitor used in the actual circuit
performed adequately.
4.
Analog-to-Digital Converter
Conversion time.--
The minimum data conversion cycle
was chosen as 100 microseconds for user simplicity.
A 20
microsecond minimum between consecutive conversion periods
is required for a resolution of eight bits.
Therefore,
the conversion period must be 80 microseconds or less.
Resolution of digital result.--
The cost and conver-
sion periods increase with increasing resolution.
Also,
the minimum period between consecutive conversions
increases for resolutions above eight bits.
Two values
of the converter would have to be read and stored by the
microcomputer.
Additional time for the logic control of
16
the output enables would be required.
An 8-bit data word
is the upper limit for a data conversion cycle of 100
microseconds using inexpensive converters.
Component selection.--
The ADC0800 was the lowest
priced device that was available to the unit buyer which
meets the above requirements.
clocks per conversion.
The device requires 40
For the 500 kilohertz clock, the
device required 80 microseconds per conversion.
Converter references.--
Zero and full scale adjust-
ments for the analog-to-digital converter require two
independent adjustable voltages.
The inverting and non-
inverting basic operational amplifier circuits were used
to provide the positive and negative references from a
single zener diode voltage source.
These voltages were
also used as the limits of the window discriminator
circuit.
5.
Input/output
Logic Control and Timing
de~oding.--
The S-100 bus does not
transfer input/output data by memory addresses.
Instead,
256 input ports and 256 output ports transfer data by the
location $FOXX, where XX is the hexadecimal two digit port.
A load command to the location $FOXX enables the signal
SINP.
A store command to the location $FOXX enables the
signal SOUT.
The KIMSI microcomputer interface decodes
input and output ports by the location $FNXX, where N
t'
2, 4, 6, 8, A,
c,
or E.
= 0,
17
Write data enables.--
The circuit design required
seven write data enables to be decoded from the eight least
significant bits of the address bus while the SOUT signal
is high.
The decoded addresses are enabled by the data·bus
phased clock to ensure that no decoding spikes are allowed
on the write enables.
The seven write data enables are of
two types:
1.
Four of the decoded signals are inputs to J-K
flip-flops.
One input will set and another input will
reset the sample/hold flip-flop.
One input will set the
mode flip-flop to the single-ended input mode, and another
will reset it to the differential pair input mode.
enables are clocked on the falling edge of ¢ •
2
The
Refer to
Figure 3 for the timing of the write data bus enables.
2.
Three of the decoded signals are used as enables
to 8-bit bistable latches.
from the data bus.
These latches store the value
One of the latches stores the 4-bit
gain selection input to the programmable gain amplifier,
the 3-bit digital input to the analog multiplexer, and the
bit that is used by the analog switch.
Two of the latches
store 8-bit digital inputs to the digital-to-analog
converters.
Read data enables.--
The circuit design required two
read data enables to be decoded from the eight least sig,....
nificant bits of the address bus while the SINP signal is
high.
Anothert address decoded signal was required to
strobe the start conversion input of the analog-to-digital
18
-J/..,._
__¢_1_ _
,.,..:\'------------....J/
430ns """ ___
\'-+-;________
_...j/"r-- 430ns
rn•n
--~'' ' - - - - -
I
. I
4- 300ns
max ~
'
R/W ..
ADD~tSS
FZ/7/hl
I:
k lOOns~
_i- - - - - ___o_A_T_A_F_R_o_M__M_P_u____~1_______~~··---------~~-----
I
.
tnQ)(
·I
-
hiOO!'\S
__s_o_u_r______________~/~--------------~\'----
&J
_·
\~
{rca)
-_~l_
__.l
_______./
'"----__...j/
WRITE DATA ENABLES
figure 3.
•
r
VJri te Data Bus Enables
19
converter.
Refer to Figure 4 for the timing of the read
data bus enables.
Signal buffers.--
The data bus requires non-inverting
buffers to drive the three standard TTL loads on each line.
Two 7417 (hex buffers/drivers) were chosen for their common
availability.
Each decoded signal requires an inverter
except for the signal CONV-L.
Two 7416 (hex inverter
buffers/drivers) were also chosen for their common availability.
Both devices have open-collector outputs that
require a pull-up resistor connected to the +5 volt power
supply.
Two 1000 ohm dual-in-line resistor packages
(A-B 316A102) were chosen because they require much less
space than discrete components.
External register.--
One of the two read data enables
is used to determine the logic levels of two signals.
One
digital signal is gated onto the data bus during a conversion.
A logic level low indicates that the input signal
is saturated and the value which is read from the analogto-digital converter is invalid.
Another digital signal is
gated onto the data bus just prior to the data acquisition
process.
The program waits until the signal becomes a
logic level high.
After a logic level high has been read,
this signal has no effect on the software.
Clock input for the converter.--
The ADCOSOO has a
maximum clock frequency of 800 kilohertz.
has a frequenqy of 1.0 megahertz.
triggers on the falling edge of ¢2•
The ¢
2
clock
A divide by two circuit
The CLOCK-H signal has
20
' ----------'
-~-'---..~!1
\'-----1
-R/W
i
r//ff/Z/l
I
I
f/777/
I
~!OOMP<-1rr. ""~ ~ !-+- 30n.s
__D_A_T_A__T_O__M_P~U-------+'------------------~~
r::IOOno
\~\L
_R_E_A_D_D_A_T_A_EN_A_S_L_E_s_ ___,/
---~X
t.L oc K- H
Figure 4.
~-------
mo•
j
SINP
tr p
X\...._ _ _ __
Read Data Bus Enables
a frequency of 500 kilohertz.
The decoded signal CONV-L
asynchronousl::,:- sets a flip-flop.
The flip-flop will remain
set until it is clocked by the rising edge of CLOCK-H.
21
CLOCK-H may have a rising edge (Figure 5, Case 1) or a
falling edge (Figure 5, Case 2) during the decoding of
the start conversion strobe.
Address decoding mechanization.--
The present design
incorporates two 74154 1 s (1-of-16 decoder/demultiplexer)
which decode only six of the eight lower address bits.
The 74154 1 s were originally selected for the following
reasons:
1.
Easily obtained at a time when very few 74LS
series parts were available.
2.
Versatility when the number of outputs and the
logic to the enables was unknown.
Address decoding improvements.--
An improvement to
the circuit (actual hardware was not modified due to the
difficulty of implementing changes after the wiring had
been completed) would be the following:
1.
Replace ICS with a 74LS138 (1-of-8 decoder/
demultiplexer) and IC5 with a 74LS155 (dual 2-line to
4-line decoder/demultiplexer).
2.
Add logic to decode all eight lower address bits.
6.
High Voltage Protection
Input voltage limitation.--
The analog-to-digital
converter's voltage input is specified for values between
+5.0 volts and -5.0 volts.
The input limitation was deter-
mined by the input voltage range of the converter when the
i
gain is set to unity.
Each external input is protected by
'
22
\.________.!
\.,___~/
\_
CONV-L
CASE I
\""--_ ______,~{
_c_L_o_c_K_-_H_ ____,/
CONV-H
I
\~--------------------
CASf 2
CLOCK-W
CONV-
\.._____ _----JI
HI
\. .________
figure 5.
Start Conversion Pulse
'
23
1N4001 diodes to +5 volts and to -5 volts.
To limit the
signal after the gain stage, a window discriminator circuit
enables or disables the input signal to the analog-todigital converter.
An analog switch is disabled when the
input is greater than the positive reference or is less than
the negative reference.
The enable signal is also gated
onto the data bus through a buffer.
The maximum tolerances
for each analog device (for valid data) and the maximum
value obtained in the circuit are shown in Table 3.
Table 3.
Analog
Device
( 1)
DG507
LF13331
3606A
LF398
LM311
ADCOBOO
7.
Input Voltage Ranges
for Analog Components
l\iaximum Range
(volts)
( 2)
+15
+10
+10
+15
+15
+5
to
to
to
to
to
to
-15
-10
-10
-15
-15
-5
Range in Circuit
(volts)
(31
+5.7
+5.7
+5.7
+12
+12
+5.0
to
to
to
to
to
to
-5.7
-5.7
-5.7
-12
-12
-5.0
Digital-to-Analog Converters
Separate from data acquisition system.--
The two
digital-to-analog converters are not required for the data
acquisition function, but were included to provide a single
board with both analog inputs and outputs.
Desired qualities.--
The two considerations for this
optional function were cost and size, including all of the
~·
required external components.
For simplicity of software,
24
a device with 8-bit resolution was chosen.
Device selection.--
The DAC90 was selected for the
following reasons:
1.
Low cost when ordered with the Burr-Brown 3606A.
2.
Small size:
3.
Internal reference.
4.
Selectable output voltage range.
5.
Minimal number of external components.
16-pin dual-in-line package.
Each DAC90
requires only one half of a dual operational amplifier, one
potentiometer, one capacitor (additional capacitors are
required on +15 volts and -15 volts), and three resistors.
8.
Requirements.-volt supply.
Power Supplies
The digital components require a +5
The analog components require both +15 volt
and -15 volt supplies.
Additionally, the analog input
protection circuit requires a -5 volt supply.
Voltage Regulator Circuits.--
Voltage regulators
mounted on heat sinks are used to provide the four required
supply voltages.
The three unregulated voltage inputs from
the bus were decoupled with 39 microfarad, tantalum capacitors.
The +5 volt supply is provided by a 7805
voltage regulator connected to the +8 volt unregulated
source.
The +15 volt supply is provided by a 7815 voltage
regulator connected to the +18 volt unregulated source.
The -15 volt supply is provided by a 7915 voltage regulator
connected to the -18 volt unregulated source.
The -5 volt
..
25
supply is provided by a 7905 voltage regulator connected
to the -18 volt unregulated source.
Each regulated voltage
supply is also decoupled by tantalum capacitors.
Addition-
al tantalum and ceramic capacitors are dispersed throughout the board.
Grounds.--
The digital components were connected to
the board's ground plane or ground strips.
One ground
strip was dedicated to the analog components that are
associated with the input signals.
create ground loops.
These strips do not
Also, the analog components were
grouped together to minimize lead lengths and :for greater
noise immunity from the digital components.
CHAPTER I I I
SOFTWARE
1.
r1Iaj or Tasks
System initialization.-address $8000.
The program starts at
The program defines parameters that are
not under user control.
Next, tl,le program gathers all
necessary information from the user to define the parameters that are variables.
Once the user defined parameters
are stored, the data acquisition and display processes
can be repeated without redefining these parameters.
Finally, the temporary counters and registers are initialized.
Data acquisition.--
Two types of data sampling and
display are provided.
1.
For sampling rates that are less than 1 second,
all of the samples are converted and stored in memory prior
to being transmitted to the terminal.
The interval timer
is used to generate interrupt requests which
channels.
sar~le
the
Transmission to the terminal is not permitted
while interrupts are being generated.
The synchronization
between the microcomputer and a terminal is lost when an
interrupt occurs while data is being transferred.
Another
program may be executed during this process.
2.
For sampling rates that are equal to or greater
26
27
than 1 second, each input is sampled and converted to a
digital value.
The value is processed into a signed, four
binary-coded-digit number.
The input number and processed
value are transmitted to the terminal.
The program uti-
lizes wait loops for proper sampling time intervals.
No
other program may be executed during this time.
Data display.--
For sampling rates that are less than
1 second, the data for each channel is processed individually after all samples have been taken.
The digital values
are retrieved in the same order as the samples were taken.
Each value of the first channel is processed into a signed,
four binary-coded-digit number.
to the terminal.
The number is transmitted
Each value is processed and transmitted
until all samples have been displayed.
The second channel
and subsequent channels are likewise displayed.
2.
System Initialization Process
Program procedure.--
The initialization procedure
is the following:
1.
The non-maskable interrupt vector address is set
to the KIM monitor program.
The STOP key can be used prior
to the data acquisition process to alter the JMP instruction at address $0000 to the starting address of another
program or to change the location of the zero offset table.
2.
Address $0000 is loaded with the OPCODE 4C 00 00
which will cause the program to loop on itself.
3.
t
The present channel register and processor status
·.,.
28
register are cleared.
The addresses $0047 and $0048 are
loaded with the ASCII character for a space.
4.
The messages are displayed and the responses are
processed.
5.
The mode flip-flop is set for single-ended inputs
and cleared for differential pair inputs.
6.
Locations $0060 and $0061 are loaded with the
address of the zero offset table.
The table starts at
address $87EO and contains sixteen zeros.
A zero offset
table located in RAH memory locations can be created for
offsets other than zero.
The offsets are in two's comple-
ment and are in the same order as the channels were entered.
7.
11 P.EADY?
8.
The program waits for a Y response to the message
( y) •
II
The memory locations that contain the address
where the next data from the analog-to-digital converter
is to be stored is loaded with the starting address of the
memory locations to be used for data storage.
For a rate
multiplier of one or two, this address is decremented by
one.
9.
The latch which is enabled by the address $F002
is loaded with the input number and gain for the first
channel.
10.
The decimal digit pointer is initialized to
address $8774, the starting address of the binary-codeddecimal equivalence table as shown in Table 4.
~
11.
The present channel register and the counter of
29
·-:.• .
•
the number of samples that have been taken are cleared.
12.
The register that counts the number of interrupts
since the last conversion is set to one.
13.
The address $F010 is read to determine the logic
level of the digital signal STARTCON-H.
A logic level low
will cause the program to repeat this process until a logic
level high is detected.
After these instructions, the
level of the digital signal has no effect upon the program.
14.
The sample/hold flip-flop is set.
The circuit's
output will follow the input voltage.
15.
For sampling rates that are equal to or greater
than 1 second, the program jumps to the data acquisition
process at address $8053.
16.
The sample/hold flip-flop is cleared.
The cir-
cuit's output will remain constant.
17.
The stack pointer is decremented.
The process
of stopping the interrupt process increments the stack
pointer; therefore, the stack pointer requires a preliminary decrement.
18.
The value of the signal OVERFLOW is read from
address $F010 and is stored at address $0049.
19.
The start conversion pulse to the analog-to-
digital converter is created by the address $F018.
20.
A wait loop with eighty instruction cycles allows
the converter to complete the analog-to-digital process.
21.
Agaip the sample/hold flip-flop is set.
22.
The I bit of the processor status register is
•,.
'
..
30
cleared.
The interval timer is set to enable the genera-
tion of interrupt requests.
The timer is set for
e~ght
instruction cycles.
23.
The program jumps to address $0000.
The interrupt
request created by the interval timer will start the
dat~
acquisition process.
Table 4.
Binary-Coded-Decimal Equivalences
Address
(1)
Value
J2)
$8774
$877A
$8780
$8786
$878C
$8792
$8798
251969
125984
062992
031496
015748
007874
003937
I Address I
User defined parameters.--
( l)
$879E
$87A4
$87AA
$87BO
$87B6
$87BC
$87C2
Value
\2)
001969
000984
000492
000246
000123
000062
000031
The follovving questions
must be answered prior to the data acquisition process.
1.
Are the inputs single-ended or differential pairs?
2.
How many channels are to be sampled?
Each differ-
ential pair is counted as one channel.
3.
For each channel, what is its input number and
4.
What is the time period between consecutive
gain?
samples?
5.
How much memory is available for data storage?
6.
How m?DY samples per channel are to be taken?
7.
What is the starting address of the memory
31
locations that are to be used for data storage?
8.
Should the data acquisition process begin?
Messages and responses.--
The program transmits
messages to and receives responses from a terminal.
When
the correct number of input characters is received, a
carriage return is automatically transmitted.
The user may
enter this selection with a carriage return or may select
a different response.
Illegal responses will cause the
message to be repeated, except as noted.
Jl!lessages that
require a response of four hexadecimal digits will only
repeat the FOUR HEX DIGITS portion of the message.
The
messages are shown in Table 5.
1.
Message--
SINGLE-ENDED? (Y OR N).
Response--
Type Y for single-ended inputs or N for differential pair
Table 5.
Address
( 1)
$868A
$86A2
$86AC
$86B8
$86C2
$86D1
$86DB
$86E5
$86FB
$8719
$8727
$8731
$873D
$874C
$875F
$s76B
Printed Hessages
Message
Length
{3)
(2)
23
9
11
9
14
0
~·
9
21
29
13
9
11
14
18
11
6
/SINGLE ENDED? (Y OR NO)
# OF CHS
(01 TO 16)
(1 TO 8)
INPUT NUIVIBER
(0 TO F)
(0 TO 7)
GAIN = 2EXP(O TO 7)
RATE (0=100us, 1=10ms, 2=1s)
X (01 TO 99)
HEH SIZE
SAI'1PLES/CH
STARTING ADDR
(FOUR HEX DIGITS)
READY?
//END/
(Y)
32
inputs.
2.
8).
Nessage--
# OF CHS (01 TO 16) or # OF CHS (1 TO
Differential pair inputs are limited to eight channels.
Response--
Input the decimal number of channels that are
to be sampled.
3.
Nessage--
( 0 TO 7).
INPUT NUJYrBER (0 TO F) or INPUT NUIV.t.BER
Differential pair inputs
lower eight input numbers.
~:_re
Response--
limited to the
Input a hexadecimal
value for the next analog input as shown in Table 1.
An
illegal response will not cause the message to be repeated,
but a legal response is required prior to continuation.
4.
Nessage--
GAIN= 2EXP(O TO 7).
Response--
Input a decimal value as shown in Table 6.
Table 6.
Response
( 1)
5.
Message--
Response--
Gain Selection
Gain
(2)
Response
(1)
0
1
2
1
2
4
6
3
8
7
4
5
Gain
121
16
32
64
128
RATE (0=100us, 1=10ms,2=1s).
Input a 0 or
1
for interrupt generated sampling
or input a 2 for software timed samPling.
6.
I\1essage--
X ( 01 TO 99).
digit decimal number.
t
Response--
Input a two
This number multiplied by the rate
from the previous response will determine the time period
33
between consecutive samples.
It is not the time period
between consecutive samples for a given channel.
7.
Nessage--
NEJ.\1 SIZE (FOUR HEX DIGITS).
Response--
Input the size of the contiguous RAN locations that are·
available for storage of the converted data.
hexadecimal digits.
Use four
For the software timed sampling rates,
this message is not transmitted.
8.
Message--
Response--
SAMPLES/CH (FOUR HEX DIGITS).
Input the number of samples per channel that
are to be taken.
Use four hexadecimal digits.
This number
multiplied by the number of channels is compared to the
amount of memory that is available for data storage.
If
the available memory is the smaller value, the program will
jump back to the previous message.
9.
Iflessage--
Response--
STARTING ADDR (FOUR HEX DIGITS).
Input the lowest address of the contiguous
memory locations to be used for data storage.
hexadecimal digits.
Use four
For software timed sampling rates,
this message is not transmitted.
10.
Message--
READY? (Y).
Response--
to start the data acquisition process.
Input a Y
No carriage return
is required by this message.
Memory location of system parameters.--
The system
parameters are stored in the zero page memory locations.
The advantages are that both the memory size and the
execution time is reduced.
f
For clarity of this report,
these memory locations have been given a name as shown in
34
Table 7.
Software implementation for messages.-tine MESSAG uses eleven subroutines.
The subrou-
Each subroutine
loads the starting address of its message into the 16-bit
register OUT.
The starting address contains the number of
characters that are to be transmitted.
The subroutine
PRTCHS is used to execute the transmission of the message.
This subroutine uses the microcomputer provided subroutine
at address $1EAO to transfer a value in the accumulator
onto the 20 milliampere current loop.
Software implementation for responses.--
The eleven
subroutines used by MESSAG have different requirements for
Table 7.
Zero Page Address Registers
Number
Address
of
start-·end;ncr
ina bvtes
{ 1)
(3)
(2)
20
30
32
34
36
38
39
3A
3A
3B
3C
3D
3E
40
41
49
4A
2F
31
33
35
37
3B
3F
46
16
2
2
2
2
1
1
2
1
1
1
1
2
1
6
1
1
,,
Name
(4)
CHANNEL
BLOCK
!POINTER
I NUMBER
COUNTER
NOOFCH
NOWCH
PRODUCT
REGISTERA
REGISTERB
TYPE
BIT COUNT
DDPOINT
SIGN
BCD
OVFLO\v
IVIULT
Number
Address
of
start- ending
ing bytes
(3)
(1)
(2)
4B
4C
4D
4E
4F
53
54
56
57
58
59
5A
5B
5D
5F
60
52
55
61
1
1
1
1
4
1
2
1
1
1
1
1
1
1
1
2
Name
(4)
MULTX
Bil'lGAIN
ZERO
PASS
TEMP IN
LAST
OUT
I COUNT
IRATE
IRQ RATE
ERROR
INPNUM
OUTCOUNT
CONDATA
DELAY
OFFSET
35
the number and type of inputs.
Each subroutine, except
READY, uses the subroutine READ to input the responses.
The microcomputer contains a subroutine located at address
$1E5A that will transfer an ASCII coded character on the
20 milliampere current loop to the accumulator.
The
subroutine READ inputs the character, masks the parity bit,
and stores the results.
After the requested number of
characters (a'maximum of four) is received, a carriage
return is automatically generated.
Next, the user must
provide a carriage return to exit from the subroutine and
continue the program.
Any other response will reset the
subroutine to its initial condition, and the response will
be processed as the first character.
A carriage return
provided at an incorrect time will reset the subroutine
to its initial condition.
A flow chart of the subroutine
PASS is shovm in Figure 6.
Hexadecimal resoonses.--
Hexadecimal responses
require a conversion from the ASCII coded value to a
hexadecimal value.
Additionally, some hexadecimal re-
sponses require a conversion from four ASCII coded values
into two hexadecimal values.
These conversions are done
by the following programs:
1.
The subroutine HEXDIG (1) masks the four most
significant bits (msb) for a numerical response,
(2) masks
the five msb and adds nine for an alphabetical response,
or (3) sets an error detection
e
hexadecimal response.
regist~r
for a non-
The 4-bit result is stored in the
36
I
X -
pass
0
=
0
tE-------· A
Call subroutine
at address $1E5A:
Input character is
stored in ACC
Mask parity bit
yes
no
>----.A
Call subroutine
CRLF: Transmit
a carriage return
~
Figure 6.
Flow Chart of the subroutine READ
37
accumulator.
This 4-bit value is shifted four times to
the left and stored at REGISTERA.
The error detection
register is cleared at the beginning of this subroutine.
2.
valu~s
The subroutine GETHEX requests four hexadecimal
from the user.
Each input is converted to a hexa-
decimal number by the subroutine HEXDIG.
The shifted
result of the first input is combined with the non-shifted
result of the second input and stored in the high byte of
the 16-bit register BLOCK.
The shifted result of the
third input is combined with the non-shifted result of
the fourth input and stored in the low byte of the 16-bit
register BLOCK.
The subroutine GETHEX is repeated after
an error has been detected.
A non-zero value in the reg-
ister ERROR shows that an error has been detected.
Message subroutines.--
The eleven subroutines which
communicate with the user are as follows:
1.
The subroutine SNGEND initializes the mode to
either single-ended or differential pair.
read and compared to Y or N.
One input is
For a Y response, the reg-
ister TYPE is loaded with a value of zero.
For anN
response, the register is loaded with a non-zero value.
2.
The subroutine NUiviSNG is called when the first
response is Y.
Two input characters are read.
The second
input is converted to a hexadecimal value by the subroutine HEXDIG.
This subroutine is repeated after an error
has been deteq,ted or vv-hen the value is not a decimal value.
If the first input is the ASCII coded character for 0, then
38
the number of channels is the previous decimal value.
If
the first input is the ASCII character for 1_, then the
number of channels is the previous decimal value plus ten.
The number of channels is stored at register NOOFCH.
If
the first input is not zero or one, then the subroutine
is repeated4
The number of channels is checked4
If it is
equal to zero or greater than sixteen, then the subroutine
is repeated.
Next, the subroutines GETSIN and GETG are
used to define the input number ru1d gain for each channel.
These two subroutines are repeated until all channels have
been defined.
3.
The subroutine GETSIN uses the subroutine GETCH
to get the input number for the present channel.
character is read.
One input
The subroutine GEXDIG is used to con-
vert and store the response as a hexadecimal value in the
four msb locations at REGISTERA.
The subroutine GETCH is
repeated after an error has been detected.
4.
The subroutine GETG reads one input character,
the gain for the present channel.
The input number which
is stored at REGISTERA is moved to REGISTERB.
The sub-
routine HEXDIG is used to convert the gain into a hexadecimal value.
The subroutine is repeated after an error
has been detected or when the gain is greater than seven.
A
loot-~-up
table (refer to Table 8) starting at address
$87C8 is used to convert the user input to the correct
encoded value .-ror the programmable gain instrumentation
amplifier.
This encoded value is combined with the input
39
Table 8.
Look-up Table for Encoded
Gain Values
X- index
Register
( 1)
Encoded
Value
(2)
0
0
1
1
3
5
2
3
number into a single value.
X-index
Recister
(1)
Encoded
Value
(2)
4
5
6
7
6
8
9
A
This value is stored at the
memory location $0020 offset by the value of NOVJCH, the
register that contains the present channel.
The register
NOWCH is incremented.
5.
The subroutine NUI•IDIF is called when the first
response is N.
One input character is read.
This input is
converted to a hexadecimal value by the subroutine HEXDIG.
This subroutine is repeated after an error has been detected or when the number of channels is greater than
eight.
Next, the subroutines GETDIN and GETG are used to
define the input number and gain for each channel.
These
two subroutines are repeated until all channels have been
defined.
6.
GETSIN.
The subroutine GETDIN is similar to the subroutine
The input number is converted and stored, but the
subroutine GETDIN is repeated when the input number is
greater than seven.
7.
The Sllbroutine
RATE determines which of the three
\
data acquisition programs will be used.
One input is read.
40
For a 0 response, the interrupt rate register, IRQRATE, is
loaded with a value of zero and the interrupt request (IRQ)
vector address is loaded with the address $80F5.
For a 1
response, the register IRQRATE is loaded with a value of
one and the IRQ vector address is loaded with the address
$8108.
For a 2 response, the register IRQRATE is loaded
with a value of minus one.
8.
The subroutine
multiplier.
SID~
determines the sampling rate
Two input characters are read.
The subroutine
HEXDIG is used to convert the first input into a hexadecimal value.
The subroutine is repeated after an error has
been detected or 'Vlhen the value is greater than nine.
value is stored at REGISTERB.
esses in the same manner.
The
The second input is proc-
A hexadecimal value of ten is
added to the accumulator for each count in REGISTERB.
The
result is stored in IRATE, the register which contains the
interrupt rate.
The subroutine SRIVI is repeated when this
value is zero.
9.
The subroutine IvlEIVISIZ uses the subroutine GETHEX
to get the amount of memory locations that are available
for data storage.
The converted data in the 16-bit
register BLOCK is stored in the 16-bit register POINTER.
This subroutine is only used for interrupt generated
sampling rates.
10.
to get the
The subroutine NOSPCH uses the subroutine GETHEX
nu~ber
of samples per channel to be taken.
converted data in the register BLOCK is stored in the
The
41
16-bit register NUMBER.
The registers NOWCH, which con-
tains the present channel number, and COUNTER, v;hich
contains the total number of samples to be taken, are
cleared.
The value that is still in the 16-bit register
BLOCK is multiplied.!/ by the register NOOFCH, which contains the number of channels.
The result is stored in the
16-bit register COUNTER, the register which contains the
total number os samples to be taken.
If the carry bit is
set after the addition with the high byte of COUNTER, then
the error detection register is incremented.
The 16-bit
register COUNTER is compared to the 16-bit register POINTER.
If the total number of samples to be taken is greater than
the amount of memory locations that are available for data
storage, then the error detection register is incremented.
This subroutine is only used for interrupt generated
sarnp ling rates.
The subroutine IVIES SAG will repeat the
subroutines IviEl'llSIZ and NOSPCH after an error has been
detected.
11.
The subroutine !liSA uses the subroutine GETHEX to
get the starting address of the data storage memory block.
The converted data in the 16-bit register BLOCK is stored
at the correct location.
This subroutine is only used for
interrupt generated sampling rates.
The subroutine VISA is
repeated after an error has been detected.
Halt until
the~
is ready to oroceed.--
The
1./N. Ivlorris l'1qr:tO, Computer System Architecture, Prentice-
Hall, Inc., Englewood Cliffs, New Jersey, 1976, pp 367-369
42
subroutine READY is used prior to the data acquisition
process and prior to the display of the data taken for each
channel.
The subroutine uses the microcomputer provided
program at address $1E5A to input an ASCII coded character.
For a Y response, the program continues.
For any other
response, the subroutine is repeated.
3.
Data Acquisition by Interrupt Request
Interrupt program procedure.-is generated by the interval timer.
An interrupt request
After the first inter-
rupt, the two programs RATEO and RATE1 reset the interval
timer to have an approximate period of 100 microseconds
and 10 milliseconds, respectively.
The IRQ vector at
addresses $17FE and $17FF contains the address of either
RATEO or RATE1.
A flow chart of the interrupt request
programs is shown in Figure 7.
These programs use the
following procedure:
1.
Count the number of interrupts that have occurred
since the last sample was taken.
2.
When this number equals the sampling rate multi-
plier value, take an input sample and store the previously
converted value in memory.
3.
The interval timer is loaded with a value that
will provide the next interrupt request.
Return to the
program that was being executed.
4.
When all samples have been taken, break the inter-
rupt cycle and start the data display process.
43
ICOUNT
=
ICOUNT - 1
no
yes
Call subroutine CONYER:
take an input sample
and store the previous
sample
sample
RAT EO only
Set interval timer J
~
( Return
Figure 7.
J
Flow Chart of the Interrupt
Request Programs
Input sampling.--
The subroutine corNER is used to
sample the input for the present channel and store the data
from the previous channel.
is shown in Figure 8.
A flow chart of this subroutine
A list of the addresses that are
decoded in the hardware is shown in Table 9.
The input
sampling procedure is the following:
1.
The address bus decodes the signal HOLD-H.
signal clears the sample/hold flip-flop.
This
The output of
the sample/hold circuit will remain constant.
2.
The address bus decodes the signal DATA-H.
This
signal enables the A/D converter's digital outputs onto
the data bus. • This value is from the previous conversion.
44
A
ACC =
=
POINTER
=
I NOWCH
POINTER + 1
t
+ 1
no
memor
COUNTER =
A
Change return
address to $8118
Disable interval
timer
Load new input number
and gain into ACC
Store the new input
number and gain into
the hardware latch
ICOUNT
=
IRATE
interrupt
Figure 8.
Flow Chart of the Subroutine CONVER
The value is stored in the accumulator.
3.
The address bus decodes the signal CONV-L.
signal sets the start conversion pulse flip-flop.
f
This
The
output of the flip-flop is the start conversion pulse to
45
Table 9.
Decoded Addresses
Address
(1)
Signal
Name
(2)
Function
(3)
FOOO
FOOl
F002
F004
F005
F006
F007
FOOB
FOlO
F018
SAN!PLE-H
HOLD-H
CHGAIN-H
DTOAl-H
DTOA2-H
DIFFII10DE-H
SNGMODE-H
DATA-H
EXTREG-H
CONV-L
Sample/hold circuit to sample input
Sample/hold circuit to hold output
Latch input number and gain
Latch data for D/A converter #1
Latch data for D/A converter #2
Analog switches: S2 closed, 83 open
Analog swithces: S3 closed, S2 open
Read data from A/D converter
Read OVERFLOW-L and STARTCON-H
Set start conversion pulse flip-flop
the analog-to-digital converter.
The flip-flop is self
resetting.
4.
If the signal OVERFLOW-L was low during the previ-
ous conversion, then a key value is stored in the accumulator.
The key value indicates that the output of the gain
amplifier exceeded the acceptable range.
5.
The value of the accumulator is stored at an
address that is computed from the 16-bit register POINTER.
This value is either the data from the previous conversion
or the key value.
6.
The 16-bit register COUNTER, the number of samples
per channel that have been taken, is compared to the 16-bit
register NUMBER, the number of samples per channel to be
taken.
The two registers are equal after all samples have
been taken.
7.
•
If the two registers are equal, then the return
46
address is pulled from the stack.
A return address of
$8118 and a value of zero are pushed onto the stack.
interval timer's interrupt capability is disabled.
The
After
the execution of the return from interrupt, the program
will jump to address $8118.
8.
The address bus decodes the signal EXTREG-H.
This signal enables the signal OVERFLOW-L onto the MSB of
the data bus.
The value of the data bus is stored at the
memory location OVFLOW.
9.
The 16-bit register POINTER, the register which
contains the address where the next data will be stored,
is incremented.
10.
The value of NOWCH, the present channel indica-
tor, is incremented.
If this new value is equal to the
value of NOOFCH, the number of channels, then the register
NO\IJCH is cleared and the 16-bi t register COUNTER is incremented.
11.
The value of the memory location $0020 offset by
the value of the next channel is loaded into the accumulator.
12.
The address bus decodes the signal CHGAIN-H.
This signal enables the appropriate 8-bit bistable latch.
The data bus contains the input number and encoded gain
value for the next channel.
13.
The sampling rate multiplier factor is stored
in the samplin,g rate multiplier counter.
14.
The subroutine returns to the interrupt request
47
program.
4.
Display of Interrupt Requested Data
Data display process.--
The program PROCES (located
at address $8118) converts and displays the stored data by
channels.
results.
9.
This program can be repeated with identical
A flow chart of this program is shovm in Figure
The program uses the following procedure:
1.
The register NOWCH, the present channel indicator,
is cleared.
\l.}'hen all the data for a channel has been
displayed, the register NOWCH is incremented in the subroutine BINBCD.
I NOWCH = o]
NEXT. • • . • • . • . • • • . . •
I
POINTER = BLOCK +
NOWCH
*
* =
I. COUNTER
------~~~~-------J
r
0
I
Call BINBCD:
convert and transmit
one value to the
terminal
no
Jump to
monitor program
~
Figure 9.
Flow Chart of the Program PROCES
48
2.
The value of NOWCH is added to the 16-bit register
POINTER.
The register POINTER now contains the starting
address of the first data for the present channel.
3.
The 16-bit register COUNTER is cleared, and the
register OUTCOUNT, outputs per line counter, is loaded
with a value of five.
4.
The subroutine BINBCD is used to convert one
binary value into a displayed BCD number.
This subroutine
is repeated until all of the data that was taken for a
channel has been displayed.
Then, the return address from
the subroutine BINBCD is changed to address $811C.
process is repeated for subsequent channels.
This
Vlhen all
data has been displayed, the overflow bit of the status
register is set.
5.
\Vhen the overflow bit is set, the program trans-
mits a message to the terminal.
The program jumps to the
KIIVI monitor program at address $1COO.
The task has been
completed.
Binary-to-BCD conversion.--
The subroutine BINBCD is
used to convert binary data into displayed BCD values.
flow chart of this subroutine is shown in Figure 10.
A
The
subroutine uses the following procedure:
1.
cleared.
The register OVFLOW, the overflow indicator, is
The accumulator is loaded with the data at an
address that is computed from the 16-bit register POINTER.
This value is
~ither
or the key value.
the data from the previous conversion
p •
49
2.
If the data is equal to the key value, then the
register OVFLOW is loaded with the ASCII coded character
for an asterisk.
3.
The subroutine GF;AG is used to convert the data
Call subroutine GHAG:
convert one data into
BCD digits
~
Call subroutine TTY:
convert BCD digits into
ASCII coded values
~
Call subroutine OUTPUT:
output ASCII coded
values to the terminal
COUNTER == COUNTER + 1
( NOidCH
=
NOvJCH + 1
L_---.
no
POINTER = POINTER +
number of channels
yes
Change return
address to
NEXT ($811C)
Figure 10.
Flow Chart of the Subroutine BI:NBCD
50
from a single binary value into six binary-coded-decimal
digits plus the sign.
4.
The subroutine TTY is used to convert the indi-
vidual digits into ASCII encoded values.
5.
The subroutine OUTPUT is used to organize the
information to be displayed and transmit data to a terminal.
6.
The 16-bit register COUNTER, the number of values
that have been displayed for the present channel, is
incremented and compared to the 16-bi t register NUf1BER,
the number of samples per channel.
7.
If these 16-bit registers are equal, the value of
NO\'lCH, the present channel indicator, is incremented.
If
the value of NOV!CH is not equal to the number of channels,
then the return address is changed to the address $811C
and a return from subroutine operation is executed.
If
the two values are equal, the overflow bit of the status
register is set and a return from subroutine.operation is
executed.
8.
The value of the number of channels is added to
the 16-bit register POINTER.
The register pointer now
contains the address where the next data taken for the
present channel was stored.
Stored data processing.--
The subroutine GHAG
processes the data that was stored from the output of the
analog-to-digital converter.
'
routine is shown in Figure 11.
A flow chart of this subThe subroutine uses the
51
Call subroutine PARAHS:
get new values for
DINGAIN
and ZERO
A
Get data by indirect
addressing of POINTER
Subtract z_ero_ offset
value
I
Call subroutine BCDADD:
add value from BCD
equivalences table to
BCD reaisters
yes
Call subroutine NE\tlBIT:
add 6 to DDPOINT
BITCOUNT
Invert
bits
and add one
no
B
Call subroutine FSGAIN:
multiply MULT times
HULTX and store result
in PRODUCT
X
=
decoded
ga~n
Shift right PRODUCT
X number of times
DDPOINT = ~;8774
Clear BCD registers
and BI TCOUNT
-
B
Shift left PRODUCT
f
Figure 11.
A
Flow Chart of the Subroutine GI'IiAG
52
following procedure:
1.
The memory location which contains the sign of
the data is loaded with the ASCII coded character for a
plus sign.
2.
The decimal mode bit of the status register is
cleared.
3.
The subroutine PARAHS is used to update those
parameters which are channel dependent.
New values for
the registers BIT·JGAIN, MULTX, and ZERO are determined.
The X-index register is loaded with the number of the
present channel.
The data from the memory location $0020
offset by the value of the present channel is loaded into
the accumulator.
This value is masked to produce only
the encoded gain.
This value is stored in the register
BIT,JGAIN and the X-index register.
Data from the full scale
gain table offset by the encoded gain value is stored in
the register NULTX.
The full scale gain table has a start,j.,
ing address of $87FO.
Since all full scale gains were
close to the mathematically calculated gains, a gain of
unity is provided in the table.
All sixteen locations of
the table contain the hexadecimal value of' $80.
The values
in the table are 8-bit unsigned, magnitude numbers.
4.
The accumulator is loaded with the data at an
address that is computed from the 16-bit register POINTER.
5.
The data from the analog-to-digital converter has
a complementary binary format.
The value of the zero
offset is subtracted from the data.
For negative voltages,
--
-
-
-
·-
-
-
---
-
--
.
--
53
the register that contains the sign of the data is loaded
with the ASCII coded character for a minus sign.
of the data is masked.
The MSB
For negative voltages only, the
remaining data bits are inverted and a value of one is
added.
This unsigned, magnitude value is stored in the
register MULT.
6.
The 16-bit register PRODUCT is cleared.
The
subroutine FSGAIN is used to multiply the register MULT
(the unsigned, magnitude value) and the register MULTX,
the full scale gain factor.
16-bit register PRODUCT.
unsigned, magnitude value.
overflow.
The result is stored in the
The high byte result is a 7-bit
This value is checked for an
Since all values of the register MULTX are the
hexadecimal value $80, the final result in the high byte
is identical to the original data that is stored in the
register MULT.
The value in the low byte of the register
PRODUCT will be zero.
7.
The X-index register is loaded with the value of
the encoded gain.
The data from the decoded gain table
offset by the value of the encoded gain is loaded into the
accumulator.
The decoded gains are shown in Table 10.
This value, the decoded gain, is stored in the X-index
register.
The 16-bit register PRODUCT is shifted to the
right by the value of the decoded gain.
The carry bit
from the high byte is shifted into the MSB of the low byte.
8.
set.
The 9ecimal mode bit of the status register is
For addition of two decimal values, the decimal mode
______._
~-
----------
----
-~--
-----
54
Table 10.
X- index
Register
Offset
Look-up Table for Decoded Gains
(2)
(3)
Encoded
Gain
(1)
0
1
0
1
0
1
-
2
3
Encoded
Gain
(1)
Decoded
Gain
4
4
5
5
2
2
2
3
6
6
7
4
4
-
X- index
Register
Offset
Decoded
Gain
(2}
(3)
8
9
8
9
6
A
A
-
5
7
7
8
9
A
A
B
c
.-,
D
E
F
bit must be set.
9.
The 16-bit register DDPOINT, the decimal digit
pointer, is loaded with the value of the starting address
of the binary-coded-decimal equivalences table.
This
table starts at address $8774 and is shown in Table 4.
10.
The six memory locations that store the BCD
digits, address $0041 through address $0046, and the
register BITCOUNT are cleared.
11.
The bits in the high byte of PRODUCT are shifted
to the left.
When the MSB is equal to one, the subroutine
BCDADD is used to add the values from the decimal equivalences table to the six memory locations that store the
BCD digits.
of five.
The Y-index register is loaded with a value
The carry bit is cleared.
The accumulator is
loaded with the data from a memory location.
The address
of this memory location is computed from the 16-bit reg~
ister DDPOINT offset by the value of the Y-index register.
55
This value is added to the address $0041 offset by the
value of the Y-index register.
For values that are greater
than one BCD digit, the carry bit is set and the four IvlSB 1 s
are masked.
location.
The carry bit is added to the next memory
The result is stored at the address $0041 offset
by the value of the Y-index register.
The Y-index register
is decremented, and the process is repeated until six
values have been added.
12.
The subroutine NEWBIT is used to advance the
16-bit register DDPOINT to the next location in the binarycoded-decimal equivalences table.
The decimal mode bit
and the carry bit of the status register are cleared.
A
binary value of six is added to the 16-bit register
DDPOINT.
The decimal mode bit is set.
13.
The register BITCOUNT is incremented.
14.
The process shown in steps 11, 12, and 13 are
repeated until the value of BITCOUNT equals seven.
15.
A similar process is used for the bits in the
low byte of PRODUCT.
16.
The decimal mode bit is cleared.
ASCII coded output characters.--
The subroutine TTY
converts the four memory locations which store the BCD
digits into ASCII encoded values.
Each of the four memory
locations has the hexadecimal value of $30 added to its
value.
Transmis~ion
of outputs.--
The subroutine OUTPUT
organizes the information and data to be displayed.
A
·-
56
flow chart of this subroutine is shown in Figure 12.
The
subroutine uses the following procedure:
1.
The decimal mode bit is cleared.
2.
The value of the present channel indicator is
compared to the input number counter.
When the two values
are not equal, a new heading for the next channel is transmitted.
When the two values are equal, the subroutine
skips to step 8.
3.
The input number counter is loaded with the value
of the present channel indicator.
4.
A carriage return and the character # are trans-
mitted to the terminal.
5.
The input number for the present channel is
computed and compared to the hexadecimal value $OA.
For
values less than $OA, the hexadecimal value of $30 is added
to the value.
The result is an ASCII coded number.
For
values equal to or greater than $0A, the hexadecimal value
of $37 is added to the value.
The result is an ASCII
coded letter.
6.
The input number and two spaces are transmitted
to the terminal.
7.
If the register IRQRATE, the interrupt rate
indicator, is a positive value, then the subroutine READY
is used to halt the display process until the user is
ready to proceed.
8.
The t;'•lO remaining memory locations which store
the BCD digits are loaded with the ASCII coded character
57
yes
no
NOWCH
Transmit a carriage return
and the symbol #
Convert the input
number into an ASCII
coded number or letter
Call subroutine READY:
wait for user response
Last two BCD digits made
equal to the ASCII coded
character for a space
Transmit sign, BCD digits,
and decimal point
After five data have been
transmitted, transmit a
carriage return
Figure 12.
Flow Chart of the Subroutine OUTPUT
for a space.
9.
The
d~ta
is transmitted in the sequence (1) sign
58
of the value, (2) first BCD digit, (3) decimal point, (4)
second BCD digit, (5) third BCD digit, (6) fourth BCD
digit,
(7) a space,
and (8) a space.
For overflow detected
values, the sign is replaced with the ASCII character for
an*
10.
If the register IRQRATE is a negative value,
then a carriage return is transmitted and a return from
subroutine operation is executed.
11.
The register OUTCOUNT, outputs per line counter,
is decremented.
When the counter equals zero, the counter
is loaded with a value of five and a carriage return is
transmitted.
The data is displayed with five data samples
of a single channel per line.
5.
Data Acquisition and Display
by Software Generated Data
Timing procedure.--
The program RATE2 is used for
sampling rates from one to ninety-nine seconds.
The input
is sampled, processed and transmitted to the terminal
prior to the time for the next input sample.
The timing
procedure is the following:
1.
Count the number of seconds that have occurred
since the last sample was taken.
2.
\vhen this number equals the sampling rate multi-
plier value, take an input sample and transmit the processed value to the terminal.
3.
Load 1 the wait loop counter with four.
Load the
interrupt disable interval timer with a value that will
_.
59
count one quarter of a second.
The program loops for one
second.
Input sampling procedure.--
\f.hen the sampling rate
multiplier counter has a value of zero, the program uses
the following procedure:
1.
The interrupt bit of the status register is set.
No interrupt requests are allowed to disrupt the synchronization between the microcomputer and the terminal.
2.
The interval counter is loaded with a value that
will count one quarter of a second.
When the time that
is required to transmit the message is greater than one
quarter of a second, the timing sequence is adjusted.
3.
The overflow register is cleared and the address
bus decodes the signal HOLD-H.
The output of the sample
and hold circuit will remain constant.
4.
After an aperture time delay, the address bus
decodes the signal CONV-L.
This signal creates the start
conversion pulse to the analog-to-digital converter.
5.
'l'he program waits for 80 microseconds to provide
the necessary conversion time for the analog-to-digital
converter.
During this time, the address bus decodes the
signal EXTREG-H.
If the signal OVERFLO\tl-L is low, then the
value of the data bus (a non-zero value) is loaded into the
overflow register.
6.
The address bus decodes the signal S.Al'JJPLE-H.
output of the .sample and hold circuit will follow the
input voltage.
The
60
7.
The address bus decodes the signal DATA-H.
The
digital output of the analog-to-digital converter is temporarily stored.
8.
The decimal mode bit is cleared.
9.
·when the value of the overflow register is not
zero, the four memory locations which store the BCD digits
and the memory location which stores the sign are loaded
with the ASCII coded character for an *
The program skips
to step 15.
10.
The register which contains the sign of the value
is loaded with the ASCII coded character for a plus sign.
11.
The subroutine
PARM~S
is used to update those
parameters which are channel dependent.
12.
The digital output of the analog-to-digital
converter which was temporarily stored is loaded into the
accumulator.
13.
The subroutine GMAGC (address $81F2) is used
to convert the data from a single binary value into six
binary-coded-decimal digits plus the sign.
The program
skips the first six operations of the subroutine GMP.G
(address $81E6).
14.
The subroutine TTY is used to convert the indi-
vidual digits into ASCII encoded values.
15.
The subroutine OUTC (address $8310) is used to
organize the information to be displayed and transmit data
to a terminal.
The program skips the first nine operations
of the subroutine OUTPUT (address $82FD).
The data is
61
transmitted in the sequence (1) input number,
(3) sign of the value,
point,
(4) first BCD digit,
(2) a space,
(5) decimal
(6) second BCD digit, (7) third BCD digit, (8)
fourth BCD digit,
(9) a space,
(10) a space, (11) a car-
riage return.
16.
The present channel indicator is incremented
and compared to the register which stores the number of
channels.
17.
When the two values are equal, the present
channel indicator is cleared and the 16-bit register
COUNTER is incremented.
18.
The 16-bit register COUNTER, the number of
samples per channel that have been taken, is compared to
the 16-bi t register NUI'1BER, the number of samples per
channel to be taken.
The two registers are equal when
all samples have been taken.
19.
If the two registers are equal, then the program
transmits a message to the terminal.
The
progr~n
to the KIIVi monitor program at address $1COO.
jumps
The task
has been completed.
20.
The data from the memory location a;o020 offset
by the value of the next channel is loaded into the accumula tor.
21.
The address bus decodes the signal CHGAIN-H.
This signal enables the appropriate 8-bit bistable latch.
The data bus contains
the input number and encoded gain
t
value for the next channel.
62
22.
The sampling rate multiplier counter is loaded
with the value from the sampling rate multiplier factor.
23.
The interrupt bit o:f the status register is
cleared.
24.
The interrupt disable interval timer is read.
I:f the transmission of data to the terminal requires more
thcw.'l one quarter of a second, the program jumps to the
beginning of RATE2.
I:f the transmission of the data to
the terminal requires less than one quarter of a second,
the program waits for the interval timer to indicate that
one quarter of a second has elapsed.
The wait loop counter
is loaded with a value of three, and the timing procedure
is continued.
CHAPTER IV
RESULTS AND CONCLUSION
1.
Results of the Hardware Design
Analog gain.--
The 3606 instrumentation amplifier
is specified with a maximum gain error of 0.02% and a
maximum zero offset error of 0.04 times the gain plus 2
millivolts.
The eight measured DC gains of the 3606
instrumentation amplifier mounted on the breadboard are
shown in Tab+e 11.
The measured gain errors were equal
to or less than 0.5%.
Table 11.
Gain
(1)
1
1
2
2
4
4
8
8
16
16
32
32
64
64
128
1?8
The eight measured DC zero offset
Tvieasured Amplifier Gains
Input
(2)
+100.1mV
-100.4mV
+100.1mV
-100.4mV
+100.1mV
-100.4mV
+100.0mV
-100.4mV
+100.0mV
-100.4mV
+100.1mV
-100.4mV
+100.0mV
-100.4mV
+50.0mV
-50.0mV
Output
(3)
Me asured
Gain
(4J
Error
+100mV
-100mV
+199mV
-202mV
+400mV
-401mV
+799mV
-804mV
+1. 60V
-1. 61V
+3.20V
-3. 21V
+6.38V
-6.43V
+6.37V
-6.41V
1.00
1.00
1. 99
2.01
4.00
3.99
7.99
8.01
16.0
16.0
32.0
32.0
63.8
64.0
127.4
128.2
0.0%
0.0%
0.5%
0.5%
0.0%
0.3%
0.1%
0.1%
0.0%
0.2%
0.0%
0.0%
0.3%
0.0%
0.5%
0.2%
63
(5)
64
errors during two independent measurements are shown in
Table 12.
Table 12.
Gain
(1)
Specified
Zero
Offset
(2)
1
2
4
8
16
32
64
128
+2mV
+2mV
"+2mV
+2mV
+3mV
+3mV
+5mV
+7mV
Measured Amplifier
Zero Offsets
J'ileasured
Zero
Offset
(3)
Ivleasured
Zero
Offset
(4)
+1.1mV
+O.OmV
+0.8mV
-0. 6mV
-3.5mV
-1. 9mV
-6.1mV
-14. 6mV
+1.1mV
-0.1mV
+0.8mV
-0.7mV
-3. 6mV
-2.0mV
-6.4mV
-15.0mV
Analog-to-digital conversion.--
The ADC0800 is
specified with a maximum non-linearity error and zero
offset error of +2 least significant bits.
The maximum
non-linearity error is approximately 1.6%.
The maximum
gain error for the digital output is the sum of the maximum gain error of the amplifier plus the non-linearity
of the analog-to-digital converter.
This error is approx-
imately 2%, and was used to specify the output error as
shown in Table 13.
The zero offset error can be elimi-
nated by the software program.
Common mode rejection.--
The 3606 instrumentation
amplifier is specified with a minimum of 80 dB from a 1000
t
ohm source imbalance.
For the differential pair input
65
Table 13.
Digital Output Specifications
Gain
( 1)
Input
Range
( 2)
1
2
4
8
16
32
64
128
+5.00V
+2.50V
+1. 25V
"+625mV
+312mV
-+156mV
+78mV
+39mV
Resolution
(31
Output
Error
(4)
39mV
19mV
10mV
5mV
2mV
1mV
1mV
1mV
+100mV
+50mV
+25mV
+13mV
+7mV
"+4mV
"+2mV
"+1mV
-
mode and a gain of unity, the output of the amplifier
measured 1.0 millivolts for input voltages of +5.00 volts,
+0.00 volts, and -5.00 volts.
The common mode voltage is
insignificant compared to the non-linearity of the analogto-digital converter.
Dynamic response.--
The 3606 instrumentation arnpli-
fier has a typical +1% response of 8 kilohertz for gains
up to 128.
The maximum sampling rate is 10 kilohertz.
Therefore, the maximum small signal frequency is 5 kilohertz.
Digital-to-analog conversion.--
The two digital-to-
analog converters' digital inputs are complementary offset
binary coded.
The data for converter #1 and #2 are latched
by writing into address locations $F004 and $F005, respectively.
The digital-to-analog converters provide an out-
put voltage range from +5.00 volts to -5.04 volts.
The
t'
vieight of the LSB is 39 millivolts.
The analog outputs
66
Table 14.
Digital-to-Analog Converter
Transfer Characteristics
Digital
Input
Codes
1'1SB to LSB
(1)
(2)
00000000
00000001
01111111
10000000
11111111
are specified to within
+Yz
output
Range
_(Volts)
+5.00
+4.96
+0.00
-0.04
-5.04
LSB accuracy.
The transfer
characteristics are shown in Table 14.
2.
Results of the Software Programs
Sampling rates for multiples of 100 microseconds.-The two possibilities are as follows:
1.
A data sample is not required at the time of the
interrupt.
The number of execution cycles required for
an interval timer generated interrupt request is not
specified.
Therefore, the value that is stored into
address location $170C was experimentally determined.
Hexadecimal values of $44, $45, and $46 produced an interrupt rate of 98 microseconds.
Hexadecimal values of $47,
$48, and $49 produced an interrupt rate of 101 microseconds.
An interrupt rate of 101 microseconds was sel-
ected.
2.
A data sample is required at the time of the
interrupt.
After a conversion, the interrupt program
67
repeats instead of returning to the program that had been
interrupted.
Therefore, the number of clock cycles to
complete the present instruction of the program which had
been interrupted end the number of clock cycles for the
interrupt request instruction are not included in determining the sampling rate.
One hundred and three clock
cycles are required to complete the interrupt program.
The calculated interrupt rate is 103 microseconds.
After
the last channel has been sampled, an additional thirteen
clock cycles are required.
The calculated interrupt rate
between the conversion of the last channel and the first
interrupt associated Vli th the first channel is 116 microseconds.
The real time interrupt rate for one channel at
the highest
sa~pling
rate was experimentally determined
to be 116 microseconds.
Sampling rates for multiples of 10 milliseconds.-Tv;enty-nine clock cycles are required to complete the
interrupt program and return to the program which had been
interrupted.
The interval timer is set for one hundred
fifty-six multiplied by sixty-four clock cycles.
The
hexadecimal value of $9C is stored into address location
$170E.
seconds.
The calculated interrupt rate is 10.013 milliThe real time interrupt rate was experimentally
determined to be approximately 10.02 milliseconds.
Sampling rates for multiples of 1 second.--
The
number of cloql{: cycles during a conversion is insignificant
compared to the number of clock cycles during the delay
68
loops.
The delay loops are approximately one quarter of
a second.
The interrupt disable interval timer is set for
two hundred and forty-four multiplied by one thousand and
twenty-four clock cycles.
The hexadecimal value of $F4.
is stored into address location $1707.
repetition rate is 0.2499 seconds.
The calculated
The loop is repeated
four times to achieve a 1 second rate.
Data display messages.--
Eleven characters are trans-
mitted per data display message.
of eleven bits.
Each character consists
The time required for the display of one
message is 121 divided by the baud rate.
The baud rate of
the terminal can cause errors in the software generated
timing:
1.
For baud rates of 110, each displayed message
will require 1.10 seconds.
The 1.10 seconds will be
counted as 1.00 seconds by the software.
2.
For baud rates of' 300, each displayed message
will require 0.40 seconds.
The 0.40 seconds will be
counted as 1.00 seconds by the software.
This rate cannot
be used.
3.
For baud rates of 600 or greater, each displayed
message will require less than 0.25 seconds.
These baud
rates have correct software timing.
3.
Conclusion
The intent of the project was to build a breadboard
f,
model of a complete microprocessor controlled data acqui-
...
.
·~g
sition system and develop the software programs to control
the system.
The breadboard in conjuncture with a S-100
bus connected to the KIMl microcomputer through an interface and the system software stored in the microcomputer's
memory does successfully accomplish the intent of the
project.
APPENDIX A
HARD\A!ARE SCHEMATIC
The circuit schematic was organized. into the following subsystems:
1.
Input multiplexer circuit.
2.
Input amplifier, sample
e~d
hold circuit, and
the high voltage protection circuit.
3.
Analog-to-digital converter and the external
register.
4.
Address decoding and the data enables.
5.
Logic control.
6.
Data bus latches and buffers.
7.
References for the analog-to-digital converter.
8.
Digital-to-analog converter circuits.
70
~
71
tN400l
-ISV
V2 2.7
tN400I
v,
~NO
-tt~V
\2
-
DG507CJ
v..~
\3 tJ/c
IC2
DQ
28
Db
2
A2 At A¢l fN
EC4ch inp:..tt protec.te:c.t by
IN4001 diode
+o
Q
15 16 \7
18
r.u.
+SV ond -5V
CH2-H~------------------~
C.H l~ H ">-----------------'
C.H~-H;:>>----------- · - - - - "
+15'1 -ISV
__gf_s9
3
'--....o...t
CHA·H·-~>--
St
~
~ L,-
Vee v£E VR
Dl
2.
1-'-'--"'"'T----+-
+iN
--+---1-ttNI
...__._........::~~- S2
LF
02 . . .7_...._,r--?-.
- tN
DPAIR- H>-----+---8~ tNl IH31
1
--1 --~
53
SNG·H>-·------+----......;9~ U.JJ
4
~---'~s4
6
CHB-H >--·-------'~ IN4
D3
IC 3
D4
Input multiplexer circuit
10
.
72
+IN
S.GK..n.
3606A
lO
Mot> I
-IN
s~~no.l
(-15V to i-ISV)
&AIN3-H ~---------'
E:AIN2-H ~----------'
GAINI-H
>----------...._.j
GAIN$·H
.J>--------·---·
-4-ISV -15V
Vet Vn
Si'3nol
lF 13'331
(·lSVto +JSV)
s
14
!C4 VR
54
o.;+sd oJjyst
JN4
+ISv' .tSV
4
v,N
Si<Jnol
(-~Vto tSV)
~AMPLE
/HOL.D
IOK.A i-SV
+RE~
\r-0
H ish volt"l)e.
prc;"tec.. ticn
~
+lSV
O'VERFLOW
-I~V
circ""·,t
7
-REF >~----------------------·--~
Input amplifier, sample and hold circuit,
and the high voltage protection circuit
73
oVERFlOW
">------.. . .S~
9
51"ARICON- H
fXTREG-H
N/C
91
EOC
t
-+REF
s
-~EF
5
CONV-H
6
CLOCK-H >
ll
>
11
VtN
MSB -1
2
R-N~TWORK
C.LK
-3
2
-4
I
DI4
-s
17
013
2
ADC0800
2
2
·..:--- l6
v,N
2
1 OE
DATA-H
017
-2. 3
2
VREF
sc
4
IC2l
2.
-7
~DII
JJ
~Dl¢1
300..n.
to% i}w
-\SV
~
Analog-to-digital converter and the external register
74
+SV
12 Gncl
2
74154
IC8
A2®
74\6
7416
3
j
20
D
4
21
c
s
4
~
P.ll.
DTOAI-H
1. P.V.
•
,. DTOA2-H
6
Al
A
23
7
Write dQta
bus eno bles
4>z >--·-------.J
+SV
.fu_ ~,2
_ 20 D Vt.c
21
1------1
22
A ""l/~
"&-
Gnd Q>
c 74154
IC 5
DATA-II
B
23 A
3
CON\'-· L.
Reqd dqtf:t
bus enabk~.
51tJP
75
14 J
SAMPLE-H >---:....:..j
\2
SAMPLE/HOlD
7 J
9
5 N& MODE- H..,.__.t----t
1/Z Q
SNG- H
\/2. Q.
74LS73
CP
3 K IC20A
flo
2.
P.o.
74 L.S 73
(f
!C206
Q8
\0 K
Dl FF MODE ·H >-~~
OPAIR-H
RD
6
P.U.
P.l.l.
f5V
t-::--t-~~ ClOCK·- H
5
CP
lClSA
·,
Qo
12.
D &
...r:1/2.
9
-=-· -- 74L.S74~ i-=-----11
CP
1wes
-~r
I ~P.O.
Logic control
--1---~
C.ONV-H
~
76
C.HA-H
D0
1C6 74\7
~07
7
7416
2Q4 17
2Q3 18
OO~·DG
~
IC.lJ
00~·
~DS
li04.G;\~~ ~·
-~04
oo3~P.v.
..
89
2
OOl~·u.
88 3 B 4
0
0
tt
IQ2 4
5
c
6
t>o~·
.
r.u.
36
9
D
8
.
Gt\IN3· H
6AlN 2- H
GAiN\·H
GAIN~-H
- DO
..f-SV 24
D·2
7
r---'--..:..1!.---
DA 0 NE7- H
~,";;"""----- DAO N E6- H
J"j:7---.::-
DO!~·U.
35
8
tQ4 20
IQ3 )9
-
D2
Ill
CH \-)-{
CH4>-H
03
I A
•'
D3,.r-"_
CH2-H
2Q2 9
2Ql
CHB-H
·
IC.IO 7417
01
IC16
r.:>_ _ ___.,._ DAO NE5- H
~--:---- DAONE4· H
CO
he-=-o----DZ
01
74100
DO
DAO NE3- H
til;-;;9---~ [)A ONE 2· t!1
t""r.,:::----____,.;- OA 0 NE \ - H
t-;5;----__.,_. 0 AO Nt ¢- H
---,;;--r-:~-___J
DATW07·H
17
IC.l2
DZ
74100
g
8
20
DATW06-H
'
OATW05-H
~
t>P~TW04·H
DATW03· H
CATW02··H
l>ATWO 1~ H
19
t>l
4
DO
DTOA2-H>- •
a
a
5
12.
Data bus latches· and buffers
)r
DATWO~-~
.
77
l
I
IK.n.
t
References for the analog-to-digital converter
78
16 Btil (Ms6)
DAONE7-H
DAONEG-H
I SIT2.
DAONE 5-H
2 Bli3
l 81T4
DAONE4- H >
aov
RQ"'Se
20V II N/c.
1\Gn~
+!SV
ADC 90
13
4 BITS
DAONE3-H
DAON£2-H
5 BIT6
6 BIT7
7 81'T 8
DAONE I· H
f)AONE4>·U
1/2
LM747
I~
IC14
I
I Jul'tlptY
Goi,
CorniM" Adj
RS
9
O.U\(t
Qdjwst
6
Vou"tl
-\SV
l K..n.
6.8KA
DATW07-H > - -If
'CA iWOG-H
DATWO S·H
2
OATW04 -H
3
DATW03-H
4
OATW02· H
~ATWCJ· H
DATWO<!>-H
,
ADC90
10
IC II
'S
I
6
I Ju,.fV
'7
<6
,Rb
O·Hst.t
odjwst
-15V
IK ..n.
6.8 K4
Digital-to-analog converter circuits
6
Vout 2,.
APPENDIX B
ASSEMBLY LANGUAGE PROGRAM
The software program format for each line is (1} the
hexadecimal address,
(3) the label,
comments.
(2) the operation code and operands,
(4) the assembler instructions, and (5) and
Two blank lines are provided between programs
or subroutines.
COLDST
8000
8002
8005
8007
800A
800D
8010
8012
8014
8017
8019
801C
801E
8020
8022
A9
8D
A9
8D
20
20
AS
DO
8D
FO
8D
A9
85
A9
85
00
FA
lC
FB
62
08
3C
05
07
03
06
EO
60
87
61
8024
8027
802A
802B
802E
8030
8032
8035
8038
8039
803A
803D
803F
8042
8044
8045
20
20
B8
8D
AS
10
4C
8D
EA
48
AD
85
8D
A2
CA
DO
AS 83
77 83
17
17
83
84
FO
FO
00 FO
58
03
53 80
01 FO
DIF
CALIB
WARMST
INTRAT
10 FO
49
18 FO
10
WT
FD
LDAIM $00
STA $17FA
LDAIM $1C
STA $17FB
JSR PGZERO
JSR MESSAG
LDAZ $3C
BNE DIF
STA $F007
BEQ CALIB
STA $F006
LDAIM $EO
STAZ $60
LDAIM $87
STAZ $61
JSR READY
JSR INTIAL
CLV
STA $FOOO
LDAZ $58
BPL INTRAT
JMP RATE2
STA $FOOl
NOP
PHA
LDA $F010
STAZ $49
STA $F018
LDAIM $10
DEX
BNE WT
79
NMI VECTOR ADDRESS=
KIM MONITOR
INITIALIZE ADDRS
PRINT MESSAGES
MODE
MODE = 0? NO, JUMP
SET MODE FLIP-FLOP
JUMP
CLEAR MODE FF
ZERO OFFSET TABLE
$8760
= ADDR
INITIALIZE REGS
SET S/H TO SAMPLE
INTERRUPT REG
INTERRUPTS?
NO, JUMP
SET S/H TO HOLD
APERTURE TIME DELAY
PUSH ACC ON STACK
EXTREG
OVERFLOW REGISTER
START CONV (A/D)
WAIT
FOR
CONVERSION
80
8047
804A
804B
8040
8050
80
58
A9
8D
4C
00 FO
8053
8055
8057
8059
805B
BOSE
8060
8062
8065
8067
8069
806C
8060
806F
8072
8074
8076
8079
807A
807B
807E
8080
8082
808S
8087
8089
808B
8080
8090
8093
8095
8096
8098
809A
809C
809E
80AO
80A1
80A3
80A6
80AB
80AA
BOAD
BOAF
eoB2
SOBS
C6
FO
A9
85
56
15
04
3B
07 17
FB
F4
07 17
3B
F2
53 80
AD
10
A9
80
C6
DO
4C
78
A9
8D
A9
85
8D
EA
EA
8D
A9
85
AD
30
85
C6
DO
8D
AD
85
DB
A5
FO
A9
A2
01
OD 17
00 00
RATE2
STORE
WAITQS
TAKE
F4
07 17
00
49
01 FO
18 FO
05
SF
10 FO
02
49
SF
FS
00 FO
08 FO
SD
DCON
DEL
NO'l'FL
49
oc
2A
05
95 41
CA
10 FB
4C BS
A9 2B
85 40
20 DB
AS SD
20 F2
20 CA
20 10
BACK
80
NOFL
82
81
82·
83
OUT
STA $FOOO
CLI
LDAIM $01
STA $1700
JMP $0000
SET S/H TO SAMPLE
YES, CLEAR I BIT
ENABLE INTERVAL
TIMER INTERRUPTS
WAIT STATE
DECZ $56
BEQ TAKE
LDAIM $04
STAZ $3B
LDA $1707
BPL WAITQS
LDAIM $F4
STA $1707
DECZ $3B
BNE WAITQS
JMP RATE2
SEI
LDAIM $F4
STA $1707
LDAIM $00
STAZ $49
STA $FOOl
NOP
NOP
STA $F018
LDAIM $05
STAZ $SF
LDA $F010
BMI NOTFL
STAZ $49
DECZ $SF
BNE DEL
STA $FOOO
LDA $F008
STAZ $SD
CLD
LDAZ $49
BEQ NOFL
LDAIM ~*
LDXIM $05
STAZX $41
DEX
BPL BACK
JMP OUT
LDAIM ~+
STAZ $40
JSR PARAMS
LDAZ $50
JSR GMAGC
JSR TTY
JSR OUTC
INTERRUPT COUNTER
CONVERSION TIME?
'NO
WAIT LOOP
READ TIMER
TIMER MSB = 0?
NO
TIMER = $F4
DECREMENT WAIT LOOP
WAIT LOOP = 0?
YES, REPEAT
DISABLE INTERRUPTS
TIMER
= $F4
OVERFLOW REG = 0
SET S/H TO HOLD
APERTURE TIME
DELAY
START CONV (A/D)
A/D CONV DELAY
EXTREG
OVER RANGE?
YES, OVERFLOW REG
A/D CONV DELAY - 1
DELAY = 0?
YES, S/H TO Sk~PLE
GET A/D DATA
STORE CONVDATA
CLEAR DECIMAL MODE
OVERFLOW REG = 0?
NO, A = *
X = 5
BCD DIGIT #X = *
X =X - 1
X LESS THAN 0?
YES, JUMP
SIGN = +
UPDATE PARAMETERS
DATA AVERAGE
CONVERT TO BCD
ASCII ENCODED
SERIAL ASCII OUT
81
SOBS
80BA
80BC
80BE
80CO
80C2
80C4
80C6
80CB
BOCA
BOCC
BOCE
BODO
80D2
80D4
80D6
80D9
BOOB
BODE
80EO
80E2
80E3
80E6
80E8
80EB
80EE
80FO
80F2
E6
A6
E4
DO
A2
86
E6
DO
E6
AS
C5
DO
AS
C5
DO
4C
B5
8D
AS
85
58
AD
FO
4C
AD
10
A9
4C
80F5
80F7
80F9
80FC
80FF
8102
8104
8107
C6
DO
20
80
4C
A9
BD
40
56
09
43 81
00 FO
F5 80
47
oc 17
8108
810A
BlOC
810F
8112
8114
8117
C6
DO
20
SD
A9
80
40
56
06
43 81
00 FO
9C
OE 17
8118
811A
811C
811D
A9 00
85 39
18
AS 39
39
39
38
OA
00
39
36
02
37
36
34
09
37
35
03
39 81
20
02 FO
57
56
F3
03
53
07
FB
03
59
NOTF
NOTG
17
80
17
WAIT
80
RATEO
MICRO
RATEl
MSEC
PROCES
~
NEXT
INCZ $39
LDXZ $39
CPXZ $38
BNE NOTF
LDXIM $00
STXZ $39
INCZ $36
BNE NOTF
INCZ $37
LDAZ $36
CMPZ $34
BNE NOTG
LDAZ $37
CMPZ $35
BNE NOTG
JMP END
LDAZX $20
STA $F002
LDAZ $57
STAZ $56
CLI
LDA $17F3
BPL WAIT
JMP RATE2
LDA $1707
BPL WAIT
LDAIM $03
JMP STORE
PRESENT CHANNEL + 1
NUMBER OF CHANNELS
FIRST CHANNEL
COUNTER (L) + 1
COUNTER (H) + 1
COUNTER (L)
NUMBER (L)
EQUAL?
YES, COUNTER (H)
NUMBER (H)
EQUAL? NO, JUMP
ALL DATA TAKEN
GET CHANNEL & GAIN
LOAD CH/GAIN REG
INTERRUPT RATE
INTERRUPT COUNTER
ENABLE INTERRUPTS
NO, READ TTY DELAY
TIMER MSB = 0?
NO, REPEAT
YES, READ TIMER
TIMER MSB = 0?
NO
JUMP
DECZ $56
BNE MICRO
JSR CONVER
STA $FOOO
JMP RATEO
LDAIM $47
STA $170C
RTI
INTERRUPT COUNTER
CONVERSION TIME?
CONVERSION
SET S/H TO SAMPLE
REPEAT
DECZ $56
BNE MSEC
JSR CONVER
STA $FOOO
LDAIM $9C
STA $170E
RTI
INTERRUPT COUNTER
CONVERSION TIME?
CONVERSION
SET S/H TO SAMPLE
LDAIM $00
STAZ $39
CLC
LDAZ $39
INITIALIZE PRESENT
CHANNEL REGISTER
INTERVAL TIMER
INTERRUPT RETURN
INTERVAL TIMER
INTERRUPT RETURN
PRESENT CHANNEL
82
811F
8121
8123
8125
8127
8129
812B
812D
812F
8131
8133
8136
8138
8139
813B
8130
8140
65
85
A9
65
85
A9
85
85
A9
85
20
50
B8
A9
85
20
4C
8143
8146
8149
814C
814E
8150
8152
8154
8156
8158
815A
815C
815E
8160
8162
8163
8164
8165
8167
8168
816A
816B
816D
816E
8171
8172
8175
8177
8179
817B
8170
817F
8181
8183
8D
AD
8D
A4
30
A9
A2
81
AS
30
32
00
31
33
00
36
37
OS
SB
99 81
FB
6B
54
NEXBCD
END
co
83
00 lC
01 FO
08 FO
18 FO
49
02
FF
00
32
36
cs 34
DO 16
AS 37
cs 35
DO 10
68
68
68
A9 81
48
A9 18
48
A9 00
48
AD 06 17
40
AC 10 FO
84 49
E6 32
DO 02
E6 33
E6 39
A6 39
E4 38
30 OA
CONVER
NOTA
NOTB
NOTC
ADCZ $30
STAZ $32
LDAIM $00
ADCZ $31
STAZ $33
LDAIM $00
STAZ $36
STAZ $37
LDAIM $05
STAZ $5B
JSR BINBCD
BVC NEXBCD
CLV
LDAIM $6B
STAZ $54
JSR PRTCHS
JMP $1COO
ADD TO START ADDR
MEMORY POINTER (L)
ADD CARRY TO
START ADDR (H)
MEMORY POINTER (H)
STA $FOOl
LOA $F008
STA $F018
LDYZ $49
BMI NOTA
LDAIM $FF
LDXIM $00
STAIX $32
LDAZ $36
CMPZ $34
BNE NOTB
LDAZ $37
CMPZ $35
BNE NOTB
PLA
PLA
PLA
LDAIM $81
PHA
LDAIM $18
PHA
LDAIM $00
PHA
LDA $1706
RTI
LDY $F010
STYZ $49
INCZ $32
BNE NOTC
INCZ $33
INCZ $39
LDXZ $39
CPXZ $38
BMI NOTD
SET S/H TO HOLD
PREVIOUS VALUE(A/D)
START CONV (A/D)
PREVIOUS VALUE
OVER RANGE?
YES, VALUE=KEY
STORE VALUE AT
MEMORY POINTER
COUNTER (L)
NUMBER (L)
EQUAL?
YES, COUNTER (H)
NUMBER (H)
EQUAL? NO, JUMP
COUNTER = NUMBER
DISGUARD PRESENT
RETURN ADDR
COUNTER (L) = 0
COUNTER (H) = 0
BCD CONVERSIONS/
PRINTED LINE
BIN IN TO BCD OUT
REPEAT FOR ALL DATA
MESSAGE AT $876B
KIM MONITOR PROGRAM
NEW RETURN ADDR
CLEAR FLAG REGISTER
DISABLE TIMER
RETURN ADDR ($8118)
EXTREG
OVERFLOW REG
MEMORY POINTER (L)
MEMORY POINTER (H)
PRESENT CHANNEL + 1
NUMBER OF CHANNELS
83
8185
8187
8189
818B
818D
818F
8191
8194
8196
8198
A2
86
E6
DO
E6
B5
8D
AS
85
60
00
39
36
02
37
20
02 FO
57
56
8199
819B
819D
819F
81A1
81A3
81A5
81A7
81AA
81AD
81BO
81B1
81B3
81B5
81B7
81B9
81BB
81BD
81BF
81C1
81C3
81C4
81C6
81C8
81CA.
81CC
81CE
81CF
81DO
81D2
81D4
81D6
81D8
81DA
81DC
81DD
81DE
81DF
81E1
81E2
81E4
A2
86
A1
C9
DO
AO
84
20
20
20
18
E6
DO
E6
AS
00
49
32
FF
04
2A
49
E6 81
CA 82
FD 82
36
02
37
36
cs 34
DO 06
AS 37
cs 35
FO OD
18
A.S 38
65 32
85 32
90 02
E6 33
BB
60
E6 39
AS 39
cs 38
DO 05
A9 7E
69 7E
60
68
68
A9 81
48
A9 1B
48
NOTD
BINBCD
OKGMAG
UPNUM
INCMEM
NEXTDA
NEXTCH
NEX
t;
LDXIM $00
STXZ $39
INCZ $36
BNE NOTD
INCZ $37
LDAZX $20
STA $F002
LDAZ $57
STAZ $56
RTS
LDXIM $00
STXZ $49
LDAIX $32
CMPIM $FF
BNE OKGMAG
LDYIM "'*
STYZ $49
JSR GMAG
JSR TTY
JSR OUTPUT
CLC
INCZ $36
BNE UPNUM
INCZ $37
LDAZ $36
CMPZ $34
BNE INCMEM
LDAZ $37
CMPZ $35
BEQ NEXTCH
CLC
LDAZ $38
ADCZ $32
STAZ $32
BCC NEXTDA
INCZ $33
CLV
RTS
INCZ $39
LDAZ $39
CMPZ $38
BNE NEX
LDAIM $7E
ADCIM $7E
RTS
PLA
PLA
LDAIM $81
PHA
LDAIM $1B
PHA
FIRST CHANNEL
COUNTER (L) + 1
COUNTER (H) + 1
GET CHANNEL & GAIN
LOAD CH/GAIN REG
INTERRUPT RATE
INTERRUPT COUNTER
RETURN
CLEAR OVERFLOW REG
MEMORY POINTER (L}
CHECK FOR KEY
OVERFLOW REG = *
CONVERT TO BCD
ASCII ENCODED
SERIAL ASCII OUT
COUNTER (L) + 1
COUNTER (H) + 1
COUNTER (L)
NU~lBER (L)
EQUAL?
YES, COUNTER (H)
NUMBER (H)
NEXT CHANNEL?
NO
NUMBER OF CHANNELS
MEMORY POINTER {L)
II
II
NEW n
CHECK FOR CARRY
f.1EMORY POINTER (H)
RETURN
PRESENT CHANNEL
NUMBER OF CHANNELS
REPEAT UNTIL
PRINTING COMPLETE
SET V=1
RETURN
DISGUARD
RETURN ADDR
~
84
BlES
60
BlE6
BlEB
BlEA
BlEB
BlEE
BlFO
BlF2
BlF3
BlFS
BlF7
BlF9
BlFB
BlFD
BlFF
B201
B203
B205
8207
B209
B20B
B20C
B20E
B210
B212
B214
B216
B21B
B21A
B21C
821E
8220
8221
B223
B225
B227
B229
B22B
B22E
8230
B233
B234
B236
B23B
B23A
B23B
823D
B23E
B240
B242
B244
A9
B5
DB
20
A2
Al
3B
30
ES
10
30
ES
30
70
10
A9
50
A9
C9
BB
DO
A9
50
C9
10
49
50
A2
86
29
lB
69
BS
A9
B5
BS
20
A6
BD
AA
FO
46
66
CA
DO
FB
A9
B5
A9
B5
RTS
2B
40
GMAG
DB B2
00
32
GMAGC
06
4D
10
04
4D
OA
OB
04
00
02
FF
7F
04
00
11
BO
04
7F
09
SF
40
7F
01
4A
00
3A
3B
Al B2
4C
DO B7
07
3A
3B
NEG
CKV
LLIMIT
CHECKZ
NOTZ
NEGNUM
SKIP A
ROLL
F9
SKIPB
74
3E
B7
3F
LDAIM ... +
STAZ $40
CLD
JSR PARAMS
LDXIM $00
LDAIX $32
SEC
BMI NEG
SBCZ $4D
BPL CHECKZ
BMI CKV
SBCZ $4D
BMI CHECKZ
BVS CHECKZ
BPL LLIMIT
LDAIM $00
BVC CHECKZ
LDAIM $FF
CMPIM $7F
CLV
BNE NOTZ
LDAIM $00
BVC SKIPA
CMPIM $BO
BPL NEGNUM
EORIM $7F
BVC SKIPA
LDXIM $5F
STXZ $40
ANDIM $7F
CLC
ADCIM $01
STAZ $4A
LDAIM $00
STAZ $3A
STAZ $3B
JSR FSGAIN
LDXZ $4C
LDAAX $B7DO
TAX
BEQ SKIPB
LSRZ $3A
RORZ $3B
DEX
BNE ROLL
SED
LDAIM $74
STAZ $3E
LDAIM $B7
STAZ $3F
RETURN ADDR ($BllC)
SIGN = +
CLEAR DECIMAL MODE
UPDATE PARAMETERS
BINARY DATA
CARRY BIT = 1
MSB = 1?
NO, SUB ZERO OFFSET
MSB = 0? YES, JUMP
JUMP
SUB ZERO OFFSET
MSB = 0? NO, JUMP
OVERFLOW? YES, JUMP
MSB = 0? YES, JUMP
OVERFLOW? NO, JUMP
YES
V BIT = 0
DATA EQUALS ZERO?
YES
JUMP
NO
NEGATIVE NUMBER?
NO, INVERT BITS
JUMP
YES
SIGN = DIS GUARD MSB
UNSIGNED BINARY
MULTIPLICAND
PRODUCT (H) = 0
PRODUCT (L) = 0
GET PRODUCT
GET BINARY GAIN
GET EXP GAIN
DATA EQUALS ZERO?
NO, SHIFT RIGHT
TO COMPENSATE FOR
EXP GAIN
X = 0? NO, REPEAT
YES, DECIMAL MODE
STARTING ADDR
FOR DECIMAL
DIGITS (DD) TABLE
.
~
85
tS246
8248
824A
824C
824D
824F
8251
82S3
82SS
8257
825A
825D
825F
8261
8263
8265
8267
8269
8 2_6_B
826E
8271
8273
8275
8277
8279
827B
827C
A9
A2
9S
CA
10
8S
06
AS
10
20
20
06
E6
A9
CS
DO
AS
10
20
20
06
E6
A9
CS
DO
827D
827F
8280
8281
8283
8285
8287
8289
828A
AS
DB
18
69
85
90
E6
F8
60
3E
828B
828D
828E
8290
8293
8295
8297
8299
829A
829D
829E
82AO
AO
18
B1
79
C9
30
29
38
99
88
10
60
OS
BCDADD
3E
41 00
10
03
OF
LOOP IN
41 00
UNDER
00
OS
41
FB
3D
3A
3A
03
BB
70
3A
3D
07
3D
EC
3B
03
8B
7D
3B
3D
OE
3D
EC
REPEAT
LOOPRA
82
82
NOADDA
LOOPRB
82
82
NOADDB
DB
60
NEWBIT
06
3E
02
3F
SDEC
EE
e
LDAIM $00
LDXIM $OS
STAZX $41
DEX
BPL REPEAT
STAZ $3D
ASLZ $3A
LDAZ $3A
BPL NOADDA
JSR BCDADD
JSR NEWBIT
ASLZ $3A
INCZ $3D
LDAIM $07
CMPZ $3D
BNE LOOPRA
LDAZ $3B
BPL NOADDB
JSR BCDADD
JSR NEWBIT
ASLZ $3B
INCZ $3D
LDAIM "$0E
CMPZ $3D
BNE LOOPRB
CLD
RTS
BCD DIGIT tX
X = X - 1
X = 0?
YES, STORE BITCOUNT
PRODUCT {H)
MSB = 0?
NO, ADD BCD DIGITS
ADD TO DD TABLE
PRODUCT (H)
BITCOUNT + 1
BITCOUNT
= 7? NO, JUMP
YES, PRODUCT (L)
MSB = 0?
NO, ADD BCD DIGITS
ADD TO DD TABLE
PRODUCT (L)
BITCOUNT + 1
BITCOUNT
= 14? NO, JUMP
CLEAR DECIMAL MODE
RETURN
LDAZ $3E
CLD
CLC
ADCIM $06
STAZ $3E
BCC SDEC
INCZ $3F
SED
RTS
DECIMAL DIGIT (L)
CLEAR DECIMAL MODE
CARRY BIT = 0
ADD 6 TO DD (L)
NEW DD ADDR
CARRY = 0?
NO, ADD 1 TO DD (H)
SET DECIMAL MODE
RETURN
LDYIM $OS
CLC
LDAIY $3E
ADCAY $0041
CMPIM $10
BMI UNDER
ANDIM $OF
SEC
STAAY $0041
DEY
BPL LOOP IN
RTS
Y INDEX REG = s
CARRY BIT = 0
GET DIGIT #Y
ADD BCD DIGIT #Y +C
DIGIT LESS THAN 10?
NO, DISGUARD 4 MSB
CARRY BIT = 1
BCD DIGIT iY
y =y - 1
Y = POSITIVE NUM?
NO, RETURN
.
86
82A1
82A3
82AS
82A6
82A8
82AA
82AC
82AE
82BO
82B2
82B4
82B6
82B8
82BA
82BB
82BD
82BF
82C1
82C3
82CS
82C7
82C9
A2
AS
18
10
AS
6S
8S
A9
6S
8S
06
26
06
CA
DO
AS
10
A9
A2
86
82CA
82CC
82CE
82DO
82D2
82D3
82DS
82D7
A2
BS
09
9S
EB
EO
DO
60
82D8
82DA
82DC
82DE
82EO
82E1
82E4
82E6
82E8
82EA
82EC
A6 39
BS 20
29 OF
as 4C
AA
BD FO 87
85 4B
A4 39
B1 60
8S 4D
60
82FD
82FF
8300
8302
8304
8306
DB
AS SA
cs 39
FO 2F
AS 39
8S SA
FSGAIN
FSLOOP
08
4B
oc
4A
3B
3B
00
3A
3A
3B
3A
4B
NOAD
E6
3A
08
7F
2A
40
as 3A
60
REGAOK
TTY
THREE
00
41
30
41
04
FS
PARAMS
OFFSET
OUTPUT
f
LDXIM $08
LDAZ $4B
CLC
BPL NOAD
LDAZ $4A
ADCZ $3B
STAZ $3B
LDAIM $00
ADCZ $3A
STAZ $3A
ASLZ $3B
ROLZ $3A
ASLZ $4B
DEX
BNE FSLOOP
LDAZ $3A
BPL REGAOK
LDAIM $7F
LDXIM ~*
STXZ $40
STAZ $3A
RTS
X = 8
MULTIPLIER
CARRY BIT = 0
MSB = 0?
NO, MULTIPLICAND
PRODUCT (L) +
MULTIPLICAND
PRODUCT (H) +
c
SHIFT RIGHT
PRODUCT
SHIFT MULTIPLIER
X = X - 1
X = 0? NO, REPEAT
YES, GET PRODUCT(H)
NO NEGATIVE NUMBERS
LIMIT OF $7F
OVERFLOW; MAKE
SIGN = *
PRODUCT (H) = MAX
RETURN
LDXIM $00
LDAZX $41
ORAIM $30
STAZX $41
INX
CPXIM $04
BNE THREE
RTS
X = 0
BCD DIGIT #X
ASCII NUMBER
LDXZ $39
LDAZX $20
ANDIM $OF
STAZ $4C
TAX
LDAAX $87FO
STAZ $4B
LDYZ $39
LDAIY $60
STAZ $4D
RTS
PRESENT CHANNEL
GET CHANNEL & GAIN
MASK
BINARY GAIN
CLD
LDAZ $SA
CMPZ $39
BEQ MASK
LDAZ $39
STAZ $SA
CLEAR DECIMAL MODE
INPUT NUMBER
PRESENT CHANNEL
= INPUT NUMBER?
NO, PRESENT CH
INTO INPUT NUMBER
X
=X+
= 4?
1
X
YES, RETURN
FULL SCALE GAIN
MULTIPLIER
INDIRECT ADDRESS
FOR ZERO OFFSET
ZERO OFFSET REG
RETURN
.....
87
8308
830B
830D
8310
8312
8314
8315
8316
8317
8318
831A
831B
831D
831F
8321
8323
8326
8329
832C
832E
8330
8333
8335
8337
8339
833B
833D
833F
8341
8342
8345
8347
8349
834B
834E
8350
8352
8354
8356
8358
835A
835C
835E
8361
20
A9
20
A6
BS
4A
4A
4A
4A
C9
18
30
69
10
69
20
20
20
AS
30
20
A9
85
85
A2
AS
DO
BS
E8
20
EO
DO
A9
20
EO
DO
AS
30
C6
DO
A9
85
20
60
BS 83
23
AO 1E
39
20
8362
8364
8366
8368
836A
836C
836E
A9
85
85
A9
85
A9
85
20
47
48
4C
00
00
01
OUTC
OA
04
37
02
30
AO
9E
9E
58
03
AS
20
45
46
00
49
02
40
1E
1E
1E
NUMB
ALPH
83
MASK
LDSIGN
OUTSN
AO 1E
02
05
2E
AO 1E
07
ED
58
08
SB
07
05
5B
BS 83
NODP
SUBCR
SAMELN
PGZERO
t
JSR CRLF
LDAIM ~~
JSR $1EAO
LDXZ $39
LDAZX $20
LSRA
LSRA
LSRA
LSRA
CMPIM $0A
CLC
BMI NUMB
ADCIM $37
BPL ALPH
ADCIM $30
JSR $1EAO
JSR $1E9E
JSR $1E9E
LDAZ $58
BMI MASK
JSR READY
LDAIM $20
STAZ $45
STAZ $46
LDXIM $00
LDAZ $49
BNE OUTSN
LDAZX $40
INX
JSR $1EAO
CPXIM $02
BNE NODP
LDAIM $2E
JSR $1EAO
CPXIM $07
BNE LDSIGN
LDAZ $58
BMI SUBCR
DECZ $5B
BNE SAMELN
LDAIM $05
STAZ $5B
JSR CRLF
RTS
LDAIM $20
STAZ $47
STAZ $48
LDAIM $4C
STAZ $00
LDAIM $00
STAZ $01
PRINT CR & LF
PRINT #
PRESENT CHANNEL
GET CHANNEL & GAIN
SHIFT RIGHT
4 TIMES
CHANNEL ONLY
CARRY BIT = 0
CHANNEL = LETTER?
YES, ASCII LETTER
JUMP
NO, ASCII NUMBER
PRINT INPUT NUMBER
PRINT A SPACE
PRINT A SPACE
GET INTERRUPT RATE
INTERRUPTS?
YES, GO TO READY
ASCII "SPACE"
BETWEEN
OUTPUT VALUES
X = 0
OVERFLOW REG
= 0? NO, JUMP
YES, ASCII DIGIT tx
X =X + 1
PRINT ASCII DIGIT
X = 2? NO, JUMP
YES
PRINT DECIMAL POINT
X = 7? NO, REPEAT
YES, INTERRUPT REG
INTERRUPTS?
YES, OUTPUT COUNTER
= 0? NO, JUMP
YES
OUTPUT COUNTER = 5
PRINT CR & LF
RETURN
ASCII SPACE
TWO SPACES BETWEEN
PRINTED DATA
PROGRAM WILL JUMP
TO ADDR $0000 WHILE
INTERRUPTS ARE
GENERATED. JUMP TO
-.
88
8370
8372
8374
8376
85 02
85 39
85 F1
60
8377
8379
837B
837D
837F
8381
8383
8385
8387
8389
838A
838B
838D
838F
8391
8393
8396
8398
839A
839C
839E
83AO
83A2
A4
A6
AS
C9
FO
C9
DO
EO
DO
88
CA
84
86
A2
BS
8D
A9
85
A9
85
A9
85
4C
82ED
82EF
82F1
82F3
82F5
82F8
82FA
85
85
A9
85
2C
50
60
36
37
01
56
10 FO
FB
83A5
83A7
83A9
83AC
83AF
83B1
83B3
83B5
83B7
83BA
83BC
83BF
A9
85
20
20
29
C9
DO
A9
20
A9
20
60
SF
54
READY
83
SA lE
7F
59
F4
OD
AO 1E
OA
AO lE
GETYES
31
30
57
01
04
02
06
00
01
33
32
00
20
02 FO
74
3E
87
3F
00
39
ED 82
co
INTIAL
DECADR
PGOK
STADDR
CON TIN
WAITT
CRLF
STAZ $02
STAZ $39
STAZ $Fl
RTS
ADDR $0000
PRESENT CHANNEL
CLEAR FLAG REG
RETURN
LDYZ $31
LDXZ $30
LDAZ $57
CMPIM $01
BEQ DECADR
CMPIM $02
BNE STADDR
CPXIM $00
BNE PGOK
DEY
DEX
STYZ $33
STXZ $32
LDXIM $00
LDAZX $20
STA $F002
LDAIM $74
STAZ $3E
LDAIM $87
STAZ $3F
LDAIM $00
STAZ $39
JMP $82ED
Y = BLOCK (L)
X = BLOCK (H)
STAZ $36
STAZ $37
LDAIM $01
STAZ $56
BIT $F010
BVC WAITT
RTS
LDAIM $SF
STAZ $54
JSR PRTCHS
JSR $1E5A
ANDIM $7F
CMPIM .. y
BNE GETYES
LDAIM $0D
JSR $1EAO
LDAIM $0A
JSR $1EAO
RTS
=
0
YES, Y = Y - 1
X = X - 1
POINTER (L) = Y
POINTER {H) = X
1ST CHANNEL & GAIN
LOAD CH/GAIN REG
DECIMAL DIGIT {L)
DECIMAL DIGIT (H)
PRESENT CHANNEL = 0
CONTINUE AT CONTIN
COUNTER = 0
INTERRUPT
COUNTER = 1
CHECK EXTREG FOR
STARTEN = 1
RETURN
MESSAGE AT $875F
GET ASCII INPUT
MASK PARITY BIT
INPUT = Y?
YES
PRINT CR
PRINT LF
RETURN
89
83CO
83C1
83C3
83C5
83C7
83C8
83CA
83CC
83CE
83DO
83D3
83D5
83D8
83DA
83DC
83DE
DB
AO 00
B1 54
85 53
PRTCHS
B1
84
C9
DO
20
A9
20
A4
C4
DO
60
54
F4
OD
05
AO 1E
OA
AO 1E
F4
53
E9
83DF
83E1
83E3
83E6
83E8
83EA
83EC
83EE
83FO
83F2
83F4
83F6
83F7
83F9
83FB
83FE
8400
8403
8405
8407
A2
86
20
29
C9
FO
A4
FO
A2
86
95
E8
E4
DO
20
E6
4C
A4
FO
60
00
4E
SA 1E
7F
OD
17
4E
04
00
4E
4F
8408
840B
840D
840F
8412
8415
8418
841A
841C
841E
8421
8424
8427
20
AS
DO
20
20
20
E4
DO
50
20
20
20
E4
cs
GETNCH
3D
E8
BS 83
4E
E3 83
4E
F4
47
3C
OF
6B
D6
00
38
F6
OD
AD
E8
00
38
84
84
84
85
84
84
85"
NOTCR
READ
NEXTRD
STORE
LF
CR
MESSAG
NEXSCH
DMODE
NEXDCH
CLD
LDYIM $00
LDAIY $54
STAZ $53
INY
LDAIY $S4
STYZ $F4
CMPIM $0D
BNE NOTCR
JSR $1EAO
LDAIM $0A
JSR $1EAO
LDYZ $F4
CPYZ $53
BNE GETNCH
RTS
LDXIM $00
STXZ $4E
JSR $1E5A
ANDIM $7F
CMPIM $0D
BEQ CR
LDYZ $4E
BEQ STORE
LDXIM $00
STXZ $4E
STAZX $4F
INX
CPXZ $3D
BNE NEXTRD
JSR CRLF
INCZ $4E
JMP NEXTRD
LDYZ $4E
BEQ LF
RTS
JSR SNGEND
LDAZ $3C
BNE DMODE
JSR NUMSNG
JSR GETSIN
JSR GETG
CPXZ $38
BNE NEXSCH
BVC GETRAT
JSR NUMDIF
JSR GETDIN
JSR GETG
CPXZ $38
CLEAR DECIMAL MODE
y = 0
DATA POINTER
LAST OUTPUT
y =y + 1
MESSAGE CHARACTER
TEMPORARY STORE Y
CR? NO,JUMP
OUTPUT ASCII CR
LF
OUTPUT ASCII LF
GET Y
Y = LAST
OUTPUT? NO, REPEAT
RETURN
X = 0
PASS = 0
GET INPUT CHARACTER
MASK PARITY BIT
CR? YES, JUMP
NO
PASS = 1?
YES, X = 0
PASS = 0
ADDR = TEMPIN + X
X = X + 1
INPUTS = REQUESTED?
NO, REPEAT
OUTPUT CR & LF
PASS = 1
REPEAT
PASS = 0?
YES, JUMP
RETURN
GET MODE
DIFF PAIR MODE?
NO, GET # OF INPUTS
GET INPUT NUMBER
GET INPUT GAIN
NUMBER OF CHANNELS
ALL CHANNELS?
YES, JUMP
GET # OF INPUTS
GET INPUT NUMBER
GET INPUT GAIN
NUMBER OF CHANNELS
I
90
8429
842B
842E
8431
8433
8435
8438
843B
843D
843F
8442
8443
8446
DO
20
20
AS
30
20
20
A4
DO
20
60
20
60
F6
AF
EE
58
OE
2E
3E
59
F2
7E
3E 86
NO INT
8447
8449
844B
844D
844F
8452
8454
8456
8459
845B
845D
845F
8461
8463
8464
8466
8468
846A
A9
85
A9
85
20
ll.9
85
20
AS
C9
DO
A9
85
60
C9
DO
85
60
BA
54
86
55
SNGEND
83
01
3D
DF 83
4F
59
05
00
3C
GETSD
4E
E7
3C
NO
846B
846D
846F
8472
8474
8476
8479
847B
847D
8480
8482
8484
8486
8489
848B
848D
848F
8491
A9
85
20
A9
85
20
A9
85
20
EO
DO
AS
20
A4
DO
C9
10
85
A2
54
NUMSNG
85
85
GETSIZ
86
86
86
co
co
83
AC
54
co
GETRAT
83
02
3D
DF 83
02
E7
50
84 85
59
DE
OA
DA
38
BNE NEXDCH
JSR RATE
JSR SRM
LDAZ $58
BMI NOINT
JSR MEMSIZ
JSR NOSPCH
LDYZ $59
BNE GETSIZ
JSR MSA
RTS
JSR NOSPCH
RTS
LDAIM $8A
STAZ $54
LDAIM $86
STAZ $55
JSR PRTCHS
LDAIM $01
STAZ $3D
JSR READ
LDAZ $4F
CMPIM .-y
BNE NO
LDAIM $00
STAZ $3C
RTS
CMPIM .-N
BNE GETSD
STAZ $3C
RTS
LDAIM $A2
STAZ $54
JSR PRTCHS
LDAIM $AC
STAZ $54
JSR PRTCHS
LDAIM $02
STAZ $3D
JSR READ
CPXIM $02
BNE NUMSNG
LDAZ $50
JSR HEXDIG
LDYZ $59
BNE NUMSNG
CMPIM $0A
BPL NUMSNG
STAZ $38
ALL CHANNELS?
YES, GET RATE
GET RATE MULTIPLIER
INTERRUPT REG
INTERRUPTS?
YES, MEMORY SIZE
GET DATA I CHANNEL
ERROR REG
ERROR?
NO, GET START ADDR
RETURN
GET DATA I CHANNEL
RETURN
MESSAGE AT $868A
REQUESTED = 1
GET ANSWER
ANSWER = Y?
YES
MODE = 0
RETURN
ANSWER = N?
YES, MODE = N
RETURN
MESSAGE AT $86A2
MESSAGE AT $86AC
REQUESTED = 2
GET ANSWERS
NUMBER OF ASCI I
INPUTS = 2?
YES, GET 2ND ANSWER
ASCII TO HEX
ERROR REG
ERROR?
NO, 2ND INPUT =
A DECIMAL NUMBER?
YES, NUMBER OF CHS
'
91
8493
8495
8497
8499
849B
849D
849E
84AO
84A2
84A4
84A6
84A8
84AA
84AC
AS
C9
FO
C9
DO
18
A9
65
85
AS
FO
C9
10
60
4F
30
OB
31
CE
84AD
84AF
84Bl
84B4
84B6
84B8
84BB
84BD
84BF
84C2
84C4
84C7
84C9
84CB
84CD
84CF
8401
84D3
8405
A9
85
20
A9
85
20
A9
85
20
AS
20
A4
DO
C9
10
85
C9
FO
60
A2
54
8406
8408
84DA
84DD
84DF
84El
84E4
84E7
A9
85
20
A9
85
20
20
60
C2
54
84E8
84EA
84EC
84EF
84Fl
84F3
A9
85
20
A9
85
20
OA
38
38
38
C3
11
BF
co
VALIDA
NUMDIF
83
B8
54
co
83
01
3D
OF 83
4F
84 85
59
E2
09
DE
38
00
08
co
GETS IN
83
Dl
54
co
83
20 85
GETDIN
C2
54
co
83
DB
54
f.
co
83
LDAZ $4F
CMPIM $30
BEQ VALIDA
CMPIM $31
BNE NUMSNG
CLC
LDAIM $0A
ADCZ $38
STAZ $38
LDAZ $38
BEQ NUMSNG
CMPIM $11
BPL NUMSNG
RTS
LDAIM $A2
STAZ $54
JSR PRTCHS
LDAIM $B8
STAZ $54
JSR PRTCHS
LDAIM $01
STAZ $3D
JSR READ
LDAZ $4F
JSR HEXDIG
LDYZ $59
BNE NUMDIF
CMPIM $09
BPL NUMDIF
STAZ $38
CMPIM $00
BEQ NUMDIF
RTS
LDAIM $C2
STAZ $54
JSR PRTHCS
LDAIM $01
STAZ $54
JSR PRTCHS
JSR GETCH
RTS
LDAIM $C2
STAZ $54
JSR PRTCHS
LDAIM $DB
STAZ $54
JSR PRTCHS
1ST ANSWER
ASCII ZERO?
NO
ASCII ONE?
YES, CARRY BIT
=0
ADD 10 TO NUMBER
OF CHANNELS
NUMBER OF CBS = 0?
NO, NUMBER OF CHS
GREATER THAN 16?
NO, RETURN
MESSAGE AT $86A2
MESSAGE AT $86B8
REQUESTED = 1
GET ANSWER
ANSWER
ASCII TO HEX
ERROR REG
ERROR?
NO, ANSWER
GREATER THAN 8?
NO, NUMBER OF CHS
NUMBER OF
CHANNELS = 0?
NO, RETURN
MESSAGE AT $86C2
MESSAGE AT $8601
GET CHANNEL
RETURN
MESSAGE AT $86C2
MESSAGE AT $86DB
~
92
84F6
84F9
84FB
84FD
84FF
20
AS
C9
10
60
2D 85
3A
80
E9
JSR GETCH
LDAZ $3A
CMPIM $80
BPL GETDIN
RTS
8500
8502
8504
8507
8509
850B
850E
8510
8512
8514
8517
8519
851B
851D
851F
8520
8523
8525
8527
8520
852A
852C
A9
85
20
A9
85
20
AS
85
AS
20
A4
DO
C9
10
AA
BD
05
A6
95
E8
86
60
ES
54
GETG
83
01
3D
DF 83
3A
3B
4F
84 85
59
E9
08
ES
GETGN
852D
852F
8531
8534
8536
8539
853B
853D
A9
85
20
AS
20
A4
DO
60
01
3D
DF 83
4F
84 85
59
FO
853E
8541
8543
8545
8548
854A
854C
854F
8551
8554
8556
8558
20
A9
85
20
A9
85
20
AS
20
A4
DO
AS
co
CHANNEL GREATER
THAN 7? YES, REPEAT
NO, RETURN
LDAIM $E5
STAZ $54
JSR PRTCHS
LDAIM $01
STAZ $3D
JSR READ
LDAZ $3A
STAZ $3B
LDAZ $4F
JSR HEXDIG
LDYZ $59
BNE.,,,GETGN
CMP.IM" $08
BPL GETGN
TAX
LDAAX $87C8
ORAZ $3B
LDXZ $39
STAZX $20
INX
STXZ $39
RTS
REQUESTED = 1
GET ANSWER
CHANNEL (4 LSB'S)
SAVE
ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, JUMP
NO, GAIN GREATER
THAN 7? YES, REPEAT
NO, X = GAIN
EXP GAIN TABLE
COMBINE CH & GAIN
PRESENT CHANNEL
CHANNEL/GAIN REG
X =X + 1
NEXT CHANNEL
RETURN
GETCH
LDAIM $01
STAZ $3D
JSR READ
LDAZ $4F
JSR HEXDIG
LDYZ $59
BNE GETCH
RTS
REQUESTED = 1
GET ANSWER
ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
NO, RETURN
83
GETHEX
83
GETH
JSR PRTCHS
LDAIM $4C
STAZ $54
JSR PRTCHS
LDAIM $04
STAZ $3D
JSR READ
LDAZ $4F
JSR HEXDIG
LDYZ $59
BNE GETH
LDAZ $3A
co
C8 87
3B
39
20
39
4C
54
co
GET CHANNEL
04
3D
DF 83
4F
84 85
59
ED
~
3A
~SSAGE
AT $86E5
MESSAGE I
($0054)
MESSAGE AT $874C
REQUESTED = 4
GET ANSWERS
1ST ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
UPPER 4 BITS
'
93
HSSA
. 855C
855E
8561
8563
8565
8567
8569
85GB
856E
8570
8572
8574
8576
8578
857B
8570
857F
8581
8583
85
AS
20
A4
DO
65
85
AS
20
A4
DO
AS
85
AS
20
A4
DO
65
85
60
31
50
84 85
59
EO
31
31
51
84 85
59
D3
3A
30
52
85 85
59
C6
30
30
8584
8586
8588
858A
858C
858E
8590
8592
8594
8596
8597
8599
859B
859D
859F
85Al
85A3
85A5
85A7
85A9
85AB
85AC
85AE
AO
84
C9
30
C9
10
C9
30
29
18
69
90
C9
30
29
85
06
06
06
06
60
EG
60
00
59
3A
OF
47
lC
41
18
07
BSAF
85Bl
85B3
85B6
85B8
85BA
A9
85
20
A9
85
20
STAZ $31
LDAZ $50
JSR HEXDIG
LDYZ $59
BNE GETH
ADCZ $31
STAZ $31
LDAZ $51
JSR HEXDIG
LDYZ $59
BNE GETH
LDAZ $3A
STAZ $30
LDAZ $52
JSR HEXDIG
LDYZ $59
BNE GETH
ADCZ $30
STAZ $30
RTS
HEX DIG
09
06
30
OD
OF
3A
3A
3A
3A
3A
STARA
59
ERRHEX
FB
54
RATE
83
01
3D
f
DF 83
GETRA
co
LESSTH
LDYIM $00
STYZ $59
CMPIM $3A
BMI LESSTH
CMPIM $47
BPL ERRHEX
CMPIM $41
BMI ERRHEX
ANDIM $07
CLC
ADCIM $09
BCC STARA
CMPIM $30
BMI ERRHEX
ANDIM {;OF
STAZ $3A
ASLZ $3A
ASLZ $3A
ASLZ $3A
ASLZ $3A
RTS
INCZ $59
RTS
LDAIM $FB
STAZ $54
JSR PRTCHS
LDAIM $01
STAZ $3D
JSR READ
SAVE AT BLOCK (H)
2ND ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
ADD LOWER 4 BITS
SAVE AT BLOCK (H)
3RD ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
UPPER 4 BITS
SAVE AT BLOCK (L)
4TH ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
ADD LOWER 4 BITS
SAVE AT BLOCK (L)
RETURN
ERROR REG = 0
ANSWER LESS
THAN $3A?
NO, ANSWER GREATER
THAN $46?
NO, ANSWER LESS
THAN $41?
NO, MASK 5 MSB'S
CARRY BIT = 0
ADD 9 TO 3 LSB'S
JUMP
ANSWER LESS
THAN $30?
NO, MASK 4 MSB'S
SAME VALUE IN
UPPER 4 BITS
RETURN
ERROR REG = 1
RETURN
MESSAGE AT $86FB
REQUESTED = 1
GET ANSWER
94
85BD AS 4F
85BF ·C9 3·0
85Cl DO OF
85C3 A9 00
85C5 85 58
85C7 A9 FS
85C9 8D FE 17
85CC A9 80
85CE BD FF 17
85Dl 60
85D2
85D4
85D6
85D8
85DA
85DC
85DF
85E1
85E4
85E5
85E7
85E9
85EB
85ED
C9
DO
A9
85
A9
BD
A9
8D
60
C9
DO
A9
85
60
85EE
85FO
85:E'2
85F4
85F6
85F9
85FB
85FD
8600
8602
8605
8607
8609
860B
860D
860F
8611
8614
8616
8618
861A
861C
861D
861F
8621
A9
85
A9
85
20
A9
85
20
AS
20
A4
DO
C9
10
85
AS
20
A4
DO
C9
10
18
A4
FO
69
LDAZ $4F
CMPIM ~0
BNE ONE
LDAIM $00
STAZ $58
LDAIM $F5
STA $17FE
LDAIM $80
STA $17FF
RTS
31
OF
01
58
08
FE 17
81
FF 17
ONE
32
CA
FF
58
TWO
19
54
87
55
SRM
83
02
3D
DF 83
4F
84 85
59
ED
OA
E9
GETSRM
co
3B
50
84 85
59
DE
OA
DA
3B
06
OA
CKREGB
6
CMPIM ~1
BNE TWO
LDAIM $01
STAZ $58
LDAIM $08
STA $17FE
LDAIM $81
STA $17FF
RTS
CMPIM ~2
BNE GETRA
LDAIM $FF
STAZ $58
RTS
LDAIM $19
STAZ $54
LDAIM $87
STAZ $55
JSR PRTCHS
LDAIM $02
STAZ $3D
JSR READ
LDAZ $4F
JSR HEXDIG
LDYZ $59
BNE GETSRM
CMPIM $0A
BPL GETSRM
STAZ $3B
LDAZ $50
JSR HEXDIG
LDYZ $59
BNE GETSR.t-1
CMPIM $0A
BPL GETSRM
CLC
LDYZ $3B
BEQ BINSRM
ADCIM $0A
ANSWER
ANSWER = 0?
YES
INTERRUPT REG
=0
IRQ VECTOR ADDRESS
= $80F5
RETURN
ANSWER = 1?
YES
INTERRUPT REG
=1
IRQ VECTOR ADDRESS
= $8108
RETURN
ANSWER = 2?
YES, INTERRUPT
REG = -1
RETURN
f.i'.ESSAGE AT $8719
REQUESTED = 2
GET ANSWERS
1ST ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
ANSWER GREATER THAN
9? YES, REPEAT
TENS DECIMAL DIGIT
2ND ANSWER
ASCII TO HEX
ERROR REG
ERROR? YES, REPEAT
ANSWER GREATER THAN
9? YES, REPEAT
CARRY BIT = 0
TENS DECIMAL DIGIT
= 0? YES, JUMP
NO, ADD 10
95
8623
8625
8627
8629
862B
862D
C6
50
85
C9
FO
60
3B
F6
57
00
C9
862E
8630
8632
8635
8637
8639
863B
863D
A9
85
20
AS
85
AS
85
60
27
54
ED 85
30
32
31
33
MEMSIZ
863E
8640
8642
8645
8647
8649
864B
864D
864F
8651
8653
8655
8656
8658
865A
865C
865E
8660
8662
8664
8665
8667
8669
866B
866D
866F
8671
8673
8675
8677
8679
867B
867D
A9
85
20
AS
85
AS
85
A9
85
85
85
18
AS
65
85
AS
65
90
E6
60
85
E6
AS
C5
DO
AS
C5
DO
AS
C5
10
E6
60
31
54
3E 85
30
34
31
35
00
39
36
37
NOSPCH
30
36
36
31
37
03
59
ADDNOS
37
39
39
38
37
33
37
04
32
3(i
02
59
NOTOVR
BINSRM
CKNEG
POSOK
e
DECZ $3B
BVC CKREGB
STAZ $57
CMPIM $00
BEQ GETSRM
RTS
IN,TERRUPT RATE
0? YES, REPEAT
NO, RETURN
LDAIM $27
STAZ $54
JSR GETHEX
LDAZ $30
STAZ $32
LDAZ $31
STAZ $33
RTS
GET 2 BYTE ADDR
GET L BYTE
MEMORY POINTER (L)
GET H BYTE
MEMORY POINTER (H)
RETURN
LDAIM $31
STAZ $54
JSR GETHEX
LDAZ $30
STAZ $34
LDAZ $31
STAZ $35
LDAIM $00
STAZ $39
STAZ $36
STAZ $37
CLC
LDAZ $30
ADCZ $36
STAZ $36
LDAZ $31
ADCZ $37
BCC NOTOVR
INCZ $59
RTS
STAZ $37
INCZ $39
LDAZ $39
CMPZ $38
BNE ADDNOS
LDAZ $33
CMPZ $37
BNE CKNEG
LDAZ $32
Ct-1.PZ $36
BPL POSOK
INCZ $59
RTS
TENS DD - 1
JUMP
=
GET 2 BYTE ADDR
GET L BYTE
NUMBER (L)
GET H BYTE
NUMBER (H)
PRESENT CHANNEL
=0
COUNTER = 0
CARRY BIT = 0
GET L BYTE
ADD TO COUNTER (L)
GET H BYTE
ADD TO COUNTER(H)+C
CARRY BIT = 1?
YES, ERROR REG = 1
RETURN
NO, COUNTER (H)
NEXT CHANNEL
EQUALS NUMBER OF
CHANNELS? NO, NEXT
YES
COUNTER (H) =
MEMORY POINTER (H)?
YES
COUNTER (L) GREATER
THAN MEMORY PT (L)?
YES, ERROR REG = 1
RETURN
96
867E
8680
8·682
8685
8687
8689
A9
8520
A4
DO
60
3D
54
3E 85
59
F5
MSA
LDAIM $3D
STAZ $54
JSR GETHEX
LDYZ $59
BNE MSA
RTS
GET 2 BYTE ADDR
ERROR REG
ERROR? YES, REPEAT
NO, RETURN
APPENDIX C
CALIBRATION
Hard·v:are calibration.--
The potentiometers used for
trimming the gains and offsets of the analog components
should be calibrated once a year to compensate for drift.
Calibration is not required for a change in parameters.
The following method should be used for calibration:
1.
The 1000 ohm potentiometer connected to DS1 pin 2
should be adjusted until the voltage at pin 5 is equal to
the voltage at pin 3.
2.
Initialize the system to sample one input \Iii th a
gain of unity at a rate of 2 seconds.
age to 19. 5 millivolts.
Set the input volt-
Adjust :the 1000 ohm potentiometer
connected to IC25B pin 7 until the displayed value just
changes from +0.000 to +0.039.
3.
Set the input voltage to +4.98 volts.
Adjust the
100,000 ohm potentiometer connected to IC25A pin 2 until
the displayed value just changes from +4.961 to +5.000.
Software calibration.--
The zero offset voltage of
the digital-to-analog converter and any additional offset
errors can be subtracted from all data for an individual
chru1nel.
The memory locations $0060 and $0061 should be
loaded with the starting address of a different zero offset
@
table.
The offsets are in two's complement and are in the
97
98
same order as the channels were entered.
If no zero offset
for a channel is required, then load $00.
Zero offset calibration example.--
An input of zero
volts with a gain of unity produces a displayed value of
-0.039.
This value is equivalent to minus one LSB.
The
memory address in the zero offset table corresponding to
the channel of interest would be made equal to $01 in
order to produce a displayed value of +0.000.
Calibration of the digital-to-analog converters.-The zero offset voltages for the two ADC90 devices were
adjusted to within
Vout
1
±Yz
LSB.
The zero offset voltage at
with a 2.2 megohm resistor at R5 was +10 millivolts.
The zero offset voltage at Vout 2 with a 0.91 megohm resistor at R6 was +3 millivolts.
To calibrate the full scale
gain settings, a value of $00 must be loaded into address
locations $F004 and $F005.
The 1000 ohm potentiometers
connected to IC14 pin 9 and IC11 pin 9 are adjusted until
the voltages at Voutl and Vout 2 are equal to +5.00 volts,
respectively.
To
veri~y
the negative full scale gain
setting, a value of $FF must be loaded into address locations $F004 and $F005.
The voltages at Vou tl and Vou t 2
should be -5.04 volts +0.04 volts.
APPENDIX D
GLOSSARY
ASCII code. American National Standard Code for Informationinterchange. A standard alphanumeric binary
code.
assembly language program. A symbolic program in which
each symbol represents an instruction or operand in
binary code.
baud rate.
- The number of bits of information which are
transmitted over a serial data transmission path
per second.
.
binary coded decimal or BCD. A binary number system in
which a decimal digit is represented by a unique
four-bit code.
common mode rejection ratio.
The ratio of output voltage
of an operational amplifier which is a result of the
voltage common to both inputs compared to the voltage
difference of the two inputs.
interrupt request. An interrupt which can be interrupted
by a higher ordered interrupt.
interrupt vector.
The data contained at an address which
is forced by ha.r·dware when an external signal activates the interrupt cycle.
The data contair.s the
starting addl~ess of the interrupt routine.
interval timer. A hardware counter that is pre-loaded by
the central processing unit and decrements after a
fixed number of clocks.
PRON.
A programmable read-only memory integrated circuit
used for storing information which cannot be altered
by the central processing unit.
RAI~1.
A random-,access memory integrated circuit used for
storing information which can be altered by the
central processing unit.
read data enal::·le.
The enable signal which allmvs data
from·an external latch or register to be transferred
into the central processing unit.
99
100
S-100 bus. A group of 100 wires which transfer binary
information between devices. The connector and some
of the signals have been standardized.
write data enable.
The enable signal which allows data
from the central processing ~nit to be transferred
into an external latch or register.