CALIFORNIA STATE illUVERSITY, NORTHRIDGE
,,
A MICROPROCESSOR SYSTEN FOR
AUTOMATIC IC TESTING
A project submitted in partial satisfaction of
the requirements for the degree of Master of
Science in
Engineering
by
Jose Antonio Pagan-David
~r'"/
June, 1980
The project of Jose Antonio Pagan-David is
approved:
David M. Schwartz
California State University, Northridge
ii
To my wife, Rosa Elena, and my
parents, Alicia and Antonio .Pagan,
iii
TABLE OF CONTENTS
CHAPTER I.
Introduction
Page
1.
Introduction .
1
2.
Objectives . .
5
3.
Report Outline • . .
6
CHAPTER II.
Microcomputer Systems
1.
Microcomputer Organization .
7
2.
Z80 Starter System . • . . .
11
CHAPTER III.
1.
Hardware Development
Hardware Development . •
CHAPTER IV.
21
Software Development
1.
}~in
Program Description
36
2.
Subroutines Description.
40
1.
Set Initial Conditions Subroutine . .
40
2.
Program PIO Subroutine .
42
3.
P - Pattern Subroutine .
45
4.
Test Pattern and Output Subroutine .
49
5.
Clock Pulse Subroutine •
51
6.
Input - Store Subroutine
51
7.
Input- Compare Subroutine
55
8.
Power and Display Control Subroutine .
57
9.
Counter Load Subroutine.
57
10.
Remove IC Subroutine • .
61
iv
CHAPTER V.
1.
System Operational Procedures
Microprocessor System for Automatic IC Testing
Operational Procedures •
Page
63
1.
MONitor Key . . • .
63
2•
MEMory EXAMine Key.
65
3.
REGister EXAMine Key . .
65
4.
EXECute Key • •
66
5.
Cassette Dump . .
66
6.
Cassette Load .
67
7.
ATS Power-up Sequence
68
8.
Using the ATS .
69
9.
Generating Test Patterns to the DUT When ATS
is Operated in Program Mode
• • . •
75
Examining the Responses of the DUT to Test
Patterns.
• . . . .
. . . • • .
78
10.
CHAPTER VI.
Performance Evaluation and Conclusions
1.
System Implementation . •
82
2.
Performance Evaluation •
82
3.
1.
ATS Operating in Learn Mode.
82
2.
ATS Operating in Test Mode •
85
3.
ATS Operating in Program Mode.
88
Conclusions • .
89
LIST OF FIGURES
vi
REFERENCES.
91
APPENDIX A.
APPENDIX B.
Memory Map of Program, Assembly and Machine
Program Listings .
. . . . .
92
110
Data Sheets. • • •
v
LIST OF FIGURES
CHAPTER I
Page
1.1
Typical ATS System Configuration. . . . . . . • . .
3
2.1
Microcomputer System Block Diagram.
8
2.2
Z80 Starter System Block Diagram . •
12
2.3
Z80 Microprocessor Structure • .
2.4
Z80 PIO Block Diagram .
16
2.5
Z80 CTC Block Diagram ••
19
2.6
Z80 Starter System
CHAPTER II
}~mary
....
Map .
14
20
CHAPTER III
3.1
Lines Routed to the Wire Wrap Area for Connection
to Custom Circuitry . • • . •
22
Block Diagram of Circuit Designed in the Z80 Starter
System Wire Wrap Area . . .
• • • • • . . • .
23
Programming PIOs Peripheral Data Lines to Test a
7400 IC . . . • . . • . .
• . . .
24
3.4
Information Obtained from the LED Display
29
3.5
Red LED (5082-4650) Curves
30
3.6
Green LED (5082-4950) Curves.
32
3.7
Yellow LED (5082-4550) Curves . •
33
3.8
DS54450 Peripheral/Power Driver and 712-5
Relay Interconnection • • • • •
34
Components Layout of Circuit Designed in the Z80
Starter System Wire Wrap Area . . • . • . . . • . .
35
3.2
3.3
3.9
CHAPTER IV
4.1
Flow Chart of Program Used in the Microprocessor
System for Automatic IC Testing . . . • . . . . . .
vi
37
Page
..•
4.2
Flow Chart of Initial Conditions Subroutine •
4.3
Flow Chart of PIO Programming Subroutine
4.4
Information Entered About DUT
4.5
Information Generated in P-Pattern Subroutine
4.6
Flow Chart of P-Pattern Subroutine
4.7
Generate and Output Test Pattern Subroutine
• 50
4.8
Flow Chart of Clock Pulse Subroutine
. 52
4.9
Characteristics of Pulse Applied by Clock Pulse
Subroutine
• 53
. 41
• • 43
. • . 47
47
• • 48
.......... ..
4.10
Flow Chart of Input/Store Subroutine
4.11
Flow Chart of Input/Compare Subroutine
4.12
Power and Display Control Subroutine
4.13
Flow Chart of Counter Load Subroutine
4.14
Flow Chart of Remove DUT Subroutine . .
. . 54
56
' 58
59
. 62
CHAPTER V
5.1
Illustration of Hexadecimal Keyboard Used in This ATS 64
5.2
Format of ATS LED Display .
5.3
Layout of Zero Insertion Force Sockets in ATS
71
5.4
Format of Words Input to Program the ATS
73
5.5
Labeling DUT Input Pins According to the Test
Pattern Word Format .
5.6
.. .....
.. ... .
.......
. 70
• 77
Relation Between the Memory Locations of the
Test Patterns Input to DUT and Its Responses . . . . 80
CHAPTER VI
6.1
Typical Organization of Responses in ATS' Memory . , 86
vii
Page
6.2
Responses Obtained from the 7404 IC With the ATS
Operated in Learn Mode . . . . . • • • .
87
APPENDIX A
A.l
Memory Map of the Subroutine and Executive Program
Used in the ATS. • . . • . .
. . . . . . . . . •
viii
93
ABSTRACT
This project presents a Microprocessor System for Automatic IC
Testing.
computer.
The system is designed around the Z80 Starter System MicroThe Automatic Test System (ATS) performs functional testing
on both Small Scale Integration (SSI) and Medium Scale Integration
(MSI) Transistor Transistor Logic (TTL) integrated circuits.
modes of operation are provided, Learn, Test and Program.
Three
During
Test Mode test patterns are applied to the Device Under Test (DUT).
Its responses are compared with known-good responses previously stored
in memory to determine DUT performance.
These known-good responses
are obtained during the Learn Hode of operation.
Program Mode allows IC testing when a known-good device is not
available to store the test patterns responses in memory.
In this
mode the user generates the test patterns to be applied to the DUT.
At the end of the mode the user examines the responses to these test
patterns to determine DUT operation.
ix
CHAPTER I
Introduction
1.1
Introduction
Digital circuits may be disabled by almost any internal failure,
and the trend toward miniaturization makes the problem of maintenance
and fault detection even more difficult.
To determine whether a digital system operates correctly, a set
of input patterns or tests are applied and its responses analyzed or
compared with precomputed (expected) responses.
Any deviation in-
dicates the presence of a fault.
Faults can be classified as logical or parametric [Breuer and
Friedman, 1976].
A logical fault is one which causes the logical
function of a circuit element (or elements) to be changed to some
other function.
Parametric faults frequently alter the magnitude
of circuits parameters causing a change in some factor such as circuit speed, current, or voltage.
DC (static or functional), AC (dynamic or parametric) and clockrate testing are the types of testing usually performed on digital
circuits and devices [Breuer et al., 1976].
In DC testing test pat-
terns are applied to the device under test (DUT).
The responses to
these test patterns are analyzed to verify if the DUT is functionally
correct •. In AC .testing the circuit speed, voltage and current levels
are some of the DUT parameters measured to verify dynamic behavior.
1
2
Clock rate testing is functional testing performed near the maximum
DUT rate.
Those .tests can be performed faster and more reliably with the
aid of an Automatic Test System (ATS).
An Automatic Test System typically is comprised of the following
main sections:
Control, Stimulus, Measurement, Switching and Soft-
ware [Desena, 1979].
1.
See Figure 1.1.
The Control Section typically includes a computer, an executive software package, display printer, keyboard for control
of the system and a mass storage device.
2.
The Stimulus Section consists of devices like power supplies,
function generators and pulse generators which under computer control stimulate the DUT.
3.
The Measurement Section could include a digital multimeter
and a counter/timer for analog measurements.
4.
The Switching Section provides the capability of assigning
the driver or receiver configuration to the lines interfacing
the DUT.
5.
The software enables the ATS to test a particular DUT.
It
can contain the necessary information to program the measurement section, stimulus section and switching section.
This
program also could provide the algorithm that generates the
test pattern output to the DUT.
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Figure 1.1
Typical Automatic Test System (ATS) Configuration
4
ATS applications range from electronic component testing to a
large system testing.
Most of the automatic test systems available
today use one of two basic testing approaches:
Software Stimulation
or Hardware Stimulation [Mancone, 1979].
Large systems with powerful computers typically employ the Software Stimulation approach at the printed-ciccuit (PC) board testing
level.
This approach consists of having a library of programs with
equivalent models of electronic components (AND, NAND, NOR gates, etc.)
usually found in PC boards.
The ATS' computer develops the test pro-
gram from the information supplied by the user which describes the
connections between components on the PC board to be tested.
Some advantages of this approach are:
the programmer has access
to an exact measure of test comprehensiveness and except for final
verification, program preparation does not require a known-good PC
board.
The disadvantages in using Software Stimulation are that:
PC board programming is expensive and the user depends on the ATS manufacturer for successive _library updates.
Typically ATS's that employ the use of microprocessors use the
Hardware Simulation approach.
This approach consists in subjecting
each input of the DUT to either known or pseudorandom test patterns.
Then the DUT output is examined to determine if it operates correctly.
The advantages of using this approach are:. programming does not
require a description of each internal connection of the device to be
5
tested, programming is less expensive and no component modeling is
needed.
The disadvantages of this technique are:
the user has no
precise measure of test program comprehensiveness and program preparation requires a known-good device.
I.2
Objectives
The objective of this project is to design a Microprocessor Sys-
tem for Automatic IC testing.
This system will perform static or
functional testing on the Small Scale Integration (SSI) and Medium
Scale Integration (MSI) Transistor Transistor Logic (JTL) integrated
circuits.
This ATS can be used to test these digital IC's before they are
incorporated into the final circuit assembly.
This will eliminate the
possibility of system malfunction due to IC's malfunction, which otherwise would be tracked down only by detailed trouble-shooting of the
entire system.
The ATS has three different modes of operation:
Test, Learn and
Program.
In TEST Mode the DUT is tested for all possible logical faults
such as pin-shorts, opens, stuck-at-zero, stuck-at-one, etc.
2n dif-
ferent test patterns are applied to the n inputs of the DUT.
The
responses to those test patterns are then compared with known-good
responses stored in memory to determine the performance of the DUT.
The LEARN Mode allows the user to program the ATS.
mode a known-good device is needed.
In this
Known test patterns are applied
6
to this device and its responses stored in memory.
are used
IC's.
du~ing
These responses
the TEST Mode to determine the performance of similar
These known test responses can then be transferred to a non-
volatile storage medium to file them permanently.
The PROGRAM Mode is used when a known-good device is not available to program the ATS.
In this mode the programmer can generate his
own test patterns to test that particular device and to determine,
by its responses, its performance.
I.3
Report Outline
The development of the system is covered in five chapters.
Chapter II consists of two sections.-
Section one describes
briefly the basic elements that comprise a microcomputer.
The second
section describes the microcomputer used in this ATE.
Chapter III describes in detail the circuitry designed in the
microcomputer wire wrap area which allows a functional testing of SSI
and MSI ICs.
Chapter IV presents the software technique and approach used in
the system.
This chapter also includes the Assembly and Machine pro-
gram listings.
Chapter V outlines the procedures to follow when this system is
used in any of its modes of operation.
Chapter VI presents the performance evaluation of the System and
conclusions.
CHAPTER II
Microcomputer Systems
II.l
Microcomputer Organization
A microcomputer is a machine which manipulates binary numbers
(data) following organized sequences of instructions.
A microcomputer
system usually consists of a microprocessor, memory and an interface
unit [Artwick, 1980] as shown in Figure 2.1.
The microprocessor contains a central processing unit (CPU) which
consists of the circuitry required to access the appropriate locations
in memory and interpret resulting instructions.
these instructions also takes place in this unit.
The execution of
The CPU contains
the arithmetic/logic unit (ALU), a combinational network that performs
arithmetical and logical operations on the data,
a control section
which controls the operations of the microcomputer and various registers for temporary storage and manipulation of data and instructions.
·The random-access memory (RAM) is a read-write memory type and
consists of a number of IC packages connected together.
The RAM is
used to store data, variable parameters, and intermediate results that
need updating and are subject to change.
The read only memory (ROM)
consists of a number of IC packages and is used for sharing programs
and tables of constants that are not subject to change once the production of the microcomputer system is completed.
Interface units provide the necessary paths for transferring information between the microprocessor and external input and output
7
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Microcomputer System Block Diagram
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9
devices connected to the I/O bus.
The microprocessor receives status
and data information from external devices through the interface.
It
responds by sending control and data information for the external devices through the interface.
This communication is specified by pro-
grammed instructions that direct data through the buses in the microcomputer system.
The commnnication between the Large Scale Integration (LSI) components takes place via the address bus and data bus.
The address
bus is nnidirectional from the microprocessor to the other units.
The
binary information that the microprocessor places on the address bus
specifies a particular memory word in RAM or ROM.
The address bus
is also used to select one of many interface units connected to the
system or to a particular register within an interface unit.
A
memory word and an interface register may be distinguished by assigning a different address to each.
Alternatively, a control signal may
be used to specify whether the address on the bus is for a memory
word or for an interface register.
The number of lines available in
the address bus determines the maximum memory size that can be accomodated in the system.
n
2
words of memory.
For n lines, the address bus can specify up to
The typical length of a microprocessor address
. 16 , prov1. d 1ng
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memory capac1ty
of
b us 1s
z16
= 65,536
words.
The amount of memory employed in a microcomputer system depends on a
particular application and quite often is less than the maximum available in the address bus.
10
The data bus transfers data to and from the microprocessor and
the memory or interface which is selected by the address bus.
The
data bus is bidirectional which means that the binary information can
flow in either direction.
pins in the IC package.
A bidirectional data bus is used to save
If a unit did not use a bidirectional data
bus, it would be necessary to provide separate input and output terminals in the IC package.
The number of lines in the microprocessor
data bus ranges from 4 to 16, with 8 line being the most common.
A set of separate data and address buses is the most common
transfer path found in microprocessors.
The advantage of this scheme
is that the microprocessor can select a word in memory and transfer
data word at the same time.
Some microprocessors use one common bus
which is time-multiplexed for transfer of address or data.
The ad-
vantage of this scheme is that fewer terminal pins are needed.
The
disadvantages are the time lost in the sequential use of the common
bus and the need for an external latch to hold the address for memory.
To facilitate the development of special-purpose digital systems
by means of a microcomputer, many sources offer a complete
microco~
puter unit on a single printed circuit (PC) board.
Today, with an
increased number of manufacturers and board
picking the right
models~
board is itself a problem.
When choosing a microcomputer board the following basic specifications should be considered:
CPU type and instruction set, RAM
and ROM/PROM capacity of the board, serial - I/O capability, parallel-
11
I/O capability, and auxiliary features such as disk or audio-cassette
interfaces, keyboard or video
in~erface,
real-time clock or program-
mable counter/timers, direct memory access (Dl1A) capability, and
math-processor options [Bursky, 1980].
II.2
Z80 Starter System
The Z80 Starter System is the microcomputer selected for the
development of the Microprocessor System for Automatic IC testing.
The Z80 Starter System is an 8-bit single board microcomputer.
It contains a Z80 CPU along with up to 4k bytes of EPROM and 2k bytes
of RAM, two bi-directional 8 bit I/O ports (Z80 PIO), a four channel
hardware counter/timer (Z80 CTC), PROM programmer audio-cassette interface, keyboard, display, wire wrap area for custom circuitry and
2k bytes of Monitor program (Z BUG) which provides the user with complete control over the execution and debug the of the program developed.
A block diagram of the Z80 Starter System is shown in
Figure 2.2.
The Z80 CPU is the heart of the system.
Its
instruction set
contains all 78 op codes of the 8080's instruction set as well as
another 80 codes.
Of the 158 total instructions, there are 21 8-bit
Load commands; 20 16-bit Load commands; 14 Exchange Block transfer
and Search instructions; 17 Arithmetic and Logic commands for 8-bit
operations; 12 general purpose arithmetic commands; 16 shift and
rotate functions; nine Bit set, Reset and Test commands; 11 Jump instructions; seven Call/Return directives; and 12 I/O operations.
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Figure 2.2
Z80 Starter System Block Diagram
11
31
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13
The hardware characteristics of the Z80 have been improved.
just needs a single phase clock and a +5 volts power supply.
maskable interrupt line has also been added.
It
A non-
The Z80 is a register-
oriented processor containing eighteen 8-bit registers and four 16bit registers.
Two accumulators and flag registers are also provided.
Figure 2.3 illustrates the Z80 structure.
A close look at the regis-
ters, however, reveals that only about half of the registers can be
used at any one time.
The accumulator flag and registers B, C, D, E,
. t he
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set are
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An exchange instruction must be per-
formed to select which set (main or alternate) is going to be used.
This feature is used for interrupt processing in which only one command is necessary to save the interrupted program's status.
registers have also been added.
Two index
For more details on the Z80 micro-
processor refer to MK 3880 Central Processing Unit Technical Hanual.
The Z80 Microprocessor, in the Z80 Starter System microcomputer,
provides the major control signals to scan the display and keyboard
as well as reading and writing memory.
The Z80 Parallel I/O Circuit is a programmable, two port device
which provides a TTL compatible interface between peripheral devices
and the Z80-CPU.
The CPU can configure the Z80-PIO to interface with
a wide range of peripheral devices with no other external logic required.
The major features of the Z80-PIO include:
- Two independent 8-bit bidirectional peripheral interface ports
14
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Figure 2.3
Z80 Microprocessor Structure
15
with "handshake" data transfer controL
- Interrupt driven "handshake" for fast response.
- Any one of four distinct modes of operation may be selected
for a port including:
Byte output
Byte input
Byte bidirectional (Available on Port A only)
Bit control mode
All with interrupt controlled "handshake".
- Eight outputs (Port B) are capable of driving Darlington transistors.
- All inputs and outputs are TTL compatible.
- Single 5 volt supply and single clock required.
One of the unique features of the Z80-PIO that separates it from
other interface controllers is that all data transfer between the peripheral device and the CPU is accomplished under total interrupt control.
The interrupt logic of the PIO permits full usage of the inter-
rupt capabilities of the Z80-CPU during I/O transfers.
All logic
necessary to implement a fully nested interrupt structure is included
in the PIO so that additional circuits are not required.
Another
unique feature of the PIO is that it can be programmed to interrupt
the CPU on the occurrence of specified status conditions in the peripheral device.
The PIO block diagram is shown in Figure 2.4.
For
more details on the Z80 PIO refer to MK 3881 Parallel I/O Controller
16
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ZSO PIO Block Diagram
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17
Technical Manual.
In the Z80 Starter System, the Z80 PIO Port A and
Port B as well as the handshake lines are routed to the wire wrap area
for connection to custom circuitry.
The Z80-Counter Timer Circuit (CTC) is a programmable component
with four independent channels that provide counting and timing functions.
The CPU can configure the CTC channels to operate under various
modes and conditions as required to interface with a wide range of devices.
The Z80-CTC requires only a single +5 volt supply and one
phase 5 volt clock.
Major features of the Z80-CTC include:
- All inputs and outputs fully TTL compatible.
- Each channel may be selected to operate in either Counter Mode
or Timer Mode.
- Used in either mode, a CPU-readable Down Counter indicates the
number of counts-to-go until zero.
- A Time Constant Register can automatically reload the Down
Counter at Count Zero in Counter Mode and Timer Mode.
- Selectable positive or negative trigger initiates time operation in Timer Mode.
The same input is monitored for event
counts in Counter Mode.
- Three channels have Zero Count/Timeout outputs capable of
driving Darlington transistors.
- Interrupts may be programmed to occur on the zero count condition in any channel.
Daisy chain priority interrupt logic included to provide for
18
automatic interrupt vectoring without external logic.
The Z80-CTC block diagram is shown in Figure 2.5.
For more
details on the Z80-CTC refer to MK 3882 Counter Timer Circuit Technical Manual.
In the Z80 Starter System, the Z80-CTC is heavily used.
Channels 1 and 3 are used in the audio-cassette interface and channel
2 in the EPROM programmer.
Channel 0 is not used in the Z80 Starter
System; it is available to the user at the wire wrap area.
2048 bytes of 21L02-l RAM and 4k bytes of 2716 EPROM are contained in this microcomputer.
The memory map of the Z80 Starter Sys-
tem is shown in Figure 2.6.
The ZBUG Monitor program is a 2408 byte program written for the
Z80, which allows the user to enter and debug machine level Z80 programs.
This program is supplied in the mask programmed ROM in the
Z80 Starter System.
The ZBUG Monitor uses a Hexadecimal Keyboard for
data entry and a six digit Hexadecimal display for data readout.
Also
included in the ZBUG are Load and Dump programs which allow inexpensive audio-cassette recorders to be used for storage of programs.
An
EPROM programmer for 2716/2758 EPROMs is included so that user's programs can be placed in these non-volatile memory devices for on-line
use at any time.
Advanced diagnostic capability such as multiple
Breakpoints, Instruction, Single Step and Z80-CPU Register display/
modification provides the user with diagnostic capability normally
found only in expensive development systems.
For more details on the
Z80 Starter System refer to Z80 Starter System Operators Manual.
19
'Z!RO C.OUNT/
TIMEOUI 0
C.~AWNEl
o
C.LOC.K/
TR\G6C.P. 0
INlERNAL
CONTP..OL
L.OG\C
'Z'EI\0 C.OIJ'NT/
T\MEOUT \
CHANNEL I
t)ATA
INTERNAL
CPV
C.LOC.k/
Th\Go<iiP. \
BUS
sus
ZERO COUNT/
TIMEOUT 2
\/0
C."i\NNE\..
2
C.LOC.I<./
TRIGGER 2
INTERP.UPT
CONiNl\.
Z&P.O <:.OUNT/
TIMEOU\ 3
LOGIC.
3
INTERRUPT
COt-tTI\o\..
Ln"ES
Figure 2.5
Z80 CTC Block Diagram
C.\\ANNEL
'3
C\..OCK/
TR\GG&'R 3
20
2800H
UNUSED
27FFH
2400H
lK BYTES
23FFH
23ClH
2 BUG SCRATCH RAM
AND
BREAKPOINT TABLES
23COH
USER'S REGISTER MAP
23A9H
23A8H
ZBUG STACK
2390H
WORKING AREA
238FH
RAM AVAILABLE TO USER
2000H
UNUSED
lFFFH
1800H
17FFH
PROM PROGRAMMER
lOOOH
PROM 2 SOCKET
OFFFH
PROM 1 SOCKET
0800H
07FFH
ZBUG MONITOR
OOOOH
Figure 2.6 Z80 Starter System Memory Map
CHAPTER III
Hardware Development
III.l
Hardware Development
This chapter describes the circuitry designed in the Z80 Starter
System wire wrap area, which enables the user to perform functional
testing on the Small Scale Integration (SSI)
and Medium Scale Inte-
gration (MSI) Transistor Logic (TTL) integrated circuits.
The cir-
cuitry provides the interface between the system and the device under
test (DUT) as well as test results via an LED display.
The wire wrap area has room for about 25 to 30 additional ICs.
Z80-CPU, PIO and decoded system signals are routed to this area for
connection to custom circuitry.
These signals are shown in Figure 3.1.
A block diagram of the circuitry designed in the ZSO Starter System wire wrap area is shown in Figure 3.2.
The Z80 Starter System's PIO Ports A and B represent the peripheral data bus between the microcomputer and the device under test
(DUT).
Port A and Port Bare operated in the bit control mode.
In
this mode any of the peripheral data bus lines can be programmed to be
an input or an output.
With the peripheral data bus configured ac-
cording to the DUT input/output pin configuration, the Z80-CPU can
send the test patterns to the DUT and receive its resultant responses.
Figure 3.3 shows how the PIO Ports A and B are programmed to
test a particular IC.
Initially, the CPU sends a control word to
Ports A and B to establish their mode of operation.
21
The control word
PlO Port B
Data Lines
Port B
Handshake Lines
PB7
PA7
PB6
PA6
PBS
PAS
PB4
PA4
PB3
PA3
PB2
PAZ
PBl
PAl
PBO
PAO
BSTB
ASTB
BRDY
ARDY
zco
CTC Channel 0 Line C/TO
CPU
Address Lines
Al4
AlS
Al2
Al3
AlO
As
All
A9
A6
A7
A4
CPU Data Lines
PlO Port A
Data Lines
Port A
Handshake Lines
D6
D7
D4
Ds
D2
D3
Do
Dl
BUSRQ
RESET
HALT
BUSAR
lEO
RFSH
-
-
MR
WR
lORQ
CTC Channel 0 Line
System
Control
Signals
lNT
-
--
RD
MREQ
-MCS3
B0
MCS6
MCSS
PS7
MC57
As
PSS
PS6
A2
A3
lOR
lOW
Ao
Al
MEMW
MEMR
Figure 3.1
CPU
Address Lines
CPU Data Lines
Lines Routed to the Wire Wrap Area for Connection
to Custom Circuitry
System
Control
Signals
N
N
+sv
~·
·~
~~ ~'"'
l. u:
23
II.
Pl!R\P\o\iP.A\.. DATA l?.US
14 ~-+_.,,___
7
I='P.Olol\ :Z 80
S'TAP.iE!R
SYSTEM
I~
PIN
z ~~
4
..........--1
~-+
II
\l:t Pit\
z. \F
"' ~-4---~r-_...
+SV
s
I l:t l'IM
'Z.\ F S ~-_...,-...r.
+sv
Figure 3.2
Block Diagram of Circuit Designed in the Z80 Starter System ~vire Wrap Area
+5
----~~~r-~
~ ~
P\0
MODE CONTROL -a.EiioiSTEII.Ci
r - - - - - - --·
1
'i-4
I
'S3
r-------------------------1-------------------------------~~~
====+--====~
s,
I
Ml MO
IT] 'Port A
rn
'Po...t'B
!..,_ _ _ _ _ _ _ _
I
I
I
I
J
~---------------r----------------------~~
~
U?17"t00
JJ-!rt
II
I
fl]
l
~~~7
?'
7H''"
~Ar.
--~~--------------------------~A'
,---------MASK REGISTERS
--,
I
•·
L-~~----------------------~~
A7 A, As A4 A3 Aa A,
Ao
85
io
I
ltltl,lololtlolol
"!,. lie. Bs
'SJ "&a "8,
olq_L,_l9J_gJ
1 11 1 1 1 1
.___
Figure 3.3
Programming PIO's Peripheral Data Lines to Test a 7400 IC
N
.,J::-.
25
has the following format:
D7 D6 D5 D4 D3 D2 Dl DO
§1
Fol xl xl
1!1
I 1!1 I
X= unused bit
Bits D and D form the binary code for the desired mode accord7
6
ing to the following table:
D7
D6
MODE
0
0
0 (Output)
0
1
1 (Input)
1
0
2 (Bidirectional)
1
1
3 (Control)
Bits D and D are not used.
4
5
Bits D - D must be set to 1111
0
3
to specify "Set Mode".
When Mode 3 is selected, the next control word sent to the PIO
must define which of the port data bus lines are to be inputs and
which are to be outputs.
The format of the control word is shown
below:
D7 D6 DS D4 D3 D2 Dl DO
~IDtJot!p!~l/qii(#Iqi!oj
If any bit is set to one then the corresponding data bus line
will be used as an input.
Conversely, if the bit is set to zero, the
line will be used as an output.
Figure 3.3 shows the content of Mode Control Registers and Masks
Registers in PIO Ports A and B.
The content of the Mode Control
26
Registers indicate that mode 3 (control) is selected.
example the 7400 (Quad two input N gates) is tested,
Since in this
th~
peripheral
data lines are configured according to Ports A and B Mask Registers,
which in turn describe the 7400 pin input/output configuration.
The peripheral data lines not being used by the DUT such as +5V
and ground are configured
as input lines to the PIO and connected
manually to a high level (+5V) with a single pole single throw (SPST)
switch through a 5Kn register.
All peripheral data lines can be con-
nected independently, in the same way, to a high level
makes possible the testing of open collector res.
(+5V)~
This
The pull up resis-
tor value is calculated in the following way:
High-level (off-state) circuit calculation:
Jl~c
==~ ~Br---~-_...,.~-c:::;---....;;.>
To PIO
~ (max.)
where:
vee - voltage applied to DUT
VOH = high level input voltage
1
1
high level output current
oH
IH
=
high level input current
=
vee - VOH min.
1 oH + 1 IH
27
Typical Open Collector Gate
PIO
VOH min. = 2 • 4V
IOH = 250]1A
R
L (max)
=
5 - 2.4
= lOKD
250]1 + 10]1
Low-level (on-state) circuit calculation:
vee
~~~E) :1) "
) To PIO
~ (min.)
where:
v
=
I
CC
- v
OL max
OL max
- I
IL
VOL = low level output voltage
1
oL
=
low level output current
1 IL = low level input current
Typical Open Collector Gate
PIO
IOL = 16 mA
VOL = 0.4V
~ (min.)
=
5 - .4
= 287~
16m - 10]1
then, 287~ < RL< lOKD
In this Automatic Test System (ATS) a 5KD pull up resistors are
available in all peripheral data lines.
The DUT can be placed in one of the four Zero Insertion Force
(ZIF) sockets provided.
There are 2 14-pin and 2 16-pin sockets.
28
They allow testing 14 (16) pin ICs with VCC in pin 14 (16) or pin
4 (5) and Ground in pin 7 (8) or pin 11 (13).
Five 5082 HP Series LEDs are used in this ATS to display status
and test results, as indicated in Figure 3.4.
IC is used to drive low the LEDs.
PIO in the wire wrap area.
A 7404 (Hex inverters)
These inverters are controlled by a
PIO Port A is operated in mode 3 (control)
with its peripheral data lines configured as output lines.
The resistors used with LED lamps are calculated as indicated
below.
Red LED (5082 - 4650):
Refer to curves a and b in Figure 3.5.
Operating this LED at 100% of efficiency, a 10 rnA forward current
(IF) is obtained from Relative Efficiency vs. Peak Current curve,
Figure 3.5 a.
With 10 rnA IF a 2 .2V forward voltage (VF) follows from
Forward Current vs. Forward Voltage curve, Figure 3.5 b.
and IF then the resistor value can be determined.
~D =vee- vF
IF
where:
vF
vee
I
F
=
forward voltage
= supply
=
2.2V
voltage = 5V
= forward current
= 10
rnA
RRED = 5 - 2.2 = 280Q .
10 m
P = EI = 5 (10 m) = 0.050 W use 1/8 W
Knowing VF
29
Figure 3.4
MODE
INFORMATION
ALL
INSERT IC
PROGRAM
END OF PROGRAM
MODE
TEST
IC IS GOOD
TEST
IC IS BAD
0
0
0
LEARN
END OF LEARN
MODE
0
LED
.o
COLOR
RED
YELLOW
GREEN
RED
YELLOW
Information obtained from the LED display
'·"
•. s
>-u
I·~
ffi
1·3
u:
1-2
iJ
~
w
I.U
>
;:
<..J
1&1
0:
-
-
,...
,.
/
30
"'
/
ld
\.0
I
·9
v
I
.a
I
.7
.6
0
10
a.
2.0
30
.qo
so
Relative Efficiency vs. Peak Current
20
~
I
IS
/lj
,..~
I
...
%
a:
a:::0
10
tJ
a
~
~0
j
s
~
I
u.
0
o
·&
1.0
VF • F'OS\WA\\D
b.
Figure 3. 5
1-5
I
2.0
2·S
3.0
VOl."TAGE·V
Forward Current vs. Forward Voltage
Red LED (5082 - 4650) Curves
31
In the same way the resistor values for RG reen and R
-Ye 11 ow are
calculated, using curves in Figure 3.6 and 3.7 respectively.
RG reen
= 280Q, 1/8 W
Ryellow = 280Q, 1/8 W
The PIO in the wire wrap area besides controlling the LED lamps
controls the application of power (+SV) to the DUT.
The least signi-
ficant data line of Port A, A , controls the DS 54450 Peripheral/Power
0
Driver.
This IC features two standard 7400 TTL gates and two high
current, high voltage NPN transistors.
See data sheet in Appendix B.
This Peripheral/Power Driver IC, configured as shown in Figure 3.8,
controls a 712-5 series relay for the application of +SV to the DUT.
Figure 3.9 shows the actual components layout in the Z80 Starter
System wire wrap area.
B.
Data sheets of the components are in Appendix
32
I.S
t2
w
v
...~
w
,.
lu
s
..I
Ill
~
\-4
-
_,.
1·3
/
V1
....
/
/ "
1-1
/
\.o
/
·9
/
·&
/
.7
0
10
I PIOAk-
a.
2.0
PiAK
30
40
50
EoO
CUI\1\SNT- "rnA
Relative Efficiency vs. Peak Current
20
15
<)!
I
I
~
~
10
I
~
::>
u
Q
~
1
s
I
tt:
a.
-
u.
.S
1.0
/
I.S
,2.0
2..S
~.0
Vc:- ~ORWARO VOI..IAGE·V
b.
Figure 3.6
Forward Current vs. Forward Voltage
Green LED (5082 - 4950) Curves
\.7
..,
33
--
t.s
>-
1.)
'Z
Ia
'·'\
,.;
,
!::.!
J.L
LL
1.'2.
l&a
w
>
....
!(
..J
1.11
'·'
I
\.0
v
/
,. ....-
I;
-
~
/
7
.g
I
a;
·8
·7
0
10
20
IPEAIC PEAK
a.
30
'\0
50
'0
C.URP..i!NT·"'I'11.0..
Relative Efficiency vs. Peak Current
20
<
~
15
'
t;
Ill
ct
ct
a
I
10
1/
Q
~
<
~
5
~
J
~
0
0
b.
Figure 3. 7
Forward Current vs. Forward Voltage
Yellow LED (5082 - 4550) Curves
34
tSV
2.
l)OWI:~
TO l)U'T
3
--=-t--+
7\2. o-:,
-rsv
5
141>S7s.q.so
2.
'P\0 • Ao
+SV
'3
--
Figure 3. 8
7
--
DS54450 Peripheral/Power Driver and 712..,.-5 Relay Interconnections
35
[]
u
u
D
DEJ
~
~
\J-4-
IJ3
8
@
@
@
@
@
Figure 3.9
EJ
EJ
UI,U2.
14 'PIN XIF SO~KET
IJ3,U4
1" 'PIK
vs.vGt
AMP 7~0,
IJ7,\J8
999-\-l\.S'K
IJ\0
IJ\'2.
7404
LEt> 1\iS\SiO~S
75450
\.)\3
7\'lD-S
Ll,\.!1
L2,L5
L4
S0~2-4SSO
u'
Ull
:Z.\r
soc.~n
'Z.~O- 'll\0
S0~2-4C.SO
so a2.- 49oo
U9
[]
Components Layout of Circuit Designed in the Z80 Starter
System Wire Wrap Area
CHAPTER IV
Software Development
IV.l
Main Program Description
This chapter describes the software technique and approach used
in the programming of the Microprocessor System for Automatic IC Testing.
This Automatic Test System (ATS) employs the Hardware Simulation
approach, which consists in subjecting each input of the device under
test (DUT) to either known or pseudorandom test patterns.
Then the
DUT output is examined to determine its response to the input test
pattern.
The Flow Chart of the program developed for the Microprocessor
System for Automatic IC Testing is shown in Figure 4.1.
The program
generates the test patterns to be applied to the DUT, stores DUT respouses (ATS in Learn Mode), compares DUT responses with known-good
responses stored in memory (ATS in Test Mode) and stores DUT responses
to test patterns supplied by the programmer (ATS in Program Mode).
The program consists of several subroutines, specified in the
process blocks on the flow chart.
Each subroutine is documented and
explained in later sections.
Referring to the flow chart on Figure 4.1, after some initial
conditions are set, the user inserts the IC to be tested in the appropriate zero insertion force (ZIF) socket and enters IC Code Word, ATE
Operation Mode and Clock Input Code Word.
36
SET
INITIAL
CONDITIONS
IN~T
tiiJT
E'/1&0
OF
INC.I\l:MI!!..T
LE.\1\IIl MODE
COUNTER
'PP.OGI\1\M
"PI OS
GENE\\1\TE
R&MOVE'
'P-PATTEI\N
OUT
D\JT
\S
GOOD
INPUT
1\i.Sl»Ot.lS'C:
AND !oTOl\E IT
Figure 4.1
\N9UT
1\ES'PO"SE' AN
COMPAP.E IT
Flow Chart of Program Used in the Microprocessor System
for Automatic IC Testing
38
The Code Word is composed of two 8-bit words, Port A Code Word
(PACW) and Port B Code Word (PBCW), having the _following format.
Ip 3 I p 2 I p1 I pACW
P.]_ =Pin number i
where i = 1, 2, . • . 16
P
=1
input pin in DUT
P
=0
output pin in DUT
These words are used by the ATS to program the.PIO peripheral
data lines, input/output pin configuration, and to determine the number of test patterns to be applied to the DUT during Test or Learn
Mode.
During the Test Mode, each IC to be tested receives 2N different
test patterns. ·Where N is the number of input pins on the DUT.
The ATS Operation Mode is specified by an 8-bit word having the
following format:
D7
X
D6
X
Ds
D4
X
X
D3
jx
D2
Dl
X
11-11
Do
Mo
0
0
Test Mode
0
1
Program Mode
1
1
Learn Mode
The Clock Input Code Word is composed of two 8-bit words which
39
specify the clock pins in a Flip-Flop or a clocked device.
These
words have the following format:
D7
D6
Ds
D4
D3
Dz
Dl
Do
Ics c7 Ic 6 I cs jc4 c3 lcz c,
Ic16l c1sl cl4 I c13l c12l cui c10 I c9
Ci = 1, i f pin i is a clock pin
i = 1, 2,
.16
A default of OOH in those words indicate a non-clocked device.
After the description of the DUT and the Operation Mode are entered, the ATS will perform the following:
If the ATS is in the Learn Mode, it will generate a test pattern
which is applied to the DUT.
If the DUT is a clocked device a clock
pulse to the appropriate pins is applied.
test pattern is stored in memory.
Then, the response to that
New test patterns are generated in
sequence and their responses are stored in memory.
This cycle con-
tinues until 2N different .test patterns are applied to the DUT.
Then,
an LED indicates the end of the Learn Mode.
When the ATS is in Test Mode, instead of storing the responses to
test patterns as in Learn Mode, the responses are compared with knowngood responses previously stored in memory, for that particular device.
Then after 2N different comparisons the results of the tests are displayed and the end of mode is signaled.
If the ATS is operated in the Program Mode the programmer should
40
supply the test patterns to be applied to the DUT,
to these test patterns are stored in memory.
signaled by an LED.
The responses
The end of this mode is
Then the programmer can analyze the responses
stored in memory to determine the DUT performance.
IV.2
Subroutines Description
IV.2.1
Set Initial Conditions Subroutine
The flow chart of the subroutine is shown in Figure 4.2.
This
subroutine sets the ATS in a known initial state.
PIOl is programmed to be in an Output Mode to control the LED display and the +SV power to the DUT.
Initially, it is verified that all
LEDs are set off and power is not applied to the ZIF sockets.
PI02,
before the ATS operation is started, is programmed to be in the input
mode, such that no signals are applied to the DUT when inserted in the
socket.
Then the start LED is set on, to signal the user that the
IC to be tested can be inserted in the appropriate socket and that IC
Code Word, ATS Operation Mode and Clock Input Code Word can be entered
to start the test.
41
PtOI TO 6£
IN IIIN OUTPUT
MOb I'
SliT ALt..
\.EDS OFF
R~WIOVG
POWER FROM
'Z\t= SOC.K£T 5
PROGRAW\
PIQ2 TO tiE
IN AM lM\'\JT
MObE
Figure 4.2
Flow Chart of Initial Conditions Subroutine
42
IV.2.2
Program PIO Subroutine
This subroutine programs the Z80 Starter System's PIO peripheral
data lines in accordance with the device under test (DUT) input/output
pin configuration.
The flow chart of this subroutine is shown in
Figure 4.3
Port A Code Word (PACW) and Port B Code Word (PBav) describe the
DUT input/output pin configuration.
PACW and PBCW have the following
format:
D7
IPs
D6
I p7
D5
jP 6
D4
l Ps
D3
JP 4
D2
Dl
p3 JPz
IP16I P1siP14I PuiP12l PniP1o
Do
I pl I
PACW
IP9 I
PBCW
P = 1 input pin in DUT
P = 0 output pin in DUT
To program the PIO initially a Control Mode word is sent to Port
A and Port B to select the operating mode, in this case, mode 3 (control) is selected.
D7
IM1
This control word has the following format:
D6
D5
JMo
X
mode
word
D4
lx
D3
1
Dz
11
Dl
1
Do
I1 I
signifies mode word
to be set
X
unused bit
Q
43
SET MO'DE
IN l'I02.
'POm' A
A~?AC.""
A.~
SET
\N
A
PACW
= Port A Code Word
PBCW
= Port B Code Word
A
= Accumulator
MO'DE'
\)!02.
PQl\T 'S
Figure 4.3
Flow Chart of PIO Programming Subroutine
'
44
D7
D6
Mode
0
0
0 (output)
0
1
1 (input)
1
0
2 (bidirectional)
1
1
3 (control)
After mode 3 (control) is selected the next .control word sent to
each of Port A and Port B specifies the peripheral data lines input/
output pin configuration.
D7
D6
DS
D4
This word has the following format:
D3
D2
D1
DO
l11o !110 l11o !110 l110 !110 11/0 !110 I
Port A
l11o l110 l11o !110 l11o l110 l110 !110 I
Port B
1 if peripheral data line
is to be an input
0 if peripheral data line
is to be an output
Examining closely this control word with PACW (PBCt-1), it can be
concluded that one is the complement of the other, i.e if pin 1 of
the DUT is an input the peripheral data line associated to that pin
should be an output.
Thus, to configure Port A and Port B peripheral data lines, after
mode 3 (control) is selected, PACW and PBCtv are complemented and sent
as the next control word to PIO Port A and Port B respectively.
45
IV.2.3 · P-pattern Subroutine
The IC Code Word describes the DDT's Input/Output pin configuration.
The number of inputs (N) determine the total test patterns (2N)
to be applied to the DUT (if ATS on Test or Learn Mode).
A counter register is used to generate those 2N test patterns.
This subroutine generates the mapping words (P-pattern) that guide the
counter register outputs to the DUT inputs.
Refer to Figures 4.4, 4.5
and 4.6
Initially the Port A Code
~lord
(PACW) and Port B Code Hord (PBCW)
are ANDed with Port A Clock Pins Mode.Word (CPA) and Port B Clock Pins
Mode Word (CPB), respectively, to form Port A Device Word (PADW) and
Port B Device Word (PBDW).
This is done to mask out the clock pins,
in the case of a clocked device, in order not to count the clock pins
as output pins.
Port A Device Word (PADW) and Port B Device Word (PBDW) are then
examined to generate the P-pattern.
Each bit in PADW and PBDW is
tested to determine which are output bits (ones).
For each output
bit in PADW (PBDW) a P-pattern word PAi (PBj) is generated.
Each
P-pattern word will have only one bit set to one such that:
PADliJ
=
PBDW
= PBl
PAl
v
v
v
v
where K and L are the number
of output bits in PADW and
PBDW respectively
46
The P-patterns are then stored in memory in the following fashion:
In this ATS 512 bytes of memory are used to store the response to
the test patterns.
For each test pattern word generated, two memory
locations are used, one for the response from PIO Port A and the other
for the response from PIO Port B.
the memory space a maximum of 2
8
Therefore, in order not to exceed
test patterns are generated.
indicates that a maximum of 8 p-words are used.
This
For those ICs having
more than eight input lines they can be tested in two steps.
Address
47
RAM
vo,
. 1/0,]
2001
l•tq,
. \10,1
2002
lc,
c.(
CPA
= Clock
Pins Port A
2003
lc"
~I
CPB
= Clock
Pins Port B
2004
Ix,
2000
Figure 4.4
Address
1
· X3
1'2. 'P.
I
PACW
= Port
PBCH
= Port B Code Word
A Code Word
PGM = ATS Operational Mode
Information Entered About DUT
RAM
2005
PADW
2006
PBDW = Port B Device Word
2007
OPA = Number of Outputs
in Port A
2008
OPB
=
Port A Device Word
= Number
of Outputs
in Port B
2009
•
•
•
2010
Figure 4.5
P-pattern
p8
Information Generated in P-pattern Subroutine
48
PAIIW~l'At>NACPA
PB~ PSl'ff/\t'PB
NO
'n\:\, n:::o
W::O, OPA:O
OP&-:0 , '(:OtA
4-E- ')(: tAIIW
n:::o
F:::l
y:OP6
0
A-x-:P&l>W
SiT S\T n
\M '""
"'1'-t-'1' +\
Figure 4.6
Flow Chart of P-pattern Subroutine
49
IV.2.4
Test Pattern and Output Subroutine
This subroutine generates and applies the test patterns to the
DUT.
The 2N possible test pattern combinations are provided by the
Counter Register (CR).
To apply these test patterns to the DUT input
pins the P-pattern words are used.
They map the CR to the PIO Port A
and Port output lines.
The flow chart of this subroutine is shown in Figure 4.7.
tially, after the temporary register RB is set to zero, bit b
CR is tested.
If b
0
If b
0
in the
is one then:
is zero, nothing is done.
RB
If zero, nothing is done.
Next bit b
~RB
V PA
1
is tested, if one:
2
This procedure is continuously repeated
until tqe K bits in CR are tested.
pins in Port A.
0
Ini-
Where K is the number of output
The content of RB is then transferred to another tem-
porary register RA and RB is set to zero.
Now bit bK in CR is tested, if one then:
If bK is zero nothing is done.
the K + L bits in CR are tested.
This procedure is repeated until
Where L equals the number of output
pins in Port B.
Now the content of RA and RB are applied to the DUT via Port A
and Port B respectively.
50
RA~O
R~~o
..l-E--1
~-E--1
RA~R'i!l
RS~O
M~Mt\
M~O
0Ui11UT
.?------31t RA AAI> RS
N = number of outputs in PADW
K
= number
+ PBDW
of outputs in Port A
L = number of outputs in Port B
RA, RB = temporary registers
PAl, .••,PAK' p B1 ,.•• ,P BL
Figure 4.7
= 1,
2
.K
j = 1, 2
.L
i
= P-pattern
Generate and Output Test Pattern Subroutine
word
51
IV.2.5
Clock Pulse Subroutine
If the DUT is a clocked device, this subroutine applies a clock
pulse to the appropriate clock pins.
This pulse is applied after the
test pattern becomes stable on the peripheral data bus.
The flow
chart of this subroutine is shown in Figure 4.8.
The temporary registers RA and RB used in the Generate and Output
Test Pattern subroutine contain the test pattern applied to PIO Ports
A and B respectively.
are clock pins.
CPA (CPB) indicates which pins in Port A (B)
Thus, to generate the pulse at the clock pins a
change from zero to one and then back to zero is required.
done as follows:
This is
the content of register CPA (CPB) is ORed with the
content of RA (RB) and then transferred to PIO Port A (B)
then to complete the pulse
(1~0)
(0~
1) ,
the content of RA (RB) is applied
to PIO Port A (B).
The clock pulse is applied to the DUT approximately 3 7~ s after the
test pattern.
It has about l8.S4s of duration as shown in Figure 4.9.
IV.2.6 . Input/Store Subroutine
This subroutine input the DUT data and stores it in memory.
The
flow chart of this routine is shown in Figure 4.10.
In this routine an Index Register (IR) is used to supply the
memory locations where the test patterns responses (data) are to be
stored.
At the beginning of the test the IR is loaded with the starting
address where the output responses are to be stored.
0LOCK.
1\0I.ITIM1i
J,
A"-f..PAVRA
~
'POkiA~A
~
A~CPSVl'&
J.,
'PORT S~A
~
l'OI\T/1\~A
~.
fORT '&<(:-R&
J.,
Rii\lRN
Figure 4.8
Flow Chart of Clock Pulse Subroutine
52
53
I
Peripheral Data-- TV
Lines (Output) --¥\ Applied Test Pattern
I
I
I
Clock Pulse
Peripheral Data Lines
~ 371-ts
I
-4*"-
~
1l8. 5\.ls ' - - - - - - -
I
(Inpu~ 1
I
I
Clocked on Leading
Edge
==:= ==~~~--_-_]
I
I
I
Clocked on Level
I
_- === ="'j
~ ~:= ~ ~ ~
I
DUT Response
~
DUT Response
-v
Clocked on - -:- - - - - - - - - - DUT Response
Trailing Edge - -1- - - - - - - - - - - _A___.....;;...__
Figure 4.9
cparacteristics of Pulse Applied by Clock Pulse Subroutine
54
IR
= Index
Register, specifies
location where the data is
to be stored
(IR) = Content of memory location
\R~IR+I
pointed at by IR
(IR)~'PBPL
Figure 4.10
Flow Chart of Input/Store Subroutine
55
When this routine is called, the content of Port A peripheral
data lines is stored in memory location specified by IR.
Then IR is
incremented by one to point at the memory location where the content
of Port B peripheral data lines is stored.
IR is then incremented to
point at a new location where a new response will be stored.
IV.2.7
Input/Compare Subroutine
This subroutine is called during Test Mode, where the DUT data
is compared with a known-good data pattern stored in memory.
The Flow
Chart is shown in Figure 4.11.
When this routine is called the Accumulator (A) is cleared, then
the content of Port A Peripheral Lines (PAPL) is compared with the
content of memory specified by IR.
If they are the same, bit b
0
in
A is set to one and IR is incremented, if not the routine is ended.
If the previous comparison was good then the content of PBPL in the
same way is compared with the content of memory location specified by
IR.
If they are the same b
1
is set and IR incremented, if not, the
routine is ended.
Accumulator
X
X
X
X
X
X
lbl
bo
0
X
1
0
1
1
Different
The Same
'
56
A~o
COMPA~E
PAP\. 1411\T" (IR)
SET
b 0 TO
0\oll! IN
A'
COMPARE
'PSP\. 'WIT\-\ (J
S&T
b,
To
ONE
IN
A.'
1~\l\+'
Figure 4.11
Flow Chart of Input/Compare Subroutine
.
Q
57
IV.2.8
Power and Display Control Subroutine
The Flow Chart of this subroutine is shown in Figure 4.12.
When
this subroutine is called the content of the A register is transferred
to the power and LED lines in PlOl.
The content of the A register has
the following format:
Accumulator
d7
0
0
0
0
I d6 I ds I d4 Id3
0
0
0
0
1
0
0
0
0
0
1
0
d2
0
1
0
0
IdJ I dO I
0
0
0
1
0
0
0
0
End of Learn Mod
Good IC
Bad IC
End of Program Mode
1
1
1
1
This subroutine is used to indicate, via the LEDs display, the
end of Learn, Test or Program Mode.
Incase of Test Mode the result
of the test is also displayed.
IV.2.9
Counter Load Subroutine
This subroutine is called when the ATS is used in the Program
Mode.
The Flow Chart is shown in Figure 4.13.
This subroutine loads the counter register (CR) with the test
patterns that are to be applied to the DUT.
generated by the user.
They have the following format:
D3
I I I I
X
X
X
X
These test patterns are
X
Dz
I
X
Dl
Do
X
lbo
0
1
I
Flag Word
Test Pattern (TP) block has
not finished
TP block finished
•
58
D - Word
I I
1.1:0~
'DISPLAY
Figure 4.12
II
A.
Power and Display Control Subroutine
59
CR
= Counter
(IR')
Figure 4.13
Register
= Content
of memory location
pointed at b IR'
1
Flow Chart of Counter Load Subroutine
60
Test Pattern (TP) Word
TP Word specifies the test pattern to be applied to the DUT in
the following way.
b
n- 1
If the DUT has N inputs the first N bits b
in TP are used to generate the test pattern.
0
to
The Test Pattern
and Output Subroutine in conjunction with the P-pattern Subroutine will
send those output bits to the appropriate input pins of the DUT.
Flag Word is used as a flag to indicate the end of the Test Pattern Words.
The responses to those test patterns are stored in the memory
locations where the previously Flag Word and TP Word were stored.
They have the following format:
b7
b6
b5
b4
b3
b2
bl
bO
,_I_P.;:;.s_,_I_P_7:...~,l_P_6:;;.....Jll...p..;5;;......a....P-4~~-P...3;;..._"--P-=2-....l_P..::l....,l
Port A test response (PATR)
Port B test response (PBTR)
P. = DUT pin number j
J
PATR and PBTR contain the data pattern that was applied to
the DUT in the bit positions corresponding to DUT input pins, and the
response to that test pattern in the bit positions corresponding to
61
DUT output pins.
IV.2.10
Remove IC Subroutine
The Flow Chart of this subroutine is shown in Figure 4.14.
This
subroutine is called at the end of the current ATS operating mode.
Before +5V power is removed from the DUT, PI02 Ports A and B are programmed to be in the input mode.
lines behave as input ports.
In this mode the peripheral data
Thus, when +5V power is removed no sig-
nals will be applied to the DUT.
62
l'ROGR•M
P\02. TO 8£
IN ~ \MP\IT
MODE
1\~MOV\i
iSV
'\'OWER F11.DM
bUT
END OS:
Figure 4.14
MO~S.
Flow Chart of Remove DUT Subroutine
CHAPTER V
System Operational Procedures
This chapter presents the procedures to be followed when the
Microprocessor System for Automatic IC Testing is used in any of its
modes of operation.
V.l
Microprocessor System for Automatic IC Testing's Operational
Procedures
To use the Microprocessor System for Automatic IC Testing sue-
cessfully the user should enter initially the necessary information to
program this ATS.
This information is entered via a hexadecimal key-
board, it describes the IC to be tested and the ATS programming mode.
An illustration of the hexadecimal keyboard is shown in Figure 5.1.
Before outlining the steps to follow when using this ATS, an
explanation of the
~ecessary
commands to program the ATS is presented.
Also, the use of cassette Load/Dump command is explained.
Refer to keyboard on Figure 5.1.
V.l.l
MONitor Key
The purpose of the MONitor key is to suspend program execution
and to return control to that portion of the ZBUG that scans the key
for input of command.
CPU registers and
The MON key preserves the status of the ZSO-
ZBUG-R&~
variables.
This key is used to cancel or
terminate a previous command or data entry.
Depressing of the MON
key will terminate a partial or complete data entry or will allow
one to exit a command mode such as Memory Examine or Register Examine.
63
64
CASS
LOAD
C.ASS
l)UMP
~1\E.I\~
PP..O~
MEM
l'OR.T
'REG-
p.eG'
EXAM
EXAM
EXAM
EX.#\t-\
PROM
A
NEX.T
l
"
MON
3
c.
9
7
~
1-\
L
4
5
b
IX
IY
\
2.
?c.
SP
·~~=
0
r
E
Figure 5.1
PoiNT
D
SIMGLiii
ST£P
cJ(.Ec.
Illustration of Hexadecimal Keyboard Used in This ATS
65
Whenever the MON key is depressed the Prompt symbol
played on tpe left hand display.
rr ___ n
will be dis-
Make sure this prompt symbol is dis-
played before a new mode of operation is attempted.
V.l.2
MEMory EXAMine Key
The MEM EXAM key is used to examine and change memory locations.
The first step in using the MEM EXA}l key is to enter four HEX digits
(0 through F) representing the memory address desired.
Enter the ad-
dress high digit first and it will be registered on the address display as it is entered.
When all four address digits have been
entere~
press the MEM EXAM key and the data in that memory location will appear on the data displays.
Depressing the NEXT key will cause the
memory address to increment by one and the data display will update
corresponding to the new address.
At any time there are six digits
showing (four address, two data) new data can be entered into that
memory address by simply entering two more HEX digits.
The data dis-
play will not update until both digits have been entered because ZBUG
first writes data into memory, then reads it back to the data display.
V.l.3
REGister EXAMine Key
The following registers can be examined and changed by the use
of REG EXAM key; A, B, C, D, E, F, H, L, I, IFF, PC, lX, and lY.
The
Stack Pointer can be examined with this key but it cannot be changed.
Depress the data key corresponding to the register desired followed by
the REG EXAM key.
The display will show the register selected and its
66
value.
To change the value shown for a register simply enter two
digits of new data (four digits for lX, lY and PC).
This mode of op-
eration can be aborted at any time by depressing the MONkey.
V.l.4
EXECute Key
The EXECute key allows the user to command the Z80-CPU to begin
execution of a user's program in either RAM, ROM or EPROM.
of operation are provided:
Two modes
Proceed from the current address, or exe-
cute from the address entered and shown on display.
The Proceed mode
uses the content of the Program Counter register as the beginning
point of execution.
To use this mode simply depress the EXEC key and
execution will begin at the address displayed by the PC key in the
Register Examine Mode.
To execute from the ,beginning of a program,
enter the four digits of the desired starting address followed by the
EXEC key.
V.l.5
Cassette Dump
This mode of operation is used to save volatile programs or in-
formation in the RAM on inexpensive cassette tape using the Kansas
City Standard recording technique.
Conenct the recorder to the Z80
Starter Kit using an audio patch cord connecting the "AUX" connector
to the Z80 Starter Kit to the "AUXILIARY" or "MIC" input of the tape
recorder.
Once the data to be saved is in RAM, set up memory loca-
tions · 23COH-23C3H with the starting and ending address of the memory
locations to be saved using the following procedure:
1.
Place tape to be recorded into tape recorder and rewind
67
fully.
2.
Using the Memory Examine Mode, enter the starting address of
the memory locations to be saved into 23COH and 23ClH (high
byte into 23COH and low byte into 23ClH).
3.
Using the Memory Examine mode enter the address of the last
RAM location to be saved into 23C2H and 23C3H (high byte to
23C2H and low byte to 23C3H).
4.
Make sure the prompt symbol is being displayed and depress
the CASS DUMP key, followed by turning the recorder on in
the record mode.
5.
The prompt will disappear.
No volume adjustments are required as this is handled by the
AGC of the recorder.
When the Dump is completed, the prompt
sign will reappear, indicating that the Dump is complete and
that the recorder can be shut off.
V.l.6
Cassette Load
This mode of operation is used to load programs or information
from cassette tape to RAM using the Kansas City Standard as the recording technique on the tape.
To load a tape simply follow these
steps:
1.
Connect the recorder to the Z80 Starter Kit using an audio
patch cord to connect "MONITOR OUT" or "EARPHONE" to the
connector marked "EAR" on the Z80 Starter Kit.
2.
Turn the recorder's tone control to maximum treble and minimum bass.
Rewind the tape.
68
3.
Turn the recorder's volume control to minimum volume.
4.
Make sure the prompt is showing and depress the CASS LOAD
key - the prompt will disappear.
5.
Increase the volume until the LOAD LED just lights and then
increase the volume control about 20% more.
The LED should
stay lit during the load.
6.
If the load is successful (i.e., all checksums have been verified) ZBUG will respond with the prompt symbol and the recorder can be shut off.
7.
If a checksum error is detected during loading, the address
of the next block of data will be shown on the display.
All
data up to the previous block of data had been loaded successfully.
Try to load the tape again and verify the volume
and tone control settings.
8.
The LOAD LED can be used to index into several records on the
same cassette, as it will light when data is present on the
tape and go off during inter-record gaps.
This feature will
allow the user to put several programs on the same cassette
tape.
For more detailed information on these commands and the other
commands available in the hexadecimal keyboard refer to the Z80
Starter System Operations Manual.
V.l.7
ATS Power Up Sequence
Before applying power to the ATS verify that switch 3 (s 3 ) is
69
in the MONITOR RST position.
the Reset Switch (S ).
1
Then apply +5V + 5% power and depress
A prompty symbol "--- 11 should appear on the
display indicating that the ATS is ready.
For a more detailed infor-
mation refer to Z80 Starter System Operations Manual.
V.l.8
Using the ATS
The following procedure outlines the steps to be followed when
the Microprocessor System for Automatic IC Testing is operated.
In
the procedure all the user's key entries are underlined, the ZBUG responses are not underlined.
Both user's key entries and ZBUB re-
sponses are in Hexadecimal Code.
Display/Keyboard
Explanation
If prompt symbol
1
11
II
is not present, press
RESET (S ).
1
At this
moment some LEDs in the
ATS could be on •
2
.12CB EXEC
The ATS enters in a known
initial state.
When LED
No. 1 (see Figure 5.2)
goes on, insert the DUT in
the appropriate zero insertion force (ZIF) socket,
as indicated in Figure 5.3.
il
7.0
MODE
INFORMATION
LED
COLOR
ALL
INSERT IC
1
RED
PROGRAM
END OF PROGRAM
2
YELLOW
MODE
TEST
IC IS GOOD
3
GREEN
TEST
IC IS BAD
4
RED
LEARN
END OF LEARN
5
YELLOW
MODE
Figure 5.2
Format of the ATS LED Display
.
71
2
14 PIN
\'\ PIN
7GMO
4
3
ib VIN
SVcc
G~D
&G.ND
Figure 5.3
Layout of Zero Insertion Force Sockets in ATS
I?>
72
Step
3
Display/Keyboard
Explanation
MON
Prompt Symbol "---" appears on display.
4
2000 MEM EXAM
MEM EXAM Key is used to
access memory location 2000.
2000 XX
Location 2000 has random
value XX.
5
2000 XX PACW
Enter Port A Code Word
NEXT
(PACW), then use NEXT
Key to advance to next
memory location.
PACW
format is indicated in
Figure 5.4.
6
2001 XX PBCW
Enter Port B Code Word
NEXT
(PBCW), then use NEXT
Key to advance to next
memory location.
PBCW
format is indicated in
Figure 5.4.
7
2002 XX CPA
Enter Clock Pins Port A
NEXT
(CPA) word, use NEXT Key
to advance to next memory
location.
CPA format is
shown in Figure 5.4.
73
CODE WORD FORMAT
Port B Code Word (PBCW)
Pi = DUT pin number i, i
P
1
= 1,
1, 2, • • • 16
input pin in DUT
P = 0, output pin in DUT
2
Pins not used by the IC, VCC and ground are set to 0.
CLOCK PIN WORD FORMAT
D2
Dl
DO
D3
jcs
Ic16l
Ci
i
=
I cl
c1sl c14/c13 Ic12lcu I c1o I c9
c7 lc6 jcs
= 1,
jc4 lc3
J
c2
if pin i is a clock pin, otherwise is set to 0.
1, 2' • . .16
OPERATION MODE WORD FORMAT
X
Figure 5.4
I I
X
X
X
I I
X
X
0
0
TEST MODE
0
1
PROGRAM MODE
1
1
LEARN MODE
Format of Words Input, to Program the ATS
74
8
Display/Keyboard
Explanation
2003 XX CPR NEXT
Enter Clock Pins Port B
---
(CPB) word, use NEXT Key
to advance to next memory
location.
CPB format is
shown in Figure 5.4.
9
---.
2004 XX PMW MON
Enter Program Mode Word
(PMW), its format is indicated in Figure 5.4.
Use MON Key to terminate
data entry.
Prompty symbol ''---" appears
on display.
If the ATS is operated in
10
Program Mode, input test
pattern as indicated in
Section V .1. 9.
11
EXEC
ATS starts operating in
mode selected in Step 9.
The end of the operating
mode and test results are
indicated by an LED display
is shown in Figure 5.2.
75
12
Display/Keyboard
Explanation
MON
The DUT can be removed
from the ZIF socked.
If
the ATS is operated in
Program Mode, examine the
DUT responses as indicated
in Section V.l.lO.
Prompt symbol "--- 11 appears
on the display.
V.l.9
Generating Test Patterns to the DUT Hhen the ATS is Operated
in Program Mode
Hhen the ATS is operated in Program Mode the user generates the
test patterns to the DUT.
The responses to those patterns are stored
in memory, and examined by the user to determine the performance of
the DUT.
The test patterns input to the DUT have the following format:
I 0 I0
0
0
I1 s
1
0
0
0
ra
1z
Ifl
0
0
0
71 1 61
I
0
12
I~
0
0
Is
I~
0
0
I 0 IF
IJ I I? I 1J
0 I 0 IF
13 I Izl 1J
Test Pattern 2
0
Flag Word N
0
0
F
Flag Word 1
Test Pattern 1
Flag
~-lord
2
Test Pattern N
76
Each test pattern has a flag word associated with it.
The flag
word obeys the following format:
0
0
0
0
0
0
0
F
F
= 0,
F
= 1, next word is not a test pattern, indicating the end of
next word is a test pattern
the test patterns input.
The test pattern word input to the DUT obeys the format indicated
below:
I.].
= ].. th input pin in t::he DUT,
i
= 1,
. . .'
8
I.].
= 1, high level is applied to t h e J..th input in the DUT.
I.].
= 0, low level is applied to t h e J.. th input in the DUT.
Figure 5.5 shows a 7400 Quad two inputs NAND Gates), and a 7404
(Hex inverters) gates with their pins labeled according to the Test
Pattern word format.
The test patterns to be input to the DUT can be entered into
the ATS memory following the procedure below:
1
Display/Keyboard
Explanation
249 7 MEM EXAM
MEM EXAM Key is used to
access memory location
2497.
77
7
A,
s.
I, 1z.
"·
"1. lh 'h
1?. ! ..
'""
TEST PATTERN WORD FORMAT
I Ir I1~ I1~ I1~ I~~ I:r I l
1•
I. =
~
7
1
ith.
~nput
1•
pin in DUT
I. = 1, high level is applied
~
to the
ith.
~nput
in DUT
I. = 0, low level is applied
~
1<.
Is
Vc.c
Ac.
Yr. A;
I"'
.;
A,
I,
Figure 5.5
Y,
12.
At.
'1:&.
II
"1'z.
"4
'C's
JO
ll.s
"~
y""
'
9
to the
ith.
~nput
in DUT
Ys ~No
'Il
Labeling DUT Inputs Pins According to the Test Pattern
Word Format
7-8
2
Display/Keyboard
Explanation
2497 XX
Location has random value XX.
249 7 XX FWl NEXT
Enter Flag Word 1, use NEXT
Key to advance to next memory
location.
3
249 8 XX TPl NEXT
Enter Test Pattern 1, use NEXT
Key to advance to next memory
location.
Repeat steps 2 and 3 until all
4
Flag Words and Test Patterns
have been entered.
5
24YY XX MON
Use MON Key to terminate
data entry.
V.l.lO
Examining the Responses of the DUT to the Test Patterns
The following procedure allows the user to read the responses of
the DUT, to the test patterns, from the ATS memory.
1
Display/Keyboard
Explanation
2497 MEM EXAM
MEM EXAM Key is used access
memory location 2497.
2497 PART 1
Location has Port A Response
to Test Pattern 1 (PART 1)
2
2497 PART 1 NEXT
Use NEXT Key to advance to
next memory location.
2498 PBRT 1
Location has Port B Response
79
Display/Keyboard
Explanation
to Test Pattern 1.
3
2498 PBRT 1 NEXT
Use NEXT Key to advance to
next memory location.
2499 PART 2
Location has Port A Response
to Test Pattern 2.
4
2499 PART 2 NEXT
Use NEXT Key to advance to
next memory location
249A PBRT 2
Location has Port B Response
to Test Pattern 2.
Repeat steps 2 through 4 until
5
all responses are read.
The
number of responses is twice
the test patterns input, see
Figure 5.6.
Once the responses are read from ATS Memory they can be analyzed
as follows:
The response to test pattern number X has the following format:
Port A Response to Test
Pattern X (PART X)
Port B Response to Test
Pattern X (PBRT X)
P.
1
DUT pin i, i
= 1, 2, . . • , 16
80
Test Pattern Input to DUT
1>-r
l)"
Dlii D-4
n~
'Da. 'D. l>o
Response to Test Pattern
"h llc.
Ds b4 1> 3 1>2. l)o
Address
llo
lolololololololol
,,, I~~ !71 r, Irl>l"41 r~l r~l I,j
I~ I,711>~.1 Ps Ip41 P,l1>~ I1', I,AKTI
F~~lolololololololol
I1\ I
~~
2"\97
11>u.l r,s IYt41 i'.J IP,"L Ii'.. ll\o IY9 1116\UI
?7
1. Pc.l \\ IY41 p31 PL I?,
lliAl\12
TV2
j1, It?l t~ol!s I"'1:1 I!~I t, I
'"'"I P.s Ip,., Iy,,_j Pn Ir,.. IY9 ]vSRil
N3
jo!oiolololololol
Ir~ I?, IPc. I lv41 I Ir, JliAI\13
\)13
i>s
?3
l'\99
2.49A
i'a
l l lv,"~l P,,j P,l} P.. l P... l19 JvsR\3
?u. ?15
l49C
•
~~~~~~~,~~~~~~~~ ~~~N
j1.~ l r15 l r."~j ~'•31 P.,.l P.. 1?,.. ] r,
F'N
)l~\ I0 I0 I0
Figure 5.6
IVBRTN
WX'1Z+I
I0 I0 I0 I0 I I I
Relation Between the Memory Locations of the Test Patterns
Input to DUT and Its Responses
81
These two words
and its response.
(~ARTX
and PBRTX) contain the test pattern input
The test pattern input appears in the bit locations
associated to DUT input pins.
In the same way the response appears in
the bit locations associated to DUT output pins.
The DUT input/output
configuration is specified in Port A Code Word (PACW) and in Port B
Code Word (PBCW), see Figure 5.4.
CHAPTER VI
Performance Evaluation and Conclusions
VI.l
System Implementation
The Microprocessor System for Automatic IC Testing was designed
in accordance with the hardware and software development presented in
Chapters III and IV respectively.
The schematic of the circuitry
designed in the Z80 Starter System is included in a pocket in the back
cover of this project.
Appendix A includes the memory map of the sub-
routines and executive program used along with the Assembly and
Machine program listings.
VI.2· Performance Evaluation
In this section, the Microprocessor System for Automatic IC Testing is evaluated.
A 7404 (Hex Inverters) IC is used to exercise this
ATS in all its operational modes; Learn, Test and Program.
Initially, the ATS is operated in Learn Hode.
In this mode the
responses to the test patterns applied to the DUT are stored in memory.
These responses are then used to test similar ICs under Test Mode.
Finally, test patterns are applied to the DUT, with the ATS operating
in Program Mode.
The responses to these test patterns are then an-
alyzed to determine the performance of the DUT.
a known-good IC is used,
In this evaluation
thus the results obtained reflect the ATS
performance.
VI.2.1
ATE OPerating in Learn Mode
Step
Display/Keyboard
Explanation
If·prompt symbol"
1
82
"
83
Display/Keyboard
Explanation
is not present, press
RESET (S ) .
1
At this time
some LEDs in the ATS could
be on.
2
12CB EXEC
ATS enters in a known-initial
state.
When LED No. 1 (see
Figure 5.2) goes on insert
the 7404 gate in ZIF socket
No. 1.
3
See Figure 5.3.
MON
Prompt symbol
11
--"
appears
on display.
4
2 000 MEM EXAM
MEM EXAM Key is used
to access memory location
2000.
2000 XX
Location 2000 has random
value XX.
5
2000 XX 15 NEXT
Enter Port A Code Word
(PACW) for this gate (7404),
see Figure 5.4. ·use NEXT
Key to advance to next
memory location.
84
6
Display/Keyboard
Explanation
2001 XX 15 NEXT
Enter Port B Code Word
(PBCW) for this gate (7404),
see Figure 5.4.
Use NEXT
Key to advance to next
memory location.
7
2002 XX 00 NEXT
---
Enter Clock Pins Port A
(CPA) Word for this gate
(7404), see Figure 5.4.
Use
NEXT Key to advance to next
memory location.
8
2003 XX 00 NEXT
Enter Clock Pins Port B
(CPB) Word for this gate
(7404), see Figure 5.4.- Use
NEXT Key to advance to next
memory location.
9
2004 XX 03 MON
Enter Program Mode Word,
indicating Learn Mode, see
Figure 5.4.
Use MONKey to
terminate data entry.
Prompt symbol "--"
then appears.
10
EXEC
ATS starts operating in Learn
Mode.
The end of this mode
85
Display/Keyboard
Explanation
is indicated by an LED display
as specified in Figure 5.2.
11
The DUT can be removed from
MON
the ZIF socket.
Prompt symvol
"---"
appears
on display .•
The responses to the test patterns are stored on memory locations
2495 through 2514.
They follow the format indicated in Figure 6.1.
These responses obtained from the 7404 are shown in Figure 6.2.
These
responses can be analyzed following the procedure indicated on section
V.l.lO.
The responses on Figure 6.2 have been analyzed by the author;
they indicate that the IC (7404) is functionally good, thus the ATS
operates as expected, under Learn Mode.
If desired, these responses can be stored in a cassette tape.
Thus, no known-good device will be needed to generate those responses
when testing this IC type.
The procedure to follow is outlined in
Section V.1. 5.
VI.2.2
ATS Operating in Test Mode
To operate the Microprocessor System for Automatic IC Testing on
Test Mode the procedure outlined in Section VI.2.1 is repeated, except:
The Program Mode Word entered in step 9 is now 00 and the end
of Test Mode in Step 10 is signaled by LED No. 3 (see Figure 5.2), in-
86
"D.,
D"
'D~
D-4 D3 D.z
), l>o
I I I I I I I I l ))Al\i I
I I I I ?~RT\
24'37
2.515
'----~1...--l....__.,---'"--""--'---+-1--11
I I I I
I 1 I I
PARTW
= Port A Response to Test Pattern W
PBRTW
= Port
"PA f\i 2
I ] I
I I I"PS\\TN
?AR.'TN
B Response to Test Pattern W
Where W = 1, 2, . • . , N
Figure 6.1
Typical Organization of Responses In ATS Memory
MEMORY LOCATION
RESPONSES
2495
EA EA E9 EA E6 EA E5 EA DA EA D9 EA D6 EA D5 EA
24A5
6A EB 69 EB 66 EB 65 EB 5A EB 59 EB 56 EB 55 EB
24B5
EA EC E9 EC E6 EC E5 EC DA EC D9 EC D6 EC D5 EC
24C5
6A ED 69 ED 66 ED 65 ED 5A ED 59 ED 56 ED 55 ED
24D5
EA F2 E9 F2 E6 F2 E5 F2 DA F2 D9 F2 D6 F2 D5 F2
24E5
6A F3 69 F3 66 F3 65 F3 SA F3 59 F3 56 F3 55 F3
24F5
EA F4 E9 F4 E6 F4 E5 F4 DA F4 D9 F4 D6 F4 D5 F4
2505
6A F5 69 F5 66 F5 65 F5 SA F5 59 F5 56 F5 55 F5
Figure 6-2.
Responses Obtained from the 7404 IC when
the ATS is Operated in Learn Mode
87
88
dicating that the DUT (_7404) is good.
The DUT used in this mode of operation is the one used t·o generate
the responses stored in memory during Learn.Mode.
Those responses
were carefully examined in the previous section, thus a good result
on Test Mode, indicates a good ATS performance under Test Mode.
VI.2.3
ATS Operating in Program Mode
To operate the Microprocessor System for Automatic IC Testing on
Program Mode the following test patterns are applied to the DUT (7404).
I
0
0
0
0
0
1
],
0
Test Pattern 1
0
0
0
0
1
0
0
1
Test Pattern 2
0
0
1
0
0
1
1
0
Tes.t pattern 3
0
0
1
1
1
1
0
0
Test Pattern 4
These test patterns are entered in the.ATS memory following the
procedure indicated in Section V.l.9.
Then, to exercise the ATS on
Program Mode the procedure outlined in Section VI.2.1 is followed,
except:
the Program Hode Word entered in Step 9 is now 01 and the
end of Program Mode is indicated by LED No. 2, see Figure 5.2.
Once the Program Hode is ended the responses to the test patterns
input to the DUT are read from ATS memory, see Section V.l.lO.
These responses are listed below (in binary).
1
1
0
1
0
1
1
0
PART 1
1
1
1
0
1
0
1
0
PART 1
89
0
1
1
0
1
0
0
1
I
P~T
1
1
1
0
1
0
1
1
I
PBRT 2
1
1
0
1
0
1
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
jo
1
2
3
I
] PBRT 3
I PART 4
P~T
] PBRT 4
Examining them indicates the proper operation of the Microprocessor System for Automatic IC Testing on Program Mode.
A variety of ICs, besides the 7404, have been used in the evaluation of this ATS.
It has performed as expected when exercised in
its different operational modes.
VI.3
Conclusions
The Microprocessor System for Automatic IC Testing described in
this project can detect any logical fault on 14 pin and 16 pin Transister Logic (TTL) ICs.
If desired this ATS can be expanded to allow testing 24 pin ICs,
ICs having flat package, and ICs of different logic families such as:
DTL, CMOS, etc.
A new mode of operation could be added to test ICs when a knowngood device is not available.
In this mode the user supplies the
test patterns and expected responses for the DUT.
The ATS then with
this information determines the performance of the DUT.
This results
90
in an improved Program Mode.
Due to the features provided in this ATS, it can be modified and
expanded to fit the user's needs, with relative ease.
91
References
[Artwick, 1980]
Artwick, B. A. Microcomputer Interfacing.
New Jersey: Prentice-Hall, Inc., 1980.
[Breuer, Friedman,
1976]
Breuer, M. A. and Friedman, A. D. Diagnosis
and Reliable Design of Digital Systems.
California: Computer Science Press, Iric.,
1976.
[Bur sky, 1980]
Bursky, D. ~C Boards Pack the CPUs and the
Support for Every System -- But How Much is
Enough? Electronic Design, March, 1980,
28(6), 85-89.
[Desena, 1979]
Desena, A. Loaded Board Test Equipment.
Electronic Test, March 1979, 2(3), 32-40.
[Mancone, 1979]
Mancone, J. G. Guidelines for ATE Selection.
Electronic Test, September 1979, 2(9), 36-41.
[MK 3880, 1977]
MK 3880 Central Processing Unit Technical
Manual. USA: Mostek, Inc., 1977.
[MK 3880, 1978]
MK 3882 Counter Timer Circuit Technical
Manual. USA: Mostek, Inc., 1978.
[MK 3881, 1978]
MK 3881 Parallel I/O Controller Technical
Manual. USA: Mostek, Inc., 1978.
[280 ASS, 1977]
Z80 Assembly Language Programming Manual.
USA: Zilog, Inc., 1977.
[Z80 Starter, 1978]
Z80 Starter System Operations Manual.
Micro Design Concepts, 1978
USA:
APPENDIX A
MEMORY MAP OF PROGRAM,
ASSEMBLY AND MACHINE PROGRAM
LISTINGS
92
1383H
EXECUTIVE PROGRAM
12CBH
12CAH
NOT USED
1267H
1266H
REMOVE DUT SUBROUTINE (REDUT)
1256H
1255H
COUNTER LOAD SUBROUTINE (CNLS)
1251H
1250H
POlVER AND DISPLAY SUBROUTINE (PDS)
124CH
124BH
INPUT/COMPARE SUBROUTINE (INCOM)
1227H
1226H
INPUT/STORE SUBROUTINE (INSTO)
1217H
1216H
CLOCK SUBROUTINE (CLOCK)
1202H
1201H
GENERATE AND OUTPUT TEST PATTERN
SUBROUTINE (GOTD)
1196H
1195H
P-PATTERN SUBROUTINE (PSUB)
llllH
lllOH
SUBROUTINE TO PROGRAM PIO 2 TO
BIT MODE (PI02S)
10F3H
10F2H
SET INITIAL CONDITIONS SUBROUTINE
(SET)
lOCEH
Figure A-1 Memory }~p of the Subroutines and Executive Program
Used in the ATS
93
94.
Assembly Program Listing of the Subroutines and Executive Program
Used in the ATS
Set Initial Conditions Subroutine (SET)
LABEL OP CODE OPERAND
SET:
COMMENTS
LD
A, FFH
Load FFH in Accumulator
OUT
(96H), A
PIO 1 Port A Mode Word
XOR
A
Clear Accumulator
OUT
(96H), A
Output line configuration
LD
A, 07H
OUT
(96H), A
LD
A, OlH
OUT
(94H), A
LD
A, FFH
OUT
(82H), A
PIO 2 Port A Hade Word
OUT
(82H), A
Input line configuration
OUT
(83H), A
PIO 2 Port B Mode
OUT
(83H), A
Input line configuration
LD
A, 07H
OUT
(82H), A
PIO 2 Port A Interrupt Control
Word
OUT
(83H), A
PIO 2 Port B Interrupt Control
Word
LD
A, 03H
OUT
94H, A
RET
Interrupt Control Word
LEDs off; +5V off
~-lord
start LED is set on
95
Program PIO Subroutine (PI02S)
LABEL OP CODE OPERAND
PI02S:
CO.MMENTS
LD
A, FFH
OUT
(82H), A
PIO 2 Port A Mode Word
LD
A, (2000H)
Load Accumulator with PACW
Complement Accumulator
CPL
OUT
(82H), A
LD
A, 07H
OUT
(82H), A
LD
A, FFH
OUT
(83H), A
PIO 2 Port B Mode Word
LD
A, (2001H)
Load Accumulator PBQv
I/O line configuration
Interrupt Control Word
Complement Accumulator
CPL
OUT
(83H), A
LD
A, 07H
OUT
(83H), A
I/O line configuration
Interrupt Control Word
RET
P-pattern Subroutine (PSUB)
LABEL OP CODE OPERAND
PSUB:
COMMENTS
LD
A, (2000H)
Load Accumulator PACW
LD
B, A
Load PACW in Reg. B
LD
A, (2002H)
Load Accumulator with CPA
CPL
Complement Accumulator
96
LABEL OP CODE OPERAND
AND
B
PADW
LD
(2005H), A
Store PADW
LD
A, (2001H)
Load Accumulator with PBCW
LD
B, A
Load PBCW in Reg. B
LD
A, (2003H)
Load Accumulator with CPB
CPL
ONE:
COMMENTS
Complement Accumulator
AND
B
PBDW
LD
(2006H), A
Store PBDW
XOR
A
Clear Accumulator
LD
B, A
; Clear M Counter
LD
C, A
Clear N Counter
LD
D, A
Clear F
LD
E, A
LD
L, A
SET
0, E
LD
A, (2005H)
Load Accumulator with PADW
LD
H, A
Load Reg. H with PADW
LD
A, H
AND
E
JP
z,
LD
(lX + 0), E
Store Pn
INC
lX
Increment Index Register
INC
L
Increment y
Check bit n in Accumulator
(CAT)
Jump to CAT if zero
' .
97
LABEL OP CODE OPERAND
CAT:
TOY:
TWO:
LAST:
COMMENTS
INC
B
Increment m
INC
c
Increment n
SLA
E
LD
A, c
CP
08H
JP
Z, (TOY)
Jump to TOY if (n) = 08H
JP
(ONE)
Jump to ONE if (n)
BIT
0, D
Test F
JP
NZ, (TWO)
Jump to TWO if b 0 in F =f 0
SET
o, D
Set b
LD
c, OOH
Clear n counter
LD
A, L
Load Accumulator with OPA
LD
(2007H), A
OPA is stored in location 2007H
LD
L, OOH
LD
A, (2006H)
LD
H, A
SET
(ONE)
Jump to ONE
LD
A, B
Load Accumulator with (m)
CP
09H
JP
P, (THREE)
if (m) = 09H jumpt to THREE
LD
A, L
Load Accumulator with OPB
LD
(2008H), A
OPB is stored in location OPB
RET
0
=F
08H
in F
Load Accumulator with PBDW
98
LABEL OP CODE OPERAND
THREE: LD
FOUR:
YES:
COMMENTS
D, OOH
DEC
lX
LD
A, (lX + 00)
OR
D
DEC
lX
DEC
B
LD
D, A
LD
A, B
CP
07
JP
z,
JP
(FOUR)
LD
A, D
INC
lX
LD
(lX + 0), A
LD
A, (2007H)
LD
E, A
LD
A, OSH
SUB
E
OPB
JP
(LAST)
Jump to LAST
(YES)
Accumulator is loaded with Pm
Accumulate Pms
Jump to YES if m = 07H
Jump to FOUR
Load Accumulator with OPA
Test Pattern and Output Subroutine (GOTP)
LABEL OP CODE OPERAND
COMMENTS
GOTP:
; M Register
EX
99
LABEL OP CODE OPERAND
ATWO:
RED:
COMMENTS
XOR
A
Clear M Register
LD
L, A
Clear RB Register
LD
H, A
Clear RA Register
LD
B, A
Clear i Register
SET
0, B
Set b
LD
D, B
Set b
LD
E, B
Initialize shift
EX
AF, AF
LD
lX, 2009H
LD
A, C
Load Accumulator with Count
Register
AND
E
Check bM
JP
Z, (RED)
If bM is zero jump to RED
LD
A, (lX +o)
Load Accumulator with PAi
OR
L
LD
L, A
INC
lX
Increment Index Register
INC
B
Increment i Register
LD
A (2007H)
Load Accumulator with K
INC
A
CP
B
JP
Z, BLACK
EX
AF, AF
INC
0
0
in i Register
in j Register
1
If K
=
i
jump to BLACK
1
Increment M
100
LABEL OP CODE OPERAND
EX
AF, AF
SLA
E
JP
ATWO
BLACK: LD
H, L
LD
COMMENTS
1
Jump to ATWO
L, OOH
Clear RB Register
INC
Increment M
EX
SLA
E
EXX
LD
A, (2007H)
Load Accumulator with OPA
LD
B, A
Transfer OPA to B Register
LD
A, (2008H)
Load Accumulator with OPB
ADD
B
ADD OP A and OPB
INC
A
LD
B, A
1
EXX
CP
B
JP
Z, (AONE)
Jump to AONE if i = N
A, C
Load Accumulator with count
AND
E
Check bM
JP
Z, (JET)
If bM is zero jump to JET
LD
A, (lX
CLOSE: LD
+
0)
Transfer PBi to Accumulator
101
LABEL OP CODE OPERAND
JET:
AONE:
OR
L
LD
L, A
INC
lX
INC
D
LD
A, (2008H)
INC
A
CP
D
JP
z,
EX
AF
INC
A
EX
SLA
AF, AFl
E
JP
(CLOSE)
LD
A, H
OUT
(SOH), A
LD
A, L
OUT
(81H), A
COMMENTS
Load Accumulator with OPB
Compare L and j
(AONE)
'
IF L
=
j jump to AONE
1
AF
Increment M
Jump to CLOSE
OUTPUT test pattern to Port A
OUTPUT test pattern to Port B
RET
Clock Pulse Subroutine (CLOCK)
LABEL OP CODE OPERAND
CLOCK: LD
OR
A, (2002H)
Load Accumulator with CPA
H
OR CPA with Port A test pattern
102
LABEL OP CODE OPERAND
COMMENTS
OUT
(SOH), A
OUTPUT clock pulse
LD
A, (2003H)
Load Accumulator with CPB
OR
L
OR CPB with Port B test pattern
OUT
(SlH), A
OUTPUT clock pulse
LD
A, H
OUT
(SOH), A
LD
A, L
OUT
(SlH), A
RET
Input Store Subroutine (INSTO)
INSTO: IN
A, (SOH)
; Load Accumulator with Port A
data (PAPL)
LD
(lY+O),A
Store data in memory
INC
lY
Increment Index Register
IN
A, (SlH)
Load Accumulator with Port B
data (PBPL)
LD
(lY + 0), A
Store data in memory
INC
lY
Increment Index Register
RET
Input Compare Subroutine (INCOM)
LABEL OP CODE OPERAND
INCOM: EX
AF
'
AF
1
COMMENTS
103
LABEL OP .CODE OPERAND
BONE:
COHMENTS
1
XOR
A
EX
AF, AFl
IN
A, (SOH)
Load Accumulator \vith PAPL
LD
B, A
Transfer PAPL to B Register
LD
A, (lY + 00)
Load Accumulator with response
from memory
CP
B
Compare them
JP
NZ (BONE)
If different jump to BONE
EX
AF, AF
SET
0, A
EX
AF, AFl
INC
lY
Increment Index Register
IN
A, (81H)
Load Accumulator with PBPL
LD
B, A
Transfer PBPL to B Register
LD
A, (lY + 0)
Load Accumulator with response
from memory
CP
B
Compare them
JP
NZ, (nn)
If different jump to BONE
EX
AF, AFl
SET
1, A
EX
AF, AFl
INC
lY
RET
; Clear A
Register
1
Set b
Set b
0
1
1
in A Register
1
in A Register
Increment Index Register
104
Power and Display Subroutine (PDS)
LABEL OP CODE OPERAND
PDS:
LD
A, D
OUT
(94H), A
COMMENTS
RET
Counter Load Subroutine (CNLS)
LABEL OP CODE OPERAND
CNLS:
LD
C, (lY
+
CmlMENTS
0)
RET
Remove IC Subroutine (REDUT)
LABEL OP CODE OPERAND
COMMENTS
A, FFH
Load FFH in Accumulator
OUT
(82H), A
PI02 Port A Mode Word
OUT
(82H), A
Output line configuration
OUT
(83H), A
Output line configuration
LD
A, 07H
OUT
(82H), A
Port A Interrupt Mode Word
OUT
(83H), A
Port B Interrupt Mode vJord
REDUT: LD
RET
105
Assembly Listing of Executive Program
LABEL OP CODE OPERAND
COMMENTS
LD
lY, 2495
Initialize Index Register
LD
SP, 2040H
Initialize Stack Pointer
CALL
SET
HALT
CALL
PI02S
LD
LX, 2009H
XOR
A
OUT
(94H), A
CALL
064F
Initialize IX Register
ZBUG 20 ms delay routine to
debouce relay
EXX
LD
L, OOH
EXX
CONE:
CALL
PSUB
LD
C, OOH
CALL
GOTP
LD
A, (2002H)
LD
B, OOH
CP
B
Check if but is clocked
JP
NZ, CLCK
If DUT is clocked jump to CLCK
LD
A, (2003H)
Accumulator is loaded with CPB
LD
B, OOH
Clear Counter
Accumulator is loaded with CPA
106
LABEL OP CODE OPERAND
COMMENTS
CP
B
JP
NZ, CLCK
JP
PM
CLCK:
CALL
CLOCK
PM:
LD
A, (2004H)
LD
B, OlH
CP
B
Check if ATS operates in Program
Node
JP
Z, PRGM
If ATS operates in Program Node
jump to PREN
LD
B, 03H
CP
B
check if ATS operates in LEARN
Mode
JP
Z, LEARN
Jump to LEARN if Mode was selected
JP
TEST
CALL
INS TO
LD
A, (lY + 0)
LD
B, OOH
CP
B
check if all input patterns were
used
JP
NZ, EPGM
I f so jump to EPGM
INC
IY
increment IY Register
CALL
CNLS
DEC
lY
PRGH:
If DUT is clocked jump to CLCK
Program Hade Word is transferred
to Accumulator
107
LABEL OP CODE
OPERAl~D
JP
CONE
EPGH:
LD
D, 05H
CTWO:
CALL
REDUT
CALL
PI02S
CONMENTS
HALT
LEARN: CALL
CNTR:
FLAG:
INS TO
LD
A, H
OR
L
Check if all test patterns were
generated
JP
Z, FLAG
If so jump to FLAG
INC
c
Counter is incremented
JP
CONE.
EXX
BIT
0, L
JP
NZ, ELERN
SET
EXX
JP
CNTR
ELERN: EXX
TEST:
LD
D, 21H
JP
CTWO
CALL
IN COM
EX
AF,AF
108
LABEL OP CODE OPERAND
TAG:
AND
03H
XOR
NZ, ETMB
EX
AF, AF
LD
A, H
OR
L
JP
Z, TAG
JP
CNTR
COMMENTS
Jump to ETMB if DUT is bad
Check if test was finished
EXX
BIT
O, L
JP
NZ, ETM
SET
0, L
Jump to
E~l
if test was finished
EXX
JP
ETM:
ETMB:
CNTR
EXX
LD
D, 09
JP
CTWO
EX
AF, AF
LD
D, 11
JP
CTWO
Jump to CNTR if test is not
finished
MACHINE PROGRAM LISTING
lOCO FF
lODO b3
lOEO 82
lOFO 94
1100 82
1110 00
1120 47
1130 C3
1140 04
1150 65
1160 CB
1170 16
1180 85
1190 08
11AO DD
llBO 04
llCO 11
llDO 3A
llEO DD
llFO 11
1200 C9
1210 D3
1220 FD
1230 B8
1240 B8
1250 00
1260 3E
1270 FF
1280 FF
1290 FF
12AO FF.
12BO FF
12CO FF
12DO 40
12EO CD
12FO 02
1300 13
1310 06
1320 00
1330 05
1340 oc
1350 D9
1360 13
1370 CB
1380 31
FF
96
D3
C9
3E
3A
3A
3A
oc
11
C3
00
11
93
21
3A
00
08
7E
00
00
80
77
C2
C2
FD
07
FF
FF
FF
FF
FF
FF
20
4F
20
C3
03
B8
CD
C3
16
08
cs
13
FF FF
AF D3
82 D3
00 3E
FF D3
00 20
03 20
OS 20
CB 23
CB C2
C3 35
DD 2B
C3 74
C3 6C
09 20
07 20
65 2E
20 'so
00 BS
08 3C
3A 02
7D D3
00 FD
4A 12
4A 12
4E 00
D3 82
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
CD CE
06 D9
06 00
07 13
B8 CA
C2 2F
56 12
EC 12
21 C3
7C BS
D9 C3
FF 00
FF
96
83
FF
83
47
2F
67
79
OE
11
DD
11
11
79
3C
00
3C
6F
08
20
81
23
08
08
C9
D3
FF
FF
FF
FF
FF
FF
10
2E
B8
CD
38
13
CD
D9
31
CA
40
FF
3E
D3
D3
3A
3A
AO
7C
FE
00
78
7E
7A
FF
A3
B8
00
47
00
CB
B4
C9
C9
CB
CB
00
83
FF
FF
FF
FF
FF
FF
76
00
C2
02
13
FD
4C
CB
13
6A
13
FF
07
83
82
01
02
32
A3
08
7D
FE
00
DD
08
CA
CA
08
D9
DD
23
D3
00
00
C7
CF
3E
C9
FF
FF
FF
FF
FF
FF
CD
D9
04
12
C3
23
12
45
CD
13
D9
FF FF
D3 96
3E 07
3A 00
20 2F
20 2F
06 20
CA 41
CA 4D
32 07
09 F2
B2 DD
23 DD
AF 6F
AE 11
C2 11
3C 08
B8 CA
23 14
C3 DB
80 3A
DB 80
08 AF
08 FD
08 FD
FF D3
FF FF
FF FF
FF :fF
FF FF
FF FF
FF FF
FF FF
F3 10
CD 11
13 3A
3A 04
56 13
CD 51
76 CD
C2 50
27 12
C3 40
16 09
FF.
3E
D3
20
D3
AO
AF
11
11
20
70
2B
77
67
DD
08
CB
FA
3A
11
03
FD
08
23
23
82
FF
FF
FF
FF
FF
FF
FF
DD
11
03
20
CD
12
17
13
08
13
C3
109
FF
01
82
2F
83
32
47
DD
C3
2E
11
OS
00
47
7E
3C
23
11
08
7C
20
77
DB
DB
C9
D3
FF
FF
FF
FF
FF
FF
FF
21
OE
20
06
17
FD
12
CB
E6
D9
31
FF FF
D3 94
D3 83
D3 82
3E 07
OS 20
4F 57
73 00
35 11
00 3A
7D 32
57 78
3A 07
CB co
00 BS
08 CB
D9 3A
79 A3
20 3C
D3 80
BS 00
00 FD
80 47
81 47
00 7A
82 D3
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FD 21
09 20
00 CD
06 00
01 B8
12 FD
2B C3
7C BS
cs D9
03 EE
CB 45
13 08
FF 3E FF
3E FF D3
3E 03 D3
3E 07 D3
D3 83 C9
3A 01 20
SF 6F CB
DD 23 2C
CB 42 C2
06 20 67
08 20 C9
FE 07 CA
20 SF 3E
50 58 08
6F DD 23
23 C3 A4
07 20 47
CA E6 11
BA CA FA
7D D3 81
D3 81 7C
23 DB 81
FD 7E 00
FD 7E 00
D3 94 C9
83 D3 83
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
FF FF FF
95 24 31
AF D3 94
96 11 3A
B8 C2 04
CA 19 13
7E 00 06
EC 12 16
CA 44 13
C3 40 13
03 C2 7C
C2 76 13
16 11 C3
APPENDIX B
DATA SHEETS
110
111
CONNECTION DIAGRAMS
PINOUT A
54/7404
54H/74H04
545/74504
54S/74504A
54LS/74LS04
HEX INVERTER
GNQ
ORDERING CODE: See Section 9
PIN
PKGS
COMMERCIAl. GRADE
MILITARY GRADE
Vee= +5.0 v :t5%,
Vee = +5.0 v :t10%,
OUT
TA
=ooo to +70°C
TA = ·55° C to +125° C
Plastic
OIP!Pl
A
7404PC. 74H04PC
74S04PC, 74S04APC
74LS04PC
Ceramic
OIP!Ol
A
7404DC. 74H04DC
74S040C, 74S04AOC
74LS04DC
54040M, 54H04DM
54S040M. 54S04AOM
54LS040M
A
74S04FC. 74S04AFC
74LS04FC
54S04FM, 54S04AFM
54LS04FM
B
7404FC, 74H04FC
5404FM, 54H04FM
Flatpak
IFl
PKG
TYPE
PINOUT B
9A
6A
31
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PINS
Inputs
Outputs
54/74 (U.L.)
HIGH/LOW
54/74H (U.L.)
HIGH/LOW
54/74S (U.L.)
HIGH/LOW
54/74LS (U.L.)
HIGH/LOW
1.0/1.0
20/10
1.25/1.25
12.5/12.5
1.25/1.25
25/12.5
0.5/0.25
10/5.0
12.5)
DC AND AC CHARACTERISTICS: See Section 3•
SYMBOL
PARAMETER
54/74
54/74H
54/74S
54/74LS
UNITS
CONDITIONS
Min Max Min Max Min Max Min Max
leeH
Power Supply
12
26
24
2.4
feeL
Current
33
58
54
6.6
tPLH
tPHL
Propagation Delay
22
15
10
10
2.0
2.0
4.5
5.0
10
10
IPLH
IPHL
Propagation Delay
!54/74S04A only>
1.0
1.0
3.5
4.0
'DC hm1ts apply over operat•ng temperl:.'ture range: AC lim•ls apply at TA
= +25
111
C and Vee= +5.0 V.
mA
V1N = Gnd
Vee= Max
V1N =Open
ns
Fig. 3·1, 3·4
ns
Fig. 3·1, 3·4
Peripheral/Power Drivers
~
NAnONAL
DS55450/DS75450 series dual peripheral drivers
general description
AND, NAND, OR and NOR drivers, respectively, (posi·
tive logic) with the output of the logic gates internally
connected to the bases of the NPN olltput transistors.
The DS55450/DS75450. series of dual peripheral drivers
are a family of versatile devices designed for use in
systems that use TTL or DTL logic. Typical applications
include high speed logic buffers. power drivers, relay
drivers, lamp drivers, MOS drivers, bus drivers and
memory drivers.
features
•
•
•
•
•
•
•
•
The OS55450/DS75450 series are unique general purpose
devices each featuring two standard Series 54/74 TTL
gates and two uncommitted, high current, high voltage
NPN transistors. These devices offer the system designer
the flexibility of tailoring the circuit to the application.
The OS55451/DS75451, DS55452/0S75452, 0555453/
0575453 and DS55454/0S75454 are dual peripheral
connection diagrams
300 rnA output current capability
High voltage outputs
No output latch-up at 20V
High speed switching
Choice of logic function
TTL or DTL compatible diode-clamped inputs
Standard supply voltages
Replaces Tl "A" and "B" series
(Oual·fn·Line and Metal Can Packages)
.
"·
II
fO,Viftl
"
...
It
Ordat' Number
DS55450J, CS75450J, or DS75450N
,,
fl
TQPY!lW
...
Ord"' Numb"' DS75451N
Ore!"' Numb"' DS75452N
...
fO,VIIW
,.. ....... _.alf'fl'lhn-""---
Order Numbffr
DS55451H or OS75451H
Order Number
DS55452H or OS75452H
Order Number DS75453N
..............
niiii~---­
OrdMNumbur
DS55453H or OS75453H'
Ordw Numbw DS75454N
............... _....,. .....
Order Number
, DS55454H or OS75454H
113
absolute maximum ratings
operating conditions
(Note 1l
I
Supptv Voltage, IVeel !Note 21
Input Voltage
1nm1mltter Voltage !Note 31
Vec·to-Substraftl Voltage
OS55450/0S75450
Colloctor·to-Substrete Voltage
OS55450/0S75450
eonttcto,.B- Volta;t~
OS55450fDS76450
Colloctor·Smintr Voltage !Note 41
OS55450/DS754150
Emittw·Bate Voltage
. OS515450/DS75450
Output Voltage !Note 51
OS55451/DS75451, DS!!5452/DS754152,
OS55453/DS75453,0S55454/DS75454
Collector Current !Note 81
DS554501DS76460
Output Current !Nota 61
OS65451/0S7545 1. OS65462/DS75452,
OS55463/DS754153, OS55454iOS75454
Continuoua Total OilliPttion
Storage T•mperatur• R•nge
Lad Temperature !Soldering, 10 secondll
7.0V
5.5V
5.6V
35V
irl GATES
800mW
2so•c
DS55450/0S75450 (Notes 8 and 9)
Input Cl.,ll Vo~ogo
Vee • Mirt,
HiQII
Vo•
...,_ Low! Output Voluuo
I'
UNITS
v
v
v
v
v
v
-1.5
11 •-12mA, fF;guroJJ
2.4
Ve.r:. •Min, V 11• •O.BV, loN •-tO<kiA, /Figun2J
Vee~
I TV l MAX I
0.8
Min, v, ... • 2V. lo~o. • 16 mA
Vee • Mu, V1 ~ 5.5V.
l'iwu'" 41
Vee • Mu, V1 • 2.4V. tFigu,. 41
Vc:c:•Ma•. V 1 •0.4V. (FifUIWJI
3.3
0.22
0.22
05554!50
05754!50
Voltoge
Input Currfttt
MIN
2
/FitNrtll
L.ow Lavef
I
CONOITIONI
Vo,.
1,.
•e
'e
+125
+70
~·c to +150'C
(Fig:w-i! 1}
Hlglo Low! Input C..rrtnt
-55
0
v
300mA
(Figurw2J
1,,.
v
300mA
low l - Input Valtogo
Input 0.~ n M!JCimum lnpu1
5.5
5.25
30V
HiQII Lowl Input VaitO!II
I,
4.5
4.75
IS.OV
v, ..
v,.
v,
Output Voltogo
UNITS
30V
I
PARAMETER
Temperature, (TAI
OS5545X
OS7545X
MAX
35V
de electrical characteristics
Low~
.
35V
Su1>plv Voltage ,!Vee>
OS5545X
OS7545X
(Note 7).
MIN
0.5
0.4
Input A
,
lngutG
2
mA
IliA
,
InPUt A
40
inpurG
so
ilA
Input A
-1.6
-3.2
mA
mA
-55
mA
lnout G
-18
~A
los
Shcn Circuit OuuJut O..rrenr
Vee • Ma, (Figu,. 5}, (Note 10)
Icc"
Suopiy C..rrent
Vee • Max, V1 • OV. Outouu Hjgh, (Figt.;rw 6J
2
4
mA
Suopiy C..nwnt
lee•
OUTPUT TRANSISTORS
Vee • Max, \/1 • 5V. OutDutJ Low, (Figu,.6/
6
11
mA
Vra"tc~
VIILIUC:alll
V~a,.IIIO
CoiiiC1or-Bate Br•Jkdown Voll'191'
lc:. JOOl.&A. ,,
Coll..to,.Emitter 6,.111cdawn
Voltoge-
lc • 1001-&A, R11 •, 500!1
Emitter·Saa Sttlkdown
h,.
Volt~~;•
1• • 1()0yA,
D
0
'
lc • o
StatiC Forwwd CvrNnt Tr1mf•
Rollo
Ve 1
,
~
v..
•
05554!50, T4
•
+lS'C
05554!50. T4
•
-55'C
05754!50. T 4
•
+25'C
JV, (Note 11)
.
05754!50. T.o •
-
9-cmittw Voltogo
05554!50
(Noll 111
05754!50
VctGIATI
C311ector-Emitter Saturation
v.;,,.
05554!50
(Note 111
0~75460
o" C
• 100mA
10 •300mA
. lc • tOO mA
35
v
30
1/
5
v
I~
25
1/
v
v
le • 300 rnA
30 .
10
IS
1/
lc •lOOmA
25
v
lc • 300 mA
30
v
le • tOO mA
20
25
1/
le • 300mA
18 •10rrtA,Ie • 100mA
0.85
15 • 30 mA, le • 300 mA
18 • 10mA.Ic • 100mA
1.05
0.85
1.05
111 • 30mA, lc • 300mA
19 • 10mA. lc • 100mA
I• • 30 mA, lc • 300 mA
18 • 10mA.Ie • lOQmA
.le • 30mA, lc • JOOmA
-
0.25
0.5
0.25
0.5
1.2
1.4
1
1.2
v
v
v
v
v
0.5
v
0.8
0.4
v
v
0.7
v
Q
114
Z80 PIO PIN CONFIGURATION
Do
o,
19
15
20
14
1
13
40
12
39
10
38
9
3
B
2
7
Oz
CPU
0]
DATA
BUS
04
os
Ds
OJ
PORT B/A SEL
6
CONTROL/DATA
5
SEL
PIC
CONTROL
18
ZOOPIO
16
Ml
+SV
GNO
Az
AJ
44
45
PORTA
1/0
As
A7
A. ROY
As'i'B
4
27
so
28
a,
37
36
29
35
30
26
31
11
32
33
25
iNl
INT ENABLE IN
{
At
MK3681
CHIP ENABLE
iORci
iW
INTERRUPT
CONTROL
Ao
INT ENABLE OUT
34
Bz
83
B4
as
Bs
B7
23
24
22
21
~----·
17
BROV
ii!f's
PORTS
1/0
•
9.0 ELECTRICAL SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS*
115
Specified operating range.
-65°C to +150°C
-0.3V to +7V
Temperature Under Bias
Storage Temperature
Voltage On Any Pin With
Respect To Ground
Power Dissipation
.6W
9.2 D. C. CHARACTERISTICS
Table 9.2-1
TA = OoC to 70°C, Vee= 5 V
:t
5% unless otherwise specified
Parameter
Min
Max
Unit
V1tc
Clock Input Low Voltage
-0.3
0.45
VI He
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Vce+.3
0.8
v
v
viL
viH
Vce·.G
·0.3
2.0
VoL
VoH
1cc
Output Low Voltage
Output High Voltage
Power Supply Current
lu
1LOH
1LOl
1LD
Input Leakage Current
Tri-State Output Leakage Current in Float
Tri-State Output leakage Current in Float
Data Bus leakage Current in Input Mode
Darlington Drive Current
Symbol
loHD
v
Vee
0.4
v
v
1o·
v
rnA
10
10
·10
:!:10
i.tA ! v 1N = o to Vee
v 0 uT=2.4 to v cc
i.tA
vouT- o.4 v
i.tA
~v,N,;;;vcc
i.tA
2.4
I
Test Condition
loL = 2.0mA
loH = -250J..LA
·1.5
rnA
Max
Unit
Test Condition
10
5
10
pF
pF
pF
Unmeasured Pins
Returned to Ground
Vowl.SV
Port B Only
• 150mA for -4, -10, and -20 devices.
9.3 CAPACITANCE
Table 9.3-1
TA=25°C,f= 1 MHz
Symbol
e.p
eiN
eouT
Parameter
Clock Capacitance
Input Capacitance
Output Capacitance
•comment
Stresses above those listed under "Absolute Maximum Rating .. may cause permanent damage to the device. This is a
stress rating only and functional operat10:1 of the device at these or zny other condition above those indicated in the
operational sections of this ~P.Cificar1on is not implied. E'l:posure to absolute maximum rating conditions for extended
periods may affect devtCe reiHtiHiity.
HBA.C. CHARACTERISTICS MK3881-4, Z80A-PIO
"lble9.4-1B T A=OoC to 70°e, Vee= +5V :1; 5%, unless otherwise noted
SIGNAL
PARAMETER
SYMBOL
~
l
C/O SEL
CE ETC.
Ill
250
105
105
[1)
2000
2000
30
nsec
Any Hold Time for Specified Set-Up Time
0
nsec
Control Signal Set-Up Time to Rising Edge of <Pouring
Read or Write Cycle
145
nsec
cf>(CSl
tF (0)
Data Output Delay From Falling Edge of~
Data Set·UP Time to Rising Edge of <I> During Write or
MT Cycle
Data Output Delay from Failing edge of'iORa During iN'fA
Cycle
Delay to Floating Bus (Output Buffer Disable Time)
ts OEil
lEI Set-Up Time to Falling edge of !ORO during
toH ool
001
toM uol
lEO Delay Time from Rising Edge of lEI
tDI (0)
i5RQ
UNIT
th
Do·D7
lEO
MAX
Clock
Clock
Clock
Clock
toR( D)
1s cf>(Ol
lEI
MIN
'c
1w !<I>Hl
1w !<I>Ll
tr, 't
1S
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Times
116
iNi'A .Cycle
nsec
nsec
nsec
380
nsec
nsec
250
nsec
110
nsec
50
[2)
CL • 50pF
[31
nsec
140
160
130
190
nsec
nsec
nsec
1oL
lEO Delay Time from Falling Edge at lEI
lEO Delay from Falling Edge of M1 {Interrupt Occurring Just
Prior to Mll See Note A.
ts <I>URl
I ORO Set-Up Time to Rising Edge at •flouring Read or
Write Cycle
115
nsec
Ml Set-UP Time to Rising Edge of <I> During iiiiTA or Ml
90
nsec
RO Set-Up Time to Rising Edge ot.<I>During Read or Mi'
Cycle
115
nsec
Port Data Set-Up Time to Rising Edge of~ (MODE 1)
Parr Dar a Output Delay tram Falling Edge at STROBE
(Mode 21
Delay to Floating Port Data Bus tram Rising Edge of STROBE
(Mode 21
230
ts <l>rMO
COMMENTS
[51
[5) CL • SOpF
(51
Cycle. See Nate B.
F!D
ts <f>fRDl
ts IPO)
tos fi'Dl
Aa·A7,
80'87
tF (POl
me
rna
INT
Port Data Stable from Rising Edge of iO'R'O During WR
Cycle (Mode 0)
tw(STl
Pulse Width,
on
.J.RBY,
SROY
J.
tot (PO)
Sf'A6EiE
INT Delay Time from Rising Edge of STROBE
(51
180
nsec
CL • SOpF
1BO
nsec
(51
150
[4)
nsec
nsec
nsec
nsec
Ready Response Time from Rising Edge of !ORO
tc +
410
nsec
Ready Response Time from Rising Edge of S'i'i'i'OBE
tc+
360
nsec
TN'r Delay Time from Data Match During Mode 3 Operation
10H
(RY)
1oL
(nYl
2.5tc>fN-2ltQL(IQ)+ toM (10) + ts(IE!l +TTL Buffer Delay, if any
(<J>
nsec
nsec
440
650
to
to fiT3l
3. Mt must be active for a minimum of 2 clock periods to reset the PIO.
I) ~ 3 tw
210
H)+ tw (<f>Ll + tr +It
:1 Increase 'DR(O) by 10 nsec for each SOpF increase in loading up to 200pF max.
·;j Increase t 01 {D) by 10 nsec for each 5QpF increase in loading up to 200pF max.
'i For Mode 2: tw (STl> tsiPDI
'51 Increase these values by 2 nsec lor each t()pF increase in loading up to tOOpF max.
[51
CL • SOpF
(5)
-Sd[ID STATE ll-\fv1PS
~~
'i=q
HEWLETT!£§ PACKA.RD
117
HIGH EFFICIENCY RED· 5082-4650 Series
YELLOVJ • 5032-4550 Series
GREEN· 5082-4950 Series
COMPONENTS
TECHNICAL DATA
APRIL
Features
• HIGH INTENSITY
• CHOICE OF 3 BRIGHT COLORS
High Efficiency Red
Yellow
·~
tj
Green
• POPULAR T·H• DIAMETER PACKAGE
• LIGHT OUTPUT CATEGORIES
• WIDE VIEWING ANGLE AND NARROW
VIEWING ANGLE TYPES
, ) j'
• RELIABLE AND RUGGED
Description
.
The 5082-4650 and the 5082-4550 Series lamps are
Gallium Arsenide Phosphide on Gallium Phosphide
diodes emitting red and yellow light respectively. The
5082-4950 Series lamps are green light emitting Gallium
Phosphide diodes.
General purpose and selected brightness versions of both
the diffused and non-diffused lens type are available in
each family.
Package
Dimensions.
.
.
-~
1--+,-!~!:-ml
.· ..·· ·.•... ···r- ....
'
i
I
Application
4650
IndicatorGeneral Purpose
IndicatorHigh Ambient
Illuminator/Point
Source
Illuminator/High
Brightness
Indicator
General Purpose
IndicatorHigh Ambient
4657
4658
!'
....
4550
0.89 UXl5l
0.64 [Qi5)
4555
~
4557
...
0.36(.014)
4558
4950
0.411.018)
..... .1§~6)
,..-..:;~
_j__
~I
~ j ~ U'tCl
1/,
4955
·!
$.59\.Z-'.IJ}
-"~
CATHODE
__j .__
· " ' - - " - - - - 1040'1
~N ~-HE-L£~:_--·---~-· - - - '
\.
Lens
Diffused
Wide Angle
,N
Color
I
I
High
ff
Efficiency
on 0 1 used Red
Narrow Angle
I
Diffused
I
Wide Angle
I
II
Illuminator/Point Non-Diffused I Yellow
Source
Illuminator/High Narrow Angle
Brightness
IndicatorDiffused
General Purpose
IndicatorHigh Ambient
'Wide Angle
f
I
I
4957
liluminatoriPoint Non-Diffused 1Green
Source
.
,
4958
Illuminator; High
Brightness
2.!14(.101
NOTES:
1
JNOM.
f.
"LL OIMEHSIONS.ARt IN t.tiLli.,.ET!llfS ONCHESJ.
2. SllVfl't..PlA.HC LfA:J~. ':!:.f. .\9Pllr."ATIC!'f BULLETIN J.
J. A~ ~PO)(V MINJS(;US MAY r.x.T!r•O Ae.Ql:T I~
.....
•.;;,p,~~:.}·:·
... ,,'·
'\\,,I
5082-
~~
J
l_;, ., , ., ,
:
Part
I
PLASTIC
.~.·
Number
4655
~--·.
l'
r. . P
;. . i l .
• GENERAL PURPOSE LEADS
• IC COMPATIBLE/LOW CURRENT
REQUIREMENTS
;·
r
!Narrow Angle
I
1
I
118
Electrical Characteristics at TA =25°C
Symbol
lv
2e~
'-PeAK
Description
luminous Intensity
.
Included Angle
Between Half
luminous Intensity
Points
Peak Wavelength
J\d
Dominant Wavelength
rs
Speed of Response
c
Capacitance
6Jc
Thermal Resistance
VF
Forward Voltage
BVR
Reverse Breakdown Volt.
Luminous Efficacy
71v
Device
50824650
4655
4657
4658
4550
4555
4557
4558
4950
4955
4957
4958
4650
4655
4657
4658
4550
4555
4557
4558
4950
4955
4957
4958
4650s
4550s
4950s
4650s
4550s
4950s
4650s
4550s
4950s
4650s
4550s
4950s
4650s
4550s
4950s
4650s
4550s
4950s
All
4650s
4550s
4950s
Typ.
2.0
4.0
12.0
24.0
Min.
1.0
3.0
9.0
15.0
1.0
2.2
6.0
12.0
1.0
2.2
6.0
12.0
Max.
I
_t
Units
I
mcd.
Test Conditons
IF= lOrnA
(Fig. 3)
1.8
3.0
9.0
16.0
1.8
3.0
9.0
16.0
90 I
90
35
35
90
-I
I
I
mcd.
IF= lOrnA
(Fig. 8)
mcd.
IF= 20rnA
(Fig. 13)
Deg.
IF= 10rnA
See Note 1 (Fig. 6)
Deg.
IF= lOrnA
See Note 1 (Fig. 11)
Deg.
IF= 20mA
See Note 1 (Fig. 16) J
Measurement at Peak I
(Fig. 1)
I
Sea Note 2 (Fig.l)_
I
I
l
I
90
II
35
35
90
90
30
30
635
583
565
626
585
572
90
90
200
16
18
18
t35
I
135
145
2.2
22
2.4
I
nm
I
nm
l
ns
I
I
pF
I
I
'
147
570
665
l
l
I
3.0
3.0
3.0
v
lumens/watt
VF = 0, f = 1 Mr-lz
Junction to Cathode II
lead at Seating P:ana j
OCN:
v
5.0
I
I
I
IF= lOrnA (Fig. 2,
IF= lOrnA Fig. 7,
IF= 20rnA F;g, 12)
IR"' lOO;IA
See Note 3
NOTES:
1. e}S is 1he off-axis angle at which 1he luminous inrens1ty is half the axial luminous intensity.
2. The dominant wavelength, .\d, is derived I rom the CIE chromatiCity diaf]ram and represents the single wavelength whtch defines the color of the dev•ct:.
3. Radiant intensity, Ie. in watts/steradian, may be found from the equation 'a"" lvl17v. where lv is th& luminous intensity in candelas and TJv•s the luminous
etficac::y in lumens/wan.
Yellow 5082-4550 series
20
1'•
1
~25"C
T •
4
l 'l
0
•
-·
2.5
I
0
.5
1.0
V,
~II_
/i
1.5
2.0
1.5
10
FORWAnD VOLT AG£
V
I
10
15
20
'"A
FigUTe 8. Relative Luminous Intensity
vt. Forward Current.
l•f.U,
PfAK CliRR[l'\11
Figure 9. Ragtive Efficiency
{Luminous Intensity per Unit
Current) vs. Peak Currant.
;~
ow
~
.
9
---
::!
~
.!C
li
~
~
e
""~
:!;
/
/
v
- FORWARD CURR[NT
Figure 7. Forward Currant vs.
Forward Voltage.
i;
00
0
I
Il
/1
25
.,i.e
~:
ia
xo
_u
~
e
~I·
""
.,~
.iJ
,,. - I'ULS£ DURATION -111
Figure11. Relative Luminous Intensity vs. Anqular Displacement.
Figur• 10. Maximum Tolerable Peak Cur·
r•nt vs. Pulse Duration. tiDc MAX
as per MAX Ratings)
Green 5082-4950 series
20
1
I
~0:
.
T•
~ .... C I
I L
rfl
0:
"
~
u
.
~
10
~
e
-·
I
~c
~0
~!
~i
1.5
2-
1.0
~i
j-
.
~~
;
•o
1.0
.5
v, -
15
,. ...
J.O
'OAWAIID VOLT AGE - V
Figure 12. Forward Currant vs.
Forward Voltage.
1, -FORWARD CURRENT-
~ttA
Figure 13. Relative Luminous lnten•ity
vs. Forward Current.
~ .. - 'EAJC CURRENT -
onA
Figure 14. Relative Efficiency
(Luminous Intensity per Unit
Current) vs. Peak Current.
lp - PULSE DURATION -..,.
Figure 15. Maximum Tol .. ablo Peak Cur·
rent vs. Pulse Duration. lloc MAX
as per MAX Ratinqs)
Figure 16. Relative Luminous intensity vs. Angular Displacement.
Absolute Maximum Ratings
Parameter
Power Dissipation
High Efficiency Red
4550 Series
Yellow
4550 Series
120
120
201 1 1
Average Forward Current
60
(Fig. 5)
Peak Operating Forward Current
Green
4950 Series
Units
mW
20(1)
120
30(2)
60
(Fig. 10)
60
(Fig. 15)
rnA
-
rnA
-55°C to +100°C
Operating and Storage Temperature Range
Lead Solder Temperature (1 .6mm(O.C63
inch] below package base)
260" C for 5 seconds
so• C at 0.2mAJ• C
so•c at 0.4mAJ•c
1. Derate from
2. Derate from
1.0
....
..,.
~
HIOH EFFICIENCY
z
RED
!
0.5
;::
~
"'
0
5oO
650
WAVELENGTH
4
750
nm
Figure 1. Relative Intensity vs. Wavelength.
High Efficiency Red S082-4650 series
•
l
5
g ,.
j
~
x'
~
J
12
~
0
~
~
~
~
-·
1. 1
10
• I
1
0
o
.5
•
1.0
VF'- FCRVIIIAROVOLT.t.Gl- V
Figure 2. Forward Current vs.
Forward Volt111e
Figure 5. lll!aximum Tolerable Peak Cur·
rent vs. Pulse Duration. Uoc MAX
as per MAX Ratings.)
1, -FORWARD CU"RENT- mA
Figure 3. Relative Luminous lntensi!y
vs.. Forward Currant.
~
':_..1
/!
v
I
...,' 1J
J
l
I 1
I
l
l.-~-1I
: I
i
l
i
I
I
J
I
I
i
I
I
'
1020J0"050&J
"-:Ate -PEA-.; CURRENT - ftiA
Figure 4. Relative EHiciancy
(Lum•nous Intensity par Unit
Currand vs. Peak Cu<rent.
FifjJur• 6. Relative Luminous Intensity vs. Angular Displacement.
SERIES 712 T0-5 RELAY (TELEDYNE)
GENERAL ELECTRICAL SPECIFICATIONS (@ 25°C)
~-o_ntac~~~rangement
W"·~
ontact Resistance
ontact Load Ratings (DC)
~ ~'"'"'''
.,
lAC)
act Lifo Ratings
L------····--~-c~~-t-~1-~v~~~~a~ ~atlng
Contact
Carry Rating
---.
______ _,_. --· ... ·-· .. ---Coil Operating Power
--. -· ------. . -----
Operata Timo
·--·-·--·· ...... _._
Time
- Rclea~e
·- ,_ .. __
······lnlcrcontact C~;Jacltance
-· - -··· ....... - ·--Insulation Resistance
-----· -· ·----·
Dielectric Strength
~·
t
··-
- ....
······-
----2 Form C (DPDT)
Continuous
0.1 ohm max. before me; 0.2 ohm max. after life at 1AI28VDC, (measured 1/8" from header)
Resistive: 1 Amp/28VDC
lnductive:200 mA/28VDC (320 mH)
Lamp:
100 mA/28VDC
_(See Fig~!.~~':!_c~~:esis!ive vol!~9..~~~rre~!- ~!i.~~~Resistive: 600 mA/115VAC, 400Hz (Case ungrounded); 400 mA/115VAC, 60Hz (Case ungrounded).
__200 ~-~.f.!_1~Y._~_c~-~~ ~nd_~oo H~~ (Ca_s_ll_~ro~~ed)
10,000,000 operations (typical) at low level
1,000,000 operations min. at 0. 5A/28VDC resistive
100,000 operations min. at all other loads specified above
--·--·······-- ------ ----------------···-·····--·---·-· ···------·--···------------- ---- --· ... --·-· -· -- -··. ---·. --------------------5-~~~~_LC_~n_t~~~?~s.• ~n_s~itchc~_)_. ______ -----·--··-·
2 Amps/28VDC (100 operations min.)
450 milliwatts nominal at nominal rated voltage
-- ---·-·· --.- .. -- ..... ··-- ----····- ·-··-------·----4.0 msec. max. at nominal rated coil vollage
712 Series: 3.0 msec. max.
7120, 712T Series: 6.0 msec max.
·--·-··-------·---------·-····----·- -······--··-----------0.4 pl. typical
-----·-----·-···----------·-----·--- ----------1,000 megohms min. between mutually Isolated terminals
-····- -- .... --·-·-·· .. ___ . _ ----·-- - ·- -- ·- .. ·---·--· -----·
Sea level: 350 VRMS/60 Hz.
--·-···--··-··· -·- ··----·r··-·· --·-------· ·---··
------------- ··-·----····-·------ ·-··--·--- ···-----·---·-·------
1-'
N
1-'
SERIES 712 T0-5 RELAY (TELEDYNE)
DETAILED ELECTRICAL SPECIFICATIONS (@ 25°C)
,,------------ -----·
GENERIC
ll)
PART
'·
NUMBERS
I
Coil Voltage (VDC)
I
'-------------
---
Nom.
Max.
Coil Resistance (Ohms ±10%@ 25°C)(Note 3)
----·-·--···
Pick-up Voltaqc (VDC)
'---·-· ····---·. ----·
Diode P.I.V. (VOC, Min.)
7120, 712TN
r-'-----.-.
-----·-- -·Negative Coil Transient (VDC. Max.)
I
'
712-5
7120-5
712TN·5
5.0
5.8
50
3.6
712-~-7-12--9
120712TN
-
6.o
a~o
98
4.2
-
7120-9
712TN·9
-~
I- <1: <1:
~~~
-
-- ···-
-·- --- ··-- ---· ··-·
.
Collector-base Voltage (BV cso)
,_ i3
(@25°C&Ic = 100,.,a)(VDC, Min.)
---···· .. __.L.____ -- ··--·--· -------------·-·---
712·18 ! 712-26
7120-18
7120·26
712TN-13 I 712TN·26 '
I
l 712TN-12
:::J
,_,-·
12.0
18.0
26.5
12.0
16.o
24.0
32.w
220
6.5
390
8.4
880
13.0
~~
~
__________________________.
60
-
I
2.0
~12~. 7.!_2T~--
\ Base Voltage to Turn Oil (VOC, Max.)
"' ~
- r--·.... --· --·------ -------·!!:! ~ t;:; l Base Current to Turn On (mAOC, Min.)
~!; ffi ~-J"oto'~'"'!'''"·em/lte'E'"'"' /0 SOmA m"-1
::z: ~ t;
Emitter-base Voltage (BVEso) (@25°C) (VOC, Max.)
I 712-12
I 7120·12
3.00 ] ___
---·
~~~ ~]~ .36
I
l
0.3
1
6.0
60
1.03
1
0.68
1
0.50
J
·j
--
1-'
N
N
SERIES 712 T0-5 RELAY (TELEDYNE)
PERFORMANCE CURV.ES
--r4l
Rf PERFORMANCE
!>(I
:'
I
I'
I
I
'
r_ - - - - - - - : - - ·
~--
:
-~ ~'
s.~~~
~ .a
~>
"'-
i
I,
I
i
I,
'1
!
I
····- r·
I
l - --
100
fREQUENCY (MHZ)
FICUHE 1
·-·--·
·,.
!
--------·---·
200
g
ISO
;
1
g""
Cl
dr
2SO
...
1
~
:+t=:=t+-1
100
I
500
I
sot_
100
fREQUENCY (MHZ)
soo
0
.
II
0· I
FIGURE 2
------------------------
I
i
1-,+tl-H--~
c
. _j
l
30
g
··---~--,... ~------,.---,
. .
,
0~
300
I
f---------c--
;!«(
--1 l
DC CONTACT RATINGS (RESISTIVE)
\
-
j
.l1-_---T _LJ _ _i ____t.s_
o.sC)
- 0 3-----'--0.4
0.2 LOAO CURRENT lAMPS 0
os
o.7
I
og
.
FIGURE 3
--------------
1-'
N
VJ
SERIES 712 T0-5 RELAY (TELEDYNE)
OUTLINE DIMENSIONS
TERMINAL LOCATIONS ANO PIN NUMBERING (REF. ONLY)
•
SCHEMATIC DIAGRAMS
(VIewed from Ttrmln1t1)
CASE DETAIL
.370
(9.40)
OIA. MAX .
c+
.335
(8.51)
"~! .27~
~~TI
L
(6.99) MAX.
~ u~ _j_
'
.017 I .43) ~
.200 (5.08)
:t:.010(.25)DIA.
o.7Sf19.051MIN
GROUND PIN (OPTIONAl)
002 .05)
:ootl.03) OIA.
DIMENSIONS ARE SHOWN IN INCHES (MilLIMETERS)
~.. ~.
SCHEMATICS ARE VIEWED FROM TERMINAlS
1-'
N
+:-