CALIFORNIA STATE UNIVERSITY - NORTHRIDGE
AN EXPERIMENTAL SYSTEM
BASED ON Z8000 MICROPROCESSOR
p~oject submitted in pa~tial
~equi~ements fo~ the deg~ee of
A
Enginee~ing
by
Minh Q. Nguyen
May,
1983
satisfaction of the
Maste~ of Science in
The project of Minh Q. Nguyen is approved:
(Chairman)
Dr.
Dr.
uh
sun
Prof. William L. MacDonald
ii
ACKNOWLEDGEMENTS
I would like to take this
Y. Wong
P~ofesso~
Robe~t
tions and
t~emendous
in this study.
b~othe~s
and
siste~s
ene~gy
Yuh Sun's and
~eviews
since~ely
fo~
a~e
g~ateful
thei~
to my
Thomas
iii
William
pa~ents,
love, patience and
ciate
fo~
fo~th
also deeply
Finally, I would like to thank my
McCl~llan
sugges-
he put
P~ofesso~
suppo~t.
M~.
to thank
encou~agements,
amount of time,
P~ofesso~
I am
the
fo~
L. MacDonald's comments and
app~eciated.
oppo~tunity
wo~k
his assistance.
my
mo~al
asso-
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Section 1: INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . .
1
Section 2: HARDWARE DESCRIPTIONS . . . . . . . . . . . . . . .
3
I.
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . .
3
II. PRE-PROCESSOR DESCRIPTION . . . . . . . . . . . . .
4
III. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . .
6
A.
CONTROL SIGNAL CHARACTERISTICS....
6
B.
STACK POINTER.....................
10
C.
PROCESSOR STATUS..................
10
D.
DATA TYPES........................
11
E.
INTERRUPT AND TRAP STRUCTURE......
11
F.
ADDRESS MODES. . . . . . . . . . . . . . . . . . . . .
13
IV. THEORY OF OPERATION...................
17
A.
INITIALIZATION....................
17
B.
COMPUTER MEMORY CYCLE CONTROLS....
17
C.
MEMORY INTERFACE..................
19
D.
INPUT/OUTPUT INTERFACE............
19
E.
CPU STATUS CODES..................
19
F.
INTERRUPT SEQUENCE................
23
iv
Section 3: SOFTWARE DESCRIPTIONS...............
I.
II.
27
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . .
27
Z8000 INSTRUCTION SET................
27
A.
DATA OPERATIONS AND TESTING.......
28
B.
DATA TRANSFERS....................
29
C.
POINTER SETTING...................
30
D.
TRANSFER OF CONTROL...............
30
E.
INPUT/OUTPUT. . . . . . . . . . . . . . . . . . . . . .
31
F.
CPU CONTROL. . . . . . . . . . . . . . . . . . . . . . .
31
G.
BLOCK OPERATIONS..................
31
H.
MULTI-MICRO SYNCHRONIZATION.......
32
COMPUTER PROGRAM AND FLOWCHART......
33
Section 4: SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
REFERENCES.....................................
39
APPENDIX A: Z80 0 0 INSTRUCTION SET.. . . . . . . . . . . . .
40
APPENDIX B: PROGRAM LISTING. . . . . . . . . . . . . . . . . . . .
45
III.
v
LIST OF TABLES
Page
Table I.
CPU STATUS CODES . . . . . . . . . . . . . .
vi
24
LIST OF FIGURES
Page
Figu:re 1.
PRE-PROCESSOR FUNCTIONAL BLOCK
DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Figu:re 1a.
Z8002 CPU . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Figu:re 2.
Z8002 REGISTERS....................
9
Figu:re 3.
Z8002 PROCESSOR STATUS.............
12
Figu:re 4.
ADDRESSING MODES...................
15
5.
RESET CYCLE.........................
16
Figu:re 6.
PRE-PROCESSOR MEMORY MAP...........
20
7.
ROM READ- RAM BYTE WRITE CYCLE....
21
Figu:re 8.
I/0 READ - I/0 WRITE CYCLE.........
22
Figu:re 9.
INTERRUPT ACKNOWLEDGE SEQUENCE.....
25
Figu:re 10.
DIAGNOSTIC PROGRAM FLOWCHART.......
35
Figu:re
Figu:re
vii
ABSTRACT
AN EXPERIMENTAL SYSTEM
BASED ON Z8000 MICROPROCESSOR
by
Minh 2. Nguyen
Master of Science in Engineering
With the advances in Very Large Scale Integration
technologies, the developing trend leans toward the use
of faster, more powerful microprocessors and microcomputers in the design of engineering systems.·
Many of the
lastest microprocessors use 16-bit data words to increase
the operational capabilities and to reduce the number
operations needed to complete
an arithmetic task.
In
this project, an experimental system based on Z8000
microprocessor was designed as a pre-processor module.
First,
hardware descriptions are presented based
on a spe?ial application to collect and process gyro and
accelerometer data.
Second,
viii
software descriptions are
given to
desc~ibe
compute~
p~og~am
P~og~am
the Z8000
w~itten
inst~uction
to test the RAM,
Access Input/Output and CPU
ly, comments
the Z8000
a~e
made on
othe~
set and the
Inte~~upt
inst~uctions.
Final-
possible applications
£o~
In the appendix, the complete
mic~op~ocesso~s.
inst~uction
set and the
p~og~am
ix
listing
a~e
given.
Section 1
INTRODUCTION
Building faster, more powerful microprocessors and
microcomputers have always been an important goal of
semiconductor manufacturers.
With the newly developed
lithographic techniques , many IC manufacturers have
converted the existing NMOS design to CMOS design and
thereby achieved higher operating speed and lower power
consumption.
Moreover, with the advent of micropro-
grammable architecture and more powerful instruction
sets, a more flexible design can be achieved by the
additions or deletions of chips in the system.
Another
trend is to combine the functions of several chips into
a single chip to form a one-chip computer.
Many of the lastest microprocessor chips use 16-bit
data words.
processor.
One of these is the 16-bit Z8000 microIt comes in either a 40-pin package with the
addressing capability of 64K bytes or a 48-pin package
'
with the addressing capability of 8 Megabytes.
of memory is provided by a Z8002 chip.
The 64K
Similarly, an
8M of memory can be provided by a Z8001 chip.
Programs
written for the Z8002 chip can be run on the Z8001 chip
in one of its segments.
This report describes the design
of a Z8000-based microcomputer using the Z8002 memory
capability.
1
2
II·DIUCTIOIW.
IUS DIIY£ll
FROM 6 YRO ELECTRONICS
A
D
D
•
'
51!1 11
u•
E
I
I
v
. . . 111
QY£ 10M
'
TO QUAIITIZEI!COIIY£RTER
IIODULl
TO COIII'I.''l'El' .. OilULf
FIGURE 1: PRE-PROCESSOR FUNCTIONAL BLOCK DIAGRM-1
Section 2
HARDWARE DESCRIPTION
I.
INTRODUCTION
The Z8000 microcomputer's architecture is more
similar to that o£ the PDP-11/34 and other popular minicomputers than it is to that o£ earlier microcomputers
like the Z80.
The Z8000 is a 16-bit microprocessor.
Its
data paths, instructions, registers, arithmetic and
logical operations are all designed £or 16-bit words.
Length o£ instructions can be 32 bits (long-word),
15
bits (word), 8 bits (byte) and 4 bits (digit); and each
byte in its memory is separately"addressable.
The experimental system was designed using the Z8002
microprocessor as the Pre-Processor Module to collect
and process gyro and accelerometer parameters.
However,
computational tasks o£ the overall system are handled by
a computer module which consists o£ I/0 Processor, and
Nav Processor.
The I/0 Processor receives incremental
angular and velocity data £rom the Preprocessor.
The Hav
Processor performs the alignment, navigation, and baroinertial computations.
It also formats the data to be
provided as outputs.
3
4
II.
PRE-PROCESSOR DESCRIPTION
A
chip.
Module was designed using a Z8002
P~e-P~ocesso~
This chip
with its associated
togethe~
a self contained sixteen bit
fo~ms
sixty-nine
integ~ated
module which
p~og~am
p~ovide
memo~y~
input/output.
Module
a~e
~andom
access
As
The
linked
the
cont~ol,
of
wo~ds
togethe~
contained on the
4096
buffe~ing,
access
~andom
of
wo~ds
and
memo~y
Module and
data
fo~
A total of
compute~.
a~e
P~e-P~ocesso~
Compute~
t~ansfe~
via the
memo~y.
in
illust~ated
tional block
th~ough
512
ci~cuits
memo~y
diag~am
1, the
Figu~e
is
o~ganized
p~ep~ocesso~
and the
P~e-P~ocesso~
data
fo~
Di~ect
func-
t~ansfe~
Memo~y
Access bus
buffe~s.
The
p~ep~ocesso~
the following functions:
pe~fo~ms
Read
1. Compute angle changes at 2048Hz.
pulses accumulated in
to obtain total
compute angle of
2.
P~ocess
gy~o
~egiste~s
angle changes.
Compute
pulse
filte~.
X,Y,Z
This
Hz the
~aw
filte~
with 64 Hz bandwidth.
compute
Read and
angle changes at 1024 Hz to obtain total
and change in total angle.
Gy~o
ite~at~on
changes in angle.
Dete~mine
gy~o.
angle changes at 64 Hz.
3.
since last
gy~o
ine~tial
gy~o
co~~ection
Update total angle.
~outine
filte~s
outputs using a
body pitch,
angle
fi~st
at 1024
o~de~
The smoothed pulses
~oll,
and yaw
~ates.
5
4. Read
accele~omete~
and switch to
inputs,
~eset
channel, if
calib~ation
5. Send total angle change to I/O
6. Send velocity change to I/0
In
b~ief,
the
P~ep~ocesso~
angle and velocity data
mete~s.
The
P~ep~ocesso~
pulses to obtain the
placement.
mete~
a
pulses
And
pulse to that
a~e
p~ocessing
t~ue
the
gy~os
ine~tial
space
quantize~.
fo~
the
inc~emental
and the
the
accumulated by the
by the I/0
P~ocesso~.
co~~ects
th~eshold,
accele~o-
of
gy~o
angula~
dis-
numbe~
a given
accele~o-
P~ep~ocesso~
The
numbe~
P~ep~ocesso~
P~ocesso~.
necessa~y.
P~ocesso~.
p~ocesses
accumulated data
exceed a given
~eset
f~om
accele~omete~,
of
fo~
sends
~eset
fu~the~
6
III.
FUNCTIONAL DESCRIPTION OF Z8000
A.
CONTROL SIGNAL DESCRIPTIONS
The~e
eight types of
a~e
Cont~ol
can be
o~
Mic~op~ocessing
f~om
o~iginated
accept the following
eithe~
cont~ol
all CPU
signals used.
an
f~om
Unit CMPU)
1. SMHz Clock- a TTL
cont~ols
cont~ol
exte~nal
system
The module will
signals:
wave signal which
squa~e
ope~ations.
2. Reset* - a TTL LOW input having a pulse width
g~eate~
than 2
mic~oseconds
will cause the CPU to
initialize.
3.
Real Time
P~e-p~ocesso~
Inte~~upt*
input will cause the CPU to
defined location.
cont~olle~
4.
the
p~ovides
exte~nal
cont~olle~
p~e-p~ocesso~
The
clock
exte~nal
pe~iods
Request
befo~e
time
p~e-
system timing
p~og~ammable
~eal
to a
inte~~upts
and clocks.
Bus Request* - a TTL LOW input used
P~e-p~ocesso~
by an
A
t~ansfe~
- a TTL LOW
memo~y
ha~dwa~e
afte~
which
~equi~es
access to
and input/output bus.
must wait at least two CPU
~eleasing
the
P~e-p~ocesso~
Bus
pulling it down again.
5. I/0 Request* - a TTL LOW input issued in conjunction with
eithe~
P~e-p~ocesso~
p~e-p~occesso~
Bus Request* to select
Random Access
Memo~y
CRAM)
input/output depending on the logic level of
o~
add~ess
7
REAJ/'IImE
ft/0 R.MAL/J"YJTEM
BYTE/WOii'i>
S},4TVS
A!JJ)P. EssI
:PATA
cpv
CONr~oL
Z1oo.t
81.1S
CPU
C.ON/Il.o~
:CIITEUWPrS {
~u":rr
,
M.raoS
(.PIV'rltOL
l
+5" V 611})
CLJ{
FIGURE 1a: Z8002 CPU
avs
8
bit I/0 A10.
I/O Request* enables the RAM when I/O A10 is LOW.
Input/Ouput is selected when I/O A10 is HIGH.
6. I/O Data Stiobe* - a TTL LOW input used in Piepiocessoi Bus Request* and I/0 Request* to time data
to/fiom the pie-piocessoi RAM
OI
input/output.
7. I/O Read/Wiite* - this input indicates the diiection of data flow to/fiom the pie-piocessoi memoiy
OI
I/0.
Data is tiansfeiied fiom the memoiy when
I/O R/W* is HIGH and to the memory when is LOW.
8. I/O Byte/Woid* - this input indicates the type of
data transferred to/from the Pre-processoi RAM
HIGH indicates a byte (8-bits) and LOW indicates
a woid (16-bits) tiansfei.
The Z8002 computei chip utilized on the module is a
multiple source sixteen-bit processor contained a fortypin dual-inline package.
The Z8002 chip is installed
into a socket on the module to simplify maintenance.
The
CPU is organized around sixteen 16-bit geneial purpose
registers RO through R15 as shown in Figure 2.
For byte
operation~
the first eight registers (R0-
R7) can also be addressed as sixteen 8-bit registers
designated as RLO, RHO and so on to RL7 and RH7.
The
registers can also be grouped in pairs RRO, RR2 and so
on to RR14 to form eight long word (32-bit registers).
the registers can be grouped in quadruples RQO, RQ4,
9
.,, -.... + ..
-{
'"'
--
-{
-{ ..
-{ -{ •
-{ Me{
-·...
-1 -·
-I
Ia
1111
Ill
"'
lila
Iliff
liLt
IIU
IIU
...
IlLS
IlLS
IILl
•
-
1111
1112
lt13
IYSTEII STACK _ , . . .
liiORIIIAL STACII{ J10W1P
s....n•sr.t.e:«-..
""
-.nACo<-
-
oonn
FIGURE 2: Z8000 REGISTERS
10
RQ8 and RQ12 to form four 64-bit registers.
B.
STACK POINTER
The Z8002 architecture allows stacks to be stored
in the memory.
Any general purpose register except RO
can be used as a stack pointer for manipulating instructions such as PUSH and POP.
However, certain instruc-
tions (CALL and RETURN) make implicit use of the register
R15 as the stack pointer.
There are two implicit stacks,
normal stack using R15 as the stack pointer and using
R15' as the system stack pointer (see Figure 2).
If
CPU is operating in the Normal Mode, R15 is active; and
if the CPU is in System Mode, R15' will be used.
The
implied stack pointer is a part of the general registers
and hence can be manipulated using the instructions
available for register operations.
C.
PROCESSOR STATUS
The CPU status consists of the 16-bit Program Counter
(PC) and the 16-bit Flag and Control Word (FCW) register
(see Figure 3).
The following is a brief description of
FCW bits.
S/N:
System/Normal -
1 indicates System Mode and 0
indicates Normal Mode.
VIE:
Vectored Interrupt Enable -
1 indicates that
Vectored Interrupt requests will be honored.
NVIE:
Non-Vectored Interrupt Enable -
1 indicates that
non-vectored interrupt requests will be honored.
11
c:
Caxxy -
1 indicates that a caxxy has occuxed fxom
the most significant bit position when pexforming
arithmetic opexations.
z:
Zexo -
indicates that the xesult is zexo.
s:
Sign
indicates that the result is negative;
i.e .• most significant bit is one.
Paxity/Ovexflow ·- 1 indicates that thexe was an
ovexflow duxing axithmetic operation.
For
logical opexations this bit indicates paxity of
the xesult.
DA:
Decimal Adjust - xecoxd byte arithmetics.
H:
Half Carxy -
1 indicates that there was a carry
fxom the most significant bit of the lowex digit
during byte axithmetics.
D.
DATA TYPES
The Z8002 instxuctions opexate on bits. digits ,
bytes, words C16 bits), long woxd (32 bits), byte stxings
and woxd stxings type opexands.
ox tested.
opexations.
integexs.
Bits can be set, reset
Digits axe used to facilitate BCD axithmetic
Bytes axe used fox chaxactexs and small
Woxds axe used fox integer values and address.
Long words are used for laxge integer values. All
operands except strings can reside either in memory or
general registers.
E.
Strings can reside in memory only.
INTERRUPT AND TRAP STRUCTURE
Interrupt is defined as an extexnal asynchronous
13
event.
For example,
inte~ruption
pheral needing service.
is
~aused
by a peri-
Traps are synchronous events
resulting form execution of certain instructions under
some defined circumstances.
Both interrupts and traps
are handled in a similar manner by the Z8002.
The Z8002 supports three types of interrupts in
order of
descending priority - non-maskable, vectored
and non-vectored.
The vectored and non-vectored inter-
rupts can be disabled by control bits in the FCW.
The
Z8002 has three traps; system call, unimplemented opcode
and privileged instruction.
The traps have higher
priority than interrupts.
When an interrupt or trap occurs, the current
program status is automatically pushed on to the system
stack.
Program status consists of processor status
(i.e., PC and FCW) plus a 16-bit identifier.
Identifier
contains reason, source and other coded information
relating to interrupt or trap.
After saving the current program status, the new
processor status is automatically loaded from the new
program status area located in the memory.
This area is
designated by the NPSAP register.
F.
ADDRESSING MODES
Information contained in the Z8002 instructions
consists of the operation to be performed, the operand
and the location of the operands.
Operand locations
14
are designated by general, memory or I/O addresses.
The addressing mode of a given instruction defines the
address space and the method to compute the operand
address.
Addressing modes are explicitly specified or
implied in an instruction.
Figure 4 illustrates the
eight explicit addressing modes: Register (R), Immediate
CIM), Indirect Register CIR), Direct Address (DA),
Indexed (X), Relative Address CRA), Base Address (BA) and
Base Indexed (BX).
15
~ c:cntenl oltlle lOcation " ' . , . . il in tile t'8Qi51er.
~ COIMnl of tile lOcation - aha iltlle mn. in 1lle
lreuc:lion. aiiUI by 1lle c:ontenl
olllle . . . . lwgiMBr.
~-*"' ol tile lOcation " ' -
tile
tile., ........
lllldr-. is 1lle ~ of
- - · ofiMI by
. . inllluclian.
...
T i l e - of . . lOcation ,.,_
AIIISr-.
...
...
...... ...........
................. ..
~
.
......,. Clllet by . .
p'
- · 11'1 tile r.uclian.
a
"'- . . . . . al . . . . . . . ,.,_
-··= ,..
......,. at.~ by . .
in . . rwviiW·
FIGURE 4: ADDRESSINu- MODES
17
IV. THEORY OF OPERATION
A.
As
INITIALIZATION
in
illust~ated
Figu~e
the high to low level change of the RST* signal to
afte~
CPU, the following will
The ADO-AD15 bus will be in the high impedance.
2.
AS*, DS*, MRE2* and BUSAK* outpus will be HIGH.
3.
ST0-ST3 outputs will be LOW.
the RST* input
a~e
~etu~ns
HIGH and
locations 0002H and 0004H into
f~om
executed to initialize the CPU
Registe~s.
cycle
sta~ts
B.
Then a
memo~y
execution of the
~ead
memo~y
Status
(inst~uction
fetch)
prog~am.
COMPUTER MEMORY CYCLE CONTROLS
The following
se~ved
thi~d
memo~y
p~og~am
P~og~am
HIGH
~emains
clock cycles, two consecutive 16 bit
th~ee
~ead
occu~:
1.
Afte~
fo~
5, within five clock cycles
desc~iption
by the CPU pins employed
identifies the functions
fo~
all
compute~
memo~y
cycles.
1. AD0-AD15
Add~ess/Data
{I/0, active HIGH, 3-state).
multiplexed address and data lines
add~ess
memo~y
o~
a~e
input/output and to
used to
t~ansfe~
The AS* output and DS* output will indicate
the bus is used
fo~
These
data.
whethe~
address or data.
2. AS*
Add~ess
Strobe (output, active low,
3-state).
A
18
_LOW on this output indicates that the A/D lines
contain
add~ess
when AS*
The
in£o~mation.
t~ansitions
£~om
is stable
add~ess
a low to a high level.
3. DS*
Data
(output, active low, 3-state). A LOW
st~obe
output indicates that the A/D lines
data.
t~ans£e~
The R/W* output indicates the di-
o£ data
~ection
a low to high
being to
a~e
t~ans£e~.
t~ansition
Du~ing
a
~ead
ope~ation,
on the DS* output indicates
the CPU has accepted the data.
Du~ing
a
one,
w~ite
LOW on the DS* output indicates that data is on the
A/D lines.
Data will be
low to high
t~ansition
~ernoved
sho~tly
the
a£te~
of the DS* output.
4. READ/WRITE*
Read/W~ite
the
di~ection
indicates a
(output, 3-state).
Output shows
of data flow on the A/D lines.
~ead
LOW indicates a
ope~ation,
w~ite
HIGH
i.e., data into CPU and
ope~ation,
i.e.,data
CPU.
f~om
5. MREQ*
Merno~y
Request (output, active LOW, 3-state).
LOW on this output indicates that CPU
memo~y
o~
~equests
A
the
input/output taking place.
6. WAIT*
Wait (input, active LOW).
states into the CPU's
the cycle time up to
memo~y
fou~
An input
inse~ts
t~ansaction
(4) clock
wait
allowing
pe~iods.
This
19
allows slower memory or I/O devices sufficient time
to respond.
C.
MEMORY INTERFACE
Figure 6 illustrates the memory structure for the
pre-processor.
The computer with sixteen address bits
could access up to 32,768 sixteen bit memory location.
However, the module is mechanized with memory mapped I/0
and shared resources with the Computer Module.
The RAM
and I/0 are shared with, and are accesable by, the
Computer Module via the I/0 bus interface.
Although
the Computer Module can read/write to the pre-processor
RAM and I/0, the
pre~processor
cannot access the
Computer Module.
Figure 7 illustrates the timing of a ROM read cycle
followed by a RAM
byte write.
The memory controls and
associated circuitry are identical to the previous
memory controls and initialization sequence section.
D.
INPUT/OUTPUT INTERFACE
Detailed timing of an I/0 read cycle followed by an
I/O write cycle is illustrated in Figure 8.
The memory
controls and associated circuitry are identical to that
previous memory controls and initialization sequence
section.
E.
CPU STATUS CODES
These four (4) CPU outputs, STO-ST3, contain inforrnation regarding the current CPU transaction.
As illus-
20
I./C FC-00-FFFE:..
!:>12. X. \CQ
RA.M
F~-F~FE.
S,l C. X
lG:.
NOT
US.E.[:)
/
c(XX")-F7FE.
ROM
c:x:c-\ FFC..
FIGURE 6: PRE-PROCESSOH MEMORY MAP
""
CLOCK
-l'
n
I
~
-
I
(x'f \
Wiii 1 ()(
n-----
~--··
-Dito.T f>.. '::ll>..t1PLl-D
Fe ,R_ RLt..r:.
\_ hlb..ll" C..'t'C..LE.
b..DDE.D
xx.;.x: VN
()(
,'/','-(\7-Jo.. ,-,..ffi'/x
------- r-~r-if:'~
.......,
lfAIUSEI
STD-Stll
AI
iiiilci
~~~-·•-sa)
AD
IIUO {
( o•u•• }-
k
Iii
,.,.
I
AD
MIIIOIIY AIIOIIISI
DAfAOUT
...,. ( 118
Mii
FIGURE
\
r
7: ROM READ - RA:lt1 !H.TE 1-lH.ITE CYCLE
1\)
-'
22
I
I
' )
........._
H
0
........._
H
23
in
t~ated
clock
Figu~e
pe~iod
CPU
enti~e
7, the CPU outputs status
and holds these lines active
The
t~ansaction.
t~uth
table
the T1
du~ing
the
du~ing
fo~
the status
outputs is shown in the Table 1.
F.
INTERRUPT SEQUENCE
As shown in
Figu~e
9, the NVI* input is sampled
T3 of the last machine
du~ing
the
t~igge~s
non-vecto~ed
as below.
desc~ibed
P~io~
A LOW on this input
cycle~
inte~~upt
to
acknowledge sequence
ente~ing
the acknowledge
cycle, the CPU executes a dummy IF1 cycle.
cycle, the
P~og~am
system stack
the actual
The
pointe~
inte~~upt
inte~~upt
of 10 clock
will
ma~k
is not updated; instead the
(R15') will be
acknowledge cycle happens.
T1
th~ough
TS and the five automatic
As usual, the AS* output will be LOW
the beginning of the cycle.
~eflect
Then
dec~emented.
acknowledge cycle typically consists
pe~iods,
wait states.
T1 to
Counte~
this
Du~ing
the
non-vecto~ed
inte~~upt
The STO-ST3
acknowledge code
(0110), the MREQ* output will be HIGH, the N/S*
the same as in the
p~eceding
~emains
cycle, the R/W* will be
HIGH and the B/W* will be LOW.
ADO-AD15 bus with unspecified
du~ing
The CPU will
d~ive
info~mation
du~ing
T1 and
the bus will go into high impedance state
du~ing
T2.
Th~ee
wait states will automatically follow T2.
Afte~
and two
the
mo~e
thi~d
TW state, the DS* output will go LOW
automatic wait states follow.
Afte~
the
""
STJ
ST2
ST1
STO
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L.
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
KIND OF TRANSACTION
Internal Operation
Memory Refresh
Normal I/0 Transaction
SEecial ~LO Transaction
Segment Trap Acknowledge
Non-Maskable Interrupt Acknowledge
Non-Vectored Interrupt Acknowledge
Vectored Interru~t Acknowledge
Memory Transaction for Operand (data
address sPace)
Memory Transaction for Stack (stack
address space)
Reserved
Reser·ved
IFN - Memory Transaction for Instruction Fetch (subsequent words).
IF1 - Memory Transaction for Instruction Fetch (first word>.
Reserved
Reserved
I
!
TABLE 1: CPU STATUS CO.u.;;.J
1\:)
.j::-
25
H
.....
....
~
c
•,.,
i
I
i....
.....
lru
i~
g
.
~
.CI
~~
o-
!I
!lo
'I
,.
:S
ui
fl
i
•••
=·
..
.
!
26
last wait state, T3 will be entered and the DS* will
go HIGH.
cycle.
T4 and TS states will follow T3 to complete the
Following the interrupt acknowledge cycle will be
memory transaction cycles to save the status.
Note that
the N/S* output will be automatically LOW DURING STATUS
SAVING.
During status saving sequence, the machine cycles
follow the interrupt acknowledge cycle and push the old
status on the system stack in the following order: the
16-bit program counter, then the flag and control word.
Then, machine cycles fetch the new program status from
program status area, and branch to the interrupt/service
routine.
Section 3
SOFTWARE DESCRIPTION
I.
INTRODUCTION
Noting that a
tinct
is
p~ocesso~
II.
numbe~s
the application.
fo~
inst~uctions
inst~uctions
This will
go~ies.
impo~tant
and
featu~es
a~e
g~ouped
a~e
available.
could be
la~ge~
o~
p~esentation
T~ansfe~s.
Data
a~e
Ope~ations
As we discuss these
st~uctions
that
comp~ise
listed with optional
example, ADC(B)
DI and EI.
When one
lette~
appea~s
not in
othe~s
lette~s
appea~
and
T~ansfe~
va~iation
~ep~esents
lette~
in some
is in
pa~entheses,
shall list the inmnemonics
inst~uction
pa~entheses.
(D/E)I
pa~entheses,
of the
I/0, CPU
Synch~onization.
ADC and ADCB;
ve~sions
27
Cont~ol,
enclosed in
(e.g., ADC, ADCB).
in
of
catego~ies~we
The
fo~
and Testing, Data
Multi-Mic~o
them.
numbe~
chosen
catego~ies
Ope~ations
Setting,
Pointe~
Cont~ol,Block
The
inst~uctions
and the
catego~y.
smalle~.
into eight cate-
since some
ove~simplify,
don't fall cleanly into one
Fo~
Mo~e
Z8000 INSTRUCTION SET
The Z8000
this
110 dis-
ove~
a judgement about how "good" that
fo~m
of
can execute
Cas the Z8000 can) is not by itself
inst~uctions
sufficient to
the
p~ocesso~
that
inst~uction
When two
o~
a~e
but
mo~e
then one of these
lette~s
28
appea~
in any given
to this is (B/L),
So LD(B/L)
(e.g.,DI,EI).
ve~sion
which B,L
fo~
o~
One exception
may
neithe~
appea~.
LD, LDB and LDL; R(L/R)(C)(B)
~ep~esents
becomes RL, RLB, RLC, RLCB, RR, RRB, RRC, RRCB.
allows us to
sho~thand
some
in a unified way.
inst~uctions
this notation extensively
A.
bits
catego~y
set to
1.
A~ithmetic
MULT(L), DIV(L)
~eflect
I
implement usual
thei~
ope~ations
st~uctions
use
Ca~~y
is used
DAB is used
COM(B).
Logical
~eflect
p~ima~ily
fo~
1 's
The only inOn the
~esult.
to allow implementation of
a~ithmetic
inst~uc­
decimal adjustment.
inst~uctions:
AND(B), OR(B), XOR(B),
op~~ations
of and,
o~,
co~plement.
Shift/Rotate
inst~uctions:
S(D/L/R)(A/L)(B/L),R(L/R)DB.
bits of a
thei~
of the
ve~sions
These implement the
exclusive-o~~
3.
to
These
of addition, sub-
multiplication and division.
2.
I
ADD(B/L), SUB(BjL),
SBC(B), NEG(B), DAB.
a~ithmetic
Ca~~Y
tand the FLAGS
outcome.
thei~
I
that
inst~uctions
a~guments;
inst~uctions:
ADC(B)
multiple-p~ecision
'
this section.
st~action,
tions.
of
We shall be using
th~oughout
consists of the
test values of
o~
a~e
Z8000,
va~iations
DATA OPERATIONS AND TESTING
This
modify
many possible
t~eat
This
~egiste~
left
o~
These
R(L/R)(C)(B),
inst~uctions
right or in a circle.
move
29
Counter/Pointer varying instructions: DEC(B),
4.
INC( B).
These increment or decrement by an amount
ranging from 1 to 16; they differ from the corresponding
add and subtract instructions in that Carry is unaffected
and Overflow is handled differently.
5.
Testing instructions: BIT(B), CP(B/L),TEST(B/L),
TSET(B).
These instructions set FLAGS bits
a~ter
exam-
ination of their arguments.
B.
DATA TRANSFERS
This category consists of instructions that move a
value from one place to another; the value can be
contained in or implied by the instruction, or its locaThe original contents of the destination of the
tion.
transfer are lost.
The data transfer instructions leave all FLAGS bits
unaffected.
1.
RES( B)
I
Constant transfer instructions: CLR(B), LDK,
SET( B)
I
TCC(B).
These instructions move a fixed
specified value into the destination location
2.
LDR(B/L)
Variable transfer instructions: LD(B/L), LDM,
I
EX( B), EXTS(B/L).
These instructions move the
value found in their source argument into their destination argument.
3.
Stack transfer instructions: POP(L), PUSH(L).
These are the pop and push operations.
30
C.
POINTER SETTING
There are two instructions that load an address
register with address of their argument: LDA and LDAR.
These instructions allow segmented addresses to be loaded
in a single operation, and perform a uniform approach
that works with either segmented or non-segmented.
Since these are internal operations, their operation
do not depend on the status output lines from the chip,
and do not distinguish between addresses in program, data
or stack space.
The pointer-setting instructions do not affect any
FLAGS bits.
D.
TRANSFER OF CONTROL
This category consists of instructions that break
flow of control; they change the value of the PC.
Except saving and restoring of CPU status associated
with interrupts, none affect FLAGS.
1.
Jumps: JR, JP, D(B)JNZ.
2.
Subroutine instructions: CALL, CALR, RET.
These
instructions used for implementing subroutines.
3.
Interrupt/trap instructions: SC, IRET.
the "system call" trap.
sc
is
It causes the PC, FCW and the
"reason" to be saved on stack.
IRET undoes all of that,
restoring the FCW and PC and discarding the "reason".
31
E.
INPUT/OUTPUT
The Z8000
bytes
~ecognizes
its I/0
fo~
the same size
ope~ations
and
ope~ations
designed
fo~
available to it.
space of
The special I/O
add~ess/data
Inte~nally,the~e
lines AD7-ADO
is no difference
and special I/0.
o~dinary
The basic I/0
inst~uction,
affect any FLAGS bits.
F.
add~ess
use with memory managment
unit (MMU), which cannot have
between
anothe~
its "special" I/0.
fo~
a~e
an address space of 65,536
(S)CIN/OUT)(B), does not
It is a privileged
inst~uction.
CPU CONTROL
This
catego~y
of
inst~uctions
has
CPU housekeeping than with computing.
mo~e
to do with
FLAGS bits
a~e
only affected explicitly.
1.
LDCTL.
Cont~ol
These
inst~uctions
of CPU.
~egiste~s
manipulation:
~egiste~
(D/E)I, LDPS,
allow access to control
All of these
privileged instruc-
a~e
tions
2.
The
FLAGS manipulation: COMFLG, RESFLG, SETFLG.
fi~st
bits C,
3.
th~ee
z,
S,
allow
synch~onization:
instruction.
G.
BLOCK OPERATIONS
The
gene~al
~equi~es
on any combination of the
V/P.
Exte~nal
p~ivileged
ope~ating
fo~m
a counter
HALT, MOP.
HALT is a
MOP is not.
of a block operation instruction
~egiste~
and two
pointe~
~egiste~s.
32
1.
Block data testing: CP(S)(D/I)(R)(B).
A st:ring
of data wo:rds of bytes is compa:red eithe:r with anothe:r
st:ring o:r with a value in a :registe:r.
2.
Block data t:ransfe:r: LD(D/I)(R)(B).
The st:ring
of wo:rds o:r bytes is moved f:rom one place to anothe:r.
3.
Block I/O:
(S) (IN/OUT) (D/I) (R) (B).
A st:ring of
wo:rds o:r bytes f:rom memo:ry a:re output to o:r input f:rom a
constant I/0 add:ress specified in a :registe:r.
4.
Block t:ranslate and test: TR(T)(D/I)(R)B.
inst:ruction uses a 256-byte t:ranslation table;
lation of any value i
This
the t:rans-
between 0 and 255 is the i-th byte
of the t:ranslation table ..
H.
MULTI-MICRO SYNCHRONIZATION
This catego:ry of inst:ructions deals with synch:ronization of access to a sha:red :resou:rce by seve:ral CPU's.
The:re a:re two CPU pins and a 4-bit exte:rnal bus p:rovided
in the system a:rchitectu:re.
associated with this scheme.
MREQ conducts the p:rotocol
MBIT tests the input pin
and :repo:rts its state using S and Z; MRES and MSET
cont:rol the output pin and leave FLAGS bits unchanged.
These a:re all p:rivileged inst:ructions.
33
III.
COMPUTER PROGRAM AND FLOWCHART
The following is the description of tasks performed
by the program which is listing in Appendix C.
1.
RAM Test- This routine searches for RAM chips
which are incorrectly loaded.
First, each RAM
location has its address stored in itself.
Then, a check is made to see if the stored
address is in fact that address.
If everything
matches, continue to next test.
Secondly, put into each address the complement
of that address.
After all addresses have again
been filled, a check is made.
matches, continue to next test.
The third test loads FFFF, AAAA, 5555, 0000
patterns into RAM and the patterns are checked.
If everything matches, the test is done.
If at any time something does not match, the
address that was being checked is put into
RAMEADR, the error data put into RAMEADR+2, the
expected data put into RAMEADR+4.
2.
CPU Instruction Test - This routine checks all
z8000 instructions.
If an error is detected,
CPUFLFG flag is set to the address which
indicates instruction fail.
The following instructions are not checked:
IRET, DI, EI, HALT, LDCTL, LDCTLB, LDPS, SC, I/0
34
and MULTI-MICRO instructions.
3.
Interrupt Test - Certain tests are performed by
the program upon the occurance of a Non-Vectored
Interrupt.
They are Program Cycle Fail Timer
Test, Input/Output Test.
35
STAR.T
J)XSA8LE"
>----~
FAilE] ..UJ)/l.ES.S
EXPE(.TfJ) ])ATA
AC:fUAL
i),4TJ\
!N Ffoo, F/Ow, Fiv..z.
/;N~r3LE
INiE.J'.fi.IJP"i
CPU
:£rJSII(t.JC !tON
FA~LE])
A J)pP.Esr
IN
FfO(,
:INCJl EM E NT
(OUNI£R
IN Frtoc-noE
FIGURE 1 0: DIAGNOSTIC: PROGRAH FL0\1'CHART
36
/IION-ll!c.."To~E]>
rM7E£/l.
vrl
/lourT.v£
S~ lltiiCE
P/l.C>C.~SS
C. YC
PRcJ&R.AM
Lc rAJ I..
TrMiiR.
PP.occ.s.s
1""HE T.A
1"E ST
l>~.t..TA
COU/1/T~Il.S
C.AL
P..OM
PoRT
c
fl,.ETvll..w Tv
J:trrE{(A.uPr
FIGURE 1 0: .u.LAGNOSTIC PROGRA1'1 FLOI~CHART
(continue)
Section 4
SUMMARY
This
pape~
has detailed the
aspects of the 16-bit
P~e-P~ocesso~
and
p~ocesso~s
fou~
gy~o
data.
othe~
have been
applications
~ecognized
example, the flight
Z8001
ment by
p~ocesses
fo~
the Z8000
in the
mic~o­
milita~y
and
systems.
ae~ospace
Fo~
softwa~e
mic~op~ocesso~s-based
Module which collects and
accele~omete~
Howeve~.
Z8000
and
ha~dwa~e
mic~op~ocesso~s
Lea~-Siegle~
compute~
fo~
Ast~onics.
system built
the F-15 is
All the
unde~
a~ound
develop-
ai~c~aft's
flight control elements are completely dependent on the
electronics, and have no mechanical backup is needed.
Also, at Litton Data Systems, engineers are developing
sophisticated battlefield command and control systems
around multiprocessor-based briefcase terminal consisting of a four MHZ Z8001 as the main processor with 512 K
bytes of directly accessible memory
periphe~al
and five eight-bit
processors, each with 64K bytes RAM.
a sophisticated
microprocesso~-based
Mo~eover,
Missile Autopilot
system that has been proposed for use in the WASP antitank missile is being developed by the Boeing Aerospace
Company.
Built around two Z8002s working in tandem with
six AM9511 arithmetic processors, the missile autopilot
37
38
performs a variety of floating point 32-bit operations,
as well as trigonometric and inverse trigonometric
functions.
In summary, a small, powerful microcomputer system
can be implemented with a Z8000 CPU, memory and peripheral devices.
39
REFERENCES
1. "AmZ8000 Family Reference Manual: Principles of
operation AmZ8001/2 Processor Instruction Set".
Advanced Micro Devices,
1979.
2. Bursky ., Dave, "For Microprocessors and Microcomputers,
The Key Word is Microprogramming", Electronic
Design. Vol. 29, No. 24. Nov.
1981. pp. 79-94.
3. Mateosian. Richard. "Programming the Z8000", Sybex
Inc .• pp. 75-113.
1980.
40
APPENDIX A
Z8000 INSTRUCTION SET
Advanced Micxo Devices,
1979.
41
-- - -£II
£1111
- --· --c...y
-
Clur
"' •-o
llDC
ADell
x.
ADO
ADOB
ADDL
11'1
DA
"-•
R
11'1
DA
b:Nnga
"-""'
R
1M
CP
CPB
CPl.
......,inlo~
R--
1M
IR
DA
C.P
CPB
X
IIA
IX
ID
1.08
IDL
ID
IDO
IDA
dlt,R
....
........
IDAR
........
IDII
"-•
LDIIII
A.IIC.n
11'1
DA
X
IIA
ax
DA .
X
M
IX
..
AA
"
DA
X
LDIIII
!DR
l.DNI
IDRL
!DR
l.DNI
IDRL
Pc.
flOP\.
-.A.n
....
....
....
IR
DA
X
M
...R
DA
..... ....."
I'U8tL
DA
X
DEC
DEC8
R
Ill
DIY
DM.
CIII=IM
........
~re
• c:.ny
R-A•.-
....
~~--EXTS
EXTSII
EX1'SL
..--.~
~~--..-c:-
R- n (n • 0 ... 111
.......,,...,....
IIIC
INCa
IR
DA
X
- ..
-.n
"--
......, ...... ,s.-........,
MA.T
MA.n.
ciii-R(n--.
(ft- 1 ..• ,.,
lEG
!EGa
..........:
--"
~--~~
..
-
11'1111>
••ac•-otR
IR-.-c
-
"'-gioW
~--
Clll- . .
R
o.c;..,., .....
R
o--bpn
R
IY
•-•-n
111
(11•1 ...
Di¥D(ii9*11
R,-Lang _,
...........
- : A..t=A...-... ==
- - --.....
--··"
II
-R,._..a• •
.........
~Sign
~-"'-. . . "'
"lhrciugll .... -
-.n
"--
.._,_._
,._...,
+3r7'171
eo..-. -
R-..,
DA
X
R
IR
DA
X
R-~~e(n--.
(ft• 1 ••• 111
..-~(s:-
...."
X
IR
DA
X
..__
fi'OII
R - fit •
IR
DA
X
.......,.
ciii-R
(. . . -327111 ... +327t0.
X
~
.......,
{l8llgt -32711 ...
RA
DAB
_ . , (SIInl
ciii-R
11'1
DA
X
__
......, -
......
...... "
DA
R-~~e
X
ID
1.08
IDL
~
~
~
()pMWNie lilllllllee
a.R
CLAB
....
."
R
R...,
SUB
SUIIII
lUlL
R.IIC
..
Lang-""·--·
-............
(11•1 ... 111
_..,._,_,._,
......,~
DA
X
"PPua _ . . , _ - .... ,
.
......
•-o-•
R
,._ . _...,_....,
R
.
s.ar.c.
Ill
R-R-IIC
R
DA
X
sac
_..,"
SBC8
DA
X
...................
SolillriiQ-c.ny
42
-....... ....... -·
~
a..R.•
11100
NOr
NCR"
IC)R8"
....
lilt"
..lA"
IIIIIR8"
OUT"
f-CUTr
CUTO"
OUTDtr
OTDR"
01'l)R8"
..... ....
~
OA
R-on=
IR
lf'IIIUI-o.:..n.....
.,._...,
__ _
--· '"'--__ __
__
~Jlk11131U ....L64ACIII'addrea
"-A-1
........
IR
R
.,._.,.,
.... c...--,....
...
ltlcM.
A-A- I
"-.-R•O
IR
R
e.-on=
IR'
~-....,..., ..,
.._.
A
..._...._
IR
DA
........
IR
R
,~:c.-
I
Oulpo,l.
~- " - "
•·1GdiC..,_.lfB***-
A-R-1
.._._A•O
01/Tl"
OUT1II"
~
OTIR8"
IR
A
........
IR
A
.-.-.......
R-R-1
Outu. _ _ ,....
.....,._
- -- . ---..........
-- ::::;..o-.
....... ... -- ----................... -......
.... -- ----................
,............
__
111-111-1
,....._..111•0
DA
R.•
...,. .
..,..
8INII"
SINCA"
SIN OM"
IR
A
lA
SOUT\8"
SOTlR"
so.,..-
.
R
--
•· la4JC
.,,_.Ill:....,_
, .. _ .. -1
..,
i"-•WIIiiR•O
IR
R
-- ---
1'R-R-1
-.-IIOWCIM.
R
Ole-
Sooculo.&--
Soocul 0... ....... - , . . . .
R
~SIC-
- ... ·-·-·
._
-~-
Sociollf'IIIUI--
lA
A-R-1
~
-
or
........
- c...
(An,.,..._"' 1M. VI)
Er
HII&.T-
LDCn.·
LDCn.·
..
-
---
C1\R.
C1UI
ux:na
LOPS"
•-.-:
--.
o..r.-
COIIA.G
'121
A-A-1
R
SOU1't"
LOCIUI
R
llfiR"
SOTOfl"
SOlllAa
$tloocolllnput- ' * " -
111-111-1
,_._111•0
a.a-
*•lJJJC . . . . . IIt: . . . .
R-R -1
cili-A
---Oulpul--- --- __--A
lA
~~c-._,._
c..-.
.,
lA
s-.to..-a--
R-R-1
"-11.-R-o
'"*'c~re-.R-A- 1
........
a.--
1~~--'0..
lA
A
R-A-1
.._. ...... 0
.....
OA
SOUTII"
,._ .. -1
........
..,
~
sour
IR
..
- -IIC ....-· __
-- --=- ........
--__
....
l8r
loiiECI"
aMES"
MSET"
NOP
RESfUI
IElR.G
-
-
-
,....,_oiC.Z.S.PM
&fte!t ........
I M P - - oiiM. VII
-.,y
R
~-ea.- Aogiow
A
~._ea.-......,
cn..R---en..R
........... _.,...
. FUiR-. --fiLaR...............
-- ..
PLGR.
R.GR
.
-
~Flee
1M
X
-
II
~
,.. __
............
~-
~
T•-·
.....
----
s.ISIOII·I.or.-SIOII
- - -__..,_..
-s.l
- -- NDo.--
...- - ..........
... - ..,...
~-·c:.z.a.,.,...,
~Mr---"'c:.
z. .. ....,
4 '3
--- --·
~
OpM.-
CP'D
CPD8
R,.ft.
R,,cc
Ill
LDI
R,-""'
LDI9
Aulocttcl•• wnltrc ...,...
R,-R,-1
~
CPDRB
Rx.ore.
R,. cc
IR
c.cr-- Rep..-
~-
Rx--
......,.ca••••trt: addNSI
R,-R,- 1
----
Reput until= • tow "' R,
CPI
CPIB
Ax. ft.
IR
·_!.._
c:cr.--Ra-...,
R,.oc
Ro-A..- 1
CPIR
:::PIP8
Rx. ft.
R,.oc
IR
-- --- --IFI
A,oc
•true
lA
TADB
"TlliDI'a
nue
Clll.ft.
R.cc
IR
R
Oil.
on:.
R
--
--
---
Slmg.
Doer.- Ro!>Mt
TAIAII
~Scm;-,._..,
-- ----- ----.. . .....---· -------·---A-A-1
IJ)D
UIOit
lA
R.coc
-
IR
..._...._._..,
~.-~-o.:r-
IJlOA
I.DORII
IR
1.-1.
o.c.-- .._..
R
A-A- 1
AlpMI-111·0
-
R -R- 1
IR
TATD8
1.
en:Z.A
lfC
_
_
........
---IIIII)
... J
lA
-
T--o...-
R-A- 1
T-. c.:....... ...,.._..
........
·-=ll!oll
"'uc
A-A- 1
~-A•O
Tr
___
IR
•-orcla.)
..........
A-A- 1
lA
Tr-. _ _ .._.
•-orcccllll
-~~~~-
R-A- 1
"'
...
R• 0
T--T-.o.a.....
AH1-M:2(1fc11
~
··-~-1-
R-A- 1
TRTDAII
II'C1.
II'C 2. A
lA
T--Tftl.
o.a......-~
IIIHI- 11e2 ~wo;1)
-·
I
·-·~1
....
A-R-1
AlpM!uniiA• OorAH1• 0
nnw
OOC1,
•2.R
IR
TATIIW
lrC1,
IR
T--T--
AH1-II'C2(en:1)
--1R-A-1
R
A -A- 1
..,
.,._...,
Aoo11N1 -
~am;.n:r.-AIIoMI
A-R-1
"--unlla:illnlearR•O
R-A- 1
1.-1. . . . , _ - .._..
............ o
A
~---
CPSIA
CPSIM
"IR
R
A-A-1
,.._unllccillnlet:wA•O
CPSI
CF'SIB
~
IR
fl
1
--····--~
~·
A
orR, • 0
. . - lfC
A:uiOdlc••••~t Clll..S •
R.oc:
LDIR
LDIRS
c:cr.- Slmg- o.c.~-A-
CPSOA
aosoRII
.
~---~
Ax-..,
...........,_...,_
R,-R,-1
AopHt unlil cc
CPSD
CPSDa
-·- -- --· --ui.a-----___
~-0.:.......
T_ _ T.._
'"'2. ~
--~
-.-.....,,_
AHt · - - 2 (lrC1)
R-111- 1
AoouluPIIA•OorRMt•O
44
.....
...,...,
.!~o.--,A. .,.
AH08
~
R
AHO
""IR
A-AN~D.c
- -·
.....
lilT
a--
...._
dii.D'
BITB
ll
COMe
~
llof
a.- NOT'*
Ill
DA
ll
""
OA
R-AO'Ion:
A
Ill
IR
R.on:
OR8
..
DA
!liT
lliTll
d.. A
R
RES
AESB
dsi.D
R
""
DA
X
AES.
RE5II
d.. R
R
SET
dll.b
R
IR
DA
X
X
TFST
TESTS
TESTL
A
lA
d.
TEST
CIIIORD
SETB
..
DA
X
TCC
TCC8
cc. dll
XOR
A,IIC
r .. Com~Uon c...
R
S..L.Sa~ccis,..
XOR8
R
~OR
1M
A-RXORIIIC
IR
SET
dii.R
~
DA
X
CAUl
DMZ
D&INZ
!RET"
./11
dll
....
cc. dll
RA
Ill
IR
~
Cal~
A~..tD.:twu•J1911tSP
RA
c:c
Clll
TSETB·
11'1
A
Ill
r .. -s.c
Sf119-M58alclll
dll-1111
- ---·
......
a--
a.--
ALDB
A.ft
I "'-'- 091 Ld
R.IIC
Cal,.._
dll.n
R
Aclc-. Ld
II
torn-(n•l,zt·
OSP-PC
PC-PC•dll
RLC
ALC8
dll.n
R
A
Ld - . . c...,.
tornblll(n • 1,2}
o.::r-- ..... , fOI.lMI
RR
RRII
dll.n
R
II
AIU8 Ri;lll
torn-(n • 1,21
R-A-1
FR•O: PC-fiC+elll
ARC
MCII
....._
.. ,•• Sf'
~
---
(. . . -254 .. 0)
PS-OSP
-ICJOII-SP
!iDA
SDAII
.....
.....
A
II
R
~
A
dii.A
Icc • ..._.: PC-dll
SCI.
SOLS
SDU.
SlA
SlAB
dll.ll
A
c..-.. ... _
dll,n
A
...
A
Jt.mp~
Jt.mp
su.
......... eor-
SU.8
SLLL
-
Icc•-: PC-OSP
~
s.,_c.a
..... SJII
~~
.., •• SP
8SP-OIIIPS
"""".....,.._, ...
.,._..,_CII
SRA
SIWI
SRAI..
SAL
SRJS
R.L.
"""- Oiqot Ai;N
"""*
-0,...-.......
Roe.- Ai;N-.. c..,
" ' " - { " - 1,21
_ _ .... ...,tor
_,,.
_......... "'
-~
-alA
SlAI.
{. . . -25tb +25oll
Ao
sc
S...~S«o,..-
RADB
Icc•-: PC-PC • elll
RET
Sec I!« SialiC
s.c dll c. -""<! by b
AL
ALB
OSP-PC
PC-dll
X
cc. dll
.......... "' .
R
R
DA
JA
~-ao~
-CIIIDO-'-<Sby
MJTATE AND SHtFT
(. . . -40M ..
RA
. . DOII*>Aecl by b
)(
~-
IR
-~~~~
-
=-otll
TSET
DA
I'ROGRAM CONTROL
CAI.L
T•lllle>yr....,.
Zfii9-NOT•III-by...-aiA
r... .:.~o~~--tor
X
- .. --
A
SETII
DA
.....
Z 11ot- HOT dll ~~~~--tor D
X
R
Clll
o-TISIIIIIS<nc
DA
DA
COM
R
IR
dll.ll
A
SIIIILd-
"'""'"-
SIIIILdf.I09ai
SIIIIA911-
"'"-
Slllllli;lll'-byn-
45
APPENDIX B
PROGRAM
LISTING
ZTI:STER
r.AGR08000 AmZ8000 Assembler
0000
0000
PROGRAM
~000
%
% PROGRAM
%
% PURPOSE
:t
00~0
%
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
%
1
%
r~00
%
ZTESTER
%
TO ISTABLISH MINIMUM TlST REQUIREMENTS
FOR 'I HE LTN-90 PRE-PROCESSOR ,AS FOLLOWS:
1. I/0 BUllER AND fRE-PROGESSOR BUFFER. TEST
2. COUN'l'ER CLOCI TIS 'I
3. RAM TEST
4. CPU INSTRUCTION TEST
%
I
%
l
%
%
!l
%
%
l
%
%
I
%
%
%
%
%
%
%
%
n:tnn%%UU:tn%%~'-~'~n,.:u:t:t.:a,:t:auuu.u:u~:t.u~:tu:uu:t~u
GONST
CONST
CONS 'I
0000
0000
£000
0000
0000
0000
0000
0000
0000
0000
0000
%
%
=Nl800i
=#UF!i
=I#FB00i
% START ADDR. I'OR RAM
I END ADDR. FOR RAM
% RAM ERROR ADDRESS
%
%
%
THIS DATA PROVIDES THE NEW FLAG/CODE
~ORD AND ENiRY POINT
lOR SERVICING IN1EERUP'IS, SYSTIM CALLS AND TRAPS.
:t
1
0001
4000
0100
RAMSTRT
RAMEND
RAr.EADR
THE FOLLOWING IS THE NEW PROGRAM STATUS AREA DATA
NOTE TEAT THE NEW PROGRAM STATUS AREA MUST BEGIN ON A
256
WORD BOUNDARY (XX00).
I
I
fl00~
01101
ZTlSUii i
%
' REGISTERS
R0-R15
% USED
%
:t SUBROUTINES
RAMDIAG, GPUTEST
% GALLED
%
1 EXECUTION
MEMORY
% TIME
USED
%
:t PROGRAMMER
MINH NGUYEN
%
% IATE
OCT 15,1982
1
0000
0000
0000
0000
0000
£000
0002
Pap,e 1
%'UU%%%%%%%%Ut:U:t~~l:t:i.UUtUtU,~:l~UUU:U~'U:l1U1U:t!U:U
00021
0000
0£00
0000
0000
0000
1.0.1
XNPSA:
WORD
WORD
WORD
0001i
0100000000000000£;
~PSTARTi
~
FROGRAM REVISION NUMBER
% INITIAL FCW
% ADDR. OF PSTART, ON
PO~ER
B0
UP.
+:-
0\
Zl.ESTER
0006
0008
1Hl0A
000C
000C
ee0c
000C
000E
0"'10
0012
MACRC8000 AmZ8000 Assembler
0000
4000
0136
WORD
WOED
WORD
~016
0018
0018
4000
0136
4000
0136
4000
0136
~018
0018
001A
001C
001C
001C
001C
4000
0138
%
4000
0011
001E
0024
002A
0030
~036
003C
01B6
01P6
01B6
01B6
01B6
01]6
Par,e 2
;
0100000000000000!
~PRIV_INSTR
% PF.IVILEGEt INSTRUCTION
i INTERRUPT ENTRY PI
%
% SYSTEM CALL - SYSTiM MOtE, EXT. STOP ON, INTFRRUFTS BLOCKED
%
WORD:
0100000000000e00s;
~ FLAG/CODE
WORD
"xsts;
WORt:
% STSTE~ CALL ENTRY POINT
WORD:
0100000000000000Bi
:t FC'I :
WORD:
"TRAP_VCTR
I
% INTERRUPT ENTRY PT
%
% NON-MASKABLE INTERRUPT - SYSTEM MODE, EXT. STOP Oh, lNTR BLOCKED
%
WORD:
0100000000000000!1
t FLAG/CODE
WORD
WORD:
"XPOWER;
% PO~ER INTERRUPT 1NTRY
%
% NON-VECTORED INTERRUPT - SYSTlM ~Ott, tXT. STOP ON, NVl BLOCKED
%
WORD:
0100000000000000B;
:t FLAG/CODE
WORD
WORt:
~XCINTR;
%
% VECTORED INTERRUPT - SYSTEM MODE, EXT. STOP ON, VI BLOCKED
0014
0014
0014
0014
0
1.0.1
01B6
01l!6
01B6
01B6
0U6
01B6
01E6
01ll6
01B6
01£6
WORD:
FOR 16 DO
WORD:
0100000000000000Bi
% FLAG/CODE
~VI00_VIFFi
% DUMMY VECTOR
WORD
003E
003E
0100
0100
0104
0106
010A
010E
0110
0114
011A
0120
0122
0122
2104
7D4D
210F
2104
7D4B
5F00
4D05
4D05
7C06
0000
ZTESTER:
PST!RT:
F89A
0000
01BB
F808 2000
.1!89C ICE0
PLOOP:
ORIGIN
#1001
LD
LDCTL
LD
LD
LDCTL
CALL
LD
LD
R4,"XNPSAi
PSAPOU ,R4
R4,1#0000 ;
REFRESH,R4i
RAMDI!Gi
C!LROMll ,1t2000i
PPADDR,I#FC80i
II
NVH
R15,~XST!Cii
% INITIAL ENTRY
% LOAD NPS!P
~ LOAD
CONTROL REG.
% SYSTEM STACK
% REFRESH REG
~ TO DISABLE
% TEST RAM
% CLEAR CAL ROM INDEX
I SET PP ADDRESS Ai #FC80
% ENAELi INTEnRUPT
~
BACKGROUND LOOP
+:-
--..1
ZTESTER
MACR08e00 AmZ8000 Assembler
0122
0126
012A
0130
0134
5100
5400
1600
5D00
0134
EEF6
0136
0288
JE0C
0000 0001
F80C
EJECT;
1.0.1
PagE' 3
CALL
LDL
AttL
LDL
CPUTIST;
% TIS'I CPU INSTRUCTION
RR0, BACKGRNDH
RR0,H
BACKGRNDl,RRilll
1
JR
PLCOP;
INCRE~ENT
BACKGRNDl COUNTER
.j::-
00
Z'IESTER
0136
0136
0136
0136
0136
0136
0136
0136
0138
0138
0138
0138
0138
0138
0138
0138
013C
0140
0144
0146
0148
0148
014C
0150
0154
0158
015C
0160
et60
0160
0160
0160
0160
. 0164
0168
fli16C
0170
0172
MACR08000 AmZ8000
017C
01e0
0180
0184
1.0.1
Pa~n
4
l
% PROGRAM STATUS AREA
%
PJIIV INSTR:
ISYS'i
TRAP VCTR:
XPOWER:
IRET;
7E00
"
% NON-VECTORED INTERRUPT
%
ICINTR:
030f
1Cf9
6106
6F06
001E
0a0E
lC0E
FBJB
6106
6F06
6106
6F06
6106
6f06
FC02
UFA
IC04
FBIC
FC06
IBIE
% NON-VECTORED INTERRUPT ENTRY
% PROCESS PRCGRAM CYCLE JAIL TIMER
% INITIATE A MEMORY RIAt CYCLE TO LOC fCOE
SUB
R15~30i
% MAlE SPACE ON THE STACK
LDM
R15 ,R0,15;
% SAVE ALL ACTIVE REGISTERS
LD
R6,#IC0E-;
LD
fBIB,R6;
% PROCESS DELTA THETA COUNTERS : I,Y,Z
% AT #FC02,#fC04~#fC06
LD
R6,#FC02 ;
LD
FEFA,R6i
% STORE I IN #FBI!
LD
R6,NFC04-J
LD
fBIC,R6i
~ STOhE Y IN #FBFC
LD
R6,#IC06-;
LD
FBIE,R6i
% STORE Z IN #FBFE
%
6101
6105
6105
6104
2I41
A941
1808
IC80
lACE
I89C
0174
0174
017A
A~~emble~
% TEST CAL ROM PORT
% CAL ROM RESIDES IN LOC #2000 THROUGH #23FE
%
LD
R1,CALROMII;
LD
R5,#FC80-;
LD
BABEFACE,R5;
LD
R4~PPADDRi
LL
HiC
R4 ,Rli
R4,2i
IF R4 EQ 0
~
8544 U02 2104
FC80
6F04 I89C
LD
PPADDR,R4i
6102 }'808
2123
LD
LD
R2,CALROMII;
THiN
LD
% LOAD CAL ROM INDEX
:t READ. START I/0 ADDRESS
% S'IOR:E IN #iACE
% OUTPUT CAL ROM INDEX
% TO PP BUS
Rt,#FC80;
If R4=0 THEN SET R4=#FC80
% PPADDR DISPLAY INCREMENT fROM
% #FC80 TO #FFFE
R3,R2~;
.j:-
\0
ZTES'l'EP.
0186
0168
0188
018i
0190
0192
0194
0194
019A
019E
019E
01A4
01A8
01A6
01AC
01ll0
01B4
01116
0lll6
flt:B6
01B6
01ll6
MACR08000 AmZ8000 Assembler
ll324
Rll
R2,1i
IF RL3 NI RL2
8AA:B E602 6F01
IE0A
1!320
A921
THEN
LD
CALROMJL,R1i
RL
INC
0ll02 23IE E202
2102 2000
0ll02 2000 E902
2102 2000
6F02 J808
1Crt 000I
0101' .0011:
7B00
Par,e 5
% IF TEST OF DATA FAIL THEN
~ SET ~DDR CAL ROM FAIL FLAG
R2,H
R2 ,2;
II' ll2 G'l' #23F'E
THEN LD R2,#2000l
% IJ R2)#23Fl THEN SET
II ll2 LT #2000
THEN LD R2,#2000;
% IF l2<N2000 THEN R2=#2000
LD
CALROMII,R2l
LDM.
R0,R15~,15l
ADD
R15,30l
IRET;
1.0.1
R2~#2000
% POP THE ACTIVE REGISTERS
%
71!00
1 VECTORED INTERiUPT
%
YI00_VIFF:
IRITl
i'l£8
01ll8
EJECTi
\.]{
0
ZTESTER
M!CR08000
01.BE
01B8
IHB8
01!18
01B8
01B8
0lB8
01B8
~
% FILE
%
% PURPOSE
%
% METHOD
~
%
%
%
%
%
%
01B8
01B8
01B8
01B8
011l8
01B8
%
%
%
01B8
%
01BB
011l8
01B8
%
%
01B8
01BS
%
% REGISTER
1 USED
%
% PROGRAMMER
%
%DATE
%
01B8
ElllB
01B8
01B8
01B8
01:E8
01B8
~1C0
t
RAMDIAG.ZSC
~
THIS ROUTINE SEARCHES lOR BAD RAM CHIP~
.
FIRST EACH RAM LOCATION HAS ITS ADtRESS STORED
IN ITSELF. THEN A CHECl IS MADE TO SEE IF THE
ADDRESS STOiiED IS IN FACT THAT ADDRESS. IF
EVERYTHING MATCHES, CONTINUE TO NEXT TEST.
THE THIRD T'EST LOAI:S HFF, AU!, 5555, 0000,
PATTERNS INTO RAM AND THE PATTERNS ARE' CHECKED.
IF EVERYTHING r,ATCBES, THE TEST IS DONE
%
%
%
%
%
01.B8
0U8
01C4
01C8
01CC
Page 6
THE SECOND TEST PUTS INTO EACH ADDRESS THE
COMPLIMtNT OF THAT !DtRISS. AFTER ALL. ADDRESSES
HAVE AGAIN BEEN FILLED A CHECl IS MADE TO SEE IF
THE IA'l'A STORED IN'IO THE ADDRESS IS TBE
CO~PLIM~NT OF THi. ADDRESS.
IF EYERYTHUG
MATCF.ES, CONTINUE TO NEXT TEST.
%
01B8
01B6
01B8
01Bi
1.0.1
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%t%t%%%%%%%%%%%
01B8
01E8
01B8
01E8
01B8
01B8
01BE
01BA
!~Z8000 !sse~bler
1
I
~
%
%
~
%
%
~
%
%
~.
%
%
%
%
%
~.
%
%
IF AT !NY 'liME SOMETHING DOES NOT MATCH, THE
ADDRESS THAT WAS BEING CHECKED IS PUT ~N ADDRESS
RAMIADR , TB! Ui.ROB DATA PUT INTO RAMEAtR+2,
THE EXPECTED DATA PU1' IN RAMEADR+4.
%
%
R6-R12
%
~
~
t
%
%
l
%
%
MINH NGUYEN
OCT 15,1982
U.U~~:tUUU%%U.U:lUU%U%:U~%%:UlUl:U:n.ll:U:t%U:t!UU%~U~:UU.U
97F6
2109
A19A
210B
210C
0DC5
A9Cl
RAMDI!G:
FE00
nn
F800
0000
POP
LD
LD
LD
LD
LD
INC
R6,
R9,
R10,·
Rll,
R12~
R12 ,
R12,
R15~;
R!MSTRTi
R9i
li.AMEND;
RArEADRi
0;
2i
l SAVE RETURN ADDRESS
% START ADDRESS
% SAVE START ADDRESS
~· END ADDRESS
% OUTPUT !RROR ADDRESS
% I~ITIALLY CLEAR ADDRESS
....
\Jl
...
ZUSTER
l:llCE
01D2
011:4
01D4
l:llD4
01D4
01D4
01D6
elDe
1/JlDA
1/JlDE
01IE
01E0
01E2
01E4
01E8
1/JlES
01EA
0UC
01F0
01F0
01F0
01F0
0tr2
0114
01F6
01F8
0UA
01FC
e:::e0
0200
0202
0204
0206
e206
0208
020C
021/JC
0201
0210
0214
0214
0214
0214
0216
MACR08000 AmZS000 Assembler
0DC5 0000
ABC1
LD
DEC
R12-,
R12,
% CHFCK ADIRESSES
2F99
A991
81!119
5E02 l:llD4
ADDRESSL:
LD
INC
CP
JP
AlA9
A197
0B97
5E0F 0252
ADDRl:
A991
EllB9
5E02 01E0
Page 7 ·
0i
2i
(TEST #1)
R9-,
R9,
R9,
IE,
% STORE ADDRESS INTO SA~f. ADIRESS
R9i
1 GET NEXT ADDRESS
2i
% FILlED ALL ADDRESSES' ?
Rlli
ADDRESS!;
LD
LD
CP
JP
R9,
R7,
R7,
NE,
R10i
% GET START ADDRESS AGAIN
R9i
% GET ADIRESS FROM ADD.lSS
R9-;
1 DO ADDRESSES MATCH ?
RAMFAili
% IF NOT, GO TO :BAD DATA LOOP
INC
CP
JP
R9,
R9,
LE,
2i
R11i
ADDRli
% CHECK ADDRESSES
A1A9
A197
8D70
2F97
!991
8BB9
5E02 0112
1.0.1
% CHECKED ALL ADDRESSE~ ?
% II NOT, CONTINUE THIS LOOP
('!EST #2)
% GET START ADDRESS
% GET ADDRESS
% COMPLEMENT ADDRESS
1 STORE COMPLEMENTED ADDRESS INTO ADDRESS
% GET NEXT ADDRESS
% FELLED ALL ADDRESS?
LD
LD
COM
LD
INC
CP
JP
R9,
R7,
li7i
R9-,
R9,
R9,
LE,
LD
LD
COM
R9,
R7,
R7i
0B97
5E0I 0252
CP
JP
R7,
NE,
% GET DATA FROM ADDRESS
R9';
I DOES DATA MATCH?
RAMFAJLi
A991
S:BP9
5E02 0202
INC
CP
JP
R9,
R9,
LE,
Rll;
A1A9
A197
SI70
HDR2:
ADDR3:
% CHECK PUTERN
A1A9
BLOOP:
R10i
R9i
. R7;
2i
Iilli
ADDR2i
R10i
R9i
% STARTING ADDRESS
% GET ADDRESS
%
2i
AIIIi3i
:l
% FINISHED CHECKING?
(TEST #3)
LD
R9,Ji10i
% GET START ADDRESS
\.Jl
1\)
ZTES'IER
0216
021A
021C
021E
0222
0226
0228
022A
022E
ltl2:32
02:34
0236
023A
023[
0240
0242
0246
ltl248
024!
024E
e252
0252
0252
E254
0256
0258
e25A
025C
025E
0260
0260
0262
0264
0264
MACR08000 AmZ6000 Asserr.bler
2107
2!97
01!97
5E0E
2107
2197
0B97
5E0E
2107
2F97
0ll97
5E0E
2107
2197
0B97
5E0E
A991
8E:e9
5E09
5E08
2198
2IC9
A9C1
2IC8
A9C1
2iC7
I800
93!6
9!08
rrn
Lt
lD
CP
JP
LD
LD
CP
JP
LD
LD
CP
JP
LD
LD
CP
JP
INC
CP
JP
JP
R7,_#FF!Fi
119 ,R7i
R7,R9-i
NE,RAMFAIL;
R7,_1iAAAAi
R9 ,R7i
R7,R9-;
NE,RAMFULi
R7 1 #5555i
R9 ,R7i
R7 ,119-;
Nl,RAMFAILi
R7J.#0000;
R9 ,R7i
R7,R9-;
NE ,RAMF! IL;
R9,2i
R9 ,Rll i
GE,RDONEi
RLOOPi
LD
LD
INC
LD
INC
LD
JR
116,
R12-,
R12,_
1112 •
R12,_
R12 ,
RDCNEi
R9~i
PUSH
RET;
R15--,R6i
0252
UAA
0252
e555
0252
0000
0252
0260
0216
RAMHIL:
RDONE:
R9i
2;
119;
2;
R7i
1.0.1
Pa11:e 8
% LOAD, 1 's
%READ 1'5.
% IF NOT 1'S, JUMP TO RAMFAIL.
l LOAD ALTERNATING 1'5 & 0'S.
%READ ALTERNATING 1'5 & 0'S.
i II NOT 1'S & 0'5, JUMP TO RAMFAIL.
%LOAD ALTERNATING 0'S $ 1'S.
%READ AL'IERNATING fit'S &1'S,
% II NOT 0'S & 1'S, JUMP TO RAMiAIL.
l LOAD ALL Ill'S,
% READ ALL r/J'S.
~ IF NO~ ALL 0'S, JUMP TO RAMFAIL.
l INCRE~INT POINTER.
% CMPARE POINTER TO FINISH ADDR.
i II )~ JUMP TO RDONE.
% LOOP
DA'IA
% LOAD CONTENT OI AtDRESS INTO REG 8
% START ADDRESS WHERE .RIIOR WAS
1 EAD
%
% SAVI ERROR DATA
1
% SAVE EXPECTED DATA
% HALT LOOP
% RECLAIM RETURN ADDRESS
% RETURN
EJECTi
\J'
w
Z'IESTER
MACR08000 AmZB000 Assembler
£1264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
~
0276
Page 9
INCLUDE 'B:CPUTST3.ZSC';
!U:tU!tU:t:U:t:t.U:tU:U,:t1%%%%%%%%%%%%U%%U%%%%%%%%%%%%%%t%%%%%%%%%%U%%%%
%
% CPUTST
1
% PURPOSE
%
1
%
%
1
%
%
% ROUTINES
% CALLED
%
1 REGISERS
% USED
~264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0264
0266
0268
026A
025C
. 026I
0272
1.0.1
%
~
%
'
CP U T ES T
THIS SUBROUTINi CHECKS ALL Z8000 INSTRUCTIONS
II AN IRROR IS DETECTED iHEN CPUILIG FLAG IS SiT
TO THE ADDRESS WHICH INDICATE INSTRUCTiON FAIL
FOI.LOWING INS·rRUCTIONS ARE NOT CHECKED:
IRIT,DI ,EI ,HALT,LDCTL,LDCTLB,LI:PS ,SC
I/0 INS'fRUCTIONS
MULTI MICRO INSTRUCTIONS
%
%
%
:t
%
%
:t
NONE
%
%
R1-R14
%
%
:t
EXEC UTI ON
TIME
%
1 PROGRAMMER
%
%
%
%
1
MICRO SECONDS
MEMORY
USED
WORDS
.
MINH NGUYEN
% .DATE
%
%
%
%
%
%
%
%
:t
:U%%%%%%%%%%%%%%%%%%lU~UUlU:t:t%UU11U11:l.:tUU1~U~UU.11U:UU.~U%%
:t
%
%
1
%
%
1
0030
IFFF
5555
AAAA
0DF8
HH0 AA55
1541 4243 4445
4647 4849 4A4E
10000:
THIS SUBROUTINE CHECKS ALL Z8000 INSTUCTIONS '
IF AN ERROR IS DETECTED THEN CPUFLFG ILAG IS SET
TO THE ADIFESS WHICH INDICATE INSTRUCiiON FAIL
FOLLOWING INSTRUCTIONS ARE NOT CHECKED:
IRET,DI,EI,HALT,LDCTL,LDCTLB,LDPS,SC
1/0 INSiRUCTIONS
MULTI MICRO INSTRUCTION
WORD:
WORD:
15555: WORD:
1AAAA: WORD:
ACPUERR: WORD:
U0F0A: LOtiG:
TRTAEL: STRING:
IHII:
#0000i
#lFfFi
#5555;
NAAAA;
~CPUERR;
1 CPU ERROR ADDRESS
NF0F0AA55i
'ABCDEIGHIJKLMNOP',#00,#00,#00,#00,#00i
\Jl
+;-
Z'IESTER
027E
0284
0268
12128E
0288
0288
028C
0290
0292
0298
02S8
0298
029E
02A0
02A4
e2u
02B0
02B4
02B8
02BE
02BE
02l!E
02C0
02C4
0:2CA
02D0
02D4
02t8
02DE
02DE
02lll
02E2
02E4
0218
02EE
02F2
02F8
02fA
02H
0304
0308
030E
030E
030E
0310
MACR08000 AmZ8000
Asse~bler
1.0.1
PaP,e
10
4C4ll 4E4J 5:;,021
0000 00a0
2101 0DF8
6102 026C
8321
E602 5F00 flDFB
1404
8C48
0304
1:602
4C05
4C08
4C04
1602
8ll58
0B05
E602
4£05
4D08
4D04
1602
2106
ACD6
01!06
1602
0B05
I602
AD 56
0])06
I602
0B05
E602
HFI HFr
CPUTEST:
LDL
CLRB
RR4 ,#FIFU'FlFi
RH4i
Stl!
R4,#00Fr;
IF NZ THEN CALL CPUERRi
LDB
TlCPUT (5) ,#FH
CLRB
T1CPU'J(5)i
'11CPUT(5);
USTB
IF NZ THIN CALL CPUERRi
:t CLEAR
55AA
00AA
5!00 0DF8
0055
5100 0DJ8
0055
5H'I0 0DI8
00AA
5F00 0DFB
A0E7
0A07 5555
% SET RETURN ADDR. U' ERROR
' SET ADDR. 2.· TIME IN OTHER WAY
% ERROR ADDR. PERMAMENT IN R2
i LD ADDRESS
% CLEAR BYTE
00H
5!00 0DFB
F817 nn
1817
F817
5100 0DFB
0000
5100 0DF8
1612 AAAA
F812
!812
5F00 0DF8
R1, ~CPUERR;
R2,ACPUERR;
Rl,R2i
IF NZ THEN CALL CPUERR;
LD
LD
SUE
:t CLRB
% CLEAR BYTi MEMORY
CLR
CP
R5i
R5,0i
IF NZ THEN CALL CPUERRi
LD
TlCPUT,#AAAAi
CLR
TlCPUTi
l'EST
TlCPUT;
U NZ 'lHIN CALL CPUERRi
% EXCHANGE
LD
Ell!
CP
IF NZ
CP
IF NZ
EX
CP
II NZ
CP
IF NZ
R6,#55AA;
RH6,RL5;
R6,#00AAi
'JHEN CALL CPUERRi
R5,#0055;
THlN CALL CPUERRi
R6,R5i
R6,#0055;
THEN CALL CPUERRi
R5,#00AA;
THEN CALL CPUERRi
:t CLR REGISTER,
% CLR MEMORY
% EXB DEST
% U:B SRC
% EX SRC
:t EX DEST
% LOAD TO REGISTER
LDB
RH7,RL6i
CPE
RH7,#5~i
\.Jt
\.Jt
ZTES 'lEfi
0314
031A
0311
0320
£1326
032C
0330
0336
0336
0336
0336
033A
033C
e342
0348
034C
0352
0358
035C
0360
0366
036C
036C
036C
036C
il370
0374
037A
e380
121382
0368
121388
0388
0388
ll38C
038E
0394
121394
121394
121396
039A
03!0
03U
03A0
03A0
MACR08000 AmZ€000 Assembler
1602
6108
!980
1602
1408
5008
1602
5l00 0DJ8
0266
If NZ THEN CALL CPUERRi
LD
R8,XHFFi
INC
RB,U
If NZ THEN CALL CPUERRi
LDL
RRB,IIF0F0AA55i
CPL
RR8,II0F0Ai
IF NZ THEN CALL CPUERR;
51'00 0Dl8
I0U AA55
02€E
5f00 0Df8
1.0.1
Page 11'
% LDB REGISTER.
% LD REG I STEll :
% LDL REGISTER
t LOAD TO MEMORY
2101
2U7
4C1211
E602
3318
4D01
E602
5L08
540C
120C
1602
% RH7
1812
F812
510121
0002
1814
5F00
IE12
F812
F010
511210
5555
121llf8
1010
0DF8
AA55
121DF8
= #55, RR8 = #I0F0AA55
LD
R1~-T1CPUTi
LDB
fil ,RB7i
CPB
T1CPU'I,#55i
IF NZ THIN CALL CPUERRi
Rl- (2) ,R8i
LD
CP
T1CPUT(2),#F0F121i
IF NZ THEN CALL CPUERRi
LDL
T1CPU'I,RR8i
LDL
RR12,T1CPOTi
SUBL
RR12,#F0F0AA55i
IF NZ THEN CALL CPUERRi
511210 0lll8
% LOAD IHMiDIATE TO MEMORY
% Rl = ~TlCPUT
Rl-,0;
LDB
TESTB
TlCPUT i
IF NZ THEN CALL CPUERRi
LD
T19PUT ,UIFfi
INC
R1 ,li
If NZ THEN CALL CPUERRi
210A 0DF8
8.BA2
161212 5100 0DI8
:t LOAD ADDRESS
% R2 = ~CPUERR
R10,-CPUERRi
LD
CP
R2 ,JIUH
IF NZ THEN CALL CPUERRi
121C15
4C1214
1602
4D05
29Ul
1602
~000
FE12
511210 0Dl8
1812 lff1'
BDAF
1213121! 121121"1
F.602 5100 0DF8
21310
UDB MEMORY
:t LD MEMORY
% LDL MEMORY
% LDB
IMMEDIAT~
% LD IMMEDIATE
% LDA
% LOAD CONSTANT
LDK
R10 ,ltf; ·'
li.10, 15i •
SUE
IF NZ THEN CALL CPUEJIRi
:t LDI
% LOAD RELATIVE TO REGISTER
l T1CPUT = #IIFIAA55
DEC
Rl-,11
\Jl
0\
ZTESi'ER
03A2
03A6
03AA
031!0
031!4
031!8
03BA
03C0
03C4
03CA
03D0
03D0
03D0
03D0
03D4
03DA
~3E0
0314
03EA
0310
03F4
03IA
0400
0406
040C
£40C
040C
0410
0412
0418
0418
£418
04H
0420
0426
0428
042E
0434
043!
043A
043A
043C
0442
0446
044C
MACR08000 AmZSr-00 Assembler
3006
0A06
i602
310B
610C
SBCB
I602
350C
100C
E602
3206
4C01
1602
330D
4101
E602
3?0C
4.D01
1602
4D01
!602
J46C
FHF
5F00 0D1'8
f45E
F812
51'00 0Dl8
F44E
HFF AA55
5f00
H46
ISlA
5i00
1436
IEU
5100
F426
}81A
5F00
I81C
5100
~DFB
HFI
0DJ8
AA55
0Dl8
IFH
0DF8
AA55
0LI8
LDRB
RH6,T1CPUTi
CPB
RH6,#FFI
U NZ IHtN CALL CPUERRi
LDR
R11,T1CPtJTi
LD
R12,71CPUTi
CP
R11 0 Jl12i
IF NZ THEN CALL CPUERR;
LDRL
RR12, T1CPU'Ii
CPL
JiR12 ,NFilFAA55i
IF NZ THEN CALL CPUERRi
% LOAD RELATIVE TO MEMORY
% RH6 = NFF, R13 = NAA55 0 RR12
LDRB
T2CPUT,RH6i
CPB
T2CPUT,#FF;
IF NZ THEN CALL CPtJERRi
LDR
T2CPUT,R13i
CP
T2CPUT,#AA55i
IF NZ THEN CALL CPUERRi
LDRL
T2CPtJT,RR12i
CP
T2CPUT,#FFFFi
If NZ THEN CALL CPtJERRi
CP
. T2CPUT(2),NAA55i
IF NZ THEN CALL CPtJERRi
3403 0918
81!32
F602 5J00 0DF8
% LOAD ADDRESS RELATIVE
LDR
R3,~CPUERRi
CP
R2,R3i
IF NZ THEN CALL CPUERRi
5C01
E:£64
E602
A970
1602
1008
E602
% LOAD MULTIPLE TO REGISTER
LDM
R6,I0000 0 4i
lEST
R6i
IF NZ THEN CALL CPUERRi
INC
R7,1i
IF NZ THtN CALL CPUERRi
CPL
RR8,#5555!AAAi
IF NZ THEN CALL CPUERRI
U70
5C09
4D04
E602
6900
0603 0264
5100 0DFB
5100 0DJ8
5555 AA!A
5100 0DJ8
1.0.1
Pape 12
% L1JRB REGISTER
% LDR REGISTER
% LDRL liEGISiER
= #JJFIAA55
% LDRB MEMORY
% LDR MEMORY
% LDRL MEMORY !.WORD
,
% LDRL MEMORY 2.WORD
~
LDR ADDRESS
% LDM REGISTER. 1. WORD
% LDM REGISTER: 2. WORD
I LDM REGISTER 3. 4.
~ORD
% LOAD MULTIPLE TO MtMORY
0603 1812
1812
5I00 0DFB
F814
DEC
R7,1i.
lDM
T1CPUT,R6 0 4i
TEST
TlCPUTi
IF NZ THEN CALL CPUERRi
INC
TlCPtJT(2),1i
~
LDM MEMORY 1. WORD
\Jl
-...J
""
ZTESTER
0450
0456
045A
0460
0460
0460
0460
0464
0468
~46A
0461
0472
0478
047A
0480
0484
0486
046C
0490
0496
049A
£4A0
04A2
04A6
04AC
04AE
04:80
04:82
04:88
04BA
04C0
E4C6
04CC
04CG
04CC
04CC
04CE
04D2
04D8
04DE
04E2
04EE
04EA
04lC
04E.E
MACR08000 AmZ8000 Assembler
E602 5100 0DI8
50r/J8 F816
E602 5100 0DF8
IF NZ THEN CALL CPUERRi
CPL
RRS,T1CPtJT(4)i
If NZ THiN CALL CPUERRi
1.0.1
Page 13
% LDM MEMORY 2'. WORD
% LDM MEMORY 3. AND 4. WORD
% LOAD AND DECREMENT
2104
2105
944C
2HJ6
JlJJ59
EC02
8:851
E602
210A
8E4!
I602
4D04
E602
01)06
1602
9448
BA49
I402
!940
A£,50
9084
E602
8D64
E602
4c01
E602
F81C
!814
0£02
0648
5100 0DI8
5100 0D'f8
F81A
5100 0DI8
F81C
5100 0DF8
0001
5F00 0DF8
0658
5100 0Df8
5I00 0DF8
5!00 0DF8
1e12 nn
5100 0DF8
% T1CPUT = #0000IIIF5555AAAA, R1 = -T1CPUT
LD
R4,-T2CPUT(2)i .
R5,~T1CPUT(2)i
LD
LDL
RR12,RP.4i
LD
R6,_2;
LDt
R4 ,R5" ,R6i
IF OV THEN CALL CPUEP.Ri
% LDD OVI.RFLOW
CP
Rl,R5i
IF NZ THlN CALL CPUERRi
% LDD REGISTER R5
RHJ, -T2CPUT i
LD
CP
R10,R4i
IF NZ THEN CALL CPUERRi
% LDD REGISTER, l!4
TEST
T2CPUT (2);
IF NZ THEN CALL CPUERRi
): LDD MEMORY
CP
R6,1i
IF NZ THEN CALL CPUERRi
% LDD REGISTER R6
LDL
RR€,RR4i
R5-,R4~,R6i
LDDB
IF NOV THEN CALL CPUERRi
% LDDB NO OVERlLOW
INC
R4,1i
INC
R5,H
CPL
RR4,RR8i
IF NZ THEN CALL CPUERRi
' LDDB REGISTER R4,R5
TEST
R6i
IF NZ THEN CALL CPUERRi
i LDDB REGISTER R6
CPb
T1CPUT ,llfr;
IF NZ THEN CALL CPUERRi
% LDDB MEMORY
% LOAD, tECREMENT AND REPEAT
94C4
2106
4D05
4105
BE59
E402
A943
!953
90C4
l6r/J2
l RR12
0002
FE12 !Ali
1814 0055
0640
51'00 0DF8
5100 0DF8
= ~T2CPUT(2) AND -T1CPUT(2), T2CPUT = #AAFfAA55
LDL
RR4,RR12i
LD
R6,2i
LD
T1CPUT,#AAl'Fi
T1CPUT(2),#0055i
LD
R4-,R5~,R6i
LDDR
IF NOV THEN CALL CPUERRi
l LEDR NO OVERFLOW
INC
R4 ,4i
INC
R5,4i
CPL
RR4,RH12i
IF NZ THEN CALL CPUERR;
% LDDR DICRIMENT R4,R5
\Jl
CXl
...
ZTISTER
041'4
0416
04lC
0502
0508
0501
0514
0518
051E
0524
0528
052E
05:30
05:36
05:38
05:3A
05:3C
0542
0546
0541
0554
055A
055A
055A
055A
.055C
055E
0562
0568
056C
0572
0574
0576
0578
0571
0584
05SA
058C
0590
0596
0598
059E
05!0
e·5A2
05A4
MACR08000 ArnZ8000 Asserr,bler
6D64
1602
4001
E602
4I01
E602
2106
4t05
4D05
EA49
I402
8D64
E602
A942
A952
90C4
E602
4D01
1602
4C01
E602
0D48
A961
BB51
IC02
0B06
1602
AB41
AB51
90C4
1602
4D01
E602
0C58
BA41
E402
8164
E602
AE40
AB50
90C4
1602
5100
ISlA
5!00
I81C
5F00
0003
lElA
l81C
0650
5100
0DI8
AAII
0DF8
0055
0Di'8
0245
BACE
0Dl8
5100 0DF8
'
5100
F812
5100
f814
5100
0DF8
0246
0Jll'8
8A6A
0DF8
0648
5!00 ens
0001
5F00 0DF8
51'00 0DI'8
FBlC SA55
5100 0DFB
0658
5F00 0DF8
5F00 0Dl'8
5!00 0H8
TEST
R6i
IF NZ THiN CALL CPUifRi
CP
T2CPUT ,#!AFJ;
IF NZ THEN CALL CPUERRi
CP
T2CPUT(2),#0055i
II NZ THEN CALL CPUEF.Ri
LD
R6,3i
LD
T2CPUT,#0246i
LD
T2CPUT(2),#8ACE;
R5~ ,R4- ,R6;
LDDRE
IF NOV THEN CALL CPUIRRI
TEST
R6i
II ·Nz THEN CALL CPUERRi
INC
R4,3;
INC
R5,:31
CPL
RR4,RR12i
IF NZ iHEN CALL CPUERRi
CP
T1CPUT ,1Hl246i
IF NZ TH1N CALL CPUERRi
CPE
TlCPUT (2) ,#8Ai
IF NZ THEN CALL CPUERRI
% LOAD AND INCREMlNT
'l T2CPUT = #02468ACE
R4~i
CLR
INC
R6 ~2i ..
LDI
B4 ,R5 ,R6i
IF OV THEN CALL CPUERR;
CP
R6,U
IF NZ THEN CALL CPUERRi
R4,2i
ti:C
DEC
R5,2i
CPL
RR4,RR12i
IF NZ THiN CALL CPUERRi
CP
T2CPUT(2),#8A55i
If NZ THEN CALL CPUERRi
R5 •. ;
CLRB
R5r ,R4- ,R6;
LDIB
If NOV THEN CALL CPUERR;
UST
R6i
IF NZ THEN CALL CPUERRi
DEC
R4,1i
IEC
R5,1i
CPL
RR4,RR12;
IF NZ THiN CALL CPUERRi
1.0.1
Par,e 14
'l LDDR R61
'- LDDR MEMORY l.WORD
% LDDR MEMORY 2.WORD
l LtDRB NO OVERFLOW
I
l LDDRB R6
% LDDRE
DECREM~NT
R4,R5
% LDDRB MEMORY. 2. :3. BYTE
l LDDRB MEMORY 1.BTTI
% LDI OVIR1 LOW
~
LDI R6 DECREMENT
% LDI INCREMENT R4,R5
:t LDI MEMORY
~
LDIB NO OVERFLOW
% LDIB R6 DECREMENT
% LDIB INCREMENT R4,n5i
'Vt
·-.o
ZTES 'IER
MACR08000 AmZE000
.
05AA
051!0
0516
051!6
051!5
051!6
051!8
05BC
05C0
05C4
£15C8
05CE
05Df21
05))2
f215D4
05DA
05IC
f215E2
e5E6
05EC
121512
05F6
05FA
051'E
0604
0606
060C
060E
0610
061.2
f618
f2161C
0622
06.22
121622
06.22
0624
0626
062A
0630
0632
0634
063A
063C
0642
4C01 I814 SABA
E602 5Hl0 0DF8
9484
2106
4D08
4D08
BB51
E402
AE43
AB53
9084
1602
8D64
1!602
540C
100C
1602
5D08
211216
BA41
E402
8D64
1602
AB43
AB53
9064
1602
500C
1602
0002
ISlA
F81C
0640
5F00 0DF8
5F0f21 0Dl'8
5100
1'81A
0246
5F00
f812
0004
0650
5F00
0Dl'8
8A55
0DF8
0DF8
5100 01JI8
5I00 0DF8
1812
5F00 0DF'8
A116
~767
0li07
E602
AB61
8:616
E602
9564
1004
E602
0246
5100 0DF8
5f00 0DFB
0246 8A55
5f00 0DF8
Asse~bler
CPB
T1CPUT(2),#8A;
IF NZ THEN CALL CPUEHR;
1. 0.1
Page 15
:t LDIB MEMORY
% LOAV ANV INCRlMENT AND RIPlAT
I RRS = -T2CPUT(2) AND -T1CPUT(2), RRS. = #0246BA55
LVL
RR4 ,RREi
LD
R6,2i
CLR
T2CPUT;
CLR
T2CPUT (2);
R4-,R5-,R6i
LDIR
IF NOV THEN CALL CPUERRi
1 LCIR NO OVERFLOW
nc
R4,4i
DEC
R5,4i
CPL
RR4,RRB;
If NZ THEN CALL CPUERRi
% LDIR INCREMENT R4,R5
Tl:ST
R6i
IF NZ THEN CALL CFUERRi
% LDIR DECREMENT R6
LDL
RR12, T2CPUT;
CPL
RR12,#02468A55;
IF NZ THEN CALL CPUERRi
% LDIR MEMORY
LDL
T1CPUT,RRS;
R5J.4; _
LD
LD IR.B · Ji5 ,R4 ,R6i
IF NOV THEN CALL CPUERR;
% LDIRB NO OVERFLOW
TEST
R6i
IF NZ THEN CALL CPUERRi
% LDIRB DECREMENT R6i
DEC
R4,4i
II:C
R5,4;
CPL
RR4,RR8i
IF NZ THEN CALL CPUERR;
% LDIRB INCREMENT R4,R5
CPL
RR12,T1CPUT;
II NZ THlN CALL CPUERRi
% LDIR MEMORY
% POP STACK MANIPULATION
% R1 = -TlCPUT
LD
R6,Rli
R7,R6-;
POP
CP
R7,#0245i
IF NZ THEN CALL CPUERRi
DEC
R6,2i
CP
R6,Rli
IF NZ THEN CAL~ CPUERRi
POFL
RR4,R6 ;
CPL
RR4,#02468A55i
IF NZ THEN CALL CPUEJiRi
% POP REGISTER
% POP INCiitMENT
% POPL REGISTER
0\
0
ZUSTEil
0648
064A
064C
0652
0652
0652
0658
065A
065C
065i
0664
E668
0661:
0670
0672
0674
0676
067C
067I
0684
068A
068A
068A
068A
068A
0690
0696
0698
069A
06A0
06A6
06A6
06A6
06A8
06AE
06B4
06BA
06C0
06C6
06CC
06CE
06D4
06llA
06DE
£6E4
MACR08000 AmZ8000 Assembler
AB63
8B16
E602 5100 0DF8
1404
/1961
9364
8B16
I602
0D61
E602
!116
A963
9164
8b16
1!:602
146C
l00C
E602
FFAA 5500
5100 0DF6
FUA
5F00 0DF8
5100 0DIB
HAA 5500
5F00 0DFB
DEC
R6,4i
CP
ll6,R1i
IF NZ THEN CALL CPUERRi
% PUSH
LDL
RR4,#lFAA5500i
INC
R6_.2;
PUSH
Ji6 ,R4i
CP
R6,Rli
IF NZ TH~N CALL CPUEJiRi
R6-,#HAAi
CP
IF NZ THEN CALL CPUERRi
LD
R6,Rli
INC
R6,4i
PUSBL
R6 ,RHi
CP
R6,R1i
IF NZ THEN CALL CPUERRi
RR12,R6~i
LDL
CPL
Rli12,#1FAA5500i
IF NZ THEN CALL CPUERRi
% ARITHMETIC INTRUCTIONS
140C
140A
81DB
B5CA
100!
E602
96CA
IC02
IF02
ED02
H02
100A
E602
EltA
EC02
E702
0Il0A
I602
Be-55
0000 IFFF
4320 0001
4321 0000
5F00 0DF8
5100
5F00
5F00
5!00
4321
5F00
0:CF8
fiHJFB
0DJ'8
0LF8
IFH
0DF8
5100 0DFB
5100 0DF8
4320
5100 0D18
1.0.1
Paf;e 16
% POPL INCREMENT
% PUSH DECREMENt
' PUSH MEMOilY '
% PUSHL DECREMENT
% PUSHL MEMORY;
****************
% ADD WITH CARRY
LDL
RR12,#2J000FFFFi
LDL
RR10,#43200001i
ADD
Rll ,R13i
ADC
R10,R12i
CPL
RR10,#43210000i
IF NZ tHEN CALL CPUERRi
% At:CITION
ADDL
IF OV
IF CT
IF MI
IF ZJi
CPL
IF NZ
ADr
IF OV
IF NC
CP
IF NZ
ADDB
RR10,RR12i
THEN CALL CPUERRi
THEN CALL CPUEilRi
THEN CALL CPUEERi
THEN CALL CPUERRi
llR10 ,#4321FHFi
THEN CALL CPUERRi
R10,1l13i
THEN CALL CPUERRi
THEN CALL CPUERR;
R10 ,#4320i
THEN CALL CPUERlli
RH5,Rfl5i
' ADC,ADD
% CHECK STATUS iLAGGS
% CHECK STAtUS' ILAGGS
~ CH!CK STATUS' lLAGGS
%
:l. ADDL
% C§ECK STATUS' 1LAGGS
:l
% ADD
~
55+!55
....0\
ZTESTER
06E6
06EC
06F2
06F4
06FA
06IA
06FA
e6FE
0700
0702
0706
070C
070C
070C
0701
0712
0718
0718
0718
071C
07U
0724
0'72!
072C
0730
0732
0734
0736
073A
073C
0742
0748
074E
0754
0754
0754
0758
075A
0751
0764
0768
076!
0770
0776
077A
MACR08000 AmZ8000 Assembler
I402 5100 0Dl8
E502 5I00 0D1'8
eu:5
E602 5I~0 0DFB
2105 1539
80D5
:S050
I!IA05 5454
E61112 5F00 0DF6
AA53
0A05 5050
1602 51'00 0Di8
2U5
91l5C
100C
E602
8D88
2109
BDAS
8DE8
etta
210C
9AC8
1008
1602
1E0A
1602
211.04
1!140
01l04
1602
2105
E14A
1004
E602
2106
E147
ADJU~T BYTE
LD
R5 ,111539i
ADI:B
RH5,RL5i
DAli
RH5i
CPB
RH5,N54i
IF NZ THEN CALL CPUERRi
000! 0333
5f00 0Df8
8000
000A
0000
0Dl8
ecce
0Df8
AB34
0034
5!00 0DF8
8F34
HH EI34
5F00 0Dle
05FE
%
Page 17
.
% CHECK STATUS FLAGGS
% AIIDB
% DECIMAL
% DECREMENT
DECB
RH5, 4i
CFB
RE.5,N50i
Ii NZ THEN CALL CPUERRi
% DIVIDE
0050
0008
5F00
eecc
5!00
IF NOV iHEN CALL CPUERii
IF PL THEN CALL CPUERR;
CPB
RH5,RL4i
IF NZ TEEN CALL CPUERRi
1.0.1
LD
R5,#0050i
DIY
RR12,R5i
CPL
RR12,N000F0333i
li NZ THEN CALL CPUERRi
CLR
RBI
Lt
R9 ,N8000i
CLR
R10i
CLR
RlH
CLR
R13i
LD
R12,11000Ai
DIVL
RQ8,RR12i
CPL
RR8,#00080000i
IF NZ THEN CALL CPUERRi
CPL
RRH!I ,N0CCCeCGC i
IF NZ THlN CALL CPUE~Ri
% 15
+
42 DECIMAL
~
57
:t DAB
't DICB
% 0000FI'H/5~ .
% 000F REMAIDER 0333 RESULT
% DIY
% DIVL REMAINDER
% DIVL R1SULi
:t EXTEND SIGN
LD
R4,NAB34i
II'IS.b
R4i
CP
R4 ,1100341
IF NZ THEN CAlL ePUERRi·
LD
R5,#8F34i
EXTS
RRH
ePL
RR4,11FIFF8F34i
IF NZ THEN CALL CPUERRi
R6 ,110s:n;
LD
1X'l'SL
RQ41
% EXTSB
% EXTS
0'\
N
ZTESTER
077C
077E
0784
0788
078!
078E
078!
0790
0796
0796
0796
079A
079E
07!4
07AA
071!0
07:85
071!C
071!E
07C4
07CA
07D0
07£6
07DC
07DC
07lC
07DE
07E2
0?18
07EA
07EE
07F4
07F4
07F4
071!
0800
0802
0604
080A
0810
0810
0810
0810
0814
0818
MACR08000 AmZ8000 Asserebler
9C48
E602 5!00 0DF8
0E06 05IE
E602 5I00 0DF8
TESTL
11R4i
IF NZ THEN CALL CPUERRi
CP
It6,#05:FEi
IF NZ THEN CALL CPUERRi
AEE1
!602 5F00 0LF'8
% INCREMIN'I
INCB
RL6,2i
IF NZ THEN CALL CPUERlli
2107
1906
E.E02
Il02
1006
E602
140A
9tl68
E502
1008
E602
000A
0064
5F00
5100
0000
5F00
HH
~
0DF8
0tl8
0:3!8
0DF8
Hi'6
5!00 0DF8
nn nn
51'00 0Dl8
HIF I8F0
1602 5!00 0Dl8
H~0A
8[72
0ll07
E602
8C72
0A07
E602
1404
1406
8:375
1!764
121214
E602
MULTIPLY
LD
I"UlT
IF ZR
II MI
CPl
IF NZ
LDl
MULTL
IF PL
CPL
IF NZ
CPL
II NZ
:t NEGATE
FC18
5Hl0 0DF8
0404
5F00 0DF8
0038 400"'
000A !000
002L 5000
5Hl0 0DF'8
6104 0268
4704 026A
!602 5F00 0DF8
R7,#000Ai
It116,#0064i
tHEN CALL CPUERRi
THEN CALL CPUERRi
Rli6,1t00000:3E8i
THEN CALL CPUERRi
RR10 ,#1iFUU'F6i
RQ8,RR6i
THEN CALL CPUERRi
RRS,H'l'FFFF'FH
THEN CALL CPUE~Ri
RR10,#HFID8F0i
THEN CALL CPUERRi
NEG
R7i
CF
R7,#1C18i
IF NZ TH~N CALL CPUERRi
NEGE
RH7i
CPE
RH7,#04i
IF NZ THEN CALL CPUERRi
% SUll1RACT WITH CARRY
LDL
RR4,#00.384000j
LDL
RR6,1i000AHJ00i
SUB
R5,R7i
SBC
R4,R6i
SUBL
RR4,#002])5000i
IF NZ THIN CALL CPUERRi
1.0.1
~
l'age 18
EXTSL 1,2 WORD
% EITSL :3. WOIW
% INCB
~
%
MULT STATUS FlAGG
..
:t. MULT
~
MULTL STATUS. FLAGG
% MULT 1,2 WORl>
% MULT :3,4 WORD
:t NEG
% SUBC,SUB,SUBL
% LOGICAL INSTRUC'IION*************************
% AN:t
LD
R4,I5555i
AND
R4,IAAAAi
IF NZ THIN CALL CPU~RRi
% AND
0'\
w
""
ZTESTEJl
~81E
0620
0824
0826
082C
11:8.2C
082C
082C
082E
08:34
06:36
08:38
11:8:3E
08:3E
08:3E
11:84.2
0846
084A
0850
0854
085!
ll85!
085!
085C
085E
0864
0864
0864
0866
0668
086E
086E
086E
086E
0870
0876
067!
087E
0884
0686
088C
086C
088C
0E8C
0690
MACR08000 AmZ8000 Assembler
C4FF
4604 0266
A840
E602 5!00 0DF8
RH4, #FF;
LDB
ANIB
RH4 ,nrn;
INCB
RH4 ,li
IF NZ THEN CALL CPUERRi
8180
E62J.2 5F00 0DF8
8C40
A640
E60.2 5100 0DF8
% COMPUMUT
:t. liS = #FFFF
COM
R8i
IF NZ THEN CALL CPUERRi
COMB
RB4i
I NCB
RH4, 1i
If NZ THEN CALL CPUtRRi
6104
4504
0ll04
E60.2
4406
!602
0268
026A
JHF
5F00 0DF8
0264
5f00 0DF8
9266
9C68
E602 5F00 0DF8
Af66
AB60
E602 5100 0DF8
% OR
:t TEST
Lli
R4,X5555i
OR
R4,IAAAAi
R4,NFFI'ii
CP
IF HE THEN CALL CPU!RRi
ORB
RB6,l0000;
IF NZ THiN CALL CPUERRi
SUBL
RR6,RR6i
TESTL
RR6i
IF NZ THEN CALL CPUERRi
% TEST CONDITION CODE
TCC
EQ,R6i
DEC
R6,1i
IF NZ THlN CALL CPUERRi
1.0.1
Page 19
:l ANDB
% COM
% COMB
t OR
:l TESTL
% TCC
% EXCLUSIVE OR
8844
1602
6104
4904
1502
!940
E60.2
5J00 0tF8
026A
0268
5J00 0H8
5H!0 0DF8
% RH4 = #H
XORB
RH4,RHH
IF NZ iHEN CALL CPUERRi
LD
R4,XAAAAi
XOR
li4,X5555;
IF PL THlN CALL CPUERRi
INC
R4 ,li
IF NZ THEN CALL CPUERRi
:t XORB
% lOR
~
XOR
% ROTATl AND SHIFi*************************
2104 12:34
BEC4
I ROTATE LEFT DIGIT
Lli
RLDB
R4,ff12:34i
RH4,RL4i
0'\
+:"
Z'liSTER
MACR08000 AmZ8000 Assembler
0692
0.B04 1342
0896
!602 5F00 0tF8
089C
089C
089C
BCC4
0t9E
0.B04 1234
0tA2
!602 5100 0rF8
08A8
08AS
06A8
1!342
08AA
1!342
08AC
E702 5100 0DF8
08B2
0ll04 2341
08.B6
E602 5F00 ·0DF8
08.BC , .B242
06llE
IF02 5F00 0Dr8
08C4
0A04 sese
08CS
E602 5F00 0DFB
08CI
08CE
08CE
08CI
.B34A
08D0
B34A
08D2
.B348
08D4
E702 5F00 0DF8
08DA
0.B04 8828
08DE
E602 5100 0DF8
0814
8DS1
08E6
.B24A
08E8
EF02 5F01il 0DF8
0A04 2323
08EE
0812
E602 5HJ0 0DF8
08F8
08F8
08F8
08F8
.B346
0EllA
1!346
08FC
E71il2 5i00 0DF8
0902
0E04 8232
0906
E602 5F00 0DI8
1!246
090C
0~0E
E702 5!00 0DF8
0914
0A04 A0A0
0918
E602 5Fe'0 0DF8
091E
CP
R4,111342i
IF NE THiN CALL CPUERRi
% RLD:S
% ROTATE RIGHT DIGIT
RRLB
RH4,RL4i
CP
F.4,#12.34i
IF NE THEN CALL CPUERRi
% RRDB
~
ROTATE UlT
RL
RL
If NC
CP
IF NE
RL.B
IF CY
CPB
IF NE
R4,2i
R4,2i
THEN CALL CPUERRi
R4 ,112341;
THEN CALL CPUERRi
IIH4,2i
THEN CALL CPUERRi
RH4,118Ci
TtiEN CALL CPUERRi
% ROTATE LIFT THROUGH CARRY
% R4 = #EC41
RlC
R4 ,2i
RLC
R4,2i
RLC
R4,1i
IF NC THEN CALL CPUERRi
CP
R4,#882Bi
IF NE THEN CALL CPUERRi
SITFLG cy;
RLC.B
RH4,2i
IF CY THEN CALL CPUERRi
CPll
RH4,1123i
IF NE THEN CALL CPUERRi
% ROTATE RIGHT
% Ii4 = #2328
RR
R4,2i
RR
R4,2i
IF NC THEN CALL CPUE!iRi
CP
R4,#8232i
II NE THEN CALL CPUERRi
RH4·, <:i
RR.B
IF NC THEN CALL CPUERRi
CPE
RH4 ,#A0i
IF NE THEN CALL CPUERRi
1.0.1
Pap:e 20
1 RL CARRY
% RL
% RL.B NO CARRY'
1RLB
% RLC NO CARRY
1 RLC
l RLCB CARRY
% RLC.B
l RR NO CARRY
l RR
~
RRB NO CARRY
% RR.E
'· 0\
. \.]t
ZTESTER
MACR08~0~
0A4A
lilA 50
0A52
0A56
0A5C
0A5C
0A5C
0A5C
0A60
0A64
0A6A
0A6E
0A72
0A78
0A78
0A78
1602 5100 0DF8
A340
0E04 A854
E602 5F00 0DF8
0A7~
!444
0A7A
0A7E
0A84
0A88
0A8E
0!94
0A94
0A94
0A94
0A98
0A9C
0AA2
0AA6
0AAA
0AB0
0Al30
0AB0
0AE0
0A:B2
0AB8
0ABA
0AC0
0AC4
0ACA
0ACI
0AD4
0AD4
0AD4
2205
0#.04
E602
2305
01l04
E602
0A04
E602
6501
41:01
E602.
2405
0A04
E602
2505
0£04
E602
8C56
II:IIJ2
A850
E602
4£06
E502
6900
I602
AmZ8000 Assembler
IF NE THEN CALL CPUIERi
RES
R4,11Ji
CP
R4,11A854i
IF NE THEN CALL CPUERRi
1.0.1
Page 23
l RISB STATIC MIMORY
I RFS STATIC REGISTER
0400
2828
5i00 0Dl8
0400
2854
5F00 0DJ8
% RESET BIT DYNAMIC
% R5 = 7
RESB
RH4,R5i
CPE
RH4,1t28i
IF NE THEN CALL CPUERRi
RES
R4,R5i
CP
R4 ,#2E!54i
IF NE THEN CALL CPUERRi
% JIIS:S IlYNAMIC'
3838
5F00 0Dl8
FE12
!812 !257
5100 0DF8
% SET Bit STATIC
% T1CPUT = #A255
SETB.
F.H4,4i
CPB
RH4 ,1t3fi
If NZ tHEN CALL CPUERRi
SET
T1CPUT ,11
CP
'l'1CPUT,IIA257i
IF NE THEN CALL CPUERRi
% SITE STATIC REGISTER
0400
BEES
5F00 0Di8
0400
1E!I4
5i00 0DF8
% SET BIT DYNAMIC
% R4 = #3854
SE'IB
RH4,R5i
CPB
RH4,111i6i
IF NE THEN CALL CPUilRi
SET
R4,R5i
R4 , II:BS D4;
CP
IF NE THEN CALL CPUERRi
5!00 0If8
5F00 0DF8
1812
5F00 0DF8
IS12
5100 0rF8
% TEST AND SIT
% R5 = 7, TlCPUT = #A257
TSlTB
RH5i
IF MI TH1N CALL CPUERRi
INCB
RH5,1i
IF NE THEN CALL CPUERRi
TSET
T1CPUTi
IF PL THEN CALL CPUERRi
INC
TlCPUT, U
IF NZ THEN CALL CPUERR;
% RES DYNAMIC
% SET STATIC
ME~ORY
'
'
% SlTB .DYN.
l SET DYNAMIC
% TSETB S
~
FLAGG
TSETE REGISTER
% TSET S FLAGG
%
TSET MIMO!iY
~ COMPARE****************************************
% COMPARE AND DECREMENT
0\
(X)
ZUSTEii
EAD4
0AE4
0AD6
0AIA
0ADE
0AE4
0H6
0AEC
0AF0
0AF6
0AF6
0AF6
0AF6
0Ar8
0AFA
0AFE
01:04
0E0A
0130C
0.B0E
0ll14
01l18
0B1E
0B1E
0BH
0B22
0B24
0ll28
0ll2E
0B34
0B36
0B38
0ll3I
0E42
0E48
0ll48
0B48
0B4C
0ll52
0B54
0B5A
0B5C.
0.B5E
0B64
0B64
~ACii08000
BIJ57
2106
BA68
E102
8£61
E602
0B05
E602
2U4
A&67
BE6C
I602
EC02
A961
81!61
!602
0B05
1602
4D06
BD74
B£60
iC02
U02
AB61
8B61
E602
01307
!602
I!A64
E402
8L74
E602
A.B62
8:861
E602
~
181:3
0546
51'00 0DF8
5100 0DI8
0006
5!00 0DF8
'
0546
5F30 0Die
5F00 0DF8
51'00 0DF8
E001
5J00 0DJ8
J814
074E
5Ji'00 0Dli 8
5F00 0DF8
5100 0DF8
000:3
5F00 0DF8
0756
5F00 0DF8
5100 0DFB
51'00 0DFS
R4
= #E8D4,
I.DK
AmZE000 Assembler
1.0.1
Pa~e
24
R1 = -TlCPUT
R5,7j
R6, ~Tl CPUT ( 1) ;
LD
IiH4,1i6~,R5,EQ;
CP.tB
II EQ iH£N CALL CPUEiiRI
CP
R1,R6;
IF NE THEN CALL CPUEiiRi
CP
R5,6;
IF NE THEN CALL CPUERR;
% CPU CC
% CPDB DEC. ADDRESS
' CPDB UEC. COUN1ER
% COMPAREa DECREMENT AND REPFAT
:l R6 = 'flCPUT
Rl~ ,R4;
LD
INC
R6,8;
R4,R6-,R5,EQ;
CPDR
IF NZ THiN CALL CPUERRi
IF OV THEN CALL CPUERRi
INC
R6,2;
CP
R1,R6;
IF NE TH1N CALL CPUERRi
CP
R5,1;
IF NI THEN CALL CPUERiii
1 CPDR Z HAGG
% CPDR OV
% COMPARE AND
TSU
LDK
CPI
IF OV
IF ZR
DlC
CP
IF NE
CP
IF NE
% CPI OV
:t CPI
% CPDR DEC. ADDRESS
'
% CPDR DEC.
INCREMENT
T1CPUT(2);
R7,4j
R4,R6- ,R7,NE;
THIN CALL CPUIIiRi
THEN CALL CPUERRi
R6,2;
Rl,R61
THEN CALL CPUERRi
R7,3j
THEN CALL CPUEFRi
:t CPI INCR. ADDRESS
% CPI DEC. COUNTER
% COMPARE,INCREMENT AND REFEAT
CPIRB
RH5,R6~,R7,EQI
IF NOV THEN CALL CPUERRI
TEST
R71
IF NZ THEN CALL CFUERRi
DEC
R6,3;
CP
Rl,R6;
IF NE THEN CALL CPUERRi
% COMPARE STRING,DECREMENT AND
COU~TER
:t CPIIlB OV
% CPIRE COUN'l'ER
% CPIRE ADDRESS
REP~AT
0\
\0
ZTESTER
0]64
0Jl6A
0E6C
01!70
0:E74
0E78
0B7C
0B7E
0BS0
0B84
0ESA
0:890
0B92
0ll94
0Jl96
0B98
0B9E
0U0
0U6
0BA6
01>!6
0I!A8
01iAC
0Isll2
0BB6
0B:SC
0B:BE
0BC0
0BC2
0BC8
0BC8
0BC8
01lCA
0ECE
0ED4
0EDe
01lDE
0.BDE
0BN:
0BE2
0BE8
0HA
0BIC
rrJEEE
0BF4
MACR08000 AmZ8000 Assembler
140A
1D1A
371A
371A
2106
2107
9468
BDC5
BA?E
1402
EE02
946A
A964
A974
9086
E602
8DC4
1602
.ELC9
:SB7A
E602
0Is0C
E602
A961
A971
9086
E602
94!6
1lA72
E602
01l0C
I602
l!ll76
E602
A:B65
AB75
9086
E602
0li0C
0102 0304
0004
0008
JE16
Feu
0C6E
51:110 0DF8
5100 0DF8
51!00 0DF8
5F00 0DFS
LDL
RR!0,#01020304i
LDL
R1 ,RR10i
R1 ~ (4) ,RR10i
LDI
LDL
Rl-18) ,RR10i
LD
R6, T1CPUT(4);
LD
R7,-T1CPUT(B)i.
LDL
RRS,RR6i
LDK
R12,5i
CPSDRB R6-,R7-,R12,NEi
IF NOV !HEN CALL CPUERRi
II ZR THEN CALL CFUERRi
LLI.
RR10,RR6i
INC
R6,5i
INC
R7,5i
CPl
RR6,RR!?i
IF NE THEN CALL CPUERRi
TEST
R12i
If NZ THEN CALL CPUERRi
5100 0DF8
1 COMPARE ~TRING AND DECREMENT
LDK
R12,9i
R6-,R7-,R12,IQi
CPSD
IF NE THEN CALL CPUEER;
CP
R12,8i
IF NE THtN CALL CPUERRi
INC
R5,2i
INC
R7,2i
CPL
RR6,RR8i
IF NE THEN CALL CPUEF.Ri
0C6I
5!00 0DJ'8
0007
5f00 0DF8
% COMPARE STRING AND INCREMENT
LDL
RR6, liR10i
R6- ,R7- ,R12 ,NEi
CPSI1l
IF NE iHtN CALL CPUERRi
CP
R12,7;
IF NE THIN CALL CPUERRi
0C66
5!00 0DF8
0008
5F00 0DF8
0C6E
5F00 0DF8
5F00 0DF8
0002
% COMPARE ETRING, INCREMENT AND REfEAT
CPSIR
R6-,R7-,R12,NE;
Ii NE iHEN CALL CPtiRRi
DEC
R6,6f
IEC
R7,6i
CPL
RR6,RR8i
IF NE THEN CALL CPUERR;
CP
R12,2i
1.11!.1
Page 25:
% CPSDRB NO OVERFLOW
:t CPSDR:S NE
% CPSDRB DEC ADDRESS
% CPSDF.:S COUNTER
:t CPSD CONDITION
% CPSD
~
~OUNTER
CPSD DEC ADDRESS
% CFSIB CONDITION
l CPSIB
D~C.
COUNTER
% CPSIR CONDITION
~
CPSIR INC. ADDRESS
-..J
0
ZTESTER
EBI'S
0:BFE
MACR08000 AmZ8000 Assembler
1602 5.li'00 0DF8
0:BH
0:HE
0:BFE
0:BH.
0C02
0C04
0C06
0C0A
0C10
0C12
0C16
0C1C
0C1E
0C24
0C28
0C21
0C:30
0C:30
0C:30
0C:34
0C:3A
0C:3C
0C42
0C44
0C4A
0C4C
0C50
0C56
0C5C
0C5C
0C5C
0C5E
0C62
0C64
0C66
0C6C
0C70
0C76
0C7A
0C80
0C60
0C80
0C80
210:3 027:3
A114
ELC6
1!878
EC02
A970
0C71
E602
81!97
E602
0B0C
I602
A:B70
1!87C
E402
8.E47
E602
8DC4
1602
BD52
754C
100C
E602
:BDC4
E€!70
AJ!70
8B47
E602
0D41
E602
0.ll0C
1602
A878
0C30
5!00 0DF8
4242
5F00 0DF8
'
5F00 0DF8
0007
5F00 0L1i8
0C:30
5F00 0DF8
OF00 0DF8
5100 0U'8
0500
4445 424:3
5l00 0DI8
0C30
oF00 etD1i'8
424:3
5F00 0DF8
000:3
5F00 0D1i'8
IF NE THEN CALL CPUERR;
1.0.1
Page 26
% CPSIIi COUNTER
% TRANSLATl INSTRUCTIONS **************************
~ TRANSLATE AND DEC~EMENT
% R7 = R9 = ~T1CPUT(8), R7~ = #01020304
LD
R:3,-TRTABL(1)i.
LD
R4,R1i
R12,6j
LDK
R7-,R3~,R12j
TliL:B
IF OV THEN CALL CPUERR;
~ Tli.DB OVERFLOW
INC
R7.lH·
R7 ,'1!';
CPB
IF NE TH~N CALL CPUERRi
~ TRDB TRANSLAT
CP
R7 ,R9i
IF NE THEN CALL CPUERRi
% TRD:B ADF.ESS
CP
R12,7i
IF NE TH£N CALL CPUERRi
% TRD:B COUNTER
DEC
R7 ,U
% TRANSLATE DECREMENT AND REPEAT
R7- ,Ji3 .. ,R12i
TRI!Illl
IF NOV THEN CALL CPUERRi
CP
R7,R4i
IF NE THEN CALL CPUEJiRi
TEST
R12;
IF NE 'IHEN CALL CPUE~Rj
LDK
R5,2i
Rli12 ,R4 .. (ll5);
LDL
CPL
Rli12, 'DE:BC ';
IF NE THEN CALL CPUERRi
% TRANSLATE AND INCREMENT
LDK
R12,4»
R7-,R:3 .. ,R12i
TRill
I:EC
R7 ,li
CP
R7,R4i
IF NE THEN CALL CFUERRi
u-,'JBc';
CP
IF NE THEN CALL CPUERRi
CP
R12,39
II NE THEN CALL CPUERRi
:l TRDR:B NO OV
% 'IRDRE
uuss'
% TRDRJ:! COUN'IER
% TRDR:B TRANSLATE
:1.
TRIB ADDRESS
% TRill TRANSLATE
% TRIB COUNTER
% TRANSLATE, t~CRE~ENT AND R~PEAT
.
% R7 = R4 = TlCFUI, R3 = TRIA]L(1!
INC
R7,9;
-....]
......
ZTESTEli
0C82
0C86
0C6C
0C81
0C94
0C96
0C9C
0CA2
0CA4
0CA6
1/JCAC
eCAC
0CAC
0CAC
0CAE
0Cb0
0CB4
0C:BA
0C.BI
0CC4
0CC6
0CC8
0CCE
0CD2
0Ct8
0CD8
1/JCDS
0CDE
0CE2
I/JCE6
1/JCEC
0CI"0
0CF6
0CF8
0C:rA
0D00
1/JI-04
0D0A
0D0A
0I0A
0D0E
0D12
01:18
0DlE
0D20
MACR08000 AmZ8000 Assembler
1l874
E402
8DC4
1602
l49C
100C
1602
AB73
8B97
1602
BDC4
0C98
1l67A
EC02
0A01
1602
A970
8B97
I602
0B0C
E602
140A
776A
1l87I
EE02
0A01
E602
A971
8li97
E602
0B0C
I602
0C95
B872
E602
i402
8Cl4
t602
0C30
5100 1/JDFB
5Ji/J0 1/JDFS
4243 4445
5100 0DJ8
5100
:ana
0C30
5f00 0DF8
4141
5J00 0I:r8
5100 0DF8
0003
5F00 0DF8
0E0E 111/Jf
0500
0C3E
5100 0Df8
4F4J
51'00 1/JLJ'S
5F00 0D.F8
0001
5!00 0DF8
1010
0C30
5F0e' 0Dl'8
5100 0DlE
sr00
enra
R7~,1i3~,R12i
TRIRll
If NOV THEN CALL CPUERR;
U2;
tEST
If NZ THEN CALl CPUERR;
lDL
RR12,R9~;
CPL
RR12,'BCDE'; .
IF NE THIN CALL CPUERR;
DEC
R7,4;
CP
R7,R9;
II NI THlN CALL CPUE&R;
:t TRANSLATE AND TEST DECREMENT
% R7 = R9 = ~T1CFUT(8)
LDK
R12,4;
R9~;
CLRll
R7~ ,R3'· ,R12;
TRTD:B
If OY THIN CALL CPUERR;
RH1,'A';
CPB
IF NE THiN CALL CPUERR;
INC
R7 ,1;
CF
R7,R9;
IF NE THIN CALL CPUERR;
CP
R12,3;
IF HE THEN CALL CPUE~R;
% TRANSLATE,TEST,DICEIMlNT AND RlPEAT
LDL
RR10,#0E0Ell0F;
LDL
R6: (R5l,RRHH
TRTDRB R7 ,R3 ,R12;
IF ZR THEN CALL CPUERR;
RH1,'o';
CPE
IF NE THEN CALL CPUERR;
INC
R7,2;
CP
R?,R9;
II Ni THEN CALL CPUERR;
CP
R12, 1;
If NE THEN CALL CPUIRRi
1 TRANSLATE AND TEST INCREMEhT
R9~ ,ua;
LDB
R7-,P.3~,R12i
TRTIB
IF NE THEN CALL CPUEliRi
IF NOV THEK CALL CPUERRi
TESTB
liHH
IF NZ THEN CALL CPUERRi
1.0.1
Pap,e 27
% TRIRB NO OV
:t TRIR:B COUNHR
% TRIR:B TRANSLATE
% TRIRJJ HDRESS
% TRTD:B OV
% TRTD:B TEST
% TRTDB ArJ)R.ESS
:t TRTD:B COUNTER
:t TRTDRB TEST
% TRTDRB TEST
% TRTDRB ADDRESS
% TRTDR:B COUNTER
:t TRTIE TEST
% TRTJll NO OV
:1:
TRTIE TEST
-.J
N
ZTESUR
0I26
0D2A
0D30
0D32
0D38
0I3A
0D3C
0D42
0D42
0D42
0D44
0L4E
0D4E
I?JD52
0.1)58
I?JD5A
0D5C
0D62
0D64
0D6A
0I6A
0D6A
0D6A
0I6C
0D6E
0D70
0I72
0D74
0D78
0I7A
0D80
liJD82
0I82
liJD84
EDBA
0I8E
0D90
0D96
0L9S
0D9A
liJD9C
0IA0
0DA0
0DA2
0IA8
MACR08000 AmZBe00 Assembler
0C91
E602
HC4
1:602
AB70
81i97
1602
BDC5
E676
IE02
1/JAI/Jl
E602
1010
5F00 0DF8
R9~ ,#HH
CPh
Il NZ THIN CALL CPUERRi
TEST
R12i
IF NZ THEN CALL CPUERR;
.DEC
R7,1;
CP
R7,R9i
IF NE THEN CALL CPUERRi
5100 0DFB
5100 0DF8
% TRANSLATE,TEST,INCREMENT AND
LI'K
R12,5i
TRTIRB R? .. ,R3- ,B12i
IF ZR !HEN CALL CPUERRi
RHl, 'p';
CPI!
IF NE THEN CALL CPUERRi
IEC
R7,2i
CP
R7,R9i
IF NE THEN CALL CPUERRi
nc
Rl2,3i
Il NZ THEN CALL CPUERRi
0·C3E
5I00 I?JD:F8
5050
5100 tlDF8
AB?l
BB97
E602 5.F00 0DF8
ABC2
E602 5100 I?JDIS
AlFC
At Cis
ABBl
AlBA
ABU
5f00 0D82
8BFC
1602 5f00 0DJ8
E814
BUB
E602
2105
0llF5
E602
DHC
8llFE
9.1!.06
5FiiJ0
5100 0DF8
liJD78
% TRTIE
Paee 28
TRA~S
VALUE
% TRTIE CCUN!'IR
% TRTIB Ari:RESS
REP~AT
% TRTIRB TEST
:t TRTIJiB TEST
:t TRTIRB ADDRESS,
% TRTIRB COUNTER
% PROGRAM CONTROL***********************************
% CALL,CALR,RET,JUMP
LD
R12,Rl5i
LD
Rll,Rl2i
DEC
R11,2i
LD
Rte,Rlli
IEC
R10,2i
CALL
CPUT2i
CPUTl: CP
R12,1i15i
IF NE THIN CALL CPUE~Ri
% RET INCiilMENT R15
JR
CPUT4i
CPUT2:
5Hl0 0DF8
0Df6
8BFA
E602 5FiiJ0 enFa
9Ul8
1. 0.1
CPUT3:
CP
Rll,R15i
IF NI: THIN CALL CPUERRi
li5, ~CPUTli
LD
R5 ,R1e'·;
CP
IF NE THIN CALL CPUERRi
CALR
CPUT3i
CP
Rll,R15i
RET
ZI!i
CALL
CPUE.I\Ri
CP
Rli?J,Il15i
IF NZ THEN CALL CPUERRi
RETi
% CALL R15 DECRIMENT
I CALL RETURN ADDRESS
~
RET INCREMENT R15
~
CALR DECREMENT
w
"""
""
ZTESTER
0DAA
0DAA
0IAA
0DAC
0DAE
0LB0
0DE2
0DB4
0LBA
0DBA
0DEA
0I'EA
01lBC
0DC2
0I'C8
0DCE
0DD4
0DL6
0DDC
0DE2
0U:4
0DEA
II!DF0
0LI6
0DI6
0DI6
0tF8
0DI8
0DI'8
0U8
0DJA
0DFE
0E02
0E06
0E08
0108
0E08
0E08
0108
MACR08000 AmZ8000 Assembler
BD64
!167
AB70
H02
9C68
E602 5FIIJ0 0DF8
1 DECREMENT AND JUMP IF NONZERO
CPUT4: LDK
R6 ,4i
LD
R7,fi.6i
CPUT5: DEC
R7,U
t:BJNZ
RL6,CPUT5i
TESTL
RR6i
IF NZ THEN CALL CPUERRi
1.~.1
Page 29
'- DBJNZ
% CPU CONTliOL
Slfl
E602
E702
I502
1402
BDC5
U.02
EF02
8D73
1E02
1C02
ED02
5F00 0DFB
5J00'0DFB
5100 0DF8
5F00 0DFB
5100 0!'18
5F00 0DIB
5F00 0DF8
5F00 0Di'8
5F00 0DF8
9E08
21FE
010F 0002
030E 0006
610]!. 1806
181'7
1 SET JLAG,RESET FLAG, COM. fLAG
SETJLG ZR,CY,SGN,OVi
If NZ THEN CALL CPUERRi
IF NC TH~N CALL CPUERR;
IF PL THiN CALL CPUERRi
IF NOV THEN CALL CPUERRi
COMJLG ZR,Cli
IF ZR THEN CALL CPUERRi
IF CT THEN CALL CPUERRi
RESJLG ZR,SGN,OVi
II ZR THtN CALL CPUERRi
IF OV THEN CALL CPUERRi
IF MI THEN CALL CPUERRi
CPUIND: RET;
CPUiliR:
LD
ADD
SUB
Lli
JR
't
1
t
FlG
% "
%
%
%
%
1
1 END CPUTEST
R14,R15"i
R15,2i
Rl4,6i
CPUFLI'G,R14i
Cl'UENDi
C~1Ci
1 CPU
******************
E R R 0 R
% RETRIEVE NEXT PROGRAM COUNTER
% RETRIEVE ADDRESS INDICATE INSTR fAIL
% STOHE ADDRESS INTO CPUFLF3
EJECTi
-..,J
+:-
"'"
ZTES'IEF.
0E08
0!08
0E08
0!08
0E08
1800
1e0a
!802
F804
1806
1808
F80A
180C
1810
1Sll2
ISlA
1822
J69A
J89C
189E
!891
FACE
lAD0
MACR08000 AmZ8000 Assembler
Ill FE
30
% RAM AREA
:t
ORIGIN
R!MERRA:
#Fe00;
STACK:
PP!DDR:
WORD
WORD
WORD
WORD
WOliD
WORD
WORD
WORD
LONG
LONG
WORD
WORD
WORD
(1)
(1)
( 1)
(1)
(2)
( 1)
(2)
(2)
(621);
(1) ;
(1);
ORIGIN
.B!BlFACE:
#FACE;
WORD
( 1) ;
% SCRATCH ARIA'
ORIGIN
#FEF8;
(1);
:t STORI DELTA THETA COUNTER
CPUFLFG:
CALJiOMIX:
CALROMFL:
.BACKGRND1:
RAMERR:
T1CPUT:
T2CPUT:
I
J.Bl8:
F.BFA:
F.BlC:
F.BFE:
JC00
IC00
Pa~e
:t
lALiil
F.BFS ·
nre
JllFA
n:rc
1.0.1
WORD
WORD
WORD
WORD
(1);
(1)
( 1);
(1);
( 1) ;
% RAM ERROR ADDRESS
% RAM ERROR DATA
l RAM ERROR EXPECTED UATA
% CPU 'fEST INDICATE ADDRESS OF INSTR FAIL
% CAL ROM INDIX
:t ADDRESS OJ CAL ROM FAIL TEST
% BACKGROUND COUNTER
% RAM ERROR FLAG (NZ=TliUE)
:t CPU SCRATCH AREA
%
"
% INITIAL STACK 'f·OP (SYSTEM),
% PP ADDRESS SCRATCH AiEA .
% STORE I
% STORE Y
l STORE Z
INr.
-...}
\.lt
·ZTES'IER
MACR08000 AmZ81il00 Assembler
1.e.1
Page 31
ASSIGNED LABELS:
ACPUERR
026C
ADtltlSSL 0114
CALROMII F808
0D78
CPUTl
CPUT5
0tU:
iBJC
IBFC
PRIV INSTIH'l136
ltAMIRF.A
1!800
'11CPUT
1'812
VI00 vnr 11JlB6·
XCINTR
0138
XPOWER
0136
ADDR1
EABHACi
CPU END
CPUT2
CPUTIST
IBIE
PST AliT
IIAMl'AIL
T2CPUT
X0000
Xl0I0A
XSTACI
01EIIJ
l!'ACF
0DF6
IIJD82
0286
FBFE
0100
0252
F81A
0264
026E
F89A
ADDR2
BACIGRND1
CPUERR
CPUT3
JUS
PLOOP
RAMDIAG ·
RIJONI
TRAP YCTR
X5555
XFFl!F
ISYS
01F2
I80C
0DF8
0DA0
IBI6
0122
01E8
0260
0136
0268
0266
0136
ADDR3
CALROMFL
CPUFLFG
CPUT4
FPFA
PPADDR
RAMERR
RLOOP
TRTABL
IAAAA
XNPS!
ZTESTER
02e:2
IE0A
1806
lilDAA
lElA
I89C
J8Hl
0215
0272
025A
0000
0100
NEITHER WARNING NOR ERROR MESSAGES
--..]
0\