CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
A BCH ERROR DETECTING
AND CORRECTING SYSTEM
A project submitted in partial satisfaction of the
requirements for the degree of Master of Science 1n
Engineering
by
Johann Sebastian Acosta
May 1983
The Project of Johann Sebastian Acosta is approved:
,...ProfessQEdWard Dombourian
Prof
Professor
Committee
California State University, Northridge
ii
TABLE OF CONTENTS
1.
2.
List of Figures
v
List of Tables
vii
Abstract
viii
Introduction
1
1.1
1.2
1
4
BCH Codes
5
2.1
2.2
Description of the Codes
Encoding of BCH Codes
5
2.2.1
9
2.3
3.
7
Systematic Encoder
Decoding of BCH Codes
10
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
16
18
18
23
23
25
Decoding Algorithm
Syndrome Generator
Circuit to Calculate Det(Lt)
Circuit to Complement Syndrome Bits
Modified Syndrome Generator
"k" Bit Buffer Register
Selection of Optimum Code
3.1
3.2
3.3
3.4
3.5
4.
Introduction
Objective
26
Code Selection Criteria
Code Comparisons
Data Segmenting
Code Selection
Burst Correction With BCH Codes
26
27
32
36
37
EDCC Hardware Design
46
4.1
4.2
46
48
Introduction
General Description of System Hardware
4.2.1
4.2.2
4.2.3
Description of Front Panel Switches and
Indicator Lights
User Procedure for Data Encoding
User Procedure for Data Decoding
iii
51
54
55
~
Page
4.3
Detailed Hardware Description
4.3.1
4.3.2
Description of System Block Diagram
Description of System SEQUENCER
56
61
4.3.2.1
61
4.3.2.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.8.2
4.3.8.3
4.3.8.4
4.3.10
4.3.11
4.3.12
5.
Description of SEQUENCER Generated
Control Signals
Description of SEQUENCER Hardware
Description of MASTER CLOCK Circuit
Description of DATA AND ERROR PATTERN
GENERATING Circuit
Description of DATA STORAGE Circuit
Description of MISCORRECTION DETECTION Circuit
Description of RECEIVED DATA BUFFER REGISTER
Description of PARITY AND SYNDROME BIT
GENERATOR
4.3.8.1
4.3.9
55
Determination of Shift Register
Feedback Connections
Generation of Parity Bits p(x)
Generation of Syndrome Bits s(x)
Syndrome Bit Complementing
65
71
75
79
84
87
89
89
92
93
94
Description of MODIFIED SYNDROME GENERATOR
95
4.3.9.1
Determination of Modified Syndrome
Generator Polynomial a (x)
97
Description of SYNDROME BIT EW BIT
COMPLEMENTING Circuit
Description of DETERMINANT OF LT (DET(LT))
COMPUTING Circuit
Encoding and Decoding Speed
97
103
117
Summary and Results
121
References
124
Appendices
A.
Electrical Specifications of System ICs
125
B.
Schematic Symbol Legend
141
iv
LIST OF FIGURES
Block Diagram of a General Data Storage System
With Error Correcting Capability
2
2.1
An (n-k) Stage Shift Register Encoding Circuit
10
2.2
General Step-by-Step Decoder for Binary BCH Codes
19
2.3
Block Diagram for DET(Lt) Computing Circuit
21
2.4
Detail Design of "Cube" Element
24
3.1
Segmenting of "k" Bit Data Block
33
3.2
Coding of "k" Bit Data Block Without Segmenting
33
3.3
Coding of "k" Bit Data Block With Segmenting
33
3.4
Block Diagram of Error Correcting System for
800 Bit Data Block Using Data Segmenting
38
3.5
Interleaving Scheme for (15,7) Code With I=5
40
3.6
Transmission of Code Vectors Without Interleaving
41
3.7
Transmission of Code Vectors V3 and V2 from
Figure 3.6 With 18 Bit Error Pattern
41
Interleaving Scheme for 100 Byte Data Block Using
(62,50) Code With Interleaving Degree I=l6 and
Single Burst of 20 Errors
42
4.l.a
Encoding Process Using Segmenting
47
4.1. b
Decoding Process Using Segmenting
47
4.2
Encoding and Decoding Processes Using Interleaving
49
4.3
Encoder/Decoder Box Front Panel
50
4.4
Block Diagram:
57
4.5
System Sequencer
4.6
Sequencer Address Bit Control Signals
1.1
3.8
BCH Encoder-Decoder
v
70
4. 7
Time Diagram for Sequencer Circuit Data Access
72
4.8
Master Clock Circuit
74
4.9
Data and Error Generating Circuit
76
4.10
Example of Memory Allocation for Data and Error
Pattern PROM (Z20)
77
4.11
Data Storage Circuit
80
4.12
Data Storage Process Time Diagram
82
4.13
RAM Memory Allocation
83
4.14
Data Fetch Process Time Diagram
85
4.15
Miscorrection Detection Circuit
86
4.16
Received Data Buffer Register
88
4.17
Parity and Syndrome Generator
90
4.18
J-K Flip-Flop Connection to Simulate D Type
Flip Flop
91
4.19
Modified Syndrome Generator
96
4.20
Syndrome Bit Complementor
98
4.21
DET(Lt) Circuit
4.22
Use of Exclusive OR Gates to Generate
104
V1
11
C5"
116
LIST OF TABLES
=
2.1
List of Det(Lt) for Values of t
3.1
BCH Codes Generated From Primitive Elements of
Order <z10
3.2
Available BCH Codes With t
100 Bytes or More of Data
> 20
1, 2, 3 and 4
15
28
for Encoding
31
3.3
Codes of Table 3.2 Shortened for 100 Byte Encoding
31
3.4
List of BCH Codes for Different Values of I and
Code Rates > 78.2 Percent
34
Comparison Between the (62,50) and (995,800) BCH
Codes
37
3.5
3.6
3.7
List of M versus B for (995,800) t
Using Interleaving Degree 1
List of M versus B for (62,50), t
Using Interleaving Degree 16
=
20 BCH Code
44
=
2 BCH Code
44
Polynomial Representation for the System Selectable
Data Sequences mo(x) through ffi7(X)
52
Polynomial Representation for the System Selectable
Error Sequences eo(x) through e7(x)
53
4.2
Hardware Subsystems
58
4.3
List of System Control Signals
66
4.4
Truth Table for Syndrome Bit Complementor 4 Bit
Counter
99
4 .1. a
4.1.b
4.5
Truth Table for JUMP Function
101
4.6
Truth Table for SyndroiiE Bit "i" Complementing Logic
101
4.7
The Galois Field of 26 Elements for p(x)
x6 + x + 1 = 0
vii
=
108
ABSTRACT
A BCH ERROR DETECTING
AND CORRECTING SYSTEM
by
Johann Sebastian Acosta
Master of Science in Engineering
This project presents the design of a digital information encoding
and decoding system using a Bose-Chaudhuri-Hocquenghem (BCH) code.
code chosen for this system 1.s a 1 bit shortened (62,50) code
error correction capability of two errors.
The errors to be
Encoding
are randomly independent occurring errors.
information is performed using a
linear
feedback
Step-by-step
generate appropriate code words.
of
criteria used in
encoding
selecting
and
a
decoding
code
for
methods
the
system
as
of
the
method.
well
are
however, emphasis 1.n this project is mainly on the design and
implementation of the encoder-decoder pa1.r.
digital
register
decoding
This includes a
to
BCH
The
as
the
presented,
hardware
specially
designed exerciser implemented to verify proper system operation.
viii
an
corrected
the
shift
codes, devised by James Massey, is used as the decoding
theory of both the
with
The
CHAPTER I
INTRODUCTION
1.1
Introduction
One of the concerns when using a digital communications system has
been the system's vulnerability to error caused primarily by
the communication channel.
communication links and
caused
by
crosstalk
lightning, etc.
noise
Typical examples of such systems are
telephone
between
lines
channels
where
or
disturbances
lines,
in
space
may
thermal
be
noise,
Similarly, if the storage medium of a digital computer
system is considered to be a transmission channel, then magnetic tapes,
floppy disks, etc. can be added to the previous examples.
However,
in
this case the disturbances are more likely to be caused by tape or disk
defects and contaminants such as dust,
smoke
reduce the possibility of such disturbances
and
fingerprints.
To
causing
problems
the
reliable recovery of digital data, error correcting systems
developed
to
detect
and/or
correct
data
corrupted
in
have
been
a
noisy
by
transmission channel or data storage device.
This project \·Jill only be
concerned
w·ith
data
storage
rather than the other transmission channels mentioned.
data will be assumed to be in binary
form.
With
In addition all
this
general digital storage system with its corresponding error
encoder-decoder pair is shown in Figure 1.1.
meditm1s
in
mind,
correcting
The encoder, according to
some rules, transforms the input information sequence of binary
digits
"m" into sore longer binary sequence "c" which is called the code word
1
a
2
.. m..
Error Free Data
(From Sour ce)
ENCODER
.. cu
Error Free Encoded Data
,~
STORAGE MEDIUM
(Error Source)
.. r ..
Corrupted Encoded Data
~
DECODER
.. m..
Free
. Decoded Data
'v Error
(To Dest1nation)
FIGURE 1.1
BLOCK DIAGRAM OF A GENERAL DATA STORAGE SYSTEM WITH
ERROR CORRECTING CAPABILITY
3
device during a "write" operation.
This sequence could be corrupted by
the error sources previously mentioned
generating a new sequence "r".
11
the original code word
errors in
11
c 11 , where
11
(defective
disk,
This new sequence
"r"
etc.),
thus
corresponds
to
c" plus an error pattern "e 11 indicative of
the
During
the
e" may or may not be equal to zero.
"read" operation, the decoder based on the read sequence "r",
to detect and/or correct any errors
sequence "c", and then transform
1
that
may
have
attempts
occurred
c 11 to the original sequence
to
11
the
m".
Various error correcting codes (ECC) and their respective encoding
and decoding schemes can be used in
Figure 1.1.
systems
like
the
one
shown
1n
Which code to use depends mainly on the type of
error
to
be corrected, the amount of storage space available for parity bits and
the allowable degradation in data transmission
rate.
In general,
all of these factors can be met at once and some compromise has
reached.
For example, the more errors required
more complex the code will be
and
hence
to
more
be
more storage space than is available or may make
interfaced with other systems.
to be encoded or the amount
of
bits
This
it
to
may
too
to
be
be
require
slow
corrected
the
will
to
In this case either the amount of
errors
be
corrected
parity
required, thus reducing the data transmission rate.
not
has
be
data
to
be
reduced.
To correct random errors some of the most powerful codes available
are the BCH codes.
Compared to other
codes,
the
BCH
codes
have
relatively good information to parity bit ratio for the same amount
error correction capability of other codes.
cyclic codes which have
efficient
encoding
Also
the
methods.
BCH
In
codes
a
of
are
addition,
4
relatively
s~ple
and fast decoding algorithms
11
decode the received sequences
r
11
One
•
step-by-step BCH decoding procedure,
by
of
have
such
James
been
devised
algorithms
Massey,
used
to
1s
the
in
the
design of the system for this project.
The following chapters discuss in detail the theory of
BCH
codes
applicable to the data storage system, and the methods used 1n encoding
and decoding the
data
sequences.
Hardware
implementation
of
the
encoder-decoder pair and its exerciser circuit is also presented.
1.2
Objective
The objective of this project is to study the theory of binary BCH
codes and apply the obtained knowledge in the design of a random
correcting system.
Such a system could be used in applications such as
for magnetic disk storage devices.
implementation and testing.
The design is verified by
The error correcting capabilities
selected code are tested using preselected error patterns.
designed in this project encodes and decodes strings
of
according to the characteristics of the BCH code chosen,
proper performance by comparing bit by bit
digital sequences.
error
Verifying the
design
correcting technique.
digital
and
with
hardware
rather
amount
considerations
1n
and
This 1s
selecting
data
verifies
and
the
the
The circuit
original
hardware required for such an encoder-decoder pair.
major
of
the
simulating it in software, gives an idea on
since it is one of the
hardware
decoded
than
type
of
important
an
error
CHAPTER II
BCH CODES
2.1
Description of the Codes
One of the best known classes of error correcting codes 1s the BCH
codes.
These codes were first discovered by Hocquenghem
independently by Bose and Chaudhuri in 1960.
Since
the
error
1959
The BCH codes are
random error correcting codes which have been defined for
and nonbinary symbols.
in
correcting
both
system
and
cyclic
binary
requires
encoding and decoding of digital sequences of information, this chapter
will
only
consider
a
subclass
of
narrowsense or primitive BCH codes.
the
binary
BCH
called
codes
These codes are the most important
BCH codes from the standpoint of both theory
and
implementation.
A
description of their characteristics follows.
For any positive intergers "m" and "t" where
t<2m-l
a
BCH
code
with the following characteristics can be obtained:
Block length
n = 2ffi-l
Number of parity bits
n-k
Minimum distance
dmin ~ 2t+l
< mt
Since dmin of this code is greater than or equal to 2t+l it is
capable
of correcting "t" or fewer errors.
t-error
correcting BCH code.
code
is
The generator polynomial g(x)
defined as the least common
(m2t(x)),
This
multiple
i.e.
5
(LCM)
of
called
of
m1 (x),
a
this
m2 (x)
code
is
6
(2 .1)
where mi(x) is the minimum polynomial of the primitive eletrent
the Galois field
GF(2m).
From
the
definition
of
code
generator
polynomials the primitive elements ai, i.e. a1, a2
a2t are roots of
g(x).
Also,
In other words g(xi) = 0 for i = 1, 2, ... 2t.
an even integer, it can be expressed as
a
product
of
if "i"
the
is
following
form:
i
where i'
~s
an odd integer and
.Q, ~
= i'2.Q,
(2.2)
It can be shown that ai and
1.
have the same minimum polynomial, i.e.
mi (x)
(2.3)
mi' (x)
This means that every even power of "x" in
the
sequence
of
equation
(2.1) has the same minimum polynomial as sore previous odd 'Power of "x"
in the sequence.
This leads to the
following
simplification
of
the
equation for g(x):
(2.4)
g(x) = LCM Cm1 (x), m3Cx) ... m2t-1 (x))
An example on how to
obtain
g(x)
using
equation
Section 4.3.8 when the generator polynomial for
system is computed.
the
2.4
is
error
given
in
correcting
Meanwhile, the parameters for all binary BCH codes
of length 2m-1 with m
< 10
are given in Table 3.1 of Section 3.1.
7
2.2
Encoding of BCH Codes
Encoding of BCH codes can be accomplished using any of the methods
available for encoding cyclic codes. The method employed for this error
correcting system generates the parity bits using an
n-k
register.
popular
This is one of the most widely
circuits available.
used
and
stage
encoding
Its popularity stems from the fact that
relatively fast parity generator and the same circuit can
most cyclic code decoding algorithms.
theory of encoding cyclic codes
and
A
the
detailed
it
be
1s
used
discussion
implementation
shift
in
on
a
in
the
hardware
using an n-k stage shift register follows.
When encoding a k-bit binary sequence "m", where m
=
Cmo, m1, ....
mk-1) it is desirable to obtain a systematic code vector v
.... Vn-1).
By definition, the code
vector
"v"
is
said
systematic form when the first "k" digits of the vector
to
be
1n
correspond
to
the unaltered information digits "m" and the last n-k digits correspond
to the parity bits "p" of "m".
or
Such a vector is shown below.
v = Cvo, v1, v2, · · · .Vn-k-1• Vn-k · · · · ·•·· · · .vn-1)
Given the generator polynomial g(x) of an (n, k) cyclic code,
code can be put in systematic form by performing the
algebraic manipulations
with
the
transmitted
following
message
"m".
the
simple
Using
polynomial representation
m ( X ) -- mo + m1
X
+ • . • • + mk-1
X
k-1
•
(2.5)
8
Multiplying m(x) by xn-k
xn-k m(x)
is obtained,
positions.
which
= mo
is
xn-k + ml xn-k+l + .... + mk-1 xn-1
the
transmitted
polynomial
If equation 2.6 is divided by g(x) the
shifted
following
(2.6)
by
n-k
equation
is obtained:
xn-k m(x)
= q(x)g(x)
where q(x) and r(x) are the quotient and
+ r(x)
the
remainder
(2. 7)
respectively.
Since the degree of g(x) is n-k, the degree of r(x) has to be n-k-1
less.
Thus
r(x)
r(x)
or
~s
= ro
+ r1Cx) + ... + rn-k-1 xn-k-1 .
(2. 8)
defined as the parity bit polynomial p(x) of m(x), or
(2.9)
r(x) = p(x) .
Equation 2. 7 can be rearranged as follows:
r(x) + xn-k m(x)
= q(x)g(x)
(2.10)
= g(x)q(x)
(2.11)
v(x)
= g(x)q(x)
Equations 2.11 and 2.12 indicate that v(x) is a multiple
has degree n-1 or less.
(2.12)
of
g(x)
and
Therefore, from the definition of cyclic codes
9
v(x) = r(x) + xn-k m(x)
(2.13)
is a code polynomial of the code generated by g(x).
From equation 2 .11
it
can
be
seen
that
the
coefficients of v(x) correspond to the transmitted
"k"
high
message
polynomial
m(x) and that the n-k low order coefficients correspond to
bit polynomial p(x).
order
the
parity
This is the configuration for v(x) desired for
systematic code vector.
a
A circuit to encode m(x) in systematic form is
discussed next.
2.2.1
Systematic Encoder
It is clear from the
systematic
form
1s
above
equivalent
polynomial p(x) which is
nothing
dividing xn-k m(x) by g(x).
explanation
to
that
calculating
more
than
encoding
its
the
m(x)
parity
remainder
1n
check
r(x)
of
This can be accomplished with an n-k stage
shift register encoding circuit as shown in Figure 2-1.
connections of this circuit are selected
according
to
The
the
feedback
generator
polynomial
g(x)
=
1 + gl x + g2 x2 + ••• + gn-k-1 xn-k-1 + xn-k
and the encoding procedure is acomplished as follows:
Step 1:
=
With the gate turned on, the "k" information digits
roo + ml (x) +
+ mk-1
xk-1
are
shifted
simultaneously into the comm.Jnication channel.
into
As
the
register
soon
information digits have entered the shift register, the n-k
the register are the parity bits.
as
the
digits
m(x)
and
"k"
1n
10
Output
Code
Word
FIGURE 2.1
AN (n-k) STAGE SHIFT REGISTER ENCODING CIRCUIT
Step 2:
Break the feedback path by disabling the gate.
Step 3:
Shift the contents of the shift
them into the channel.
register
out
and
send
These n-k parity digits p(x) =PO+ P1(x) + ...
.. . + Pn-k-1 xn-k-1 with the "k" information digits xn-k
m(x)
make
a
complete code word v(x) = p(x) + xn-k m(x).
In the
above
circuit
premultiplication
of
m(x)
division by g(x) is accomplished simultaneously by
by
feeding
the shift register at the output of register n-k-1.
xn-k
m(x)
and
into
A detailed example
and description on how to design this circuit for the
system
designed
in this project is presented in Section 4.3.8.
2.3
Decoding of BCH Codes
Since 1960 various decoding algorithms have been developed for the
various classes of BCH codes.
One of these is the so
step decoding algorithm devised by
developed for either
binary
or
changing received symbols one at
James
Massey
nonbinary
a
time
BCH
with
1n
called
1965.
codes,
testing
and
to
step-byIt
was
involves
determine
11
changing received symbols one at
a
time
with
whether the weight of the error pattern has
testing
been
to
reduced.
section first some properties of the BCH codes which are
this algorithm are reviewed.
narrow sense case and its
described.
Then,
general
Discussion of the
system, however,
information
implementation
this
to
this
exploited
in
binary
with
hardware
are
for
arbitrary
BCH
algorithm
irrelevance
about
In
the decoding method for the
decoding
codes are omitted because of its
determine
the
subject
design
of
be
found
can
the
in
reference [ 1].
Some properties of cyclic codes in general, and of the
are now stated.
BCH
codes
It is assumed that the code vector is systematic, i.e.
v(x)
xn-k m(x) + p(x)
(2 .14)
and that it is transmitted with highest order digits first.
is transmitted, r(x)
= v(x)
When
v(x)
+ e(x) is received, where
(2.15)
~s
the received code polynomial and
(2.16)
~s
the
error
pattern
coefficients of e(x)
~s
polynomial.
The
the Hamming weight of
total
number
error
the
of
nonzero
pattern
and
calculate
the
equals the total number of errors in r(x).
As usual one of the steps of decoding a code
syndrome s(x) from the received vector r(x).
~s
to
The syndrome s (x)
= so
+
12
s 1 x + ... sn-k-1 xn-k-1 is
defined
as
the
remainder
when
r(x)
is
divided by g(x) i.e.
s(x) = Rem (r(x) /g(x))
(2.17)
and hence can be formed at the receiver using a simple n-k stage
shift
register as the one discussed in Section 2.2.1.
From the definition of cyclic code
generator
=
known that g(x) divides v(x), (Rem (V(x)/g(x))
polynomials
0).
Since
it
is
=
r(x)
v(x) + e(x) it follows from equation 2.17 that s(x) can be expressed in
terms of the error pattern rather than the received vector as:
s(x)
=
Rem (e(x)/g(x))
Now, if the error polynomial e (x)
is
(2.18)
e'xpressed
as
the
sum
of
two
polynomials ei(x) and ep(x) where:
=
LS
en-k x
the error pattern
~k
+ en-k+1 + · · · + en-1 x
polynomial
for
errors
~1
occurring
(2.19)
only
in
the
information positions and
=
eo + e1 x + ... en-k-1 x n-k-1
(2.20)
is the error pattern polynomial for errors occurring in the parity
bit
positions, the syndrome polynomial s(x) can therefore be expressed as
s(x)
=
Rem (ep(x)/g(x)) +Rem (ei(x)/g(x))
Since the degree of ep(x) is less or equal than n-k-1 i.e.
Rem (ep(x)/g(x)) = 0
(2.21)
13
equation 2.21 can be rewritten as
s(x)
=
(2.22)
For the binary narrowsense BCH codes a vector
Sj is
now
defined
as follows:
s·J =
r(ai)
j
=
(2.23)
1, 2, .•. 2t
The quantities Sj are elements of GF(2m) and have played
an
role in previous decoding algorithms of BCH codes.
can
Sj
important
also
be
expressed as
(2.24)
for j = 1 , 2 , . . . 2 t
Proof:
By definition Sj
= r(a~),
this ~s equal to
(2.25)
Since the ai's are roots of the code polynomial v(x), i.e. v(ai)
=
0,
equation 2.25 can be expressed as
(2.26)
Now, if equation 2.22 is rewritten in
terms
of
ai's
the
following
equations are obtained
(2. 2 7)
(2 .28)
14
From the definition of a BCH code, all of the arguments
are
roots
of
g(x), i.e. g(ai) = 0, thus
s(ai)
s(ai)
ei (ai) + ep(ai)
=
e(ai)
(2.29)
By substituting equation 2.29 into equation (2 .26)
S·J
~s
=
s(ai)
J = 1' 2
for
...
'
2t
obtained, which completes the proof.
Since
s(x)
is
computable
equation 2.24 that so are
"S j" for j
~
sl,
at
the
receiver
In
s2
2t+l is not computable at the receiver.
~n
algorithm the importance of the "Sj" lies
the
it
follows
from
general,
however,
For the
decoding
following
property
which is essentially theorem 9.3 in Peterson [3].
Property 1.
"t" such that 1
For any binary BCH code with dmin = 2t+l and for
< t < n-1
the following (txt) matrix can be fortred
1
=
any
0
s2
S2t-2
S2t-3
0
0
1
0
S2t-4
This matrix can be proven to be singular if the weight of "e" is t-1 or
Some
of
the determinants (Det) have been calculated for the matrix Lt (t=l,
2,
less, and is nonsingular if the weight of "e" is "t" or t+l.
3 and 4) and are listed for reference in Table 2-1.
15
TABLE 2-1.
LIST OF Det (Lt) FOR VALUES OF
t = 1, 2, 3 AND 4
1
s1
2
sl3 + s3
3
sl6 + sl3 s3 + sl s5 + s32
4
sllo + sl7 s3 + sls ss + sl3 s7 + sl2 s3 ss + sl s33 + s3 s7 + ss2
The actual Massey decoding algorithm for
BCH codes is discussed next.
the
narrowsense
binary
This algorithm makes use of the following
two theorems.
Theorem 1:
Assume an error patten "e" of weight "t" or less in
narrowsense binary BCH code.
If Det(Lt)
=
0
change
so, s1 ... , s2t-2 of the syndrome s(x) until
Det(Lt)
F 0.
(as
in
will
Then, this new syndrome corresponds to an
of weight exactly "t" with the sme ei (x)
as
for
the
a
order
digits
always
occur)
error
pattern
original
error
pattern.
s.
J
1S
equivalent to changing the corresponding error bit ej in ep(x) with
no
Proof 1:
From equation (2.22) changing the
change to the bits in ei{x).
or decrease the weight of
syndrome
bit
However, changing ej will either increase
the
whether ej was originally "O" or
error
11
1 11 •
pattern
by
one,
Since the error
changes in unit steps, the first occurrence of Det(Lt)
depending
pattern
1
the presence of exactly "t" errors as stated in Property
0 will
1.
weight
signal
If
changing is required at most t-1 of the ej 's could be "1" and hence
most 2t-l changes will be needed to increase the error
pattern
on
any
at
weight
16
most 2t-1 changes will be needed to increase the error
to "t".
2t-1
pattern
weight
The fact that g(x) has 2t distincitive roots, guarantees
< n-k
that
and thus assures that there will always be enough digits
to
be changed.
Theorem 2:
Assume an error pattern "e" of weight exactly "t" in a
narrowsense binary BCH code.
Consider changing temporarily and one
a time the received information digits rn-1• rn-2 ... rn-k and
each time whether Det(Lt) vanishes.
at
testing
When and only when Det(Lt) = 0 the
corresponding received information digit was received in error.
Proof 2:
bit.
Suppose
rj ~ ij where ~j is
Since it is assumed
that
the
the
initial
changing rj reduces the error
pattern
weight
Property 1 Det(Lt) vanishes.
Conversely,
original
weight
to
suppose
of
t-1
r·J
information
"e"
and
~s
"t"
hence
=
by
Then
changing rj increases the error pattern weight to t+1 and hence Det(Lt)
remains nonsingular i.e. Det(Lt) = 0.
2.3.1
Decoding Algorithm
Theorems 1 and 2 together establish the validity of the
algorithm for the correction of "t" or fewer errors
in
a
following
narrowsense
BCH code.
Step 1:
Set j = 0
Step 2:
Determine from s(x) whether Det(Lt) = 0
Step 3:
If Det(Lt) = 0 complement Sj; increase Sj by one, and
to step 2.
Otherwise, set j=1 and go to step 4.
go
17
Step 4:
Temporarily complement rj and determine from the modified
syndrone whether Det(Lt)
Step 5:
=
0.
If Det(Lt) = 0, set the information bit 1'J
r.
J
to
+
1.
go
to
Othen11ise set i·J to rj.
Step 6:
If j=k stop.
Otherwise,
by
one
and
decodes
the
k
received
the
received
increase j
step 4.
It should be noted that this algorithm
only
information digits.
to
If it is
desired
also
decode
parity digits step 3 has to be modified to read " ... complenEnt Sj
rj ... 11 and step 6 has to be modified to read
As can be seen,
the above
algorithm
initial error pattern (step 2).
11
•••
checks
if j=n ...• "
the
weight
If this weight is less than
syndrome bits are changed in order,
starting with so,
pattern of weight ''t" is obtained (step 3).
and
until
of
the
"t",
the
an
error
At this time the algorithm
proceeds to check the syndrome of the received vector when the received
digit rj to
be
decoded
theorem 2, if the received
1s
monentarily
digit
r·J
is
inverted
in
error
(step
4).
(r.
J
inverting it reduces the weight of the error pattern to t-1.
result in Det(Lt) being zero.
i·)
J
If this is the case, the received
other hand, if the received digit rj was correct (rj
it increases the weight of the error pattern to t+1.
=
ij),
digit
On
the
inverting
This will
In this case no correction to rj is necessary
then
This will
is complemented in order to obtain its correct value (step 5).
in Det(Lt) ~ 0.
From
result
18
(step 5).
Each received digit is decoded one bit at a time thus
steps
4 and 5 have to be repeated "k" times (step 6).
A block diagram
of
the
decoder
algorithm is shown in Figure 2-2.
used
to
implement
the
above
It consists of five major subsystems
which are listed below and discussed in the next few sections.
2.3.2
1)
Syndrmre generator
2)
Circuit to calculate Det(LT)
3)
Circuit to complement syndrome bits
4)
Modified syndrome generator
5)
"k" bit buffer register
Syndrome Generator
The syndrome s(x) of r(x) is generated using the
same
shift register used for generating the parity bits for m(x).
case, however,
shifting
~n
the
circuit
performs
the
all "n" bits (starting with bit
register at the left most stage (bit so).
division
rn-1)
of
of
n-k
stage
In
r(x)/g(x)
r(x)
into
this
by
the
After all "n" bits have been
shifted into the register, the register will contain the
r(x)/g(x) which by definition is the syndrome s(x).
remainder
of
These
bits
are
the
weight
of
then used by the Det(Lt) calculating circuit to obtain
the error pattern of r(x).
2.3.3
Circuit to Calculate Det(Ltl
One method to calculate Det(Lt) ~s to
construct
circuit whose inputs are the m-tuple representation of
a
combinatorial
the
vector
s.J
19
11
m11 STAGES
ECODED
OUTPUT
r o ... rn..;;..:-._1___,
CIRCUIT TO
COMPLEMENT
IN ORDER
so,sl, s2t
UNTIL 0
INPUT SIGNA
1.
2.
3.
4.
5.
BINARY OUTPUT IS 11 111 WHEN AND
ONLY WHEN det(Lt) = 0
DECODING PROCEDURE
(a 0 , a1 , ... ,an-k-l) is the syndrome for e~(o,o, ... O,l).
Gate 1 is energized while the 11 m11 received information
digits are read into the upper shift-register and is
de-energized thereafter. Upper shift-register does not
shift again until 11 decode 11 order it given.
Complementing circuit begins to function after all 11 n 11
received digits are read into the decoder. It ceases to
function when it receives a 11 011 input signal at which
time the 11 decode 11 order is given.
Gate 2 are energized by the decode order.
Lower shift-register, after all 11 n11 received digits are
read in, does not shift again until 11 decode 11 order is
given.
FIGURE 2.2
GENERAL STEP-BY-STEP DECODER FOR BINARY BCH CODES
20
and whose binary output is a "1" when and only when Det(Lt)
a combinatorial circuit is shown in Figure 2-3 for
correcting code.
0.
Such
2
error
parameters
shown
a
A description on how to obtain the
=
(15,7)
in Figure 2-3 follows in the following example:*
From Table 2-1 it can be seen that for a 2 error
Det(L2) = S13 + S3.
correcting
code
The objective is to express this equation in terms
of the syndrone bits so, s1, ... s7.
Let Cao, al, a2, a3) be the 4-tuple representation of sl
=
s(a)
and let (bo, b1, b2, b3) be the 4-tuple representation of S3
where aL is a primitive element of GF(24) obtained from
polynomial
x4
+ x + 1.
the
primitive
Then:
+ s2a 2 + ... + s7a 7
and
Since all elenents of GF(24) can be expressed Ln terms of 1, a, a2 and
a3 it can be readily verified that:
*NOTE: Section 4.3.11 explains in full detail the procedure followed
in obtaining the parameters used to calculate Det(Lt) for the code
used in the design of the system for this project.
21
~~~
v
v
CUBE
v
~
ll f~l
DJT (Lt}
FIGURE 2.3
BLO<X DIAGRAM FOR DET (Lt) COMPUTING CIRaJIT
and
=
where
=
22
=
s2 + ss + S6
=
's3 + S6 + S7
=
SO + S4 + SS
=
S3 + S4
=
S2 + S4 + S7
and
To obtain the cube of S1 advantage can be taken of the
s1 3
= [s( a )]3
=
s( a)
representation of s(a2)
s( a2).
=
With
this
(do, d1, d2, d3) is
fashion as for s(a) and s(a3).
This 4-tuple
1n
mind
obtained
can
be
fact
the
1n
a
that
4-tuple
similar
expressed
as
a
function of a1, a2, a3 and a4, 1.e.
=
=
d2
=
=
Doing the proper calculations, the cube of the vector (ao, a1, a2,
is found to be the vector (co, c1, c2, c3) where:
co
=
=
a3)
23
=
=
A detailed design for the cube element of the vector Cao, a1,
a2,
a3)
is shown in Figure 2-4.
2.3.4
Circuit to Complement Syndrome Bits
This circuit is enabled after all
shifted into the syndrome generator
circuit is
11
1 11 •
11
n 11 received
and
the
output
of
If these conditions are satisfied the
complementing syndrome bits so, s1 ... s2t
~n
~s
disabled.
have
the
is
circuit
zero,
been
Det(Lt)
starts
order and one at
until the output of the Det(Lt) computing circuit
time the circuit
digits
a
at
time
which
The circuit is not enabled again until a
new sequence is to be decoded.
The detailed design for this circuit
~s
shown in Section 4.3.10.
2.3.5
Modified Syndrome Generator
The modified syndrome generator takes advantage of the
fact
that
the cyclic structure of the code makes it possible to treat
successive
received digits as though each where rn-1·
each
Then
changing
digit is equivalent to adding a fixed polynomial a(x) to
the
such
syndrome
where a(x) is the syndrome when rn-1 is the only digit in error, i.e.
a(x)
=
Rem (xn-1 I g(x))
The modified syndrome generator
is
enabled
after
the
original
syndrome bits have been complemented as required by step 3 of the
24
FIGURE 2.4
DETAIL DESIGN OF "CUBE" ELEMENT
decoding algorithm (see Section 2.3.1).
When
a(x)
1s
enabled
the
syndrome bits used to compute Det(Lt) correspond to the syndrome of the
original received vector r(x) except for bit rn-1·
bit rn-1 is assumed to
be
1n
error.
The
computing circuit is now used to decide
should not be corrected.
By
output
whether
enabling
of
this
A zero at the output of the
the
bit
a(x),
Det(Lt)
should
Det(Lt)
or
circuit
will not change rn-1, whereas a "1" will.
After bit rn-1 has been decoded, both the syndrome shift
as
well
as
the
k-bit
buffer
information bits is shifted once.
register
containing
the
This will move bit rn-2 to
rn-1 in the k-bit shift register and will also
generate
the
corresponding to r(x) shifted cyclically once.
The syndrome
register
received
position
syndrome
for
this
shifted vector is modified by a(x), hence resulting in the syndrome for
x·r(x) with bit rn-2 assumed in error.
This modified syndrome is
used
25
to compute Det(Lt).
Bit rn-2 which
now
occupies
the
position
held
previously by rn-1 in the k-bit buffer register is decoded according to
the output of the Det(Lt) circuit.
The above process is repeated until all k-bits have been decoded.
2.3 .6
11
k 11 Bit Buffer Register
This register is used to serially store the "k"
of r(x), starting with bit rn-1·
They remain in
information
bits
register
until
this
the bits of s(x) are complemented according to step 3 of
algorithm (see Section 2.3.1).
out of the buffer register.
corrected value for rj.
decoding
At this time r(x) is shifted bit by bit
Each bit is Exclusive-ORed with the output
of the Det(Lt) computing circuit.
the Det(Lt) circuit will
the
If bit rj 1s 1n error, the output of
"1",
=r·J
r·+l
J
1S
the
On the other hand, if rj 1s not 1n error,
the
be
a
thus
output of the Det (Lt) computing circuit will be
which again is the correct value for rj.
11
0 11 ,
Decoding
which
r·+O
J
r.
complete
after
thus
is
J
all "k" information bits of the received vector r(x) are shifted out of
the buffer register.
This completes
the
description
methods used in this project.
of
the
encoding
and
The design requirements as well
decoding
as
the
selection of an appropriate code to be used in the design of the system
is presented 1n the next chapter.
CHAPTER III
SELECTION OF OPTIMUM CODE
The first and probably most important step in
the
design
of
error correcting and detecting system is the selection of a code
an
which
will satisfy the requirements and needs of the system in consideration.
When choosing a code for a magnetic disk storage
device
most important factors to be considered are
type
errors to be corrected, the code rate,
correcting the data block.
the
and
are
of
number
the
of
the size, and the probability of
The type and number of errors
the probability of correction
obtained
from
as
analytical
based primarily on the type of errors
ex?ected
to
system, and on the importance laid on
assuring
proper
those errors.
some
occur
well
as
studies
within
correction
the
of
On the other hand, the data block size and code rate are
determined mainly from the type of memory device being considered.
3.1
Code Selection Criteria
The design of the ECC system of
this
project
following specifications:
1)
Memory sector size - 128 bytes
2)
Data block size - 100 bytes
3)
Correction capability/sector -
4)
Error type - random
5)
Probability of miscorrection - <lcr1o
26
)20 errors
is
based
on
the
27
The search for an optimum code such that all of the above
requirements
are met follows.
3.2
Code Comparisons
From
the
storage
capacity
(lOO bytes) the code rate
"R"
(128
for
bytes)
the
and
system
can
data
block
be
size
obtained
as
follows:
R
=
(3.1)
k/n
where
k
n
total number of data bits (data block size) and
=
total number of bits (data and parity bit sector size)
Hence, from the design requirements presented in the previous
section,
the code rate for the system is found to be
R
=
100 bytes/128 bytes
=
78.2%
For random error type error correcting systems, one
powerful classes of codes available are
the
BCH
of
the
codes.
The
characteristics and qualities of these codes for encoding and
of digital data sequences were discussed in detail in
list of BCH codes generated by primitive elements of
2lO is shown in Table 3-1.
three codes are available to
basic
decoding
Chapter
2.
A
less
than
A quick look at this table shows that
only
encode
100
correcting capability of t=20 or better.
bytes
of
order
most
data
with
error
These codes are listed in
"
1c
,
TABLE 3-1.
1
127
1
4
15
11
1
1
2
5
3
2fi
21
16
I
3
II
5
6
1
Jl
(JJ
57
51
45
39
36
30
24
18
16
10
7
127
120
113
106
99
,.
I
3
4
5
6
7
10
II
13
IS
I
2
3
4
5
92
85
6
78
7
I
71
64
9
10
51
II
so
13
14
15
21
23
27
31
15
8
255
,.
k
43
36
29
22
2
2
BCH CODES GENERATED FROM PRIMITIVE ELEMENTS OF ORDER<2 10
247
239
231
223
215
207
199
191
187
179
171
163
ISS
147
139
131
123
1I5
255
II
12
13
14
15
18
19
21
"
k
107
99
91
87
79
71
63
22
23
25
26
27
29
30
31
42
43
45
47
55
59
63
511
376
367
358
349
340
331
322
313
304
295
286
277
268
259
250
241
238
229
220
47
45
37
29
21
13
9
s
8
9
10
I
55
1
2
3
4
6
1
k
511
502
493
484
475
466
457
448
439
430
421
412
403
394
I
2
3
4
5
6
7
8
9
10
II
12
13
211
202
193
184
175
166
157
148
139
,
,.
15
16
18
19
20
21
22
511
JO
31
36
37
38
39
41
42
43
45
46
47
51
53
54
94
85
76
67
58
49
1023
,
31
28
19
10
62
63
85
87
91
93
95
109
111
119
121
1013
1003
2
~93
3
983
973
963
953
943
933
923
9Jj
903
893
883
4
5
6
40
23
25
26
27
28
29
k
I
1
8
9
10
II
86.1
12
13
14
15
16
858
17
873
,.
1023
k
I
818
808
798
788
778
768
21
22
23
24
758
748
738
728
718
708
698
688
678
668·
658
648
638
628
618
608
598
588
578
573
'563
553
25.
26
27
28
29
30
31
34
35
36
37
38
39
41
42
43
44
45
46
47
49
50
51
52
N
00
"'
TABLE 3-1.
BCH CODES GENERATED FROM PRIMITIVE ELEMENTS OF ORDER<2lO (Continued)
"
t
t
"
k
1023
S03
493
483
473
58
1023
328
318
308
298
288
278
268
258
248
238
228
218
208
203
193
183
173 .
163
59
60
358
348
61
62
63
73
74
75
77
78
79
82
83
85
86
87
338
89
463
453
443
433
423
413
403
393
383
378
368
I
90
91
93
94
95
102
103
106
107
109
JIO
111
J15
117
118
119
122
) 23
"
k
I
1023
153
143
133
125
126
127
170
1:3
121
J)J
101
91
86
76
66
56
46
36
26
16
JJ
171
173
175
181
183
187
189
191
219
223
239
147
255
N
1.0
30
Table 3-2 with their respective code rates.
to be encoded the above codes can be
Since only 800
shortened
changing their error correction capabilities.
by
"s"
bits
bits
have
without
The shortened codes with
their respective code rates and "s" are shown in Table 3-3.
For random errors, the probability "P"
sector in a
binary
symmetrical
channel
of
can
miscorrecting
be
obtained
a
data
from
the
following formula:
t
"''
p
./_,
(3.2)
P_Q,
}1,=0
where
=
p
n!
R,!(n-£)!
PR, (1-p)n-R,
(3.3)
and
p
n
=
probability that one bit 1s in error (assumed to be 10-5)
=
number of errors
=
sector size
t
correctability of selected code
For the (1015, 800) t=22 error correcting BCH code
22
p
=
\
1o151
/_,_J .Q,! (1015-£)!
R,=O
P
< 1o-5o
oo-5)}1,
o- 1o-5) 1015-R,
31
TABLE 3-2. AVAILABLE BCH CODES WITH t )20 FOR
ENCODING 100 BYTES OR MO,RE OF DATA
(n,k)
t
R
(1023, 828)
20
80.9%
(1023, 818)
21
79.9%
(1023, 808)
22
78.9%
TABLE 3-3. CODES OF TABLE 3.2 SHORTENED
FOR 100 BYTE ENCODING
(n,k)
t
s
R
(995' 800)
20
80.4%
28
ooo5, 8oo)
21
79.6%
18
(1015, 800)
22
78.8%
8
The above result means that there is less than 1 in
1
x
10-50
of
chance that a random error pattern of weight greater than 22 bits
occur in a 1015 bit binary sequence.
requirement of P <lo-10.
will
If P is calculated for the
two codes available it is found that they also easily meet
the
a
other
design
Thus, in theory any of the above codes can be
used in the design of the error correcting system of this project.
addition to correcting random errors, the above codes can also be
to correct single bursts of 20, 21 and 22 errors respectively.
is, however, one important drawback.
Hardware implementation
above codes is almost impossible if not impractical.
In
used
There
for
the
For example, when
using the (1015,800) code, the error correcting system would require an
32
=
"n-k" = 1015-800
syndrome bits.
215 bit shift register to generate
In addition decoding for such BCH
its
codes
parity
and
becomes
very
complex.
3.3
Data Segrenting
To save hardware and simplify the system design,
block can be segmented into "I" sectors of equal
the original data
length
as
shown
in
Figure 3-1, where
(3.3)
k' /k
I
and
k'
k
number of information bits 1n original data block
=
number of information bits in shortened data block
In the case of the k' bit segrent the encoded n' bit word send
be stored in memory consists of
the
k'
information
bits
and
to
n'-k'
parity bits as shown in Figure 3-2.
For the segmented case the
memory
will
rece1ve
a
sequence
of
I code vectors "v" as shown in Figure 3-3.
Table 3-4 shows various BCH codes for different values of I,
code rates
>78 .2
percent.
It
can
correctable errors decreases as the s1ze
encoded is shortened.
in the memory sector
be
seen
of
the
that
data
the
with
number
blocks
However, the total number of correctable
to
of
be
errors
33
k'
I
1
2
...
. ..
3
I
"
•••
~k
~(
)~
k
+ ... +
k
k
:4
FIGURE 3.1
SEGMENTING OF "k 1 " BIT DATA BLOCK
~--------~----------n'
parity bits
information bits
k'
n '-k'
CODING OF
11
k
111
FIGURE 3.2
BIT DATA BLOCK WITHOUT SEGMENTING
I·n
I n-k
:
k
In-k
:
•••
k
•••
I'
n
~(
n
~(
....
~
v,
*
v2
~
•••
In-k
~I.:
i
'T'
n
*
VI
FIGURE 3.3
CODING OF "k 111 BIT DATA BLOCK WITH SEGMENTING
k
>t
>{
34
TABLE 3-4. LIST OF BCH CODES FOR DIFFERENT VALUES
OF I AND CODE RATES >7B'. 2 PERCENT
BCH
Shortened
BCH
I
k/n
Info
Bits
1
.7BB
BOO
( 1023, BOB)
2
. 784
400
2
.787
4
t
n-k
p
( 1015, BOO)
22
215
<lo-so
(1023, 913)
(510, 400)
11
110
5.64x1o-37
508
400
(511, 403)
(508, 400)
12
108
1.01x1o-37
3
.800
200
(1023, 973)
(250, 200)
5
so
3.18x1o-19
773
4
.787
200
(511, 457)
(254, 200)
6
54
1.24x1o-22
257
4
.806
200
(255, 207)
(248, 200)
6
48
1.04x1o-22
7
5
.BOO
160
(1023, 983)
(200, 160)
4
40
2.53x1o-16
B23
5
.816
160
(511' 47 5)
(196, 160)
4
36
2.28x1o-16
315
5
.800
160
(255, 215)
(200, 160)
5
40
8.22x1o-20
55
8
.833
100
( 1023' 1003)
(120, 100)
2
20
2.80x1o-10
1003
8
.787
100
(511, 484)
( 127, 100)
3
27
1.03x1o-13
384
8
.806
100
(255, 231)
( 124, 100)
3
24
9.37x1o-14
231
8
.826
100
(127, 106)
(121, 100)
3
21
8.48x1o-14
6
10
.800
80
( 1023' 1003)
(100, 80)
2
20
1.61x1o-10
923
10
.816
80
(511, 493)
(98, 80)
2
18
1.51x1o-10
413
10
.833
80
(255, 239)
(96' 80)
2
16
1.42x1o-10
159
10
.792
80
(127, 106)
(101, 80)
3
21
4.07x1o-14
26
16
.833
so
(1023, 1013)
(60, SO)
1
10
1. 77x1o-7
963
16
.847
so
(511, 502)
(59, SO)
1
9
1. 71xlo-7
452
16
.862
so
(255, 247)
(58, SO)
1
8
1 .6Sxlo-7
197
16
.877
so
(127, 120)
(57' 50)
1
7
1.59x1o-7
70
16
.806
so
(63, 51)
(62, 50)
2
12
3. 77x1o-ll
s
8
1
35
TABLE 3-4. LIST OF BCH CODES FOR DIFFERENT VALUES
OF I AND CODE RATES )78.2 PERCENT (Continued)
I
k/n
Info
Bits
BCH
Shortened
BCH
20
.800
40
(1023' 1013)
(SO, 40)
1
20
.816
40
(511' 502)
(49, 40)
20
.833
40
(255, 247)
20
.851
40
20
.869
40
p
s
10
1.22xlo-7
973
1
9
1.17xlo-7
462
(48' 40)
1
8
1.13xlo-7
207
(127' 120)
(47' 40)
1
7
1.08xlo-7
80
(63, 57)
(46, 40)
1
6
l.03xlo-7
17
ttotal
=
I
n-k
t
(3 .4)
· t
is maintained equal or above the specified value of 20 errors/128
byte
sector.
One drawback in segmenting the original k' bit data sequence
smaller "k" bit segments is in the performance of the error
codes for shorter segments.
The probability of correction
independent errors is reduced drastically and in
errors will not be able to be corrected.
Since
addition
the
error
into
correcting
for
random
most
burst
correcting
system in this case is not required to correct burst errors it is
necessary to comply with the probability of
errors staying within specification.
For
miscorrection
systems
that
for
only
random
require
burst correction capability the reader is referred to Section 3.5.
some
36
3.4
Code Selection
The optimum BCH code for the system 1s now selected.
This
code
should achieve the following:
R >78.2%
ttotal
=
I · t >20 errors/128 byte sector
P <lo-10
n-k
= smallest
possible
From Table 3-4 such
correcting code.
a
code
1s
found
to
be
the
(63,51)
2
error
Since the 51 information bits of this code are not
multiple of the 800 information bits to be encoded
from
the
a
original
data block, the (63,51) code is shortened by 1 bit to produce a (62,50)
code.
From Table 3-4 the characteristics of this code are:
t
=
2 errors
R
=
80.6%
p
=
3. 77
n-k
=
12 bits
ttotal
=
16
10-11
X
2
=
32 errors per 128 byte sector
The (62,50) code is compared to the (995,800) code in Table 3-5.
this table it can be
seen
that
both
the
(62,50)
as
well
From
as
the
(995,800) code fulfill all the requirements specified for the design of
the error correcting system.
When using the (62,50) code a
circuit is required to divide the 800
bit
information
16-50 bit long segments for encoding and into 16-62 bit
segmenting
sequence
long
into
segments
37
TABLE 3-5.
(n,k)
(62, 50)
COMPARISON BETWEEN THE (62, 50)
AND (995, 800) BCH CODES
I
R
t
tTOTAL
s
16
80.6%
2
32
1
1
80.4%
20
20
28
(995, 800)
for decoding (see Figure 3-4).
required to generate
the
p
3.77
segtrents,
the
10-11
overall
195
circuitry
is
circuitry
is
reduced when using the (62,50) code rather than the (995,800)
encode the 100 byte data block of the system.
the fact that the (995,800)
code
will
12
<Io-50
Although some additional
data
X
n-k
code
to
For one, this is due
to
require
a
195
bit
syndrome
register which drastically increases the amount of hardware required by
the system.
The (62,50) code is therefore selected to demonstrate
error correcting and detecting characteristics of BCH codes,
the
which
1s
correction
of
the main purpose of this project.
3.5
Burst Correction With BCH Codes
The BCH codes are codes designed primarily for the
random errors.
therefore poor.
Their error correction capability of
burst
errors
To enhance the burst correction capability of the
1s
BCH
codes as well as any other nonburst and burst correcting cyclic code, a
process known as interleaving may be used.
Given an (n,k) cyclic code,
interleaving is accomplished by arranging I code vectors
of
into I rows of a rectangular array and then transmitting
them
storage device column by column.
A pattern of errors can be
the
to
code
the
corrected
38
800 BIT Data Sequence
SEGMENTING CIRCUIT
16-50 BIT Da ta Sequences
~
ENCODING CIRCUIT
16-62 BIT Co de Words
128 BYTE MEMORY SECTOR
Received Oat a Sequence (992 BITS)
',
SEGMENTING CIRCUIT
16-62 BIT Co de Words
!,
DECODING CIRCUIT
Original 800 BIT Data Sequence
~
FIGURE 3.4
BLOCK DIAGRAM OF ERROR CORRECTING SYSTEM FOR 800 BIT DATA BLOCK
USING DATA SEGMENTING
39
for the whole array if and only if the pattern of errors in each row is
a correctable error pattern for the code.
burst of length I will affect
no
more
No matter where it starts, a
than
one
bit
Therefore bursts are effectively divided into I groups
in
of
each
raw.
correctable
length b, where
=
b
I ·
(3.5)
t
Figure 3-5 shows an example of an interleaving scheme of degree
for the (15,7) 2 error correcting
BCH
code.
In
this
example
5
the
maximum correctable single burst length is
b
=
5 • 2
=
10
It can be seen that even though the total number of errors in the burst
1s 10, no more than 2 errors occur in each code vector, and
therefore,
the sector is correctable.
used,
If interleaving
had
not
35-bit data segment of the previous example could
been
be
encoded
the
with
(63,36) t=5 error correcting BCH code shortened to a (62,35) code.
a
The
max1mum correctable single burst length in this case is
b
=
1 . 5
=
5
which 1s half the correcting capability of the interleaving case.
As another example the case of the 16-(62,50) code
to encode the 100 byte data sector of the system is
segments
taken.
When
interleaving is used the 16 code vectors Vi are transmitted to the
used
no
40
tc:fE~-- CHECKS - - - - - t i E - - - - - - DATA-------~
Sequence of Transmission
CODE
WORDS
1
71
E
E
E
6
1
2
72
E
E
E
7
2
3
73
E
E
E
8
3
4
74
E
E.
E
9
4
5
75
E
E
E
10
5
10
9
8
2
1
15
14
13
12
11
7
4
5
6
3
WHERE E • ERROR LOCATION
FIGURE 3.5
INTERLEAVING SCHEME FOR (15. 7) CODE WITH I = 5
storage device as shown in Figure 3-6.
v2 and v3 only.
bits.
than
Figure 3-7 shows a
of
The shaded area represents the scattering of the error
As can be seen the amount of errors present
the
diagram
allowable
correctable
quantity
for
in
v2
the
is
greater
(62 ,50)
code.
Therefore v2 and hence the entire memory sector are uncorrectable.
interleaving is.used each 62~bit code
vector
storage device as shown in Figure 3-8.
is
In this
transmitted
case
error shown as bits E1 to E20 when de-interleaving,
that each code vector has no more than 2 errors.
a
1s
If
to
20-bit
broken
the
burst
up
This guarantees
so
that
all code vectors and thus the entire memory sector is correctable.
To
help
1n
selecting
the
interleaving
degree
of
correcting system, the effects of single and multiple burst
an "n" bit IIEmory sector where analyzed.
following equation:
an
error
errors
in
This analysis resulted in the
41
h16~1 6 ..a,~~ •• • 4P 3
I
v,6
~: ~
I
+-m 4'P -¥- m+p -+-m
3
V3
2
~
2
V2
1
1
~
v1
r~Burst
Error
TO
m =messaqe section of code vector v
p =parity section of ·code vector v
M~ORY
FIGURE 3.6
TRANSMISSION OF CODE VECTORS WI TROUT INTERLEAVING
62
I
18 BIT Burst Error
2
62
If
44
I
*
FIGURE 3.7
TRANSMISSION OF CODE VECTORS v 3 AND V2 FROM
FIGURE 3.6, WITH 18 BIT ERROR PATTERN
1
Vector
BIT
I Number
42
~CHECKS-···+··· ---DATA
.
v1
97
v2
97f
v3
97~
v4· ~8(
~81
v5
v6
v7
98l
VB
98~
v9
98~
v, 0
98€
v,
98~
98,
vl2 98E
v13
98~
··~~~~~~~~-r~
~t~
33 17
1
~
~
• 18
2
~
• 19
3
f&
. 20
4
~
21
5
• • •
--+--1~~~+--+"-""+-''-t--..:.....;
• • •
--+--1---t~i--+--~~~~
•••-+-r~~~-+-r~
···~~~~~+-~~~~
···~~~~~+-+-~~~
~
~
22
6
23
7
~
24
8
[(J§
25
9
~
26 10
lfJV.
~r.
27 11
• • •
--+--1___,~,.__+--+-+--+----4
• • •
--t---1----'l~t--+--+-+--+----4
• • •
--+~-lol4'!~+--+-~-+-~
• • •
--+--1-~-+--+--+--+--+--i
• • •
• •
•
•• •
~~
~~
28 12
~
29 13
--+--f--~T---+--+--+--+----4
v14 99(
vl5 ~91 975
vl6 ~92 97E
FIGURE 3.8
INTERLEAVING SCHEME FOR 100 BYTE DATA BLOCK
USING (62,50) CODE \flTH INTERLEAVING DEGREE
I=16 AND SINGLE BURST OF 20 ERRORS
p •
43
= I (T - M + 1)
B
+ M- 1
(3.5)
for
=
i = 1, 2, ••• M
where
B
=
total number of error bits guaranteed to be
corrected l.n the "n" bit sector
I
=
interleaving degree
M
=
number of bursts (single, double, etc.)
T
=
correctability of code
L"1.
=
burst length of burst number i
The 100 byte data
equation.
sequence
of
the
using
this
When no interleaving is performed (I=l) the k=800 data
bits
can be encoded using the (995,800),
system
t=20
is
analyzed
shortened
BCH
number of guaranteed corrections "B" for various number
code.
of
The
bursts
1.s
listed 1.n Table 3-6.
For the (62,50), t=2 BCH code the results listed in Table 3-7 were
obtained when using an interleaving degree of 16.
The results
show
60 percent improvement in the allowable length for a single burst
interleaving is used.
a
when
However, the total number of bits guaranteed
to
be corrected for multiple bursts drops considerably when
interleaving.
Whether or not
in
to
choose
the
interleaving
technique
correcting system again depends mainly on the type of err.ors
expected to
requires
occur
additional
within
the
hardware
system.
to
perform
In
the
addition,
proper
an
that
error
are
interleaving
transmission
44
TABLE 3-6.
M
B
1
20
2
20
3
20
19
20
20
20
LIST OF M VERSUS B FOR (995, 800), T=20 BCH CODE
USING INTERLEAVING DEGREE 1
Cornnents
(the allowable burst length is anywhere from 1 to
20 bits so that LTOT = L1 ~20)
(each of the 20 bursts has to be of length 1 so that
LTOT = Ll + L2 + •.• + L20 ~20)
(correction is not guaranteed)
21
TABLE 3-7.
M
.B
1
32
2
17
3
2
LIST OF M VERSUS B FOR (62, 50), T=2 BCH CODE
USING INERLEAVING DEGREE 16
Comments
(the allowable burst length is anywhere between 1 and
32 bits so that LTOT = L1 ~32)
(does not guarantee correction between LTOT = L1 + L2
+ L3 ~2 which is impossible since all Li's have to be
integers)
45
sequence of the code vectors, and to de-interleave
these
vectors
decoding, which also has to be taken into consideration when
choice for an appropriate decoding technique.
making
for
a
CHAPTER IV
EDCC HARDWARE DESIGN
4.1
Introduction
In Chapter III an optimum code was selected for the design of
the
error correcting and detecting system implemented in this project.
The
code selected is a (63,51) 2 error correcting
1 bit to generate a (62,50) code.
BCH
code
shortened
In this manner a 100 byte long
block can be encoded by segmenting the data into 16-50 bit long
Each 50-bit word is encoded independent
of
sequence, with
bits,
its
respective
parity
allocated for the 100 bytes of data.
the
others
to
the
bits.
The encoding process is shown in the block
4-1a.
Decoding is performed by segmenting the
words.
corresponding
to
send
in
sector
assumed
plus
its
diagram
stored
data
words.
memory
The memory sector 1s
be large enough (128 bytes) to accommodate this data
16-62 bit long segments, each
and
by
of
data
to
parity
Figure
into
the
one
of
the
encoded
The 16 segments are transmitted one at a time
to
the
decoder
where they are decoded and send to their respective destination.
This
process is shown in Figure 4-1b.
In addition to the segmenting technique, single
burst
correction
can be enhanced by interleaving the original data block as explained in
Section 3.4.
in sequence,
Thus, instead of transmitting each encoded word to memory
the encoded words are used
to
form
the
16
rows
16 x 62 bit array which is transmitted to memory column by column.
46
of
a
47
100 BYTE Data Block
to be encoded
800 BITS of Data
l
Segmenter
(16-50 BIT Segments)
50 BIT Dat a Segments (Each of the 16 Data
segments i s sent to the encoder one at a time)
1
(62,50) Encoder
62 BIT cod e words
12& BYTE Memory Sector
FIGURE 4.1.a
ENCODING PROCESS USING SEGMENTING
128 BYTE Memory Sector
16-62 BIT code words
VI
Segmenter
(16-62 BIT Segments)
62 BIT cod e words (Each of the 16 code
words is sent to decoder one at a time)
II
'
(62,50) Decoder
50 BIT dec oded Data segments
~
FIGURE 4 . 1. b
DECODING PROCESS USING SEGMENTING
48
This requires the use of
an
interleaving/de-interleaving
shown in Figure 4-2 to generate the transmitted data
reproduce the original code words for decoding.
circuit
sequence
Although
and interleaving are important techniques employed
in
and
as
to
segmenting
the
design
of
many error correcting systems, and where important factors in selecting
the systems code, they have
no
direct
decoding algorithms used in the system.
hardware does not include
circuitry
effect
1n
the
encoding
Therefore, the design
related
to
the
interleaving processes, but rather, will concentrate
of
the
segmenting
and
on
the
and decoding procedure of SO-bit long data segments using
BCH code.
and
encoding
the
(62,50)
With this in mind a brief description of the encoder/decoder
hardware and its features follows.
4.2
General Description of System Hardware
The encoder-decoder circuit submitted in
(62,50) BCH code previously
binary sequences.
mentioned
to
this
project
encode
and
uses
decode
the
50-bit
Eight different SO-bit data sequences are stored
a PROM chip and are available
sequences can be encoded at
to
a
be
time
Only
encoded.
and
stored
in
one
of
these
memory.
encoding is completed, the encoded sequence is retrieved
from
After
memory,
corrupted with a pre-known selectable error pattern, decoded, and
compared to the original binary sequence to verify
a
diagram
of
front
panel
of
then
correction.
Figure 4-3
shows
enclosure.
The functions of each of the switches and LEDs available to
the system user are described next.
the
proper
in
the
hardware
49
100 BYTE Data Block to
be encoded.
~}
800 Bits of Data
Segmenter
(16-50 BIT Segments)
~~
50 BIT Da ta Segments (Each of the 16 Data
Seqments is sent to the Encoder one at a time)
(62,50) Encoder
62 BIT co de words
Interleaver
( 16-62 BIT rows)
,
62-16 BIT Columns of Interleaved code words
__1 ENCODING
128 BYTE Memory Sector
PROCESS
~DECODING PROCESS
16-62 BIT code words
i
Deinterleaver
16-62 BIT code words
~
Segmenter
(16-62 BIT Segments)
It
62 BIT co de words (Each of the 16 code
words is sent to the decoder one at a time)
(62,50) Decoder
!
50 BIT de coded Data segments
FIGURE 4.2
ENCODING AND DECODING PROCESSES USING INTERLEAVING
ENCODE
~ ®~ ~ ~ ~
D0
D1
D2
E0
1
2
~CODE P~CESS
COMPLETE
!T
P~ER
0
MI SCORRECTION
()
UNCORR.
PATTERN
FIGURE 4.3
ENCODER/DECODER BOX FRONT
•
.
RESET
ON
~
OFF
POWER
P~~EL
l..n
0
..
51
4.2.1
Description of Front Panel Switches and Indicator Lights
Toggle Switches DO, Dl and D2:
These switches generate a 3-bit
output used to select 1 of the
through DrJ (x),
available
to
8-50
be
bit
data
sequences,
The
encoded.
binary
data
mo(x)
patterns
available are shown in Table 4-la.
Toggle Switches Eo, E1 and E2:
These switches generate a 3-bit
output used to select 1 of the 8 available error
through e7(x)).
available.
listed.
for
use
Table 4-lb shows a list
It can be seen that 16
error
of
patterns
the
patterns
the
circuit,
each
containing
8
(eo(x)
error
patterns
are
actually
This is due to the fact that there are 2 PROMS
1n
binary
available
different
error
patterns.
Toggle Switch ENCODE/DECODE:
This switch is used either to select
the
This momentary contact switch 1s used to initialize
the
encode or decode mode.
RESET Switch:
circuit before starting the encoding or decoding procedures.
START Switch:
This momentary contact
switch
encoding or decoding process as determined
is
used
by
the
to
start
the
ENCODE/DECODE
switch position.
Toggle Switch POWER ON/OFF:
This switch is used to apply +SV power
to
the circuit.
POWER ON LED:
This red LED indicates the presence of +5V system power.
TABLE 4-1a.
Data Pattern Switch
Positions
Do
Dz
D1
POLYNOMIAL REPRESENTATION FOR THE SYSTEM SELECTABLE
DATA SEQUENCES mo(x) THROUGH m7(x)
Data
Pattern
Number
1
Data Pattern
Polynomial
mi (x)
0
0
0
0
0
0
0
1
1
x49 + x48 + x47 + ... + x2
0
1
0
2
x49 + x47 + x45 + .•. + xS + x3 + x
0
1
1
3
x23 + x22 + x21 + .•. + x2 + x + 1
1
0
0
4
x49 + x48 + x47 + ... + x27 + x26 + x25
1
0
1
5
x49 + x48 + x47 + .•. + x36 + x35 + x34
1
1
0
6
x33 + x32 + x31 + ... + x2 + x + 1
1
1
1
7
x16 + x15 + x14 + •.• + x2 + x + 1
+ X +
1
\.J1
N
TABLE 4-lb.
Error Pattern Switch
Positions
E2
El
Eo
POLYNOMIAL REPRESENTATION FOR THE SYSTEM SELECTABLE
ERROR SEQUENCES ea(x) THROUGH e7(x)
Error Pattern Polynomial
PROM 2
PROM 1
ei(x)
ei(x)
Error
Pattern
i
0
0
0
0
0
x61
0
0
1
1
xl2
x61 + xl2
0
1
0
2
x31
x31 + 1
0
1
1
3
x36
x36 + x35
1
0
0
4
x61 + x60
x61 + x60 + x
x45 + x44
x61 + x45 + x44 + xl2
i
I
i·
1
0
1
5
1
1
0
6
x45 + x44 + x43
x45 + x44 + x43 + xl3 + xl2
1
1
1
7
x61 + x60 + xl3 + xl2
x61 + x60 + xl3 + xl2 + x + 1
Vl
w
54
PROCESS COMPLETE LED:
This green LED indicates the conclusion
of
the
between
the
encoding or decoding procedures.
MISCORRECTION LED:
This red LED indicates a
decoded word and the
original
error
discrepancy
free
data
sequence.
implies that the weight of the selected error pattern was
It
greater
than 2 thus exceeding the error correcting capability of our
code
and resulting in the miscorrection of the received vector.
UNCORRECTABLE PATTERN LED:
This yellow LED indicates the presence of a
detectable but uncorrectable error pattern.
For
this
system
it
applies to all error patterns of weight 3.
Having explained all of the user switches and indicator lights,
step by step description of the procedures to
correctly
use
a
the
BCH
m(x)
by
encoder/decoder box is now presented.
4.2.2
User Procedure for Data Encoding
STEP 1:
Select one of the
eight
available
data
sequences
setting toggle switches Do, D1 and D2 according to Table 4-la.
STEP 2:
Set the ENCODE/DECODE switch to the ENCODE position.
STEP 3:
Push RESET to initialize
the
circuit.
This
step
can
omitted if encoding is started immediately after system power
been applied.
This
is
due
to
the
fact
that
the
system
automatically initialized when system power is first applied.
be
has
is
55
STEP 4:
Push START
to
start
encoding.
The
circuit
encodes
the
selected data pattern m(x) and stores it in a random access memory
chip.
The green PROCESS COMPLETE LED will indicate the completion
of the encoding process.
4.2.3
User Procedure for Data Decoding
STEP 1:
Select one of the
eight
available
error
patterns
e(x)
by
setting toggle switches Eo, E1 and E2 according to Table 4-lb.
STEP 2:
Set the ENCODE/DECODE switch to the DECODE position.
STEP 3:
Push RESET to initialize the circuit.
STEP 4:
Push START to start decoding.
The circuit adds
the
selected
error pattern e(x) to the encoded data pattern v(x) stored in RAM;
decodes the received pattern r(x)
the original data pattern m(x).
= v(x)
+ e (x) and compares it to
The green
indicates completion of this process.
PROCESS
The red
COMPLETE
LED
MISCORRECTION
and
yellow UNCORRECTABLE PATTERN LEDs may also be enabled depending on
the error pattern selected.
4.3
Detailed Hardware Description
In the next few sections a detailed description of
involved 1n the design of the BCH encoder/decoder
pair
the
is
In order to understand this description it 1s assumed that
is familiar with basic TTL design theory.
circuitry
presented.
the
reader
All of the IC's used 1n
the
design are described in Appendix A, including pin-out diagrams and some
of the more important data such as truth tables and propagation delays.
56
Meanwhile, a description of the symbols used in the circuit
shown throughout this chapter can be found in Appendix
required
to
U26
and
respectively.
diagram
of
Figure 4-4.
U27
through
The hardware
the
U51
located
description
encoder/decoder
pair
on
starts
and
IC's
through
U51.
accommodate
circuitry with all "Z" labeled IC's located on board
through
The
B.
shown in the schematics are labled Zl through Z32 and Ul
Three circuit boards Al, A2 and A3 were
schematics
Al
and
IC's
Ul
A2
and
A3
boards
by
showing
associated
the
a
block
circuits
The shaded areas represent circuits related
only
in
to
the
exerciser portion of the system, while the unshaded areas represent the
circuits necessary for the actual encoding and decoding procedures.
list of all system components shown in Figure 4-4 and their
classification
Table 4-2.
(exerciser,
encoder
or
decoder)
Sections 4.3.2 through 4.3.11 give a
of each of those circuits.
1s
respective
presented
detailed
A
in
description
First, however, with the aid of Figure
4-4
the system is described as a whole.
4.3.1
Description of System Block Diagram
When the START switch in Figure 4-4 is pressed,
circuit generates a 0.5
SEQUENCER.
MHz
squarewave
used
to
the
MASTER
CLOCK
strobe
the
system
The SEQUENCER sends a predetermined series
signals to the
components
of
the
encoder/decoder
signals are discussed in detail in Section 4.3.2.1.
of
16
control
circuit.
These
When in the ENCODE
mode, one of the eight 50-bit data patterns m(x) stored in the DATA AND
ERROR PATTERN GENERATING CIRCUIT
1s
transmitted
GENERATOR as well as to the system MEMORY circuit.
to
the
PARITY
After all
50
BIT
bits
R'(x):: HESS.fl(,.f: PoiZI/6N
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FIGURE 4-4
BLOCK DIAGRAM: BCH ENCODER-DECODER
Vt
'-1
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58
TABLE 4-2.
Subsystem
HARDWARE SUBSYSTEMS
Classification
Sequencer
Exerciser
Master Clock
Exerciser
Data and Error Pattern
Generating Circuit
Exerciser
Memory
Exerciser
Parity and Syndrome Bit
Generating Circuit
Encoder and Decoder
50 Bit Buffer Register
Decoder
Determinant of LT
Calculating Circuit
Decoder
Syndrome Bit by Bit
Complementing Circuit
Decoder
Modified Syndrome
Generating Circuit
Decoder
Miscorrection Detecting
Circuit
Exerciser
59
of m(x) have been transmitted, the contents of the PARITY BIT GENERATOR
will be the 12 parity bits p(x) of m(x).
These are now send in sequence to the MEMORY
are used to form the encoded word v(x)
= m(x)
circuit
+ p(x).
where
After
they
all
12
parity bits have been transmitted to MEMORY, the system MASTER CLOCK is
inhibited and the PROCESS COMPLETE LED is lit to indicate completion of
the encoding procedure.
When decoding, the SEQUENCER generates control signals to read the
encoded word v(x) from MEMORY.
v(x) is
added
to
one
operator selectable error patterns e(x) stored 1n the
PATTERN GENERATING circuit.
SYNDROME GENERATOR and 50-BIT
decoding procedure.
REGISTER.
GENERATOR.
+ e(x) which is
eight
DATA
AND
ERROR
BUFFER
shifted
REGISTER
to
m(x)
are
transmitted
to
to
start
Only the first 50 bits of r(x),
the message polynomial
the
The sum of these two sequences results
= v(x)
the received vector r(x)
of
both
the
actual
50-BIT
to
BUFFER
However, all 62 bits of r(x) are transmitted to the SYNDROME
After all 62 bits of r(x) have been read from
MEMORY,
contents of the SYNDROME GENERATOR will be the syndrome s(x)
At this time the DET LT COMPUTING CIRCUIT from now
on
the output of this circuit 1S a
11
S2t
as
required
discussed in Section 2.3.1.
Det (Lt) is recalculated.
the
r(x).
DET
s(x).
LT
If
111 and as long as it remains a "1" the
SYNDROME BIT COMPLEMENTING circuit will in
...
of
called
circuit, is enabled to calculate the determinant of Lt for
bits so, SI
the
corresponding
the
1n
by
the
order
conp lement
syndrome
Massey
decoding
algorithm
Each time a syndrome bit 1S
As will always be the case,
conp leme nted,
the
output
of
60
the DET LT circuit will be a "O" before syndrome bit s2t+l
complemented.
A
11
has
to
be
0 11 output will disable the SYNDROME BIT COMPLEMENTING
circuit and enable the MODIFIED SYNDROME GENERATOR.
The output of this
circuit is used by the DET LT circuit to calculate the determinant
Lt of the modified syndrome s'(x)
= s(x)
+
a(x),
modified syndrorre generator polynomial.
The
circuit is added to the received
bits
vector
BUFFER REGISTER circuit which at this
register one by one.
time
where
output
of
stored
are
a(x)
the
in
shifted
LT
50-BIT
If the output of the DET LT circuit is a "1"
the
out
DETECTION
circuit
50-BIT
where
if
The determinant
BUFFER
thus generating a corrected message polynomial m' (x).
it
1s
the
of
Lt
REGISTER
m' (x) is sent to
compared
original rressage polynomial m(x) to verify proper correction
0).
DET
the
is calculated for each bit shifted out of the
=
the
of
output is a "O" the bit will remain unchanged.
m(x)
is
the
bit coming out of the buffer register will be complemented and
the MISCORRECTION
of
to
the
(m' (x)
+
Any discrepancies between these two sequences (m'(x) + m(x)
~ 0) will cause the MISCORRECTION LED to turn on,
the error pattern chosen was uncorrectable.
circuit is also used to determine if
error pattern (weight of e(x)
the output of the
DET
LT
= 3)
a
decoding procedure and thus enabling
detectable
remaining
the
implying
The output of the
was present.
circuit
thus
This
low
but
DET
LT
uncorrectable
will
during
UNCORRECTABLE
that
result
the
PATTERN
in
whole
LED.
After all SO message bits have been decoded the system MASTER CLOCK
is
disabled prompting the PROCESS COMPLETE LED to indicate
of
the decoding procedure.
completion
61
Having presented the overall operation of the BCH
system each of the
subsystems
shown
~n
Figure
encoder-decoder
4-4
and
listed
in
Table 4-2 are now discussed in detail.
4.3.2
Description of System SEQUENCER
The schematic of the SEQUENCER circuit is
shown
in
Figure
Two 2K x 8 BIT INTEL 2716 PROMS (Zl and Z2) are programmed
16 output signals used to control
the
encoder-decoder
to
4-5.
provide
system
logic.
The name and function of each of these signals is discussed below.
4.3.2.1
Description of SEQUENCER Generated Control Signals
DREPCS:
Data-Ram-Error-Program Counter Strobe.
This
~n
used as the clock input to the program counters used
ERROR PATTERN GENERATING
circuit
to
select
the
signal
is
DATA
AND
the
appropriate
location of the PROM containing the 8 data and error patterns.
also used to strobe the RAM program counter to select
the
memory
It
is
appropriate
address for each of the encoded data bits vo, v1 ... v61 transmitted to
the MEMORY circuit.
RDBRS:
Received Data Buffer Register Strobe.
This signal is used
to strobe the 50 bit buffer register used in the decoding process.
PSSRS:
Parity and Syndrome Shift Register Strobe.
used to strobe the parity and syndrome shift register
This signal is
as
required
the encoding and decoding procedures to obtain the parity and
bits respectively.
by
syndrome
(i!lll
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FIGURE 4.5
SYSTEM SEQUENCER
0\
N
s
"'
63
SCOMPS:
Syndrone Bit Complementing Strobe.
This signal
to strobe the SYNDROME BIT COMPLEMENTING circuit.
used to advance a counter
whose
The strobe signal is
16
demultiplexer which in turn selects the syndrome bit so, s1 ..• s2t
to
algorithm.
the
is
used
to
be complemented as required by
output
1s
Massey
decoded
by
decoding
a
4
(Section
A secondary use for this signal is to generate the
COMPLETE signal at the end of
the
encoding
or
decoding
2.3.1)
PROCESS
procedures.
This is achieved by simultaneously setting control lines SCOMPS and LTS
to a "1" at the end of the encoding or decoding programs.
LTS:
Determinant of LI Strobe.
This signal is used to strobe the
latch containing the result of the DET
Lr
When
circuit.
strobed,
output of the latch is used to determine whether syndrome
bit
the
bit
by
complementing is necessary, or later, whether the received
bit
decoded is in error.
conjunction
In addition,
this line
is
used
in
with signal SCOMPS to generate the PROCESS COMPLETE signal at
to
the
be
end
of the encoding and decoding procedures.
CLEAR.
This signal is momentarily enabled at the beginning of the
encode and decode programs.
It clears the 50-bit buffer register,
latch containing the result of the DET
LT
circuit
and
the
4
the
x
16
demultiplexer used in the SYNDROME BIT COMPLEMENTING circuit.
LOAD.
This signal is momentarily enabled at the beginning of
encode and decode programs.
the
It is used to store the starting addresses
of the selected data and error patterns in the data and
error
pattern
PROM program counter located in the DATA AND ERROR PATTERN GENERATING
64
circuit.
This signal also clears the shift register of the PARITY
AND
SYNDROME GENERATOR.
RAMCS.
This signal enables the RAM chip
in
the
MEMORY
circuit
during data storage (encode) and data read (decode) modes.
DOG:
Data Output Gate.
This
signal
MISCORRECTION DETECTING circuit and
the
is
used
to
uncorrectable
enable
error
the
pattern
detector located in the SYNDROME BIT COMPLEMENTING circuit.
PBFG:
Parity Bit Feedback Disable Gate.
This signal enables
PARITY AND SYNDROME GENERATOR circuit feedback line.
It
when shifting the nessage
circuits
polynomial
m(x)
into
the
register during the encode mode, and the received
the decode mode.
The line is disabled while
vector
is
the
enabled
shift
r(x)
during
the
parity
transmitting
bits from the shift register to the MEMORY circuit.
TXG.
This signal 1s enabled during the
enables the received vector r(x) to be
SYNDROME GENERATOR circuit at the point
decode
shifted
mode
into
determined
only.
the
by
PARITY
the
It
AND
shortened
code polynomial T(x) (see Section 4.3.8.3).
AXG.
This
signal
1s
used
to
enable
the
MODIFIED
SYNDROME
GENERATOR circuit 1n the decode mode as required by the Massey decoding
algorithm.
SDIG:
Serial Data Input Gate.
This signal is used to enable
message polynomial m(x) to be shifted
GENERATOR during the encode mode.
into
the
PARITY
AND
the
SYNDROME
65
DPB:
Data/Parity Bit Multiplexer Selector.
This signal
to switch the input to the MEMORY circuit oetween
the
1s
output
used
of
the
DATA AND ERROR GENERATING circuit and the PARITY AND SYNDROME GENERATOR
during the encode mode.
This results in the
and parity bit polynomial p(x) to be stored
message
in
polynomial
memory.
m(x)
During
decode mode this line is held high to enable the first 50 bits
the
of
the
received vector r(x) to be stored in the 50-bit buffer register of
the
50-BIT BUFFER REGISTER circuit.
RW/SDI.
This signal is used to select between the read
modes of the MEMORY circuit RAM chip.
In the encode mode
stored vector.
decoder
in
to
The RW/SDI signal is also used to choose
(encode mode) and r(x)
write
this
1s held LOW to enable the encoded vector v(x) to be stored
In the decode mode it 1s held HIGH to allow the
or
signal
memory.
read
between
(decode mode) as the input patterns
the
m(x)
transmitted
to the PARITY AND SYNDROME GENERATOR circuit.
RAM ~.
This signal initializes the MEMORY circuit
RAM
program
counter to zero.
Table 4-3 presents a
list
of
all
the
control
origin, destination and active state (LOW/HIGH).
in tracing each signal from
circuit
to
circuit
signals,
their
This table is helpful
during
the
circuit
descriptions that follow.
4.3.2.2
Description of SEQUENCER Hardware
The starting addresses for the
respectively
addresses
OH
and
encode
200H.
and
In
decode
addition
firmware
to
these
are
two
LIST OF SYSTEM CONTROL SIGNALS
TABLE 4-3.
Signal
Name
I
DREPCS
Figure
4.
t
Active
State
I
H
Subsystem
Figure
4.
I Z6-18
Sequencer
5
Z18-2; Z2 2-2
Data and error
gen.; data storage
9; 11
RDBRS
I Z6-16
I Sequencer
5
Z26 thru Z32-8
50 bit buffer
16
H
PSSRS
I Z6-14
I Sequencer
5
U16 thru U21
pins 1 and 6
Parity and syndr.
gen.
17
H
SCOMPS
I Z6-12;
I
I
Z14-1; U15-2
Master clock;
syndr. bit compl.
18;20
I
H
Master clock
DET TJf computing
18;21
I
H
50 bit buffer;
syndr. compl.;
DET LT
116;21;201
L
19; 20; 17
I
L
lu
I
L
Origin
Z3-9
LTS
I Z6-9;
Z3-12
I
I
Sequencer
Sequencer
I
I
5
5
Subsystem
Destination
Z14-2; U46-3
I
I
CLEAR
I Z6-7
I Sequencer
I
5
I
Z26 thru 32-9;
U46-1; U14-1
LOAD
I Z6-5
I Sequencer
I
5
I
Z18- and Z19-9
US thru U6;
U18 thru U21
Data and error
gen. syndr.
compl., P&S gen.
RAMCS
I Z6-3
I Sequencer
5
Z24-1
Data storage
AXG
I Z5-18
I Sequencer
5
Ul4-4
Modified syndrome
generator
I 19
I
H
DOG
I ZS-16
I Sequencer I
5
Miscorrection
detecting, syndr.
bit compl.
115;20
I
H
I
I
I
Z14-13; U46-11
I
0'\
0'\
TABLE 4-3.
LIST OF SYSTEM CONTROL SIGNALS (Continued)
Signal
Name
I
Origin
Subsystem
Figure
4.
RW/SDI
I
ZS-14
Sequencer
5
DPB
I ZS-12
I Sequencer I
5
I
Z25-1; Z26-2
I
Data storage;
50 bit buffer
TXG
I ZS-9
I Sequencer I
5
I
U15-13
I
Parity and syndrotre generator
PBFG
I ZS-7
I Sequencer I
5
I
U14-13
I
Parity and syndrotre generator
SDIG
I ZS-5
I Sequencer I
5
I
U14-10
I
Parity and syndrotre generator
I· Sequencer I
5
I Z22-1; Z23-1
I
Data storage
RAM
-m I
.
ZS-3
H/L
9; 11
Data and error
generator; data
storage
Z17-1; Z24-14
Active
State
Figure
4.
Subsystem
Destination
I
I
I
I
I
11; 16
I
H/L
17
I·
H
17
I
H
17
I
H
11; 11
I
L
0'\
-...J
68
~s
addresses, the decode program
the routine to address
600H.
forced to jump at a certain
These
three
addresses
selected by the sequencer control hardware.
this purpose as well as the rest
of
the
The
point
are
properly
circuitry
sequencer
is
in
used
for
explained
in
detail with the aid of Figure 4-5 in the following paragraphs.
When the START switch is pressed a 10
sec wide negative pulse
generated by the dual DM9602 one shot (ZlO).
This
The
preset the sequencer program counter with "O".
which consists of three DM9613 4-bit
pulse
counters
is
used
program
connected
is
to
counter
in
parallel
(Z7, Z8 and Z9) selects the nine least significant address bits Ao,
... Ag of the two 2K sequencer PROMS
(Zl
and
Z2).
The
address bits Ag and A10 are selected by the ENCODE/DECODE
switch and the Ql output of flip-flop Zll respectively.
mode address bits Ag and A10 are set to
"O"
by
A1
other
two
mode
toggle
In the
encode
setting
the
ENCODE/
DECODE switch to ground ("O") and by pushing the RESET switch to preset
flip-flop Zll (see Figure 4-5).
The starting address
program is thus set to OH (Ao through A10 =
ro.
for
In
the
the
decode
address bits Ag and A10 are set to "1" and "O" respectively by
the ENCODE/DECODE switch to +5V ("1") and pushing the RESET
preset flip-flop Zll (IQ of Zll
= 0)
as done in the encode
encode
mode
setting
switch
mode.
to
The
starting address for the decode program is thus set to 200H.
During the decoding algorithm it is
syndrone bits in the syndrone generator
circuit output becones "O".
required
until
the
to
Det
complement
LT
The occurrence of a ''0" at the
this circuit is a random event which depends entirely on the
the
coll\)uting
output
data
of
and
69
error patterns being decoded.
Thus, at the
hardwired JUMP command instructs the
occurrence
firmware
to
of
stop
complementing instructions by directing the program
to
There it finds the instructions necessary
the
complementing
process
and
complete
to
the
exit
decoding
a
"O",
the
a
syndrome
address
600H.
syndrome
bit
algorithm.
The
hardwired JUMP command is generated as follows:
The hardware checks to see
if
the
software
=
syndrome bit complementing instruction
(SCOMPS
output of the DET LT circuit
(flip-flop
Q = 1).
1s
zero
is
performing
HIGH)
and
U46,
the
if
Figure
the
4-21,
When both of these conditions are simultaneously satisfied the
JUMP command is generated, see Figure 4-20 U15 pins 1, 2 and
3.
JUMP command is a negative pulse which 1s used to clear
sequencer
program counter (Z7, Z8 and Z9) and to
strobe
address A10 to a "1" as shown in Figure 4-5.
generates address 600H.
the
flip-flop
Thus
the
Zl1
JUMP
The
to
set
command
Figure 4-6 shows a diagram of the 11 sequencer
address bits and where and when they are generated.
To increase the addresses, the program counter is strobed
master clock pulses.
by
the
The occurrence of each clock pulse 1ncreases
the
sequencer address by 1.
Since the encoding and decoding
programs
are
executed in less than 516 instructions, only address bits Ao through Ag
are advanced.
The 16 output lines of the sequencer (Oo through 07 in each of the
two PROMS Zl
and
Z2)
are
connected
to
a
16-bit
consisting of two 74LS377 8-BIT registers Z3 and Z4.
buffer
The
register
purpose
these registers is to allow sufficient time for the sequencer
data
of
to
~
SEQUENCER ADDRESS
AlO
Ag
As
Jl'
'"
1\
A7
f\
.J
7J
BITS
A6
As
A4
I'
1\
r-
A3
A2
Al
'" '" '"
Ao
1[\
OA
Qs
QA
Os
Oc
OD
Oc
Oo
:zg:. l4: Z8-11 ZB-12 ZB-13 ZB-14 Z7-ll Z7-12 Z7-13 Z7-14
OA
~
ENCO
Q]
.f-Zll-6
t
J
--
+5v
DECODE
ENCODE=O
DECODE=l
I Preset to 11 011
at start of
Encode &
Decode routines.
I Set to 11 111 with
presence of 11 Jump"
signal during the
Decode routine
ADDRESS .COUNTER OUTPUTS
•
•
>I
Cleared to start the Encode and Decod e routines
Incremented by "1" during each master clock
occurrence to advance the
ENCODE MODE STARTING ADDRESS = 0H
DECODE MODE STARTING ADDRESS =200H
JUMP
ADDRESS =600H
FIGURE 4.6
SEQUENCER ADDRESS BIT CONTROL SIGNALS
-..J
0
""'
71
stabilize during data access.
The buffer register is strobed with
master clock pulses shifted by 180° from the
PROM counters.
pulses
The data present 1n the buffer
is
that
sent
the
strobe
to
a
the
16-bit
driver consisting of two 74LS244 8-BIT drivers Z5 and Z6 from where
it
is transmitted to the system.
to
The
sequence
of
events
necessary
access the SEQUENCER data as explained above is depicted in Figure 4-7.
4.3.3
Description of MASTER CLOCK Circuit
Figure 4-8 shows the schematic for the MASTER CLOCK
1n the system.
The
MASTER
CLOCK
circuit
performs
circuit
the
used
following
functions:
1)
Provides a 500 KHz clock for the system sequencer.
2)
Provides enabling and disabling logic for the sequencer
pulses at the start and
end
of
the
encoding
and
clock
decoding
programs respectively.
3)
Provides logic to enable and disable the PROCESS COMPLETE LED.
The heart of the MASTER CLOCK circuit is an
(Zl3).
SN555
multivibrator
chip
The output of this IC is a free running 0.5 MHz squarewave used
to strobe the SEQUENCER address counter
and
register as explained in Section 4.3.2.2.
SEQUENCER
16-bit
buffer
When the START switch on the
front panel is depressed a MASTER CLOCK ENABLE pulse is generated.
MASTER CLOCK ENABLE pulse is the
same
pulse
circuit to clear the sequencer program counter
encode and decode algorithms.
used
by
at
the
the
start
In the MASTER CLOCK circuit it
The
sequencer
of
is
the
used
72
f-'1 sec~
1
r----
MASTER CLOCK PULSES
o---'
SAMPLE OUTPUT LINE FROM
PROM
1
o
SAMPLE OUTPUT LINE FROM
BUFFER REGISTERS
I
t.
II ·~ II
1 2
34
5 6
1 - Address counter is incremented.
2 - PROM address lines are in transistion.
During this time· the output lines are
very noisy.
3 - PROM address lines are stable.
4 - Output lines contain the new data,
t 0 + 500nsec.
5 - Buffer register is enabled.
6 - Buffer output lines contain n~w data to be
transmitted to system.
FIGURE 4.7
TIME DIAGRAM FOR SEQUENCER CIRCUIT DATA ACCESS
+5'1
+5'1
f
so o K"W!
J, t/4 ..
':. ff.,-r ~-~l.)c
Sl.J'
2?-o.tL
z
Zl5
GLOC..K
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(?;=1--2)
o. 'r .....t!:.
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E'lJA~E L- - + - - _ j
{?:1o-co
FW~
lo ALL.
130R£DS
H~STER Cl.-0~
(2tb -~)
+-5V
TO LED
1\),(
:3 ~ Le.Dt.f CLR
(2-11-r~), (u..4t:.-t~)
s:; RE".SE"T
51
f't)uJ€1(
DFF
(23-q)
'~ "!
5'C.Ot--·\f'S
LTS
Jl_
(2:"?>-12.)
-
PR,OC.e:S&
C.oHr>L£1£
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SIJ1-l/O~
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l:l~
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RDI)JU£SS IUD
(7::11- 1.1)
zoo.n...
o.IJC1
,~
PU.LS£
cJI./e
vNY+S\1
PowER
LEP 2 ( GIZ.E:E1-1)
LEVi
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P~t..X...E~S
(.OHPLETE
POWE~ 0~
~-
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FIGURE 4.8
MASTER CLOCK CIRCUIT
"-.!
w
74
to clear flip-flop 1 of the SN7474 dual D type flip-flop (Z12).
sets the fQ output of this flip flop to a
11
This
1 11 which in turn enables the
clock pulses to propagate through gate Z15 pin 3 and from these to
the
SEQUENCER circuit.
of
the
encoding and decoding programs by setting the SEQUENCER SCOMPS and
LTS
Gate Zl5 pin 3
lines simultaneously to a
11
is
disabled
at
the
end
1 11 by means of firmware control.
sets the lD input of flip-flop Zl2 to a
output during the next clock cycle.
11
Doing
so,
111 which in turn clears the lQ
This effectively disables gate Z15
pin 3, thus inhibiting the master clock pulses to reach
the
SEQUENCER
and further advance the SEQUENCER address counter.
The simultaneous occurrence of a
11
111 on both the
SCOMPS
and
lines also generates a strobing pulse for flip-flop 2 of Zl2.
LTS
Input 2D
which is always set to +5V (HIGH) is transferred to output 2Q with
occurrence of the strobing pulse.
As can be seen from
the
the
schematic,
this enables the PROCESS COMPLETE LED to turn ON.
Figure 4-8 also shows
the
schematic
for
switches found on the front panel of the box.
the
By
POWER
and
RESET
flipping
the
POWER
circuit
cards
switch to the ON position +5V is applied to all
system
and the POWER ON LED is enabled.
up
the function of the RESET switch.
the lOK and 100
~f
Initial power
also
When +5V is applied to
accomplishes
the
filter shown next to the RESET switch form
system,
a
delay
line which applies +5V used to set and clear certain flip-flops in
system after the +5V power supply
~s
steady.
These
flip-flops that are set and cleared by the RESET switch.
RESET switch functions is to clear flip-flop 2 of
Zl2
are
One
which
the
of
in
the
same
the
turn
75
extinguishes the PROCESS COMPLETE LED.
Other functions
are
described
later in their corresponding sections.
4.3.4
Description of DATA AND ERROR PATTERN GENERATING Circuit
The schematic of the DATA AND ERROR PATTERN GENERATING circuit
shown in Figure 4-9.
Eight
different
data
stored in the 2716 2K X 8 BIT PROM (Z20).
and
The
error
patterns
are
address
and
starting
polynomial representation of each pattern is shown in Table 4-la.
data and error patterns share the same memory locations
However, the data bits are assigned to output bit Oo
bits are assigned to output bit 01.
is
The
in
the
PROM.
while
the
error
The PROM memory allocation for the
data and error bits is shown in Figure 4-10 for data and error patterns
mo(x) and eo(x) respectively.
Any time the PROM is
1n the encode or decode mode,
both
data
and
Oo and 01 are made available to the system.
to use is determined by
the
SEQUENCER
accessed,
error
pattern
labeled
finiMare
as
enabling the selected data pattern to reach
GENERATOR.
which
RW/SDI
the
1s
SYNDROME GENERATOR.
= v(x)
is
+ e(x) to reach the
patterns
controls
the
During
the
kept
PARITY
Similarly, during the decode mode R11/SDI
enable the received vector r(x)
outputs
Which of the two
select line of the 74LS157 quad 2 to 1 multiplexer (Zl7).
encode mode this select line,
whether
low
thus
AND
SYNDROME
set
high
PARITY
to
AND
The data output line Oo is also send to the MEMORY
circuit, where the selected data pattern is processed as
explained
in
Section 4.3.5.
To select the starting address of each
PROM address bits A6, A7
and
As
are
set
data
and
according
error
to
the
pattern,
values
(zh-s)
(t:'-- rG>)
Lo!W
D~R:.,5
1
+5V
----~
' ~r;f--:-CL-:-:-1(
1
T
~a
t-5~
6
..
t -,ilo'
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r-2 c l
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,.--!GO/I)
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,_!fA W(
,_'[ B
I
-
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q li.
1z
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.--' D1
'----,....._...
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Cl$
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(rs--14)
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Ao'
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(UH)( ~21-IDJ
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1
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• v !1:311. G
6---t-...,-1-1 [.1)
f.lZJ
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j
I
''
<>••'•M'Ili(V M(x)'
(!1.15"·/l] ,~ R(x)
l21-= SIJ 51fLS 8C, J EX 0 (l-tllf. q)
R GATE
FIGURE 4.9
DATA AND ERROR GENERATING CIRCUIT
......
0\
77
•k---
ADDRESS BITS ---~~~<-- DATA BITS
ADDRESS AloAg- A8A7 A6A5 A4A3.A2A1 Ao
*0
1
2
3
49
50
51
61
62
63
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 1
1 0
07 06 05 04 03 02 01 oo
X X X X X X 0
0
1
0
X X X X X X 0 0
X X X X X X 0 0
. . .. .. . .. .
. .. .. .. .
. .
. . . . . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
1
X X X X X X 0
0 0 0 1 1 0 0 0 1
0 0 0 1 1 0 0 1 0
0 0 0 1 1 0 0 1 1
X X X X X X 0
0
X X X X X X 0
X
X X X X X X 0
X
. .
. .
. .
.. .. .. .. .
.. .. .. .. .
. .. .. .. .
. . . . . . . .
. . . . . . . .
.
. . . . . .
0 0
0 0
0 0
0 0 0 1 1 1 1 0 l
0 0 0 1 1 1 1 1 0
0 0 0 1 1 1 1 1 1
X X X X X X 0
0 0
0 0
0 0
X X X X X X
X
X X
X X X X X X X X
**64
A8,A7,& A6
01 contains 62____j
selected by
data or error
pattern switches
on front panel
BIT error pattern
(e (X) in example)
0
00 contains 50 --~
BIT data pattern.
(m0 (X) in example)
*ADDRESS 0: Starting address for Data Pattern m0(X) = 0 and Error
Pattern e0 (X) = 0.
**ADDRESS 64:Starting address for Data Pattern m1 (x) and Error
Pattern e 1(x)
FIGURE 4.10
EXAMPLE OF MEIDRY ALLOCATION FOR DATA AND ERROR PATTERN PROM (Z20)
78
determined by the Do, D1, D2 and Eo, E1 and E2 switch settings
front panel.
Address bits
Ao
through As which are
bit A9 is always kept low.
0
Do
A9
A8
0
signal
by
the
to
zero
by
while
address
The starting addresses are either
0
0
0
0
0
0
A5
A4
A3
A2
Al
AO
Eo
0
0
0
0
0
0
As
As
A4
A7
the
controlled
two DM9 316 4-bit counters (Zl8 and Zl9) are initially set
clearing these counters with the sequencer LOAD
on
A6
or
Since in the en~ode mode the 74LS1S7 quad
select line Rlr/SDI is set low
by
the
2
to
1
SEQUENCER
multiplexer
firmware,
address lines As, A7 and A6 are set according to the position
switches Do, D1 and D2 respectively.
(Zl7)
the
PROM
of
data
In the decode mode, RW7SDI is set
high thus enabling PROM address lines As, A7 and A6 to be
set
by
the
value of error switches Eo, E1 and E2.
After the starting address for the data or error pattern has
selected the PROM program counter is incremented one bit at a
using the SEQUENCER generated DREPCS strobe signal.
by
Since the data and
error patterns are less than 64 bits long only the S least
address bits, Ao through As, have to be incremented.
time
been
significant
79
Another function of the data and error pattern generating
1s to add the error pattern to
the
encoded
vector
accomplished by exclusive-oring both sequences bit
This
v(x).
by
circuit
bit
using
is
the
54LS86 EXCLUSIVE-OR gate (Z21).
4.3.5
Description of DATA STORAGE Circuit
The schematic for the DATA STORAGE circuit
4-11.
1s
shown
in
Figure
It consists of a 2125A lK X 1 bit RAM chip (Z24), two 9316 4-bit
counters (Z22 and Z23) and a 74LS157 Quad 2 to 1 multiplexer (Z25).
In
the encode mode the encoded sequence "v" is send bit by bit to RAM
v1a
the 2 to 1 multiplexer.
low
The multiplexer select line "DPB" is
by the sequencer firmware until the first 50
received and stored in RAM.
message or data sequence "m".
bits
of
"v"
set
have
These are the 50 bits corresponding to the
After all
50
message
bits
have
received the multiplexer select line is set high.
This allows the
to receive the 12 parity bits from the PARITY and
SYNDROME
circuit.
In the meantime, the RAM address
with the two 4-bit counters, Z22 and Z23.
selection
is
been
RAM
GENERATING
accomplished
These counters are initially
cleared by the RAM~ signal thus allocating address OH for the
transmitted bit of "v".
been
The RAM addresses are
increased
the program counter with the same pulses (DREPCS) used
by
first
strobing
to
strobe
the
data generator program counter described in Section 4.3.4.
After
the
address
RAMCS,
1s
has
been
selected
the
RAM
chip
select
line,
momentarily enabled to all<M the encoded vector bit present at the
input to be stored in its allocated memory location.
encoding process the RAM read/write input, R/W,
is
RAM
During the entire
kept
LOW
by
the
(~5'-$)
IZ.~Hm
(~b-IB)
t>I2E"PC.~
.,.5V
T""
L
PIUt. IT'f ~ H
:DAT'~r
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;>
+51./
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1-
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A
g
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A~
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A,
iii
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If
If/
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:J ~ND
I$
V,C..t. SEL.
I
2.
J)l:tTA
SIT.S
(ezo-q)
3
PArt.ITY
BIT.$
( LL'2.1- II)
Q~
0
,-1.! A, 2125A
2.
Ve.c..
A
u
'~t-<..
1/ A2
I
·~
A~
-w:
L
2.
II.
' .DP.13
( l;S-12..)
<!ZI.-2)
;')
1-
--7 ~(x..)
(221-2)
( ?:21·10)
.~.-
IV1M
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C.S (rl.-3)
I'll
RtO
-~
I
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(
,.,,€,.
IZCAD~
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w~tr£"-=
L.
FIGURE 4.11
DATA STORAGE CIRCUIT
CXl
0
81
SEQUENCER control signal RW/SDI to allow the RAM chip to store the data
present at its input.
The storage process· for the
shown in the time diagram of Figure 4-12.
encoded
vector
is
The baseline for the diagram
is the system master clock pulses which strobes the
system
sequencer.
The memory allocation for each of the bits of the encoded vector "v" is
presented in Figure 4-13.
In the decode mode the stored encoded
from RAM in two occasions.
by bit
to
the
transmitted
is
respectively.
are
added
to
Section 4.3.4.
line
high
and
GENERATOR
bit
followed
for
by
decoding.
bits
The
VGO•
retrieved
preselected
error
bit
and
vo
bits
in
The vector "v" is read from RAM by setting the RAM
R~
clearing
the
as
above
described
initially
pattern
the
bit
first
v59
Before reaching the SYNDROME GENERATOR
the
~s
vector
First, the sequence "v" is transmitted
SYNDROME
v61
data
program
counter
incrementing it .until all 62 bits of "v" have been fetched.
The second
occasion in which the encoded vector is read from memory is to
the decoded data to the message portion of
first 50 bits of "v",
V61
through
MISCORRECTION DETECTING circuit.
v12,
"v".
to
be
This
before
compare
requires
transmitted
the
to
the
During this process the RAM RfW
line
is held high and the program counter is used to count from address 0 to
address 49.
The RAM chip select line RAMiCS is enabled
decoding sequence.
throughout
the
This differs from the encode mode where the
whole
RAM
line can only be enabled when the data bit present at the RAM input
stable.
For data fetching, even though the data may
be
noisy
CS
~s
during
82
..-
.
..-
0
0
....-
0
..
....-
0
0
:
~
~
DISABLE RAM - DATA STORAGE
PROCESS Cm1PLETE
STORE INPUT DATA BIT 11v 011 .
IN LOCATION 61
+- INCREMENT ADDRESS COUNTER TO 61
"i:-- DISABLE RAM UNTIL NEW DATA "v
58
IS AVAILABLE AT INPUT
II
i
'~
~
STORE INPUT DATA BIT "v 59
IN LOCATION 2
II
~t.!l
INCREMENT ADDRESS COUNTER TO 2
<
H
~
~
H
~
DISABLE RAM UNTIL NEW DATA "v 59
IS AVAILABLE AT INPUT
II
N~
.-i
• tf.l
--::ttf.l
~
~(.)
~~
~
STORE INPUT DATA SIT 11 v60
IN LOCATION 1
t.!lP-1
H
II
r.>:<~
~
0
~
tf.l
~
INCREMENT ADDRESS COUNTER TO 1
~
DISABLE RAM UNTIL NEW DATA "v 60
IS AVAILABLE AT INPUT
~
STORE INPUT DATA BIT 11v 61 11
IN LOCATION 0
~
SELECT RAM ADDRESS 0H BY
CLEARING ADDRESS COUNTER .
RAM IS IN WRITE MODE
<
~
~
II
L
:
0:::
LJJ ::...::
1-
[j
:E
c( ...J
c(
L)
0:::
:E
0
V)
L)
V)
L)
VlO
. ..
........ :E
13:
0:::
c(
0:::
.•
V)
L)
c...
LJJ
0:::
0
II
83
ADDRESS
MEMORY
CONTENTS.
0
v61= m49
v = {v61 ' v60 ' . . . v0)
1
v6o= m48
ENCODED VECTOR
2
v59= m47
3
m = (m49' m48' ·
.mo)
DATA VECTOR
v58= m46
p
= {pll,plO''
. ·Po)
PARITY BIT VECTOR
49
v12= mo
50
vll=
51
v10= P10
X= Don't care
Pn
60
61
62
X
1023
X
FIGURE 4.13
RAM MEMORY ALLOCATION
~
~
84
address changing, the RAM is kept enabled at all times.
In
this
case
the destination circuits are disabled during the tnne unstable data
present at the RAM output.
A data fetching time diagram
is
is
presented
in Figure 4-14.
4.3.6
Description of MISCORRECTION DETECTION Circuit
The MISCORRECTION DETECTION circuit is shown in Figure 4-15.
1n the decode mode and just before each bit of the
decoded
When
vector
is
shifted out of the decoder, gate Zl4 is enabled by setting control line
DOG high.
The decoded sequence and the original message
exclusive-ored bit by bit by gate Z21 pins 9 and 10 to
discrepancies between the two sequences.
sequence
check
for
are
any
If a discrepancy exists a "1"
?utput will result out of the exclusive or gate for the bit
in
error.
This "1" propagates through gate Zl4 pin 12 and strobes the 7474 D type
flip-flop (Zll).
The D input of the flip-flop 1s always set high thus causing theQ
output to clear at the occurrence of the strobing pulse.
As
can
seen from Figure 4.15, forQ=O the MISCORRECTION LED is
enabled,
be
thus
indicating an error in the decoded data sequence.
If no discrepancies occurred between the two vectors,
of the exclusive or gate remains low.
never strobed and thus Q remains high.
is disabled thus
correctly.
indicating
that
the
The
D
flip-flop
For "Q=l the
received
the
is
output
therefore
MI SCORRECTION
vector
was
LED
decoded
85
.
.
.•
.
..-Or-Or-Or-
0
..-
.
~
RAM CHIP
~DISABLE
~
INCREMENT ADDRESS COUNTER TO 61.
BIT V0 AVAILABLE AT RAM OUTPUT
11
11
INCREMENT ADDRESS COUNTER TO 3.
v u AVAILABLE AT RAM OUTPUT
58
+-- BIT
11
INCREMENT ADDRESS COUNTER TO 2.
· BIT v59 u AVAILABLE AT RAM OUTPUT
~
II
11
!
-E-
.
0:::.
~~
1--U
V>O
C::C....J
::EU
:
0
V>
::E
.........
0:::
0:::
c::c
3
"V>
•u
::E
c::c
0:::
V>~
u
0..
~
0:::
0
INCREMENT ADDRESS COUNTER TO 1.
BIT uv u AVAILABLE AT RAM OUTPUT
60
ENABLE RAM; SET TO READ; SELECT
ADDRESS 0 BY CLEARING ADDRESS
COUNTER. BIT v61 u AVAILABLE
AT RAM OUTPUT
~RAM
11
tS'I
cC...C D E:C
l)
l)qTA
YEC.TD~
~r----,~~ f
..,I (.i:.) )
·ZOf
(l.Z.I·'-)
~··
I
'l I I
''let.~
IOl
+5"
l~U-u,G.
LED!
(tEl))
H ISC..D ~ t!EGnoN
tRS
lA N!..Ott. I< IA.F'T'EJ:)
Y..,w •
.SE"RIAL. OAT"l
F t<oH ltA-M
( 't.2.t# -
...
2crii
1)
'DO~
('!5·14)
~e-seT
( iiZ-13)
Z.ZI =- 5/1151./LS 8'e:,
'!. ll.f -=
SIJ ?l/ 0 ~
FIGURE 4.15
MISCORRECTION DETECTION CIRCUIT
CX>
0\
87
~ressing
The MISCORRECTION LED can be extinguished by
the
switch on the front panel and it remains ext in~ ished until a
RESET
received
data vector is incorrectly decoded.
4.3.7
Description of RECEIVED DATA BUF.FER REGISTER
This
The RECEIVED DATA BJFFER REGISTER 1.s shown in Figure 4-16.
circuit is used in the decode mode
to
temporarily
message portion of the received vector r(x).
store
the
SO bit
The vector remains in the
register until the algorithm 1.s ready to start decoding each bit
time.
The SO bit buffer register consists of seven S4164
registers (Z26 through Z32) connected in series.
registers are cleared by the SEQUENCER CLEAR
setting signal DPB low.
At the time the
Initially
signal
decoding
the received vector to be stored in the buffer
8
and
BIT
a
SIPO
all
seven
disabled
algorithm
register,
at
by
requires
DPB
is
set
high to enable the first 8 BIT register Z26 and thus allow the received
sequence to be shifted serially into all the
other
8
bit
registers.
Strobing of the registers is accomplished with the SEQUENCER
RDBRS pulses.
After all· SO bits have been shifted into the
strobing is ceased
information
to
be
and
the
DPB
erroneously
line
is
shifted
set
into
low
the
to
generated
registers,
prevent
registers.
The
registers are strobed again when it is time to decode each stored
Again this is acconplished with the RDBRS pulses.
This time,
strobing the registers causes the stored vector to be
the circuit through Z32 pin 4.
or gate Z21 pins 4 and S.
shifted
From the Massey
decoding
with
bit.
however,
Each bit, as it 1.s shifted out
register, is added to the output of the DET LT circuit
any
out
of
of
the
exclusive
algorithm
it
is
+5V
~ ::0 F'(3
(e6"-1~)(e2~-l)
~DSR.S
......
( 'll.-1(,)
CLERR
(2~·q)
~
f<DBf<. .I.:NPtAT
( (01<~ l.At'T Cl) l)AT~)
( lJ.&/l,- 5)
'OE.TLr
,.
u
( v.ts-•z.) (u.J4.-Cf )(2r?--J2)
l2 I ::: 5N Sl/1..5
(±)
~~
"t 2.~ THRU.. l "32-:: 9J 5"11 1?:,4
ZZI
~
D£C...OOE"D
VE'vTOR.
(t:ZI- q)
FIGURE 4.16
RECEIVED DATA BUFFER REGISTER
co
co
89
known that the output of the DET
that are in error and
l.S
Lr
circuit is a "1" for bits
of
r(x)
a "O" for bits of r(x) that are correct.
Thus
the output of the exclusive or gate represents the
correct
the decoded bit rj of r(x) where j = 61, 60 ... 12.
This
value
is
for
verified
by sending the decoded sequence to the MISCORRECTION DETECTION
circuit
discussed in Section 4.3.6.
4.3.8
Description of PARITY AND SYNDROME BIT GENERATOR
The
PARITY
Figure 4-17.
AND
SYNDROME
BIT
GENERATOR
circuit
is
shown
in
The heart of the circuit are the six 7474 dual J-K master
slave flip-flops (Ul6 through U21) used for the 12 bit shift
register.
These flip-flops were used instead of more convenient D type flip-flops
because of the unavailability of the latter at the time the circuit was
designed
and
implemented.
However,
the
D
type
flip-flops
improvised with.J-K flip-flops by applying the inverse of the
to its K input.
This procedure is shown in Figure 4-18.
J
Both
were
input
of
the
configurations shown in Figure 4-18 are equivalent, however, the use of
the
J~K
flip-flops required some additional
connections
and
hardware
unnecessary when using D flip-flops.
4.3 .8 .1
Determination of Shift Register Feedback Connections
The feedback connections for the shift register were obtained from
the codes generator polynomial g(x).
This
polynomial
using the characteristics of BCH codes discussed
from equation 2.4.
1.n
is
Section
For convenience these are repeated below.
calculated
2.1
and
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FIGURE 4.17
PARITY AND SYNDROME GENERATOR
1.0
0
91
D FLIP FLOP
INPUT
D
OUTPUT
Q
D
Q(t.+1)
Q
0
1
0
1
INPUT
OUTPUT
CLK
J-K FLIP FLOP
J
Q
-
K
CLK
Q
J
K=J
0
1
0
1
0
1
o(t+1)
FIGURE 4.18
J-K FLIP FLOP CONNECTION TO SIMULATE D 'IYPE FLIP FLOP
=
a)
n
2m - 1
b)
n-k
c)
dmin 2_ 2t+l
< mt
(4 .1)
and
g(x)
LCM (ml (x)
. m3 (x)
• m2t-l (x))
For the (62,50) shortened (63,51) BCH code chosen for
in Section 3.3
n
=
63
and
t
= 2
(see Table 3-2)
Thus, from equation 4.la
m= 6
(4. 2)
the
system
92
and from equation 4.2
g(x)
=
LCM Cm1 (x) · m3 (x))
For m = 6, m1 (x) and m3Cx) can be
obtained
from
Appendix
C
in
reference [3] as:
m1 (x)
=
x6 + x + 1
m3 (x)
=
x6 + x4 + x2 + x + 1
and
Hence,
g(x)
g(x)
LCM ((x6 + x + 1) (x6 + x4 + x2 + x + 1))
=
Thus the feedback path in the shift register 1s connected
to
register
stages 0, 3, 4, 5, 8, 10 and 12 respectively.
4.3.8.2
Generation of Parity Bits p(x)
In the encode mode, the shift register is cleared
enabling the SEQUENCER
LOAD
line.
This
action
CLEAR 0 through CLEAR 11 (see Figure 4-20 gate US).
by
mone ntarily
generates
The SEQUENCER also
enables the feedback path and m(x) input gate (U14 pins 13 and
setting signals PBFG and SDIG to a "1".
signals
10)
by
In the meantime the input gate
(U15 pin 13) for r(x) is disabled by setting signal '1XG to "0".
With
the initial encode set up corrpleted the 50-bit nessage is shifted
into
the register by strobing the clock input of each register
with
signal
93
PSSRS.
After all 50 bits of m(x) have been shifted, the feedback
path
as well as the m(x) input gate are disabled by setting PBFG and SDIG to
11
0 11 •
The shift register at this time contains the 12 parity bits
p(x)
of m(x) where:
p(x)
Rem (x12 m(x)/g(x))
=
The parity bits are
now
shifted
out
(4. 3)
of
the
gate U23 pin 8 and are transmitted via a 2 to 1
RAM chip (Z25 and Z24 respectively in
Figure
register
multiplexer
4-11)
to
through
into
the
complete
the
encoded vector v(x) where
=
v(x)
4.3.8.3
m(x) + p(x)
(4.4)
Generation of Syndrome Bits s(x)
~s
To decode the received vector r(x), the shift register
used
to
obtain the syndrome s(x) of r(x) where
s(x)
=
Rem (r(x)/g(x))
(4. 5)
This usually requires r(x) to be shifted into the register at
stage 0 (U16 pin 4).
register
However, the received vector is a shortened
code
vector and therefore has to be preiD.lltiplied by a polynomial T(x) where
T(x)
=
Rem (xS/g(x));
s =number of bits shortened
(4 .6)
In this case, for s = 1:
T(x)
=
=
X
94
and hence
s(x)
=
(4. 7)
Rem (x·r(x)/g(x))
The syndrorre of r(x) is therefore computed by shifting
r(x)
the shift register at register stage 1 rather than at stage 0.
circuit, this is accomplished by enabling
pin 13) by setting signal TXG to a "1".
the
r(x)
input
In the meantime
into
In
the
gate
the
(Ul5
feedback
path gate (Ul4 pin 13) is enabled and the m(x) input gate (Ul4 pin
disabled by setting signals PBFG and SDIG to "1" and "O"
The initial decode mode set up is completed by clearing
10)
respectively.
all
registers
with the LOAD signal as previously explained for the encode mode.
62 received vector bits are now shifted into the
each flip-flop clock input with signal PSSRS.
circuit
strobing
After all bits have been
shifted into the register signal TXG is set law
input gate.
by
The
to
disable
The register at this time contains the
syndrome
the
r(x)
s(x)
of
r(x).
4.3.8.4
Syndrome Bit Complementing
The next step in the decoding process is
to
bits so through szt until the output of the DET
This 1s accomplished with the SYNDROME BIT
discussed in Section 4.3.10.
~
complement
LT
circuit
the syndrome bit to be complemented and then either sends
to
be
zero.
a
value
of
CLEAR
or
complemented.
DET LT circuit in the meanwhile uses syndrome bits so
calculate the determinant of LT.
1s
BIT COMPLEMENTING circuit
This circuit reads the present
PRESET signal to the shift register stage
syndrotiE
through
The
s11
to
This process is further explained
in
95
Section 4.3.11.
After syndrome bit
complementing
1s
syndrome bits are exclusive-ored with the modified
polynomial a(x) discussed in Section 4.3 .9.
The
completed,
syndrome
new
the
generator
syndrone
s' (x),
where
s'(x)
=
(4.8)
s(x) + a(x)
is again used to calculate det(LT).
This time however
the
the DET LT circuit is used to correct the received vector
in the 50 BIT HJFFER REGISTER of Section 4.3.7.
output
bits
Each time one
of
stored
of
the
REGISTER
the
SYNDROME GENERATOR shift register is also shifted, thus creating a
new
received vector bits is shifted out of the 50 BIT BUFFER
syndrome and new determinant of LT for every bit to be corrected.
This
process is repeated until
been
all
50
message
bits
of
r(x)
have
decoded.
4.3.9
Description of MODIFIED SYNDROME GENERATOR
The schematic for the
shown in Figure 4.19.
MODIFIED
This
circuit
SYNDROME
is
used
polynomial s(x) of r(x) to the modified syndrome
a(x).
The result of
this
addition
produces
GENERATING
to
add
circuit
the
generator
the
is
syndrome
polynomial
modified
syndrome
polynomial s' (x) where:
s'(x)
=
(4.9)
s(x) + a(x)
The decoding algorithm requires the use of a(x) after syndrome bit
by bit complementing is finalized.
Until then, as well as
entire encode mode, the circuit is disabled by setting AXG
during
to
"O"
the
at
96
r')
"'
I
(f)
'::5
"
,._'--ill
\1)~
X
t1'"
0
\n-
+
X
...
~
N
n-
:j
X
....
<r-
V)
t')
~
X
::..,
tl(
'-
V)
(\1
,4-
0
\!j
l1l
D(
\...
-
u..
-:s
f"'
--
~
V')
Jl
....
0
V)
~
""
G
\1)
,....
VI
(1
~
\)
-vtil
/"""'
...
.._
l<)lu
0
\l'l
r
0
lL
~
-J
.....__,
\
~
l-
)(
"-..J
-:!""
0
~
}:
,,
,.......
V)
l.u
+
x
ri-
\1)
:t:.
t1
"X
""
~
!.U
+
,),.
0
~
~
...$)
Oo
'\I)
~
ln
"<
\/)
~
()
0
N
~
II
.....
(\
"'::t1\J
~
-
0
0
\/)
'0
:tJi..
~
V)
97
gate U14 pin 4.
to s (x).
This results in a(x) being zero and s'(x) being
When the use of a (x) is required line AXG is set to
11
equal
1 11
thus
enabling the addition of a(x) to s(x).
4 .3. 9 .1
De termi.. nation of Modified Syndrone Generator Polynomi.. al a(x)
The polynomial a(x) is obtained by assuming that the only
r(x) in error is bit r61 as explained in Section 2.3.5.
a(x)
=
Rem (e(x)/g(x))
bit
Therefore,
Rem (x61jg(x))
=
of
(4.10)
Since r(x) is a shortened code vector a(x) is actually cou:puted as
a(x)
=
Rem (T(x) e(x))/g(x))
Rem (x · x61jg(x))
=
As can be seen 1n Figure 4-19, the position of each exclusive
used to add s(x) to a(x) corresponds to one of the
powers
(4.11)
or
of
"x"
gate
1n
a (x).
4.3.10
Description of SYNDROME BIT
~
BIT COMPLEMENTING Circuit
The schematic for the SYNDROME BIT BY BIT COMPLEMENTING circuit is
shown in Figure 4-20.
The principal components of this circuit are the
9316 4-bit counter (U1) and the 9311 4 to 16 demultiplexer (U2).
The
output of the 4-bit counter is decoded by the demultiplexer and used to
select the syndrone bits to be conplemented as shown in Table 4-4.
4-bit counter is cleared at
the
start
of
the
decoding
routine
The
by
+5V
L/10..!2
21'5
j
(.!..(
f .,I)
1Q
i&
5'
I
1~ (.
N·C.
-r
G~.r>
UlJf.
f'
I
ztJ-L '-l•G.
r--+-+~~---t---J-.:.-......---1--+-=-+-~ LOAD
(!(.-5)
I
?Wf.'fj
V:J•
~ESET
(liZ.- 1~)
U/5''!. s~ t-4oo
ug.) uq I
U SJ U Ill = SAJ 1'1 Of
U.. '!> -:: SN 14Dlf
zJ:)
1'5¢ CLR<$
::DO("
(2.5- It)
(
CU?:3
)
THeiL CLRti
PSi
IC
CU~i
CLEA,e5
1'52. C.LI12.
PIU211'/
;~~F'I"n:
4 S'/A-1Df201-'\E-..
G.EtJERA71'·~ .SHifT Rc61STER
FIGURE 4.20
SYNDROM BIT COMPLEMENTOR
"'co
/
/
99
TABLE 4-4.
TRUTH TABLE FOR SYNDROME BIT COMPLEMENTER
4 BIT COUNTER
Decoder
Output
4 Bit Counter (Ul) Output
0·1
Enabled
Syndrome Bit Sj to be
Com:p leme nted
Qn
Qc
QB
QA
1
0
0
0
0
0
None
0
0
0
1
1
0
0
0
1
0
2
1
0
0
1
1
3
2
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
J
This condition will never
occur.
For t=2
highest syndrome bit
complemented is s 2
100
momentarily sending a low CLEAR signal.
11
that an all
From Table 4-4 it can be
0 11 counter output selects decoder line
none of the syndrome bits.
To
increment
the
Oo
which
counter,
affects
both
of
conditions necessary to perform syndrome bit complementing have
satisfied.
1)
seen
the
to
be
These again are
tr.
has to
SCOMPS
has
Lr circuit, signal DET
The output of the DET
be
a
"1".
2)
The syndrome
bit
coup lementing
command
to
be
present.
In the circuit the SCOMPS signal is used to strobe the
If DET LT
=
4-bit
1, the counter CLR line is disabled and the occurrence of a
SCOMPS pulse causes the counter to increment
from
OR
to
Table 4-5 it can be seen that this results in syndrome
complemented.
DET
Lr = 0.
disabled.
Syndrome
At this
bits
time
the
are
complemented
counter
is
bit
so
to
order
in
cleared
From
lH.
(CLR
=
be
until
0)
and
The next SCOMPS strobing pulse will not cause the counter to
increment, but instead will generate a
JUMP
SEQUENCER to JUmp out of the
bit
explained 1n Section 4.3.2.2.
syndrone
signal
that
causes
conplementing
the
routine
as
The JUMP signal is generated at gate UlS
pin 3 by NAND'ing the SCOMPS pulse and the
signal.
counter.
conplement
of
the
DET LT
The truth table for this function is presented in Table 4-6.
As previously mentioned, the output of the 4 to
16
demultiplexer
is used to select the syndrome bit (so through s4) to be
conplemented.
The demultiplexer outputs 01 through Os are send after
being
inverted
101
TABLE 4-5.
TRUTH TABLE FOR JUMP FUNCTION
JUMP
SCOMPS
0
0
1
0
1
1
1
0
1
1
1
0
JUMP
TABLE 4-6.
c ircuit
.
LOAD
-
Qi
Syndorme Bit "i"
After Completrenting
Qi
COMPi
-CLRi
PRESETi
0
-< i -< 4
0
X
X
0
1
0
1
0
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
0
1
l
1
I
LOW
TRUTH TABLE FOR SYNDROME BIT "i"
COMPLEMENTING LOGIC
Circuit Output Signals
Input Signals
= ACTIVE
O<i<4
l
0
102
(see U3) to an array of AND and NAND gates (U5
gates are used
to
determine
whether
the
through
syndrome
UlO).
These
generator
shift
register stage containing the syndrome bit to be complemented shall
either cleared or preset.
Each of the Q outputs of the
five
stages, so through s4, that may be colll' leme nted is read by
When a complement signal "COMPi"
l.S
register
the
array.
g1.ven for one of the syndrome
(in this case Si) signal CLRi is set to 0 for 1h=O or signal
set to 0 for 1h=I.
bits
PRSTi
When no COMPi signal is given, both CLRi and
are set to "1 11 thus not affecting syndrome bit Si.
A
be
is
PRSTi
coiqllete
thruth
table for this process using syndrome bit si as an example is presented
in Table 4-6.
It can also be seen that the complete syndrome
register
can be cleared by setting SEQUENCER signal "LOAD" momentarily
"0".
to
This is done at the start of both the encoding and decoding routines as
explained in Sections 4.3.8.2 and 4.3.8.3.
The last part of the SYNDROME BIT
consists of the two
7474
flip-flops use the DET
Lr
D
type
signal
sequencer "DOG" signal to detect
patterns of weight 3.
BY
BIT
flip-flops
from
the
COMPLEMENTING
U46
DET
uncorrectable
LT
but
and
U51.
circuit
weight 3 the DET LT signal will always be zero.
and
detectable
For
error
the
error
patterns
of
This fact is' used
by
this circuit to enable the UNCORRECTABLE ERROR PATTERN LED.
Both
flip-flops are reset before the start of the decoding routine.
Lr
These
The three error-error patterns are uncorrectable
by the code but are 100 percent detectable.
the routine, if DET
circuit
never becomes a 1, flip-flop
strobed thus leaving output Qat 1.
U51
fails
7474
During
to
be
103
The second flip-flop is strobed by signal "DOG" during the bit
bit decoding of all 50 bits in the 50 BIT BUFFER REGISTER.
by
A "1"
at
input D changes output Q to a ''o" thus enabling the UNCORRECTAJLE ERROR
PATTERN LED.
If, however, during any
time
of
the
decoding
routine
DET 1r becores a "1", flip-flop 1 is strobed thus causing its Q
to becotre a
11
0 11 •
When flip-flop 2 is strobed later on
Q output remains at "1" thus keeping the
LED extinguished.
turns
on
for
by
UNCORRECTABLE
"DOG",
ERROR
I t is ~rthwhile to tre ntion that this LED
error
patterns
of
weight
greater
output
than
the
PATTERN
sotre times
3.
characteristics of some of these error patterns are such that
The
~n
sore
instances the decoder is able to detect or correct them.
4.3.11
Description of DETERMINANT OF LT (DET LT) COMPUTING CIRCUIT
The DET LT circuit is shown in Figure 4-21.
It uses the output of
the MODIFIED SYNDROME GENERATOR to calculate the following equation.
(4 .12)
The result of this equation is used twice in the
algorithm.
First,
to
determine
which
of
the
Massey
decoding
syndrome
bits
so, s1 ... s4 are to be complemented and second, to determine which of
the 50 message bits of r(x) have to be corrected.
for the first case is the following:
The
procedure
used
104
I
a
lf
105
1 - After the syndrome s(x) of r(x) has
been
obtained,
use
the
output of the modified syndrome generator, which in this case is
s'(x)
=
s(x) + 0
to calculate Det(Lt).
! -
If Det(Lt)
=
0
enable the SYNDROME BIT COMPLEMENTING circuit by
circuit out put line "DET
Lr"
setting
the
DET
LT
to a "1".
3- Every time a syndrome bit ~s co~q>lemented recalculate Det(Lt).
!±_ - when DetCLt) = 0
disable the SYNDROME BIT COMPLEMENTING circuit and generate a
firmware
JUMP signal by setting signals
DET
Lr =
To decode the
50
0
and
bit
=
DET LT
message
1
portion
of
r(x)
the
following
procedure is followed:
1 - Use the output of the modified
this case
syndrome
generator
which
in
Lr
of
~s
s'(x)
=
s(x) + a(x)
to obtain Det(Lt)
2 - Add the bit to be decoded "ri" with the output line DET
the DET
Lr circuit.
106
1-
If Det(Lt)
=
set output line DET
Lr
0
to a "1".
The bit to be decoded is
assuned
to
assumed
to
be in error and wi 11 be conp leme nted
ri decoded
=
+
ri undecoded
1
thus,
ri decoded
~-
=
?I
undecoded
If Det(Lt) = 1
set output line DET
Lr
be correct and will not be
ri decoded
"O".
to a
=
The bit to be decoded 1s
co~lemented
+
ri undecoded
0
thus,
ri decoded
~
=
ri undecoded
- Repeat steps 1 through 4 above until all 50 bits stored in the
50 BIT BUFFER REGISTER have been decoded.
The representation of the equation to calculate Det(Lt)
in
terms
of the actual syndrone bits so, s1 . • . su is presented next.
For the (63,51) 2 error correcting code where m
=6
(4 .13)
Let (ao, a1 ... as) be the 6-tuple representation of s1
Similarly, let (bo,
b1
bs)
be
the
6-tuple
=
s( a ) .
representation
of
107
s3
=
s(a3) and
Ceo,
c1 ... cs) to be
6-tuple
representation
where ai is a primitive element of GF(26) ~btained from
polynomial p(x) = 1 + x + x6.
the
of
s13,
primitive
This polynomial is listed in Table
of reference [2] as a primitive polynomial for m=6.
The
Galois
2-3
field
of z6 elenents for this polynomial is sh~n in Table 4-7.
Then,
s(a)
(4 .14)
From Table 4-7, a6 thru all can be expressed in terms of 1, a, a2,
d+
and aS.
a3,
Thus,
(4.15)
Rearranging equation 4.1S
=
s (a)
=
(4 .16)
Hence, the coefficients of the 6-tuple representation of 81
... as) can be expressed from equation 4.16 as
foll~s:
=
(ao,
a1
108
TABLE 4.7
THE GALOIS FIELD OF -26 ELEMENTS
WITH p(a) = a
6
+ a+ 1 = 0
0
1
a
a2
a3
a
4
as
a
6
=
a + 1
a 7 = a 2 +a
8
a
= a 3 +a 2
a 9 = a 4 +a 3
10
a
=as+ a 4
a 11 = a 6 +a s =a s +a + 1
12
= a6 +a 2 +a =a 2 + 1
a
13 = a3
a
+a
14 = a4
a
+a 2
1S = as
3
a
+a
16
= a6 +a 4 = a 4 +a + 1
a
al7 =as+ a2 +a
a
18
= a6 + a 3 + a 2 = a 3 + a 2 + a + 1
19 = a4
2
+a 3 +a +a
20
a
= as + a4 + a3 +a 2
21
= a6 +a s +a 4 +a 3 = a s + a 4 + a 3 + a + 1
a
a
109
TABLE 4.7 (Continued)
a.
a
a
22
23
24
= a6
+a s +a
4 +a 2 +a
a 6 +a s +a 3 +a
= a6
4
+a
+a =a
4
= as
+ 1
a2S = a s +a.
a
a
a
a
a
a
a
26
27
28
29
30
=a
= a
6
3
= a4
=a
= a
s
s
2
+a
2
+a
3
+a
2
4 +a + 1
= a3 + 1
a 3S
+a
+a
32
a 34
+a
4 +a 3
= as
= a4
+a + 1
+a
31
a33
=a2
2
+a
+ 1
+a
as +a 2
= a3
+a+ 1
a 36 = a 4 +a. 2 +a
a37 = as +a 3 + a2
a
38
3
= a4 +a +a+ 1
a 39 = as +a 4 +a 2 +a
a
a
a
a
40
41
42
43
as +a 3 +a 2 +a + 1
2
3
= a4 +a +a + 1
= a
s + a.4 + a3 +a
= as
+a
4 +a 2 +a + 1
a 44 = as + a3 +a. 2 + 1
a
4S
= a4
+ a3 + 1
a 46 = as + a4 +a
= a.s
+ a.
3
+a
+ 1
4
+a
2
+ 1
110
TABLE 4.7
(Continued)
2
a.4 7
= (1.5
+ a.
48
= a. 3
+a
(1.49
= a.4
+ a.
50
= (1.5
+ a. 4 + a. 2
51
= a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
a.
52
53
54
55
56
57
58
59
60
61
62
63
a.
=
a.
a.
= a.
a.
= a.
5
a.
= a.
= a.
1
+ 1
3 + a.
3
+ a. + 1
4 + (1.2 + 1
5
4
5
4
5
= a. 5
= a.
+ a.
2
+a. + 1
5
5
5
5
+ a.
+ a.
+ a.
+ a.
+ a.
+ a.
+ a.
+ a.
+ a.
+ 1
3
2
3
3
4
4
4
4
4
+ a.
+ a. + 1
+ a.
+ a.
+ a.
+a.
+ a.
+ a.
+ 1
2
2
3
3
3
3
+ a.
+ a. + 1
+ a.
+ a.
+ a.
+ 1
2
2
2
+ a.
+ a. + 1
+ 1
111
ao
=
so + 86 +su
al
=
Sl + 86 + 87 +su
az
=
sz + S7 + ss
a3
=
S3 + sa + sg
a4
=
84 + s9 +slO
as
=
ss + s1o +
8
(4 .1 7)
11
gl3, however, is obtained from the fact that
gl3
Thus,
to
=
obtain
s(a) 3
sl3,
=
Sz
S2 = s(cx.2) can be obtained as
=
s(a2) s(cx.)
has
to
be
= Sz sl
obtained
(4 .18)
in
addition to Sl.
foll~s:
=
+ S4(Q8) + ss(alO) + S6(a12) + S7(al4)
+ ss(al6) + sg(al8) + slo(a20) + 81l(a22)
Using again Table
=
s (a2)
4~7
(4 .19)
and rearranging Equation 4.19
=
+ (s3 + ss + sg)cx.+ (8 1 + S4 + 86 + 87
+ s9 + 810 + s u)a2 + (s4 + s9 + slO)a3
+ (sz + ss + S7 + ss + 8 10 + su)a4
+ (ss +
B!Q
+ su)cx.S
(4 .20)
112
s3 can be represented in 6-tuple form as (do, d1
ds)
where
from
Equation 4.20
do
=
SO + S3 + S6 + sa + sg + Sl1
d1
=
S3 + sa + sg
dz =
(4.21)
sl + s4 + s6 + S7 + sg + s10 + s11
d3
=
s4 + sg + s10
d4
=
sz
+ ss + S7 + sa + S10 + s11
=
Using Equation 4.17, these coefficients can be expressed 1n
terms
of ao, a1 ... as as follows:
=
=
=
(4.22)
=
=
=
813
= Sz
81 can be
obtained
by
multiplying
the
respective
6-tup1e
representations of 82 and sl
=
(4. 2 3)
113
Multiplying out Equation 4.23 and using the properties of modulo 2
addition the following values for co, c1 ... c5 are obtained:
=
=
(4. 24)
=
The next step is to obtain the 6-tuple representation of 83
=
(bo,
b1, ... b5) in terms of syndrome bits so, s1 ... su.
(4.25)
· g t he
Express~n
be rewritten as:
·
t erms o f 1 ,
'"'"" i ' s ~n
a~
a 2 , :x 3 , a 4 a nd a 5 ,
83
can
114
=
s (a))
+ s4Cl + a.Z) + ss(o:3 + aS) + s 6 (1 + a+ a2 + a3)
+ s7Cl + a3 + a4 +aS) + sg(l + a4) + sg( a+ a2 + a3)
(4.26)
Equation 4.26 can be rearranged as follows:
=
s (a 3)
=
(4.27)
Thus the values of the coefficients bo, b1 ... bs in terms of
the
syndrome bits so, s1 ... s11 are
bo
=
so + 82 + S4 + 86 + s7 + sg + 8 10
bl
=
s2 + 56 + S7 + sg + 810 + 811
b2
=
84 + 86 + sg
b3
=
sl + 53 + ss + 86 + 87 + sg
b4
=
83 + 87 + sg + 8 10 + 5 11
bs
=
ss + 87 + 8 10
and Det(Lt)= s1 3 + 83 can be expressed in teriiB of
q
... cs) and (bo, bl ... bs) as
(4 .28)
the
6-tuples
(co,
liS
(4 .29)
The circuit calculates the determinant
manner.
The input to the DET LT
so, s1 ... s11·
circuit
of
are
LT
in
the
the
12
syndrome
These bits come from the MODIFIED
and are used by the DET LT circuit
to
obtain
following
SYNDROME
the
bits
GENERATOR
6-tup1es
(ao,
a1
as), (bo, bl ..• bs) and (co, C! ••• cs).
The 6-tuple (ao, a1 ... as) is obtained
by
adding
the
syndrome
bits according to Equation 4.17 with the S4LS86 exclusive or gates U47,
U48, U27 and U28 shown in the upper left hand
corner
To obtain the 6-tuple (co, cl ... cs) the first step
products between
Equation 4.24.
the
coefficients
ao,
a1
as
of
Figure 4-21.
to
1S
as
form
the
required
in
This is done by the group of 7408 AND gates U32 through
U3S, shown in the left-center section of Figure 4-21.
these gates in conjunction with the output of the
The
output
Exclusive
OR
of
gates
previously mentioned are used to form the coefficients (co, c1 ... cs).
Since the equations for these
coefficients
require
the
addition
approximately nine terms, S4180 parity checkers (U40 through U4S)
used instead of exclusive or gates to accelerate the computation
of
were
time.
For example to calculate cs were from Equation 4.24.
=
Exclusive OR gates could have been used as shown in Figure
have a propagation delay of 3 Tg, or the parity
propagation delay of only 1 Tg.
checker
4-22
which
which
has
a
116
Propagation
=3
delay
T
g
FIGURE 4.22
USE OF EXCLUSIVE OR GATES TO GENERATE Cs
Another advantage of using parity checkers instead of exclusive or
gates is in reduction of actual hardware
equation.
necessary
to
implement
Every time more than three or four terms have to
be
the
added,
parity checkers as the ones used in the circuit are very convenient.
To obtain the values for the
coefficients
of
the
6-tuple
b1 ... bs) the syndrone bits were added according to Equation
(bo,
4.28
by
means of parity checkers (U36, U37, U38 and U39) for bo, b1, b3 and
b4
and by using exclusive or gates (U29) for b2 and bs.
The
last
part
Det(Lt) = 0 and a
11
of
the
circuit
0 11 when Det(Lt) 4 0.
is
to
This
is
generate
a
done
with
54LS266 open collector exclusive nor gates U30 and U31.
these gates are the coefficients co, q
...
cs and bo,
The
bl
IIlii
when
the
two
input
to
bs
as
117
required by Equation 4.29.
As can be seen if all of the outputs are
=
"1", 1.n other words co + bo = 0, c1 + b1 = 0, c2 + b2
c4 + b4
=
0, and cs + b5
by the circuit.
=
"O".
0, thus that Det(Lt) = 0, a "1" is generated
=1
This result
such that
is
used
Det(Lt)
as
input
# 0,
the
to
7474
a
flip-flop (U46) where it is stored at the occurrence of
an
circuit
The output of this flip-flop is the DET LT
used
syndrome
determine
correction as required by the
bit
complementation
Massey
decoding
and
D type
LTS
from the SEQUENCER.
to
= 0,
Conversely, if any of the outputs of the exclusive nor
gates is a 0, e.g., c1 + b1
generates a
0, c3 + b3
a
pulse
signal
received
algorithm.
It
bit
also
generates the JUMP signal explained in Section 4.3.2.2.
4.3.12
Encoding and Decoding Speed
In the previous sections the operation of
used 1.n the error correcting circuit were
piece of information yet to be discussed is
decoding time required by the system.
system clock frequency "fs" and the
each
of
discussed.
the
actual
the
One
circuits
important
encoding
and
These times are dependent on the
amount
"FI" necessary to camp lete both processes.
of
firmware
The encoding
and decoding time "tdec." can be calculated using
instructions
time
equations
"t enc. II
4.30
and
4.31
where
(4.30)
118
and
(4.31)
=
In the system, 186 instructions are required to encode the SO bit
sequences.
For the clock rate of 500 KHz,
11
tenc. 11 is computed to be:
tenc.
=
(186 instr/50 bits) / (5 x 105 instr/sec)
tenc.
=
372 ]J sec/50 bits
This results in an encoding rate
11
data
fenc. 11 of:
fenc.
=
135000 bits/sec
fenc.
=
16875 bytes/sec
fenc.
=
lltenc.
or
where
Similarly, to complete the decoding
instructions are required.
(4. 32)
process,
tdec.
=
(408 instr/50 bits) (5 x 105 instr/sec)
tdec.
=
816 ]Jsec/50 bits
fdec.
=
maximum
of
408
The decoding time is thus calculated to be:
which results in a decoding rate "fdec. 11 of:
or
a
61000 bits/sec
119
fdec.
=
7625 bytes/sec
=
1/tdec.
where
(4.33)
Both the encoding and decoding
rates
are
relatively
slow
compared to systems which can encode and decode data up
to
faster than ours.
slow
One of the reasons attributed to the
and decoding rates is the system's clock
propagation delays
11
tg 11 and set-up times
rate
11
"fs"·
100
when
times
encoding
Using
the
IC
ts 11 listed in Appendix A, and
with the help of the system schematics shown throughout this chapter, a
maximum time of approximately 1200 nsec
= 1.2
~sec
has
for the system to stabilize between clock pulses.
to
Thus
be
allowed
the
max1mum
allowable clock rate "fs" for the system is:
=
1/1.2
~sec
=
833KHz
A 500 KHz clock rate was chosen because of the poor
500 KHz of the multivibrator chip used to generate
Part of the 1.2
~sec,
performance
the
clock
approximately 500 nsec, however, are due
exerciser portions of the system.
above
pulses.
to
the
The encoder/decoder portions of
the
system could therefore be controlled at rates of
up
to
approximately
1.4 MHz which, although an improvement, is still slow compared to error
correcting systems presently available.
Another reason for the long encoding and decoding
system are the large
perform
the
encoding
amount
and
of
firmware
decoding
times
instructions
processes.
instructions, about 30 percent, are not required
Many
by
the
for
the
necessary
of
to
these
encoding
or
120
decoding algorithms, but are included
used to assure that certain
binary
as
software
outpu-ts
before being used as inputs to other circuits.
have
controlled
time
to
delays
stabilize
CHAPTER V
SUMMARY AND RESULTS
This project presented the design and hardware implementation of a
digital information error correcting system.
The system
was
required
to correct up to 20 random errors in a data sector of 100 bytes.
known effectiveness of BCH codes in correcting random
the use of such a
code
1n
the
design
of
this
errors
by encoding and decoding
preselected
data
prompted
Hardware
system.
implementation was to verify proper system design and code
sequences
The
performance
corrupted
with
pre-known error patterns.
The selection of an optimum BCH code was the first step
designing the system.
Various available BCH codes were
taken
presented
compared, two of such being the (1015,800), t=22 code and the
t=2 code.
The latter of these requires
the
use
of
in
a
and
(62,50),
special
data
segmenter to generate data segtiEnts of 50 bits for encoding and 62 bits
for decoding.
Even with the
additional
segmenter
circuitry
found that a system using the (62,50) code would require
hardware than a (1015,800) code based system.
by
it
was
far
less
This, plus the fact that
the (1015,800) code would be much more complex to implement,
made
the
(62,50) code the optimum code for the system.
The 50-bit data segments were encoded in systematic form using
"n-k" stage linear feedback shift
register
encoder
therefore
is
very
efficient
and
encoder.
commonly
correcting systems where systematic encoding of data
required.
This
used
is
1n
of
error
preferred
In most systems this encoder can also be used in
121
type
an
or
generating
122
the syndrome for the data sequences being decoded, thus
hardware and space.
This was the case in
the
correcting system where the decoding method
design
required
linear feedback shift regiter to generate the
code words.
saving
of
an
syndrome
The decoding method implemented
in
step-by-step BCH decoding procedure devised
by
the
system
this
error
"n-k"
stage
bits
for
the
design
was
the
James
Massey.
This
procedure is relatively easy to implement in hardware and therefore was
chosen for this system.
The
decoding
as
well
as
encoding
necessary to understand the operation of the system were
theory
presented
in
detail in Chapter II.
50-bit long data segments corrupted with error patterns of varying
weight were used to test and verify the design and performance
error correcting system.
of
The hardware automatically checked that
the
each
code word was properly decoded by comparing bit by bit the original and
decoded data sequences.
The results obtained for correcting these data
segments are listed below:
1)
The system properly corrected all error patterns of
weight
2
or less.
2)
The system properly detected
all
error
patterns
of
weight
equal to 3.
3)
The system did not detect or correct
weight greater than 3.
all
error
patterns
Some, however, were detected or corrected.
of
123
From these results it is concluded that encoding and
decoding
of
the selected data sequences was properly accomplished according to
the
capabilities of the selected code.
the
This successfully demonstrates
design of the error correcting system and
methods implemented.
and
decoding
One drawback, however, was found in the
encoding
and decoding speed of the system.
the
encoding
These were found comparatively
slow
at approximately 16800 and 7600 bytes/sec for the encoding and decoding
processes respectively.
These speeds, however, were sufficient for the
purpose of demonstrating proper error
correcting
performance
of
the
system.
In addition, interleaving techniques used
to
enhance
the
burst
correction capability of an error correcting system where presented.
formula
was
derived
to
help
in
determining
the
advantages
or
disadvantages of interleaving for different burst length and number
bursts expected. in a given data sector.
Using this formula
system are known.
and
burst
of
the
total
a
given
guaranteed correctabiity of the sector can be established for
code when the interleaving degree
A
characteristics
of
the
124
REFERENCES
1.
Massey, J.
L.,
"Step-by-Step
Hocquenghem Codes," IEEE
Decoding
Trans.
on
of
the
Information
Bose-ChaudhuriTheory,
IT-11,
pp. 580-585, October, 1965.
2.
Lin,
S.,
"An
Introduction
to
Error-Correcting
Codes,"
Sixth
Edition, Prentice Hall Inc., Englewood Cliffs, New Jersey, 1970.
3.
Peterson, W. W.,
"Error
Correcting
Codes,"
The
M.I.T.
Press,
Cambridge, Massachusetts, and John Wiley, New York, 1961.
4.
Texas Instruments, "The
TTL
Data
Book
for
Design
Engineers,"
Second Edition, Texas Instruments Inc., Dallas, Texas, 1981.
5.
National, "The
TTL
Data
Book,"
National
Semiconductor
Corp.,
February, 1976.
6.
Intel, "Data Catalog 1976," Intel Corp., Santa Clara,
California,
1976.
7.
Texas Instruments, "The Linear and Interface Circuit Data Book for
Design Engineers," First Edition, Texas Instruments, Inc., Dallas,
Texas, 1973.
APPENDIX A
ELECTRICAL SPECIFICATIONS OF SYSTEM ICs
This appendix presents the IC data
necessary
follow the schematics shown in Chapter 4.
and
assigned
is
configuration
each
IC.
diagrams,
The
truth
data
presented
tables
understand
Data for a specific
be found by the IC label number (Zl through Z32
to
to
and
Ul
Some
necessary, a block diagram of the IC content.
Power
dissipation,
levels
input and output
voltage
propagation delays irrelevant to the design
and
where
u51)
pin
applicable
and
of
supply
can
to
time parameters, such as set up time "ts" and propagation
used 1n the design are also presented.
through
limited
where
IC
and
the
critical
delays
voltages,
currents
and
disregarded.
"tg"
power
the
For
information on these items the reader is referred to the IC data sheets
found in references [4], [5], [6], and [7].
125
126
Z1, Z2, Z20; INTEL E-2716; 16K (2K x 8) Erasable PROM:
Access Time
=
450 nsec
MODE SELECTION
~/PGM
PINS
(18)
i5E
(20)
Vpp
(21)
Vee
(24)
OUTPUTS
(0-11'
12-17)
MODE
+5
+5
DouT
+5
+5
High
VIM
+25
+5
DIN
vlL
vlL
+25
+5
DouT
vlL
V1M
+25
+5
High
Read
vlL
Standby
V1M
Program
Pulsed VlL to v 1M
Program Verify
Program Inhibit
PIN NAMES
Ag - Alo
ADDRESSES
CE/PGM
COMP ENABLE PROGRAM
OUTPUT ENABLE
oo -
o,_
OUTPUTS
v1L
Don't Care
z
z
127
Z3, Z4; TI - SN54LS377; Octal D-type Flip Flop with Enable:
tg
= 27 nsec
ts
=
20 nsec
FUNCTION TABLE
(EACH FLIP-FLOP)
OUTPUTS
INPUTS
'G
CLOCK
DATA
Q
Q
H
X
X
Qo
Qo
L
t
H
H
L
L
t
L
L
H
X
L
X
Qo
Qo
128
ZS, Z6; TI - SN54LS244; Octal Buffer and Line Driver:
tg
=
18 nsec
IG
1~/
Z7, Z8, Z9,
Z18, Z19, Z22,
Z23, Ul; NAT. - DM9316; Synchronous 4-Bit Counter:
tg
=
36 nsec
Vc..c.
RCO
I
G(..,..,
I:F
/If
'/6
ly- D I.A.. T F' U.. "r S
/71,..,
""'"'
13
"'c.
~
12..
--::.t
a. .....
II
ENI!L:r.
J
~
/c
P-
r-C
I
LJ)
2
CL.E.lit:. CL.oc.(
Is
1./
~
!s
G>
I>
,.__IN F'U i'S --"I
A
C.
•
I
s
£fiii!L.) P. &~D
129
ZlO; NAT. - DM9602; Dual Retriggerable, Resettable One Shot
Pulsewidth "t":
t
tg
= 0.31 Rxcx (1
+
= 43 nsec
1/Rx)
where
Rx = k
(5 k r2
< Rx < 25
> 103
Cx
=
pF
(Cx
t
=
ns
(70 ns
km
pF)
<t
(oO)
TRUTH TABLE
PIN NUMBERS
LoG tC.
4(12)
3( 13)
OPERATION
H_.L
L
H
Trigger
H
L~H
H
Trigger
X
X
L
Reset
5(11)
H
= High Voltage Level
L
=
Low Voltage Level
X= Don't Care
D 1~G ltAM
130
Zll, Z12, U46,
USl; TI-SN7474; Dual D-type Flip Flop \>lith PRESET and CLEAR:
tg
=
40 nsec
ts
=
20 nsec
FUNCTION TABLE
INPUTS
OUTPUTS
CLEAR
CLOU<
D
Q
~
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
t
H
H
L
H
H
t
L
L
H
H
H
L
X
Qo
Qo
20::
2. ?R
PRESET
Vu...
1
14
2.C 1..~
2D
l
.,~
12-
~It
~
I
tr~
_i
&
-
-
G(
~
I
I
..__, z.
I
I
2Q
J.L
~ '!'~
~ 1 - - - ~R
.D
"f
/D
I
::D
... CL.IC
I----
,,
24;
:t
I
I Cl(
~
1 Pt<.
I
'I "
I Q.
,_
IE:l
IQ
r
I
131
Zl3; TI-SN7555; Multivibrator
fmax
=
Vc.c.
c. c.
1.0 MHz
'DI.S • /h
' cv
~~L.
.. ~
0 c.rr.
lt{
~
~
Rl!!#i
Vc.c.
3
cu.rpu.r
/RtGG~~
..L
Coi-JTI(CL
§__
? ))I$CHR~G£
FK6
~
THRE$HOI.P
VoL.T~IO
Ic
GJJ.O
l~
--
f= J,¥'1/(~.er+R's·Z)C
Zl4, US, U6,
U7, Ul4, U32,
U33, U34, U35; TI-SN7408; Quad 2-input Positive - AND Gates:
tg
=
27 nsec
I~
18
I
Y
Z~
Z/3
2.'1
Gi#JD
132
ZlS, US, U9,
UlO, Ull, Ul2,
Ul3, UlS; TI-SN7400; Quad 2-input Positive - NAND Gates:
tg
=
22 nsec
Vc,r,
116 1/A
4'/
36 3F7
3Y
Zl6; TI-SN7406; Hex Inverter Buffer/Driver with O.C. Output
tg
23 nsec
lA
)Y
214
2"1
3R
3'/
133
Zl7, Z25; TI-SN54LS157; Quad 2-line to !-line Multiplexer:
tg
=
14 nsec
FUNCTION TABLE
INPUTS
STROBE
SELECT
B
157, Ll57
LS157, S157
LS158
S158
X
X
X
L
H
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
J>
J(;.
~
I if
13
4ft
'16
J2.
II
4'1
311
J'/
113
~
~
3
J~
B
'/
VI
IV
G'
Z.~
.S
= INPU. T.S
$
•
1
1
z.,g
"
~6
ou TPUT.5
,
/I)
'36
3'/
5
l'f
I
A
H
I
r--
OUTPUT Y
I--
zy
,.
s
I
134
Z24; INTEL-2125A; 1K X 1-Bit Static RAM:
WRITE CYCLE
READ Cl.CLE
ts = 5 nsec
Access Time
45 nsec
tg = 5 nsec
PIN NAMES
cs
COMP SELECT
Ao TO Ag
ADDRESS INPUTS
•
I
Vc.c.
WE
WRITE ENABLE
z.
DIN
DATA INPUT
3
o,N
w!R
lie,
DATA OUTPUT
'I
DouT
$
AB
tt.,
"1G
A,
&
tis
Z 125' A
TRUTH TABLE
INPUTS
OUTPUT
2115A FAMILY
OUTPUT
2134A FAMILY
DouT
MODE
cs
WE
DIN
DouT
H
X
X
H
HIGH Z
NOT SELECTED
L
L
L
H
HIGH Z
WRITE "O"
L
L
H
H
HIGH Z
WRITE "1"
L
H
X
DouT
DouT
READ
135
Z26, Z27, Z28,
Z29, Z30, Z31,
Z32; TI-SN54164; 8-Bit Parallel - Out Serial Shift Register:
tg
=
ts
= 15
32 nsec
nsec
FUNCTION TABLE
INPUTS
OUTPUTS
CLEAR
CLOCX
A
B
QA
QB
QH
L
X
X
X
L
L
L
H
L
X
X
QAo
QBo
QHo
H
i
H
H
H
QAn
Qcn
H
t
L
X
L
QAn
Qcn
H
t
X
L
L
QAn
Qcn
Vc.c.
OH
OG
Ot:
'1: erR
C.LI(
i
6'-lll:.¥
•
I
I
2
I
'3
.IAJ P. A .%AII!'8
lUI
I
OA Os
I
0 's
,-
tl
I
"I
o, "1
~l<ti.
~
I
G,JJJ>
OUi?U
T.S
136
U2; NAT. - DM9311; 4-line to 16-line Decoder:
tg
= 30 nsec
INPUTS
0\JTPUTS
Gl
G2
0
c
B
A
0
1
2
3
4
5
I
7
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
H
L
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
L
L
H
H
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
"
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
L
H
H
H
L
L
L
H
H
H
H
L
L
H
H
H
L
H
"X
H
H
H
H
H
H
H
H
X
X
H
H
H
H
X
X
X
X
X
X
X
fl
10
H
H
H
H
H
H
12
13
14
15
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
·H
H
L
H
H
H
H
H
L
H
H
H
H
H
.H
H
...
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
'Z..L .Zl 2. c
H
....
X
13 c.
,
I
H
H
H
H
H
~.LNPUT.S ~
v(.(_
•
H
H
H
H
H
tg, 11
,,
IS ll./
I
3
c
k:
z.
:3
o u. r
'i
'
s-
Pu..TS
?
"
/(.)
1-
g
ct
H
H
H
H
L
H
H
L
H
H
- HH
H
H
H
H
H
H
-H
H
I
I~
II
10 G;JJ.b
~
H
H
Cfoll
•
"
H
H
lc- cuI Pv "iS ....,j
G.2 G1 IS Jl.l 13 12.
1'1
H
L
H - L
H
H
H
H
H
H
H
H
..
L
H
H
H
137
Ul6, Ul7, Ul8,
Ul9, U20, U21; TI-SN7476; Dual J-K M.S. Flip Flop:
tg = 40 nsec
ts =
0 nsec
FUNCTION TABLE
OUTPUTS
INPUTS
CLEAR
CLOCK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
R
H
H
H
.rt
L
L
Qo
Qo
H
H
IL
H
L
H
L
H
H
.n
L
H
L
H
H
H
n
H
H
TOGGLE
PRESET
138
U3, U4, USO; TI-SN7404; Hex Inverter:
tg = 22 nsec
U22, U23, U24,
U25, U26, U27,
U28, U29, U47,
U48; TI-SN54LS86; Quad 2-input Exclusive OR Gates:
tg
30 nsec
FUNCTION TABLE
INPUTS
B
y
L
L
L
L
H
H
H
L
H
H
I.( A
'IV 3C3
311
J,:}
1'/
21/
Z'/
OUTPUT
A
H
Vc..c.. 413
L
H = High level
L = Low level
18
2.8
'
~ A.JJ)
139
U30, U31; TI-SN54LS266; Quad 2-input Exclusive NOR Gates
with O.C. Outputs:
tg = 30 nsec
FUNCTION TABLE
INPUTS
OUTPUT
A
B
y
L
L
H
L
H
L
H
L
L
H
H
H
H
L
= High level
= Low leve 1
36
3~
140
U36, U37, U38,
U39, U40, U41,
U42, U43, U44,
U45; TI-SN54LS280; 9-Bit Odd/Even Parity Generator:
tg
= 50 nsec
FUNCTION TABLE
NUMBER OF INPUTS
A THROUGH I
THAT ARE HIGH
o,
OUTPUTS
2:: EVEN
2' 4, 6, 8
H
L
1' 3, 5' 7' 9
L
H
H
L
= High level
= Low level
S4 LS Z BD
•
6
11
N,, .
.:r
E
E
EVEN o.o..t>
11
~ODD
TH/2U.
I=
IN'PU..T.S
G,I.J..t'>
APPENDIX B
SCHEMATIC SYMBOL LEGEND
In this appendix some of the symbols used in the schematics shown
~n
Chapter 4 are described.
AND gate
NAND gate
OR gate
EXOR gate
EXNOR gate
-[>-
Inverter
.J_
+Sv Return
Input Signal
141
142
Output Signal
LED