CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
AN/ASM-198 FLIGHT LINE TEST SET
1
q
~RELIABILITY
IMPROVEMENT
A graduate pToject report submitted in partial satisfactio~1 of
the requirements for the degree of Master of Science in
Engineering
by
,Ja.mes Antoine G::tle
·\'
~
..
The graduate project report of James Antoine Gale is approved:
----~
Comntittee Chairman
Cahfornia State Unive:rsity, Northridge
May, 1975
J<'ORWARD
The AN/ASM-198 Project is assigned by Naval Air Syste:ns Command to
Peter Kobashikawa., project engineer, tmder a.irtask number A53:353833/0542/
'5231000001. The purpose of the project is to improve the reliability of the
flight line test set, which is not in use in the Fleet because of its deficiencies.
The Naval Air Systems Command is interested in the project, because of the
essential ground support maintenance provided with the test sei; to the Link II
fhta. link on board the E2B/C command anti control aircraft. The project is
also of interest to the Department of Defense due to the possible Tri-Ser.vice
applications of the ASM-198 Flight
Lh~.e
Test Set.
T~1ese
Tri-Service
applications ine luc1e ground support maintenance of the Link II data Enk in the
Ail' .Force Ail'borne 'Warnlng and Comms.nd System cc-nm:umd and control
aircraft, tlv.: N<wy S-3 a.nti-;:;ubrgarbe warfare
::~.ireraft
and Anny or Mc.rine
Command and Control Systems.
Acknmvledgem.ents are directed toward Petel' Koba,shikl:nva, Project
Engineer, and Bruce Helbert, task engineer, for their assistance in this
graduate project.
.........................................
·-~---.---
----..----------·--..... --------.-----________ ,. ...-------.·----.-..------.... -- -.----.-----·-· ··-··---·--=-----·-------·. "]
i
I
I
i
l
TABLE OF CONTENTS
I
I
FORW.h.._RD.
• .iii
i
ABSTRACT
INTRODDCTIO~
!
!
uii
• • t
I
Ct
•
•
1
CHAPTER I - MESSAGE MATRIX DESIGN
•5
CHAPTER II - 1A26 OSCILLATOR DESIGN •
.24i
CONCLDSIONEi.
.:34
APPENDIX A
.35 I
APPENDIX B
.46
APPENDIX C
.48
BIBLIOGRAPHY ,
.50
l
i
I
I
I
I
J.:.IST OF FIGURES
Figure 1. AN/ASM-198: Block Diagram.
Figure 2. Timing Chart: Six Frame Counter.
Figure 3. Timing Chart: Four Frame Counter.
Figure 4. Timing Chart: Static Mode For 'Word A.
I
Figure 5. Head-only--memory Array.
I
Figure G. First M:essage M:1trix Control Circuit Design.
!
Figure 7. Binary Output Indicator.
l
j·
j
Figure 8. lVIe.ssage Matrix Ci:rcuit Verification Scc)t--up.
Figure 9, Sequential Design Outline.
Fig11re 10. The ""T-K Flip-flop.
Figu.re 11. Flip--flop Transition }\laps.
Figure 12. Karnaugh Simplification l\'Ia.ps fur Sequential Circuit Realization.
Figure 13. Final :Message Matrix Control Circuit Design.
Figure 14. Block Diagram of the Oscillator 2 Modale, (1A26).
Figure 15. Basic Phs.se-locked-loop Block Dia.gratn.
Figure lEi. Schen.tatie Diagram of Phase-lock0d-eloop Design.
Figure 17.
Schem:;.t~c
Diagram of Dmd Monostab:le Mu1tivibrator Design.
Figure 18. SdH-:lrutic Diagram of Frequency Selector Design.
Note: MrS~ 1'1ffi i~
"NFffo·
= the eoroplement of message-type-S or the
1 "·t..-,ent
'-ll"'
r">()l'~')
of
.... I'
L.!.. (.':, _~o..•_
.J_~l: ..LV
. .l.J. .n... ,
~- .... IT:lP"'Sa"'e-t'•~)e····n
~ ~
., "1::::.. ~
Vl
·
'-' '-'
the corn.plement. oi
v
nle~sage-tyiJe-10.
thP:
1-·
i
ABSTRACT
AN/ASM--198 FLIGHT LINE TEST SET
i
-RELIABILITY IMPROVEMENT
by
'
j
l
!.
I
James Antoine Gale
Master of Science in Engineeri.ng
May, 1975
l!
I
This graduate project repo-rt deals 'Nith the redesign, construction and
testing of two unreliable components of the Navy's AN/ASlVl-198 flight line
test set. All phases of the design procedure are covered, including the
environmental evaluation of the two designs. The two components involved
are the rr1essage matrix module and the phase--locked oscillator module. Thc)
;
fin::tl designs we1·c eomp.letely successful. Condusions are included at the end'
of the report explaining the value of tl:..e cnviroarnen.tal testing done during the
projeet.
,
~
L.
l
l
INTRODUCTION
The ASM-198 flight Hne test stet is a piece of ground support equipment
for the E2--B/C aircraft. The E2 aircraft is a command and control platform
deployed fro-en aircraft egxriers ir:_ the various fleets of the United States
Navy. The E2 is a radar platform with:::. particular radar r::mge. Radar
inforraation is transmitted from the E2 to an aircraft carrier or to ground
!
su::~port
stations via the Link II data lint_. The AN /ASM -1 98 flight line test
set is a grmmd support test set designed to perform preflight functional tests
on the Link II data link. Link II is an air-to-surface/surface-to-air data
link. It traESTnits target location, velocity and direction of travel as well as
E2 location, velocity and direction o{ travel to the commanding aircraft
carrier or grotmd station:. Target status of hostility or friendship is also
transmitted. The material transmitted and received Is processed by the
Link II computer.
The AN/:\..SM-198 Hight line test set performs preflight
tests on the receiver, computer and
transmld:;..~:r
:::·
....:c;.r.;:lrlld.tld B~i1Cl
control aircroJt.
Recently the AN"/A_SlVI--198 has been in lixnited or no use in the fleet due
l
2
to instability and low reliability problems. These problems are generated
by high temperatures emitted from obsolete integrated circuits used in the
test set design. Temperature measurements were made by research
engineers. Temperatures in excess of 180 F were recorded. The Naval Air
Rework Facility at North Island, San Diego was tasked by Naval Air Systems
Command (NA VAIR) to modify two test set units by installing two "muffin
hns" in each unit. Temperatures were reduced to below 105 F. TbJs was a
wJ.nimum of 75 F improvement. This procedure reduced card fa:i.lure, but
did not elimim.te the problem.
There were eight ci.rc11it cards or sub-replaceable-assemblies (SRA 's),
as they are called by the original designers of the test set, involved in the
low stability and low reliability problems. Included in the eight SHA. 's are
.four phase-·locked oscillator SHA 's~
~~
R-C correlator SRA 'sand one refer-
ence oscillator SRA. The S'.tlA 's producing the highest rate of failure are the
phase-loeked oscillator SRA 'sand the R-C correlator SRA 's. The instability
problem is attributed to the refereneo oscillator SRA. It should also be noted
that the phase--locked oscillators are the main heat producing elements in the
t'3st set.
Another consideration of the AN/ASM-198 project is that of ·sofhvare
compatibilit~r
with new Link II message formats.
Due to the ever changing
threat environment :it is necessary to change data link message formats
in order t~) keep thei:c completeness up~-to-date. ~rherefore. the AN/ASM-198
flight line test set rnust be provided with software programmability so that
3
its message format may be changed to be compatible with new Link II
message formats. Therefore the message matrix and message self-check
matrix SRA 'swill also be redesigned as a part of the AN/ASM-198 project.
The scope of this graduate project will be confined to the design, test
and evaluation of two SRA 's; the message matrix, (SRA 1A3}, and Oscillator 2:
phase-locked oscillator SRA, (SRA 1A26). The block diagram showing the
relationship of these two SRA 1 S to the toLal test set is sho'.vn in .Figure 1.
'J'he block diagran1 is very simplified due to the fact that the test set is very
complieatec1 and it w:ill not serve the purpose of this report to show the entire:
I
test set in detail.
I!
I
I
!
I
,, ___ ,_ --T-•.--- ·~• ·-·-~ - -
C~N·
~~~~
---r
~
I
1.~
!
l
I
L ~-~-~-- ~-~--~~----·~-~---~·--~~-~---~~---·~· -~--~- ............... ~-·~------- ....... ---· . - - - - - - - - - - ......................... - - - · - - - - ----·------~----------•--..
~---~ ~
~-- ---~~~
4
t- - - · · - - - - - - - - - ----;
I
I
I
I
I
I
I
I
l
~
o
'2
I
C:(.
i
I
<
I
\~<
~
\---
-t
\-·
Ii
~
o .
1
I
:
·-
I
I
I
I
s_.
~
.:;
!\,!'!
-z
. .,r.
.
0
~
'
I
!
_... .
I
tf
I
0
'
!-· ~
'1' 0
oukl
-·---::('--
,
I .,.w
u(.\,.a I ·u'~<?
o t:\:J.
~:.~· _<
~ z
II
~~
.J-'
,.Ja.
~x
II
~...,
~,._
I
I
:
i
.
~
I
l
I
L ____ ---- _____ _l
_,- ---·--,
r
1
i
I
'
I
I
I
l
I
I
I
J1
I
!
J
.f
I
I
<
~a
'I
~4:
· I
!
I
L~-----------t-+: .
t___________, ___ ..J
I
I
I
f
I
I
~-
I
l
I
.4-:
0
'
1
I
~
I
I
r---
.
lU
..,.¢'!>.
I
~
Q!
~
N
~
t
I
I
I
-
I
c!
;:
-- ~ ·-· -- u~'t--
~.....
-
I
I
I
I
I
~
I
I
I
i
I
e}·
I
f
,
0
I
.
l
I
I . ~
I . - ~l~
L
r------- ___ ..._1
.
I
L.. - - ---·------·--·J
. i
CHAPTER I
MESSAGE l\1ATRIX DESIGN
i
iThe message Inatrix module, (L.4_3), of the AN/ASM-198 flight line test
set, provides the compliments of ten 30-bit words, in particular sequences,
; determined by the mode of the input control signals. These words are
labeled; IA, IB, ITA, IIB, lllA..., IIIB, A, B, C and D. These words in partic:ular sequences contain information from eight different messages which can
be selected from the front panel of the test set. Unfortunately, the nature of
the messagee rmiy not be presented in this paper, nor would it be relevent.
3. A static mode providing the
~..vord
IA
4, A static mode providing the word A
5
G
TABLE I
CONTROL MODES
~--~--~---~~~-1T_-7 1h!r8+;;T~~~-o-+-----II-lp_t_rt_s_/~11_o_a_'e----~
1
1.
six frame sequence
1
static word L\
0
1
four frame sequence
1
0
staiic word A
1
0
static word A
0
1
static word A
1
G
I
0
1
L~-~----------·L-·---------
--------b
The sequences shown in Table I are timed by the negative going slope of a
clock pulse, which is provided by the control inpttt Gp]. The pulse width of
the dock pulses is approximately l(J.1.s :::md the pulses are approximately
13 msec :::r.part. As shown in
Table:~
there are two extra modes, denoted as
5 and 6. These 1node s do uot oceu:r in the test set, but were shown to com-
plete the truth table.
Figures 2, 3 and 4 further illustrate the four control
modes and their rE:qull·od data outputs from the messagE: matrix through the
use of tilning charts. The timing charts show the relationships between the
input control signals, the d::1.te. outputs of the message matrix and the data
sample periods. The data sample periods will be of some importance later
on in the (;h::tpter.
Figure 2 illustrates the six frame count sequence and the
static mode using word L\. ·Figure 3 illustrates the four frame count controlled by
rvtr7 and one of the two conditions for static word A. .Figure 4
"i
.
""
Q)
S--1
.....f1
1'4
I
I
!
GP.:..___j
..
II
_I
,..2~B__
.
)
_
I
..l
_Jl . L'l'~lJ.
I
!__
I .
--L
H
I
.
_.r
. -r-c!15lll-\tMrssM::~E ~.~~TP.l~
W Di-3J2_!L___~ 1
-· B I ----~---1 ~0
-----
I
.
l_~j
J
---~t
"''o
RD A_._ _
4~
Figure 3. Timing Chart: Four Frame Counter
en
..
=l. I
'1J
I
~I
1 C~i
I
I
I
II
II
I
!-:)c•'!
.
!
I
!
I
-~!
I
·--"
I
~..,.._,,
ex~
r-I"""!
I
r~<c
h~
~~l
~ I
·l-I
~-
~~
1-;tl
.
P1
~<tl
--~-
~':J
--f'
'
l<t'l
LJ
I~
~I
I
.--1'
C'(.,
t·•l
;,.,q <I
I
~
t;l
I
~~O!
I
~I
\--1
·{{
u) o
~ 3.
\l'l
Vl
lul
.,_
">
'
~
·~·
9' I
,.
\~
<··~
i.J(
~I
I
I
I
~~I
.
~·i. I
~
"tJ
f.<
0
8:
~~
·o
fr-1
(!).
"C)
0
:?;
o·
.....
+->
...,cd
U)
+->
$-1
Ctl
..r:i
C)
b.O
......~
s
.......
E--l
~
(!)
f.-1
~0
~
10
illustrates the static mode using vvord A which is controlled by
There are some additional specifications which must be met in the
redesign ·of the message matrix. The unit must be physically and electrically'
compatible with its interfacing components in the test set. All components
within the unit must meet military specifications of temperature.
The first step in the design of the message matrix was to develop or
modify the message matrix so that the riew matrix could be adapted to the new
' message formats required for Link IT. It was also desired to provide repro-·
grammability to the message Inatrix at reasonably low cost. It was decided
that this capability could most easily be accmnplished by using an array of
field programmable read-only-memories. To meet the requirement of being
able to provide ten 30--bit words, four 256-bit read-only-memories were
required.
Each read-only-memory had a capacity of 32 8-bit words, so it
was necessary to hook the memory access control inputs of the read-onlymemories in parallel. This procedure produced a capability of 32 32-bit
words. Due to this capability, new flE;xibility was added to the design. A
array of read-only···mcmories, (i.10M's), is shown>i,... Ti'iCI""""'·
R.
The next step in the dcsi.gn of the message matrix was to develop the
I
:
control nnit to provide the appropriate sequence of addressing. The first
i
l
L-.. ·-· ~ .. """ ...... - .......................... ~----- ......._ ..._ ..._ ............................- .............. _ .................. --·--...................... _ .....- ................................._ ..,____,_______ ........... J
11
.
'
lJ
0
12
design included an SN5490 decade counter as the heart of the board. The
counter was controlled by a system of transistor-transistor-logic, (TTL), logic
gates designed to produce the proper sequential logic. The schematic diagram
of the first design is sho·wn in Figure 6. The six frame sequence was accomplished by the count from 0-5, the detection of the binary nui11eral six at the
output of the counter and by resetting the counter at that time through the
appropl'iate log:ic. This situation occurred when TR,
MT7' and 11TS1'1\1T9-PMTlO
are at a logical one, (5 volts). ·Under this condition the numeral six would be
reset to zero almost immediately, (within 50 ns). This situation provided a
c.our,t sequence of 0 to 5. The four frame sequence
ting the counter with the binary numeral four.
M'f7 was at a logical zero,
\V~ts
accomplished by reset-·
This condition occurred when
(0 volts), and TR and
MTS+ MT9.;.i\iffiO were at a
logical one. The static word JA was proci:.tced by resetting the counter continuously and applying a .logical one to the QD input of the ROM array. This
condition occurred when TR was at a logical zero and
Mf8+Krt~·9+l\'ITJO were· at
'iViT7 and
a logical one. The static word A was produced
by continuously resetting the counter and applying a logical zero to the QD of
the HOM array.
This condiUon occurred \Vhen 'T1-{ a.nd MTS·t· AfT8 t-MTlO
were at a logical zero and Iv.ffi was at a logical one. The primary set
ot ten
30-·bit words \vas addressed under the previous conditions when a logical zero
was applied to the QE input of the HOM array.
'I'h~~- ''"rnnrln .,.,, cwt
of ··words
was add:rcssed undm· the same previous conditions. exeept a lcgica.l one was
applied to the QE jnput of the ROM arr·ay. The word assignments in the HOM
------ -1
~~--·----·----~,··~~-'rQA
r"
I u-·.-·-·-
·----·--
,--.~-
o-I~J p
<>-GPI
"
II
'J.
~hLi
~-
t~c.
I
,Ar
I
.
~:#_ .2""
'<<
i
__j'
-
I
-
ri
(CV·'
.
.
i
r:~~
•b.,.~1.·f\..
·w ru
•- -Qi'
l11/r
. I~r
1
1
__.,__..__
·
.
-:!:.
.
__....
~
·
Figure 6.
~'"b
r·-l
··
-...
. / _._ I
11
Lf\
----11 ;:)-;-J•
Ii
-~----
Qc
. II't rl.
l.-/ f-..
' ---1 ,'
i
Qn
I
L_j
7
.
I
I
J
rI ,./
"'TTi+vm+,;;;;.!!1---f\
~
~
8 N-~ttl r-~~
.. T""i StJs4~o I=P}-l._.
I
<;~'-< "~~·~
I
·--
Ot:CAD;!.i-
-Jflo-
·-r
----------
L-4----1@
I
.JJj
-
l
-------.1.
First lVte.t:sage Matrix Control Circuit Design
t",.<)
14
~~-
-···--·- ..
~-----
.
··----~----·---------
·~--·-·-···-·---··---·~· -----~--···
··-··-·· ·-
array are shown in Tables II and III.
:---~-1
!
TA.BLE III
TABLE II
ROM ADDRESS ASSIGNMENT
PRIMARY
ROM ADDRESS ASSIGNMENT
SECONDARY
Address
QE QD Qc QB QA
Address
QE QD QC QB
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
c
1
0
0
1
0
1
D
1
0
0
1
1
0
0
IA
1
1
0
0
0
0
0
1
IB
1
1
0
0
1
1
0
1
0
IIA
1
1
0
1
0
0
1
0
1
1
IIB
1
1
0
1
J.
0
1
1
0
0
IliA
1
1
~'-
1
0
0
0
1
1
0
1
IIIB
1
1
1
0
1
c2
IA2
IIIA2
I
----·--·~L
IIIB2
J
The message matrix was then breadboarded on a proto-board and
tested. Gp 1 , {the clock pulse), was obtained from a pulse generator which
was synchronized vvith the sweep oscillator of an oscilloscope to produce a
pulse slow enough to be observed using the output indicator shown in
Fig11re 7. The equipment set-up for the test proeefl,re
Using this slow pulse technique the circuit
if:~ ~hown
in Figure 8 ... __
worke~ as designed.
Nex-t the pulse rate was speeded up to the i"eal time rate and the
1•.
;
--~-~-
_
15
Figure 7. Binary Output Indicator
- r·
• -swr::_~o
0\JT f
·-v
'
-
····-l-·
,
-·-·--e- Gt!r
~-------·-------(i-
.
QG oR Qc.
F3gure 8. Messa.go Matrix Circuit Verification Set--up
16
'"
---- -----· ---- '" ·----' ---- ---·---------- -'
'"
--·'-
------- ---- ------·---- ---' .
'
. ··---··
--------- --- ..--.. -------- ...........______.... ·-------------
·--~ ---------·--·~-'"']
counter outputs ·were monitored with an oscilloscope. The problem
!
anticipated at this point was that there might be a. glitch or part of a pulse at
1
j
the numeral six, which was not desjred. By using the proper time expansion:
on the oscilloscope, it was determh1ed that the glitch was well under the
50 ns switching time of the TTL logic.
At this point the circuit worked as
specified. At the conclusion of these tests the product prototype was built.
When the prototype was complet'3d it was placed within the A.N/ASM-198
test set to determ.ine whether or not the prototype would pass the test set's
self-check procedure at room temperature. The message matrix passed the
self-check at that time. Next the prototype was subjected to temperature
tests as outlined in Appendix A. The prototype failed at a temperature of
85
G and
investigative procedures were begun to determine the problern.
The problem anticipated was concerned with the numeral detectl0n and
reset logic. It was possible that. the rise in temperature effected the reset
pulse. This idea was investigated by monitoring the pulse with an oscilloscope. It was discovered that the pulse became so nB.rrow at higher temper-atures that it did not reset all of the flip-flops in the SN5490 decade counter
at the same time. Two capacitors v;ere placed in the reset lin8 to lengthen
the pulse slightly. The problem was eased, but not corrected. The two
capacitors are shown in dotted lines in Figure 6. The ide::t of putting one-shot;
devices in the reset line to let1gthen tl1e ptllsc evcrl_ftrrther \Vas COllSidcred,
I
i
t
!
but
\Vas
set aside until further alternatives could be studied. This delay idea
did tiot semn to be in accord \'lith good engineering practice.
'1
l'l
Further research was done in the area of sequential circuit design.
During the :research a new and seemingly more sound approach was discovered. The design was first laid out in a sequential outline as shown in
Figure 9. In this new approach a system of J -K flip-flops were used to form
I
the heart of the design rather than using an SN5490 decade·counter.
I
I
li
-!l
I
l
II
'
I
I
I
I
\
Figure 9. Sequential Design Outline
In Figure 9 there are two counting loops forTH.:: 1. One loop ·..vhere
l\ffi = .1, which is
tht~ six frame sequm1ce and one loop where MT7 = 0, which;
I
·--
.ts the four. ftamc count. The loop where TR or MTB
-
-t·
---
---
MT9 -r· MT10 are equa.l!I
I
to zero is a reset loop for the two static modes disc-ussed earlier in the
I
!
chapter. Levels six and seven are possible conditions which are not desired, :
I
therefore provisions are considered to _return the§_E:' ,.,
7('.,.,...
if ~h<"y accidently
occur. It was found by. CllLtck analysis that the transition from six to seven to
zero reCfLlired less logic thau the tra11sition frorn six directly to zero. This
-·
I --~
I
~--·--
__,
18
procedure is only a precaution against such a situation occur:ring. For a
. count sequence of 0 to 5, three J-K flip-flops are needed.
Figure 10 shows
the schematic representation of the J -K flip-flop and Table IV shows the
requirements for the four possible output transitions of the ·J -K flip-flop.
Table V indicates the transitions required for the six and four frame
counters.
J"
c;u;.~
'"c.>../.1"RQ
).
II
Figure 10. The J -K Flip-flop
TABLE IV
Q TRANSITION FOit <T-K FLIP-FLOP
Transition
Type
Transition
0
0~0
a
0
1
1--+1
.L
...
_
Q
~-+1
J
~
0
-
1
-·
I
- -o
I
I
1~o-
b
Note:
-· 1_1
~
11
-t' means do not care st.ai:e
19
-····
----~'"-
-------- -- - - --- ----_,_____ -----.. ---- - - - - --------------------.. .----.. - - - - ----- - --· ------ --------~-
---~--------
·------------------· -----
--------------------~---l
UB~V
1
Q TRANSITION STATES
0
Qc QB QA
1
l
0
1
0
0
1
0
0
1
0
0
a
0~
0
1
0
0
1
0
0
a
b
0
a
0
0
1
1
0
J
1
0
1
a
0
1
11
0
0
010
0
0
b
b
a
b
bl
a
10
al
0
0
0
0
0
1
0
1
JO
_
~~--~~......,;l\;...1'TT_7____ -~-----+---~-:r_;·a_~~-::;-~I_·t_,iorl-1~T-':yu~P_:~_s_-_-_~-t-
Outputs
110
I
0
101101
I
1
0
1
0
0
0
0
0
1
1
~ J.
1
1
1
10
I
b
I
I
~1-~~·--a-p-~-a ·1
0
I
b
0
~~-~~-~-~-o_...,..~-._o·-··~-~-~~--~~~
Note: Last two rows of states are undesirable states.
b !b
b
0
b
j ~-~--~J
Figure 11 shows the transition maps for the three flip--flops.
Figure 12
shows the Karnaugh simplification for "the J 1s and K's of the three flip-flops.
The circuit realization is then derived from the simpJJfic:ltions. After the
simplifications were completed
011
the Karmwgh, the actual sequential ci:ccuit
was realized. The :1ctual seqL1ential cin:;uit is sh.ow:1 in Figun:: 13. The new
message matrix design was then prototyped on a prototype plug-in board.
The same test procedures used for the first design we1·e used to verify the
second desig11. The environmental test procedure_ for the message matrix
SRA, (1A3), is shown in App0ndix A. The second design was verified
completely as shown i.n the results of the environrn.entaf t<.~st. p:roeedure. The
- - -~- - - - - - - - - - - - - - - - -,·~-·- . - - - - -~- - - - - - . . -__ _ _ _ _ _ _ j
2tl
'-·, A. ,-::·:;.;y::-r
~ ~
eo
J
06
QA(n+l)
;
of
I a.! o..
1
b
1
o ·
b
~-"'
t
~~-Ji
,oa_TI_:_
II
'·-'·· nY'"
. Figure 11 . :F·lip--flop Transition Maps
21
--
Figure 12. Karnaugh Simplification Maps for Sequential Circuit Realization
---·-·--·-··-·
----·---
-
=,
I ----------"·--- -~··r
:=:: := :_
---L/
G?i
o-
•
,
.
.--l
I 'r.tj}
-- I --H
.f) J
!-;_I ,J•
Jn
---
Q
i
1 1
'
I
~-__j
Mrr-r
~ I1
<-d-j)---
~_;£
~
\~
K
CtOIO
1
Q
·
.._____
-Lr--..
I -;-I P-'· ;!'ratM'f"<t+fflilo I
2 .'2. ••n...
o-lJ
?_X
•
C(O<K
+, ~0. .
-~t>---l~--
I
,,__
_,__
x· r--- ------+-~
Qc
~
QL-
~'KL~_~:LeAP. - [)
---~-__j
I
Q -
'--·
l ,
______.,
--:-----'
iJ
8
.
..
-\{
---1
_j
.
..
~---_j
---"
- -
.
.
Qo
- - - - · - - - - ___ _
V..:x,.r_
Figure 13. Final Message Matrix Control Ci:rcuit Design
l"V
'.>!i
23
new message matrix SRA was eompletely operational to temperatm'es as high
ag 100 C.
The second design of the m.essage matrix was accepted ai1d tho
design was contracted to the Instrumentation and Flight Support Division for
printed circuit board layout and fabrication.
The final circuit diagram of the entire mess::tge matrix SRA is shown in
· A ppcndix B.
I
I
CHAPTER II
l
I
1A26 OSCJLLA. TOR DESIGN
I
i
1-
!
The 1A26 phase-locked oscillator module is one of fo"'J.r oscillator
modules in the data section of the AN/ASIVl:-198 flight line test set. The data '
section also coi1tains the message matri-x, which was discussed in the last
chapter. The four phase--locked oscillator modules were the highest ft'dlure
rate itE-ms in the test set. These modules required the most power and
dissipated the most heat. The integrated eircuits used on these boards were
of the hybrid microcircuit type, which is the reason for the amount of heat
that they dissipated.
The 1A.26 phase-locked oscillator module is m2.de up of four oscillators
l! and a fre<}liency selector circuit,
as shown in
Fjg~u.re
14.
i
The fo1.<r
oscillators:I
-
I
I are
labeled A1, A2, A3 and A4 and have the follo"l.ving respective frequencies
at the outputs: 177, 7GO Hz, 179,520 Hz, 183, 0L10 Hz and 181,280 Hz,
'I'hese
frequencies are produced by multiplying a reference frequency cf 1760Hz by
101, 102, 104 and 103, respectively.
Each oscillator has thrGf; outputs.
'
I Two of the outputs are c::tlled F and Fo.
L.~~ ... ··~--~---·
24
The Fo output: must lead the F output.
.,._fl60
H~___!llft.$1Bi'i
,-,..!.1.t?· o
K 14'1.. _ _
-
-
.
_
1
-~~
I
-
J
~ rl'\t.~
co--2.'? ca,.JrA.ol-
.;,:to
!iQ~r_
c CONTROL.
~--~
+10 COI>I1"_R,Ql-
..
-
.
cf/C;
.·!)j
.J.
4-lt)
'l
-~-----
· J ··i·-l-t,--------~~Q.CKJ.!'!Ql~AIO~
."
CSCILLA"rD!\! .
·
~~-;.
1
I '
I-
H---_j
I
I
r··-
i
~~'
i7C,'.'..:.>
.t-
.
r·-·--·-t--. -
t'.:tz
1
-------o.
--
-~1
!!"P..!~~J:9
~-o
3
--------.--_£~_t:._Q
OSCtLLl\IOR
A
FCO
:-·-------{:~--~
---~-------~
E
1'83.04- ,1<.;/2.,:...l
_________
Itt
--~
L.5'_CK
_______
,. _
..
__
:F_i__~
-10 .
_,~ $E.LE:C.TOR!
. - - - O(:ITP,Qt. .
o--+-~o,J;,or~r'Rc'-~--·~
·
A
......-
-120
~D-tvj .. 1/
_ ...
I
i
~~~I
I
F£.9~
r:e,~-"
OSCI~:-Aro~
t~-~-1.__:77. 7(. K~1- 1r----
.---~
I
.
r_;-:;~>-+!01
<:!"""-30COI</TROI-
rl
• •
. ~-Q_C'S_ ltlDIC.ATOR~
l
r-
.
j
~
&
I$6.S'-kH;;:;
e
___,.
1
·-~
o ·,
1
l
I
"l
.j
I1
cc.ILLfrroR
1.)
1
1------!__S_I_~ll_K~~---A4
f=R£cpJ~::.:o.~e'l
roo
-----
'
,; 0
. ~--~:>
S.E"LE<:.TaA.
our
""'"--~---------- · - - - - - .---'--!)
Figure 14. Block Diagram of the OscU.lator 2 Module, (1A20}
!~l
C.:l
26
The amount of phase difference is not critical as long as Fo leads F. The
third output goes to one of the inputs of the frequency selector and does not
require any particular phase relationship with the other two outputs. There
is also a lock indicator which indicates whether or not the oscillator is locked
onto the 17 GO Hz reference. The lock indicator indicates a locked condition
with a logical one and an u..11locked condition with a series of negative going
pulses. The output frequency accuracy should be within 1 Hz.
In cons:idering a new design, it \'/as desired to use components which
required nmeh less power than the original components. This would greatly
reduce the heat dissirated b:; the oscillator units.
It was also desired that
components, functional over the entire nlilitary temperature range, -55 C to
125 C, be used.
It was decided that integrated cirm1it phase-locked-loops would be ideal
for the specifications desired. The basic block diagram is shown in
Figure 15. The phase comparator compares the phase of a periocUe input
signal (fr) to the phase of the output signal of the divide-by-N eounter. The
output of the phase com.parator is a voltage which is proportional to the phase
difference between the two signals.
The difference volt::tg;e is then filtered,
to remove any undesired noise, an.d then applied to the input of the voltage
controlled oscillator. The control voltage changes the frequcney of the
voltage controlled oscillator in a direction that reduces the phase difference
between the r·eference frequency and the feedback sig1wl after this signal has
been divided by N.
i
Ideally, when th-:J phase-bcked-loop is locked the output
L______ ---------- ._ . ____ -.--·-------------------··---·--·-------·-· ------------ ·-------~------···--- . . . . . . . . -----· --------------· ----· ------·-
27
I
~
.'.·~c
l
_,
~
28
frequency is exactly N tia1es the reference frequency (fr). In real world
applications, there has to be a nonzero output from the phase comparator to
maiatain a locked condWon. Therefore, the loop operates with a very slight
error,
iT~
phase, present. With proper design, this error tends to be very
small.
It was found that there is a new line of integrated circuit devices which
are nearly ideStl for the application in this project. These devices are com-·
plimentary-metal-oxide devices, (CMOS). They require very little power
for opera.tion and dissipate very little he:::.t. These CMOS dmdces are also
relatively imm_i:me to a fair amount of noise, because they have high impedance inputs,
The design of the phase-locked-loops was fairly easy. The information
for the filte:t design was a va.ilahle in the form of gTaphs in the data sheets for ·
the CD4046 AD phase-locked-1oop and the CD4059 AD divide-:by-N counter.
These particular devices were manufactured by RCA. The schematic of the
phase-locked--loop is shown in Figure lG. The graphs hom which the values
of the components were ta!-:en were only approximate, so when the device was ;
\
breadboarded the components were adj1.1stecl until tnc eircuit performed
properly.
Once the phase--locked·-loop was on8I·ating pl'operly, the outputs F and
Not only did the two pulses have to differ in phase,
F_u leading F, but the pulses
from these two outputs
. lw.d tobe
~·
condition
wa:::~
a.aeomplishcd with a IVI.otorola MC1 1kii}S AL dual
l<!S
~~·
wide. This:
m~onostable
{
L_. --.· -----·~-.-- ---··-- ···---~--· -~------·-·-······· -------··-- -----·-~---·--····--··----- .. -----· - ----- ·--- ----------·-- ... - -- ~. ----------- --·
I
2H
30
multi vibrator. To produce the phase difference, the
F
0
~ultivibrator
with
as its output was triggered by the leading edge of the phase-"locked-loop
outputpu] ses and the multi vibrator to have F as its output was triggered by
the trailing edge of the phase-locked -loop. This circuit is shown in Figure 17.
Again the approximate value of the components that govern the pulse were
approximated from the graphs found in the data sheets and then these values
;,vere adjusted until the one p.s pulse width was achieved on the breadboard.
The
10
1~'
!YHl
0 and F outputs were required to be able to interface with a
nu.ximlli~l
loac1, so switching transistors were used as interface elements, because
the ClVIOS outputs would not handle that current.
The remaining po1·tion of the 1A26 module to be designed was the
frequency selector. The frequency selector has <.;even control inputs and
seven dal::t inputs. There Is one outp;rt from which the selected frequency ls
--
taken. The output would be a 50% duty cycle pulse train of the selected fre-quency. The output would go to another board through the module connector.
Thts other Elodule is known as the the doppler shift m.odule, the operation of
which is irrelevent here, except for its input requirements. The operation of
the frequency selector is
~letermil~ed
by the control inputs. When one of the
control inputs is taken to a logical one, the data inpllt associated with that
control line is connected to the output of the selector. The cir.cult for the
fl'(lquency selector is shown in Figure 18. Again the interface between the
frequency selector and the following module is a switching transistor.
Finally the Lt\26 phase·-locked oscilhtor board was built as a prototype.
\1
o-0\}
T'f!!T
FP..ON1 _Et\ASE-LO.CI)~p- l£2QP~--~---
r
.__
~--·-·-~
.
r--·~
i
.
4.7 K.O....
II.
. --1
I . i=
~---~
-£
I
.
I l'
I
---~--~-1
I l --,
j_..__j_
____
II
.
I
.
-~
I
N\C l"i-52.8 AL
DIJAL
.i.~ I
I(})
I
1
·-.
~l
· "Ts-r•
l
I•
-------·1. .I!
-/v'\/V'---J
4.7K.n..
'if::.__...tvv
f5
hr\otJ·,~:rA&LE
.
~I TJT-l.I
4:TK.J.
t-~·
'
.
1
1
I I
j_i_1
'"i..r
I 7
~
\
K"""
!
I . -~~0
j
.
4.7 t<.n.
v·
-+----J;w'--l~
l
J
.
.
·t
---'-
Figure 17. Schematic Diagram of Dua:i. Monostable MultiYibra.tor Design
,_Cv
.
o
tt~l'J'TR.o!..
PATf4
I'N PuiS
(!-Jt>"t f'.IE'£1)C:!))
ci!-_,_CI
co N...,....,".Ol. 4r"''r}
-I /1
L_f
v
_ r-"-<~ ~
I
flJ
;tee"'~~'.y.J r-·vf
L../
I
I
·
·--
/
v
I
!
I
1
·r 3 .c <eN7~- f"\
o-----::::::.).,,-1
'o' "
L-·
-
'
;-· .~-·J
-rl•l
D..:.._
"t,?c"
-1- ;~10
'2
j
II
l,
··.
.
.
-"
1----
r
· - - l,
I
I
I
·,
I
I
r· IL-:+-1~
I 1l
I
o
I'
6i
r-.:j!
'DATA O<JT
_IL
'
!
f-1
_j_
I .,
~-
l
..
I!
1
l-LJ
I ;·- '~
I l_i_...
I'II ~
. _.L
-
L_:..J'~--·--·-··. . ---· .
. _~--.~4....
L .
J
·I
I
,_.. ____ !
·
P" T A
Il'
(1)--- .::._
L
.
'
I
,.,.
J.
:!.·~--!
SElftToRL __.J_
4.7\-<.~IL./
LC!
,
c
--·-/Vv
1
I
I
I
o;;-
I
l
q·(\c !4-;, ! 2.
o-
-'3o
.
.
. "' ~ I, f"'..
l-,l \p--, Ii
1..- 1-h;
I I
:'2.o
Coio/r~Ol. r\/--·I Ir-i / i
. . . -~-·----i
'
(>--
r,_.,...--··--···•
. ·
,~ I
0
.
-4·20eo,,r.rROI.I'H',
.I'
OYe.<.
.,..,
.
'
.. ____J
Figure 18. Schematic Diagram of Frequency Selector Design
~J
t,;:
The prototype was environmentally tested. These test results are shown
in the appendix. The board functioned correctly once the prope;· power supply's
a. c. decoupling was provided. The decoupling consisted of one 15p.f capacitor
connected from V cc to ground. The decoupling was necessary to filter out
any power supply noise that might be present. This was extremely important
due to the high impedance of the CMOS inputs. The high input j_mpedances
make the CMOS device susceptible
~o
cu..rrent spikes produced in the povvm·
supply. It turned out that the power consumption of the newly designod board
was on the order of 40 milliwatts as compared to the 2. 25 watts power consumption of the original circuit, thus rnaking heat dissipation essentially
negligible. especially considering the power consumption of four modules.
Since the integrated circuits used were manufactured to military specifications
the new mod1.:le should be highly n:.Hohle s.t tho extren1e temperatures that
were originally encountered. This situation is very satisfactory, since the
new CMOS design should not let the.se extreme temperatures occur. This
improvement is due to the low power requiremants of,tho CMOS devices. The
environmental tests proved this design to meet the 1A2o spec!.fications vel7
easily. The printed circuit board artwork has 1:H:.en contr:lcted out for the final
production model.
The final circuit
Appendix C.
diagrs~m
of the entire 1A26 Oscillator SRA is shmvn in
I
CONCLUSION
I
I
Ii
In conclusion, the results of this project have proven the value of
environmental testing. Worse case eng-ineering has been taught to some
degree in -Lmdergradmtte engineering schools, but this concept has in many
cases, fallen son1.ewh:::t to the way side.
The over confidence in standard
physic9J relationships, equations and classical theory has taken its place.
The philo,::;ophy of the environmental testing done in this project was to place
the new designs into the worse possible environmental conditions that they
may be subjected to. But, this philosophy was not overdone by overtesUng
in irrelevent conditions. Without environmental ten:1perature testing, the
design flaw :in the first m.essage matrix desig11 may not have been discovered.
However in the
ph~1.sed--loeked-loop
i
oscillator ooarct the environmental
temperature testing gs:?e credibility to the desigr1 and verified its operation
under conditions tlnt the CMOS chips used would correct. This engineering
philosophy should greaFy increRse the re1i2.bility of engineering design.
li
!
i
. .---·---" ........ - - · ·-·----·---· .,_._____,__ -·-------------·---------·-·----·-·-----·-----------·--------·-· . . --·--·-·-··----·-·---·--..------·------· -- ---------.. ..J
34
-- ------ ---------' ·--------· '""' ·-· ----------------- -----------------------..------»-----------
--------------~
I
I
APPENDIX A
TEMPERATlJRE TEST PROCEDURES
35
36
TEST PROCEDURE
1A26 OSC 2
9, 10, 11, a.nd 12}.
Observe no meter deflection.
A~3.
2.
Check pins 3, 4, 5 and 20 for lock condition. Record in Table
3.
Check mid record in Table A -4 frequency, jitter, pulse amplitude and
pulse width at pins 21, 22, 18, 17, 11, 15, C and lG. Compar;J with
Table A-1.
4.
Check pin D and record frequencies in Table A-5 as DOPPLER SHIFT
switch is changed through
l
30. Compare with Table A-·2.
r::::-:---~.,
Pin
Frequency Jitter Pulse amplii:ude 1 .Pulse width·
(khz)
J
{J\s)
(ns)
(V)
--4------·-·
~·
21 (FB)
17'.7.76
22 (FBO)
177.76
18 (FC)
179.52
..
<:: 100
.A~.t.5
..
i
1 :t . 2
I
l
!-
i
17 (FCO)
179.52
11 f.F'E)
183.04
15 (FEO) I
183.04
C (FD)
181.28
~6 (FD~l
181.28
.....
..._---..,_·
l
l
-..v
_l
l
I
t
----'-~~~~~J
!
I
l
;
l
!
- I-
3?
-~---~-·-·----"
•. ·------··--···-· ..
··-··-··-·-··-~
·---..........................
~
~-······
................
~------·----·--
----·-··---....
~----------~-
I
L
.
.
Doppler shift Frequency Pulse amplitud:l Duty cycle
.
(khz)
(V)
(%)
--
0
.I
181.28
--··------·-·-----·-··1
I
TABLE A-2
II
!
I
2:!:1
50
I
!'
'
1
i
lI·
i
Ii
-10
183.04
-20
184.80
-30
186. tiS
·HO
179.52
~20
177.7G
I
I·
38
1A.26 OSC 2
TEMPERATURE 30C
_1. LTTG self ..-test: OK
2. Lock condition:
I
TABLE A-3
I
l
~-~n-•-Sp_i_k_e <~._:ttio~__
3
< 400
I
4
<400
\
I
I
I
!
5
(400
20
< 400
I
TABLE A·-4
......,--.........,,..--------......--·------=<
~--
Pin
Frequen;:~y
(t\S)
21
176.762
<..75
2.7
-f--·
I o.s
22
176.762
(75
3.0
0.8
18
179.520
(75
I
,
17
1'79,522
(GO
1
{?5
11
15
183.040
<75
I 181.280
{75
18'1.280
(90
1
L
~fitter J PLlise amp II Plllse width
Ody•'
l
'·")
j
I
(V)
3.
o
..
') '7
~
(J.ts}
I
1.0
0.9
i
3. 0
1.0
I
s. o
0.9
t!
3.0
o. 9
J
l 08
-·~-·-~--"'--·L~___L,__~--~.
C)
5
1
I
DATA SHEET
1A26 OSC 2
1.
LTTG self-test: OK
2.
Lock condition:
TEMPERATURE 55 C
I
TABLE A--6
Pin
Spike
condition
(ns)
-·
3
( 300
4
< 400
5
< 400
20
< 400
I
r
!
TABLE A-7
I
r~JjJ;::.~~:ncy ~tte~:j-;ulse a~T~;;s~vidth
I
.
(khz)
(ns)
1
(V)
<p.s)
~
o.s
21
r~76.762
<75
22
176.762
<75
I
3.0
0.8
,
3.0
1.0
3.0
0.9
-J.tl
l'i9.521
:7 5
17
179.521
50
11
183,0·10
<75
1,.
2.7
1.0
15
133. 0 110
<7 5
,
3.0
0.9
181.2so
<75
3.o
o.9
c
I
!!
I
l!
l
L:_~ J.m~2so.-ll.-~-9_o---ll__~s- _ J
•• •·
~,....,,_~~ ~·-·-•·-·•·--w•"-·~---~·-
•
••~·-~----~~-------~·---·-~·--~ ---~-------··-•••-"""-- ~-·~-z~~~·~-----·--·~~---·-·-...- -·•~ -·---~~
·-----------·'
I
41
TABLE A-8
-
- r
--rr------,.-----~..,
I
Doppler shift I Frequency Pu.lse amp Duty cycle
(%)
(khz)
(V)
I
0
r----1-.-7--4----5-0----~
-10
181.042 1
-20
184.802
-30
186.560
-t10
179.520
... 20
177.762
+30
176.002
I
l
181.284
~--·-
i
l
I
~j___~J
I,.
i
i
!
I
i
!l
rl
!
i
I
I
l~-·-• '"~'~"' --··-·---~·•••· --···~-- ••·-.-·---•••----~-.·-~---·--·- -~---~--·~-- ~-····---...-----------~---· -~------ ---~--~-·----~~~------·--~-------M------· ~~J
J
DATA SHEET
. 1.
2.
1A26 OSC 2
TEtv1PEHATURE 71 C.
l
l
I
LTTG self-test: OK
Lock condition:
TABLE A-9
Pin
Spike condition
(ns)
3
<.500
l
4
<400
I
5
< 400
I
20
<400
l
i
~
l----~~------------~
TABLE A-10
r
l
:-r---~
Pin Frequenc.)
(khz)
i JHter l Pulse
(:1s}
I
t--
1
an1p 1P_- ulse wi.dtl_'(V)
y,.s) _ _
21
176.'764
(90
3.0
0.8
22
176.764
<90
3.0
0.8
18
179.521
<90
3.0
1.0
I'
179.521
(90
2.7
0.9
nl
183.041
<90
3.0
1.0
15
183.041
(90
3.0
1.0
c
181.280
(90
3.0
0.9
,.L.7
L 16
I
.
L18~::__<_9_0_......__2_._5_l_:__j
.
TABLE A-ll
-
I
.
Doppler shift Frequency Pulse amp Duty cycle
(khz}
(V)
(%)
-
~t--·.
0
181.281
2.0
50
-10
183.042
-20
184.801
I
-30
186.560
I
+10
179.522
-to 20
177.760
+30
176.002
I
1
l
!
\I
I
l
I
Ii
,.
l
I
I
i
I
i
i
I
I
I
. --L__ -----\
I!
I
i
I
iI
1-~.><<~-~----~-·----:·-~·-" ~·---·· --~ •-•:·-:•~--·-•--~-~..,.· ~ -·--·~--··•··-._......,...---·~-~--- ,-•--M~--~--~ ·---:--··~---·~~-------.-.-~-------~---···-:---~---~--~!
DATA SHEET
osc
1A26
2
TEMPERATlJRE 85 C
1. LTTG self-test: OK
2.
Lock condition:
Pin
I. S:~e
condition
{ns)
._,,_~-----!1
·---·
:I
<500
5
<400
~w
< 1:00
TABLE A·-13
-.,.-------,.-------Pin Frequency !Jitter Pulse amp
1
.
(ld1z)
(ns) ~L
(J"s)
~·-~·---·-.---r
3.0
0.8
(90
3.0
0.8
179.521
<90
3.0
1.0
17
179.521
(90
3.0
1.0
11
183. Otl:O
<90
3.0
1.0
15
183.040
3.0
c
181.280
3.0
16
181.280
21
177.760
{90
22
177.7GO
18
(90.
l
I
I
2.5
I
l
l--l------J.-----~L____
1.0
.9
.9
I
___j
45
TABLE A-14
Doppler
shi;;l F~·equency.! Pulse a.1~pf~uty cycle
(khz)
(V)
(%)
----~
0
181.281
-10
183.042
-20
184.801
-30
186.560
+10
1'79.522
-t-20
l .
30
l
177.761
I_ 176.002
_ _ _ __.f4. _ _ _ _
2.0
,II
50
46
···-··· ...... ' --------···-- '' ---............. -....................................... ··---·-----,.............. '--------------·-,·---··· ------------------------·-----------1
~-
1A3 MESSAGE MATRIX
ENVIRONMENTAL TEST
'I
I
1. The message matrix was tested at the temperatures listed below using the
l
j
!
i DTTG self-check feature of the test set. The DTTG self-check compares the
outputs of the message matrix with the outputs of the self-check matrix. The I
test is a pass-fail test.
I
I
1--
1
First Design Test
I
-10 C -· Pass
I
j
i
30 C -
Pass
55 C -
Pass
71 C -
Pass
85 C -
Fail
: Second Design Test
Ii
I
'-10
c -
Pass
I.
30
c
Pass
I
55
c
Pass
71
c
Pass
85
c -
Pass
I
I
I
Ii
Il
I
I
I
!
j
r·---···---··. · -· ·.··-·----· -------··· . -··· --····- ·-. -·· .-.-···--....-· .· - . ··-·· ··--.. -· ...
i
I
I
I
APPE?:-wiX B
SCHEIVIATIC-I\'IESSAGE rilATRIX
APPENDIX C
SCHE1\1ATIC-OSCILLATOR 2 SRA
II.
!
I
7
3
4
5
I
6
I
2
1
REVISIONS
ZONEILTRI
DESCRIPTION
.I DATE I APPROVED
II
I I
D
[
I!. '> G;PI
13
:I'2,'
7
24-
)-T,_,_R~----r---':='l..L-----
L
r---------------~M~M~S~--<
L-
-
'" /}
fl
1
.
II
l
n
T I I
l
/2.
9
10
1/
s
01'15'! 72.
zS'
_;'l~ A
rT-:::i===l----._J-+_J-_
I
~i
M,._'-,..-",+-,z./,-+"-l,.-91---l-,8
I
I
t-H---,;;-J
1 B
I
-±-
4>
2.
l
Z/0
t-----,,;;l> O
~ E
u,
o
5
I I
-=-
'Z.o
!-:,,--;------'-"-'-''-',---<
12 C
DM5'f73
y
~
18
MMB
h7::---=-----------l..!.!.-MM~~"",---<
/0
I
IZ3'f567
111'5610
~~-----------~M,~M,~17---<
rs-
t9
••
w
M~b
/
<;.
M M 15
h~~------------~~---<
I"IM4-
v
IS
1
I
17
3
c
~I
c..'
·/
3
Mn
I
i
MM t2.
l
zz. >>---=s"'c"'<>'+"'--------.~'-'-iz
2I
11
5
2./
N
Zl
3
)-~~~bi~·S~<~ol~·~S~Co~3---=~--------~r= ~>---~i'~L
1
y
I
sr-
rJ
l2
1;91'1
-,...-----.
01
M>-~~~--~------------------4---------------~--~0,
• /( 7
l/
I
"
IM5hl()
I
'--t-11-1-+-+--;7='1"'
L
<7
MM ?2
/
MMeS'
/E.
4-
MT-'129
F
I
r.:--r
~
7
I'IM IO
D
s
MM 2lf
3
MM I>
B
o
II
*5,. . .
M1'\ 30
'-+-+-t--:,<Oiz c lJ
1..-.-1--1--:,;,rl D
'f
-.-----t--,,T.J,. E.
s
l..£1.!'
R9
MM
2.
t£1
I
MMZ• /
Z
MM
~~/
IOK
-
t8
'---IH-t-t--;,o-;i B
" -
MM ibB-,
..,_
E
I
: zz}-
/Zr-
'f6L__n._
II
12.1K
~l.'l.K
°5
3
~
I~~
RS
__________.____________________________,
TXM, DTTf!.
c l8
il
1' Z.1.K
t~l
l3
.--Hr---,,., D
3
,_~ £
-}1?.'5
3
10
Lh..--=-=---------'"''-"'i.L__...
K
'7
MM 2.
..., "
9
.-.-t-+-t-Hr-,::-t.
A
rVct.
o(
tMS6/0
~--------------------------------·------------D_T,_TG
METER
A
5
i=
(5
r--------r--'--__._ 4'~RE~Q=D~IR=U~DE=S~--~PAA~T~.N=O·~~--~NA~MTE~~J~~--~DT~~C~RI~PT~IP~N~~--~j~M~A~T'~L~l_oo~N~D~~~~M~IL~S-~_c
___
1--------l---------1
A
1--------!--------1
1--------1--------1
DM54DOJ
QUAD
2-
INPUT
2-INl'U.T
NAND
;\l>\Nt)
-1
MAT'L
/'
USED ON
NEXI' MSY
SPEC/
~------~------~CONp'
IIND-PIIR S9JO/l0 OtEV. 1-18)
8
DIOZQDC !NH AGU'ROOP
I
7
6
5
±
JNTERPRET DfjAWING PER MIL·D-1000
APPUCATION
t
4
I
NAVAL MIss I LE
N.T
:-+-----;
3 PLACE D~CfMALS
0-C
~lz_o_NE1
UNLESS OTHERWISE SPECIFIED~/ ~DE::S=IG=NE::::R:::-t-"'j"-'.:._...;;G"-'A::!.L:=.=.E__
I
DIMENSIONS ARE IN INCHES. /
DRAFTSMAN
P.Q 1
1"1 U G U_ , (A. ") 0 4 2
REMOVE BURRS AND SHARP ,(DGES. ~~~-'-f------------1---~~~~·-~~-~~~~;.;:~.;..;.:.:::.:~----1
TOLERANcES:
ANGLEy±
1-=·c::.:HE:,::cK.:::.ED'=':-·
FRACTIONS
/
±
MATL/PROC
2 PLAC.E DECII)!A'i.S ±
·J-::,s=TR"'ES'::S-:::ED::-~1-----------;
":-'ACH FINISH
''PROT FINISH
3
TASK EXEC
(EN
ER
~
SCHEMAT!C
DIAGRAM
MESSAGE
MATRIX
IA3
CODE/EXT
J.:
M>.::.:::PR::.:O~VE::D----------1
, 1ZE !CODE I DENT NOI.l DRAWING
(DESIGN
NO.
0
loCTIVIlYl
APPROVED
i'l:W~~tNG
SCALE
2
I
I
JSHEET
1
~
8
4
5
6
3
2
ZONE LTR
20
'
I.
Rio lOOK
R;:.l.:-;4/\
;I;o/\,A/\KI'---_.
1/oo
-~,.~~ll17:Q:60Q._..~SllT~RQO~SIE_~----------------+-1~---+-t--,
S!ll'
!o
~
.L.
I
'+{;
l:~tw~ K-
:;l
18J3
.
5
K
-=10op
R37
I K
•
c3 ...J
ISJAF
.:::t
=
..::-t-181/.'..DC
Q3
-2.00
Rl
V2. WATT"
r-4----<>! Vl>o
tl, .1J~
,I
~
l
1·7K
J2.
=
·... -30 COI>ITL.
M
"
lb
IN'ao?.O~
2:2..
F'8 PI-/liSE
~~q.;JI:.
~~it..:..:.ll.LI~2.=-----t•~""·-'-"F'-'=C~CIS~
+IOVDC
. /~F 'TCI J~ VRI
c
02.
_--4.7 K
..4.7K
?-
P
Cl
,--1
J_
l~oo K
~~@, rrR'I~ ,
13i/~~;;w;i~
R.lb
0\
t
1
REVISIONS
DESCRIPTION
.4.7K
)-~+=2.~0~C~ON~T~~~~4---------------,
~
.. V )-.::.-!,!iiO!.JC:<..!O~Nl:.LF-f-1--f.-----------,
CD4059 AD
I
N= 104
I
+ W COUNT£R.
i!l/
l/4-
,...,....,~,..,...,
I l
3
7
'3 I
I
R34
- 6X
LOOI-<o
>~
Voo
~
4.7 K
A7K.
'_v:~
L
13
~
-30 DSFH
;.,
-zo
CD4059 AD
Z:6 N=-10'3
D5FF
-':-N COUNTE:'R
.n~~,_,,-.,,-.,,-.
~,-.
OS SEL FREQ ( D
. I z, 3 4 5 6J'tiJl~~o/
Ja/.'2.6
~~~~
.._lJ_J._.11~1_--,
IL_-__..,_..
r'R.EQD
/.
1--------1-------J
1--------1-------J
·A
•
1.
I
REF DES
I
PART NO.
REMOVE' BURRS AND SHARP.EDGES.
ANGLE¥±
<QLERANCES:
FRACTIONS
/
2 PLACE DECIMALS
3 PLACE DE<liMALS
VB
±
±
±
INTERPRET DRAWING PER MIL·D-1000
WATT EXCEPT" ~HER.£
NAME
I
Sf'ECIF!Ifl>
CHECKED·
J-M::::A.::.J::Lf~PR_O_;C_-f-------1
STRESSED
N2'310/XSS17
APPUCATION
5
4
3
MAT'l
I
2
COND
I
~....:._
"
NAVAL MISSILI:.. CEN iTR
POINT
MUGU,
CALIF. 93042.
---~A
SCHEMA. 1\C DIAGRAM
OSC 2
TASK EXEC
CODE/EXT
I
DESCRIPTION
-J
1-------j---------j '
NOT£: ALL R£51STAfJCE5 ARE' IN OHMS AND ARE
I
UNLESS OTHERWISE SPECIFIED:_/J.:D~E:::SI:::GN:::E::.:R::+...;JoL;·C..:G~·~A~Lf;:,~_ _
DIMENSIONS ARE IN INCHES, /
DRAFTSMAN
IA26
50
BIBLIOGRAPHY
: Dietmeyer, Donald L., Logic Design of DigitalSystems, Allyn and Bacon,
Inc., c. A71, Pages 429-550.
: Gardner, Floyd M. , Phase lock Techniques, John Wiley & Sons, Inc. ,
Nevv York, Londo;:si'd~ Z1966~
Intersil, "Bipolar Read-Only-Memory", IlVi5610, Data Sheet, c. 197 4.
.Di7-ital. Integ;rsted
------ Circuits,
Motorob, MeMos IntegTated-Circuits .....Data
____ Book, c. 1973.
~~-·
----~
National Semiconductor,
c. 19'73.
-~-
;;;;...
-.---......
~
Circuit Data Manual,
I
l
l
I
l
I
I
!