CS150
Week 2, Lecture 1
Covers:
1)
2)
3)
4)
1)
Memory
S-R Latch
Level sensitive latch ( Clocked S-R Latch )
JK Latches
Memory
__
LD
Circuits:
1
LD
__
LD
__
LD
LD
0
0
LD
1
EN (Enable)
Timing:
A
B
C
D
A 1
0
B 1
0
C 1
0
D 1
0
Time
One gate
delay
???? Note: For 30 MHz  0.5ns transistors ( gate delays ).
2)
S-R Latch
__
Output: A
0 (Zero)
Input: A
Note:
S
R
If S=0 and R=0 then
circuit is just:
S-R Latch:
R
Q
_
Q
S
R=1 Q=0
S=1 Q=0
R=1
S=1
Q = ??
Q = ??
S-R Latch rewritten:
R
Q
_
Q
S
R
1
0
S 1
0
Q 1
_ 0
Q 1
0
Time
One gate
delay
Illegal transitions…
1
0
0
0
1

S0
R0
0
0
0
0
1
1
0
Cycles without change in input values.
Therefore: 11 not allowed as an input.
S-R Latch with NAND gates:
R
S
R
Q
_
Q
Q

S-R Latch with NOR gates.
_
R
_
Q
S
Bubble push

_
S
_
Q
_
Q
3)
Level sensitive latch ( Clocked S-R Latch )
R
Q
_
Q
S
CLK
Unclocked S-R Latch ( Notation slightly different in Katz )
R
S
S
Q
R
_
Q

Same thing as:
Enable
S
R
S
Q
R
_
Q
Enable
S
Q
R
_
Q
Q
S
_
Q
S
Q
R
_
Q
Q
_
Q
R
Enable
S
0
0
0
0
1
1
1
1
4)
R
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
1
0
0
1
1
?
?
HOLD
S
*
0
0
1
1
RESET
SET
R
*
0
1
0
1
Q
0
1
1
1
1
Q+
Q
Q
0
1
?
FORBIDDEN
CLK
JK Latches
J
J
S
R
_
Q

J
J
0
0
1
1
K
0
1
0
1
Q+
Q
0
1
_
Toggle ( Q )
Q
R
_
Q
Q
K
K
S
J: Jam a 1 into Q
K: Klear value in Q
K
Enable
Q
_
Q