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Fabrication of nanowires on orthogonal surfaces of microchannels and their effect on pool
boiling
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2012 J. Micromech. Microeng. 22 115005
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IOP PUBLISHING
JOURNAL OF MICROMECHANICS AND MICROENGINEERING
doi:10.1088/0960-1317/22/11/115005
J. Micromech. Microeng. 22 (2012) 115005 (9pp)
Fabrication of nanowires on orthogonal
surfaces of microchannels and their effect
on pool boiling
Zhonghua Yao 1 , Yen-Wen Lu 2,3 and Satish G Kandlikar 1,3
1
Microsystems Engineering Doctoral Program, Rochester Institute of Technology, Rochester, NY, USA
Department of Bio-Industrial Mechatronics Engineering, National Taiwan University, Taipei, Taiwan,
Republic of China
2
E-mail: [email protected] and [email protected]
Received 21 May 2012, in final form 7 July 2012
Published 25 September 2012
Online at stacks.iop.org/JMM/22/115005
Abstract
A novel microfabrication technique was developed to create silicon nanowires (SiNWs) on
orthogonal surfaces of microchannels machined on top of a silicon wafer. Using a two-step
metal-assisted etching process, the SiNW for the first time could be selectively fabricated on
two different crystalline directions—the channel top and bottom surfaces oriented in the (1 0 0)
direction while the sidewall surfaces in the (1 1 0) direction. Different SiNW etching conditions
were investigated to get the optimal height, density, morphology and orientation for the SiNWs
on the microchannels. The resulting samples were tested as heat sinks with water for their pool
boiling applications. The sidewall SiNWs affected bubble behaviors and played important roles
during the boiling process. The critical heat flux and the heat transfer coefficient both were
thus improved compared to a plain silicon surface and a silicon chip with only microchannels.
(Some figures may appear in colour only in the online journal)
1. Introduction
However, only a few studies have addressed the
surface property of the microchannel interior walls, mainly
due to the limitation of the microchannel fabrication [6].
While it is known that both topological and chemical
properties of the surfaces play a critical role in determining
the surface wettability, the recent advancement of hybrid
micro/nanofabrications provides us a powerful tool to study
and exploit many surface phenomena [7–10]. In particular,
the nanoscale modification on surface topology has been
increasingly of interest to improve heat transfer performance,
due to (i) better durability (ii) finer control over porosity
and surface roughness and (iii) thinner coating layers, which
offer lower thermal resistance and thermal stresses [11–15].
Significantly higher pool-boiling heat fluxes have been found
on nanostructure-coated substrates against bare substrates
[15, 16].
Among the nanoscale topological techniques for surface
modification, a high aspect ratio silicon nanowire (SiNW) has
attracted great attention for its application in heat transfer
enhancement. The SiNWs create additional cavities, which
provide more active bubble nucleation sites, with increased
As continuous miniaturization of microelectronic components
urgently demands an efficient cooling technique, utilizing
microfabrication techniques to make microchannels as a heat
sink for boiling heat transfer has proven to be an effective
means of dissipating large amounts of heat from small surfaces
[1, 2]. The microchannels provide a combination of small
flow passage, large heat transfer area and efficient boiling
heat transfer. Such a combination can produce very high
heat transfer coefficients (HTCs) with low space requirement.
Although the technology to make microchannels at this scale
is currently feasible, design considerations are intertwined
and usually involve (i) geometric constraints (e.g. crosssectional shape), (ii) surface properties of channel walls and
(iii) fabrication complexity. Heat sinks with simple
rectangular, semi-circular, triangular, or trapezoidal channel
shapes have been extensively studied [3–5].
3
Author to whom any correspondence should be addressed.
0960-1317/12/115005+09$33.00
1
© 2012 IOP Publishing Ltd
Printed in the UK & the USA
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
heat transfer area through thermal pin-fin effect; thus the
boiling performance can be promoted. The SiNW-coated
substrate has been shown to efficiently remove large amount
of heat [17, 18]. A recent pool boiling heat transfer study with
SiNW-coated silicon substrates suggests a 100% enhancement
in both critical heat flux (CHF) and HTC, compared to the
same test with the plain surfaces [18]. However, to create the
SiNW on the microchannel interior walls is a challenging task.
Although methods have been developed to fabricate the SiNW
on flat surfaces using top-down or bottom-up approaches
[19–21], it is comparatively difficult to grow the SiNW on
the different surfaces of the microchannel walls with various
crystallographic directions. Therefore, this work attempts to
address this challenge by developing a two-step metal-assisted
electroless etching process. Our technology enables the growth
of the SiNW on orthogonal surfaces of the microchannels—
top, bottom and sidewall surfaces. The vertically aligned
SiNW on the (1 0 0) surfaces and the uniformly oriented
SiNW with the same inclined angle on the (1 1 0) surfaces
are demonstrated.
Further evaluating the effect of the microchannels with the
samples fully covered by the SiNW, a complete pool boiling
profile was developed. The boiling characteristics of three
sample types of (i) silicon microchannels, (ii) microchannels
with the SiNW on the top and bottom surfaces, and
(iii) microchannels with the SiNW on all the surfaces (top,
bottom, and sidewalls), are compared. To the best of our
knowledge, it is the first time to study the pool boiling
heat transfer of silicon microchannel embedded with uniform
SiNW structures on the entire surface area.
(a)
(b)
(c)
(d)
Figure 1. ((a) and (b)) Microchannel fabrication process flow and
(c) and (d) SiNW synthesis.
2.2. SiNW synthesis on the Si microchannels
Different from a flat silicon surface with only one crystalline
orientation, the silicon microchannels involve multiple
crystalline directions. For example, the channel interior walls
of a microchannel, made on a (1 0 0) silicon wafer, have the top
and bottom surfaces in the (1 0 0) direction, while the sidewall
surfaces in the (1 1 0) direction, as shown in figure 2(b).
To create a uniform SiNW on all the surface area of
the microchannel, a two-step metal-assisted etching process
targeted at two orthogonal crystalline directions has been
developed as depicted in figures 1(c) and (d).
2. Experimental methods
2.1. Microchannel fabrication
To create the silicon microchannel heat sinks as shown in
figure 1(a), a (1 0 0) p-type silicon wafer (1–3 cm) was
first cleaned with Piranha, containing H2SO4 (97%) and
H2O2 (35%) at a 3:1 volume ratio, and HF solutions to
remove organic residues and native oxide from substrates,
and then rinsed by deionized (DI) water. The wafer was
dehydrated at 150 ◦ C. A 6 μm thick photoresist (SPR220,
Megaposit) was spin-coated (WS-400BZ-6NPP, Laurell) on
the silicon wafer and then used as the masking material
for the silicon etching process (figures 1(a) and (b)) to
define the microchannels. After the wafer was soft baked, the
wafer was photo lithographically patterned by using the mask
aligner (EVG620, EV Group), developed in TMAH, and hard
baked. The sample was anisotropically etched by using the
inductively coupled plasma (ICP) machine (MESC Multiplex
ICP, STS). After the ICP process, the probe-type surface
analyzer (ET4000A, Kosaka Laboratory Ltd) was employed to
confirm the microchannel geometrical dimensions as designed.
The wafer was then diced into 20 × 20 mm2 chips by using
the dicing saw (DS-150 II, Everprecision). The remaining
photoresist was removed. Fifty 10 mm long parallel channels
with 100 μm fin width and spacing were therefore created at
the center of 20 × 20 mm2 chips, as schematically shown in
figure 2(a).
2.2.1. Fabrication of the SiNW on (1 0 0) surfaces of the
microchannel. To fabricate the SiNW in the microchannel
interior surfaces, the first step is to promote the SiNW
formation on the (1 0 0) surfaces (figure 1(c)). The
microchannel chips obtained from the previous step were
cleaned by using the Piranha solution and then by using the 5%
HF solution to remove the organics and native oxide layer.
Once cleaned, the chips were immediately immersed into
the etching solution consisting of 4.8 M HF and 0.02 M
AgNO3 at room temperature for SiNW synthesis in the
1 0 0 direction. This 1 0 0 SiNW synthesis is based on
the galvanostatic reaction between Ag+ and silicon [22, 23].
Since the electrochemical potential of Ag+/Ag was higher
than Si/Si4+, holes were injected into the valence band
of silicon from Ag+. The Ag+ was reduced into Ag
nanoparticles and deposited onto the silicon surfaces. As this
reduction proceeded, the Ag nanoparticles aggregated into
large particles. Simultaneously, the holes injected into the
valence band of silicon via Ag nanoparticles facilitated the
2
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
(a)
(b)
Figure 2. (a) Microchannel dimension, (b) internal channel size and silicon crystalline direction of the microchannel made on a p-type
(1 0 0) wafer.
(a)
(b)
(c)
(d)
Figure 3. SEM images of the (1 0 0) surfaces in sequence during first step etching: (a) after 15 min etching, (b) after 30 min etching, (c) after
45 min etching and (d) after 60 min etching.
oxidation with dissolution of silicon atoms underneath the Ag
particles. Silicon was locally oxidized into SiO2, which was
then dissolved by HF, following the reactions [24]:
Ag+ + e− → Ag
(1)
+
−
Si + 2H2 O → SiO2 + 4H + 4e
SiO2 +
2HF−
2
+ 2HF →
At this stage, the formation of the SiNW occurs on the top
and bottom surfaces of the microchannels at the (1 0 0) planes
because the charge transfer preferentially occurred at the
interface between the silicon and deposited Ag nanoparticles.
As evident later in figure 5(a), the sidewall surfaces were
barely affected because no Ag particles were deposited. In
addition, since the oxidation and dissolution of silicon atoms
on a substrate surface were required to break the back-bonds
between the atoms on and underneath the surfaces, removing
atoms from the surface proved difficult. As the number of backbonds of a silicon atom on the surface was determined by the
crystallographic orientation of the substrate, the etching rates
were different on different surfaces. On the (1 0 0) surface,
each atom has two back-bonds, while on the (1 1 0) or (1 1 1)
surface, an atom has three back-bonds [25]. Due to the different
bonding strength, the atom on the (1 0 0) surface was the most
easily removed, with etching occurring preferentially along the
SiF2−
6
+ 2H2 O.
(2)
(3)
These reactions selectively took place in the region
where etching had already initiated. As a consequence of
this selective growth of holes throughout the surface, the
remaining structure became vertically aligned SiNW arrays.
Figure 3 illustrated the sequence of the bulk silicon at the
(1 0 0) surface gradually etched into an array of SiNW along
the 1 0 0 direction. The average height was about 15–20 μm,
with a diameter of 50 nm, after 60 min etching time. The
surface cavity, formed in between bundled SiNWs, meanwhile
increased as the etching time increased.
3
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
(a)
(b)
Figure 4. SEM images of (a) SiNWs starting to form on the microchannel sidewall after a 30 min etching by the H2O2:HF solution in a
1:5 molar ratio and (b) smooth fin surface after 60 min etching by the H2O2 :HF solution in a 2:1 molar ratio.
Table 1. Effects of H2O2 concentration on sidewall morphology at the second step etching.
Molar ratio of H2O2:HF
Etching time and temperature
Sidewall structure
1:5(0.96 M H2O2 + 4.8 M HF)
1:2
(2.4 M H2O2 + 4.8 M HF)
2:1
(9.6 M H2O2 + 4.8 M HF)
30 min of etching at
room temperature (20 ◦ C)
30 min of etching at
room temperature (20 ◦ C)
60 min of etching at
room temperature (20◦ C)
Non-uniform nanowire structure formed
at certain areas of the sidewall (figure 4(a))
Uniform nanowire structure formed on
the entire sidewall surface (figure 5(c))
Entire surface etched off, no nanowire
structure found at any location (figure 4(b))
1 0 0 direction, thereby resulting the SiNW formation only
on the top and bottom surfaces. The SiNW density and height
were controlled by the HF concentration, reaction temperature
and etching time [25].
the amount of generated holes (h+) exceeding the threshold,
silicon atoms will be rapidly removed in the crystal planes
where there will be more silicon back-bonds to polarize (such
as (1 1 0) and (1 1 1) planes). This will result in different SiNW
etching behaviors—a faster etching rate in 1 1 0 direction
than 1 0 0 direction [29].
Therefore, a solution containing HF and H2O2 was
prepared to form [1 1 0] SiNW. The silicon microchannel
chips, which have [1 0 0] SiNW on the top and bottom surfaces,
after the first etching step, were immersed in the etching
solution for sufficient time.
To obtain uniform SiNW structures on the sidewall,
different recipes, as listed in table 1, were investigated. It
is found that the sidewall morphology was greatly affected
by the H2O2 concentration at a given concentration of HF.
The SiNW structure, as shown in figure 4(a), started to form
at certain locations of the sidewalls when the molar ratio of
H2O2:HF is larger than 1:5. The ideal molar ratio for creating
uniform sidewall SiNWs was between 1:5 and 2:1, because
H2O2 at higher concentrations may completely etch off the
SiNW structure, leaving smooth fin and channel surfaces, as
shown in figure 4(b). In this work, the solution was prepared at
4.8 M HF and 2.4 M H2O2; the etching duration was controlled
within 30 min at room temperature. Longer etching duration
was not preferable since it may result in significant reduction
of the microchannel fin width.
After this second etching step, the chips were cleaned
with DI water and then placed in the dilute HNO3 solution to
dissolve the Ag catalyst. [1 1 0] SiNWs were then revealed in
the microchannel sidewalls. The chips again were washed with
HF again to remove the oxide layer and then cleaned with DI
water and dried.
2.2.2. Fabrication of SiNW on (1 1 0) surfaces of the
microchannel. Recent studies on microchannel heat sinks
suggest that sidewall structures play considerable roles in
laminar flow and heat transfer [26–28]. Therefore, the effect
of the sidewall SiNW structure on microchannel pool boiling
heat transfer is another focus of this work.
To grow an SiNW structure on the microchannel sidewall,
the etching mechanism of silicon at different crystalline planes
was investigated. It is found that the etching direction of
silicon of a given crystal orientation could be changed by
altering etching conditions to yield arrays of the SiNW with
different axial orientations [29]. Therefore, to create an SiNW
at the sidewall area without affecting the structure in other
areas, the H2O2 solution was introduced in the second step
etching. Since the etching of Si atoms is a net consequence of
injection of a positive hole (h+) into bulk silicon and removal of
oxidized silicon by HF from underneath the Ag nanoparticles,
the etching rate is governed by the interplay between the two
processes.
Since the amount of holes (h+) injected into silicon can
be controlled by the H2O2 concentration and decomposition
activity, the process of catalytic decomposition of H2O2 will
determine the etching rate at different planes. Basically, at low
H2O2 concentration, the hole (h+) injection into silicon atoms
will locally occur at the (1 0 0) plane, as the (1 0 0) plane has
the fewest back-bonds to break, resulting in etching along the
1 0 0 direction. When the H2O2 concentration increases with
4
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
(a)
(b)
(c)
(d)
Figure 5. SEM images of the top (1 0 0) surface and sidewall (1 1 0) surfaces during the second SiNW etching step in sequence: (a) before
etching, (b) after 15 min etching, (c) after 30 min etching and (d) after entire etching process.
Table 2. Recipe of the SiNW synthesis process adapted in this study for boiling tests.
Etching process
Formulation
Temperature
Duration
Etching rate
Targeted surface
First step etching: 100 mL aqueous
solution of 4.8 M HF and 0.02 M AgNO3
Room temperature
(21 ◦ C)
60 min
0.3 μm min−1
(approximately)
(1 0 0) surfaces:
top and bottom areas of microchannel
Second step etching: 100 mL aqueous
solution of 4.8 M HF and 2.4 M H2O2
Room temperature
(21 ◦ C)
30 min
0.5 μm min−1
(approximately)
(1 1 0) surfaces:
sidewall area of microchannel
incorporated with microchannels, this SiNW fabrication can
further expand onto the applications of nanostructure in
advanced heat and mass transfer devices, not limited to the
flat substrates.
Finally, the two-step etching process adapted in this study
for the following boiling test is listed in table 2. The etching
rates at different steps were calculated based upon the final
SiNW height and the overall etching duration.
Figures 5(a) and (c) show in sequence the formation of the
SiNW structure on the sidewall surfaces of the microchannels
during the second SiNW etching step. The formation of the
sidewall SiNW took about 30 min of H2O2:HF etching, without
affecting the existing SiNW structure on the top and bottom
surfaces. The average height of the as-grown [1 1 0] SiNW was
between 10 and 15 μm. The SiNWs were slightly inclined to
the (1 1 0) surfaces and shorter than SiNWs grown on the (1 0 0)
surfaces due to the shorter etching duration. After the two-step
etching process, uniform SiNWs were created on the entire
surface area of the microchannels, including top, bottom and
sidewall surfaces, as shown in figure 5(d).
The successful SiNW fabrication on the designated areas
of the microchannel interior walls indicated that the metalassisted electroless etching was capable of creating uniform
SiNW on silicon-based three-dimensional geometry by
applying different etching conditions for different crystalline
directions. This two-step SiNW fabrication technique makes
itself more advantageous than other approaches of creating
nanostructures on geometrical confined surfaces because of
its simplicity, controllability and low cost. In addition, when
2.4. Boiling test setup
To study the effect of SiNW on boiling heat transfer through
microchannel heat sink, an experimental setup in figure 6
was employed [17]. The sample surface characterization is
summarized in table 3. The microchannel depth, width and
height were measured before the SiNW synthesis processes.
The 20 × 20 mm2 test samples were mounted on an
insulated and sealed copper block. Gasket cover was used to
ensure the direct contact of working liquid with targeted area
(10 × 10 mm2). A 450 W capacity cartridge heater served
as the major heating element. Three K-type thermocouples,
5
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
(i )
(f)
(e)
( j)
(h)
(k)
(d)
(g)
(c)
(b)
(a)
Figure 6. Schematic of boiling test fixture. (a) Cartridge heater, (b) ceramic block, (c) test chip, (d) gasket, (e) polycarbonate visualization
tube, ( f ) auxiliary heater, (g) K-type thermocouples, (h) data acquisition system, (i) compression screws, ( j) high-speed camera and (k)
power supply.
Table 3. Summary of microchannel surface parameters.
Characterization of microchannels
(before SiNW synthesis)
Channel length
Channel/fin width
Channel height
Channel number
10000 μm
100 μm
100 μm
50
Characterization of heated surface
Heated surface
Thermal conductivity
Heat surface area
Heated surface thickness
Silicon
104 W mK−1
10 × 10 mm2
450 μm
placed along the axis of the copper block, were used to measure
the temperature gradient through the top of the heater. The
thermocouples were 8 mm apart and the first one (T1) was
3 mm below the top copper surface. DI water was used as the
boiling liquid. Sufficient time was given to remove dissolved
air before commencing the test. An auxiliary heater (100 W)
was used to maintain the water temperature in the reservoir
under the saturation condition. The temperature of water was
monitored by a K-type thermocouple (T4). After water was
kept at the saturation temperature for 30 min, the main heater
was started and the power was increased in small increments.
A Labview program was employed to monitor the temperature
variation, and to determine when the system reached steady
state.
The heat flux was calculated from the following equation:
dT
(4)
q = −kcu .
dx
The temperature gradient, dT/dx, was calculated using a
three-point backward-difference Taylor series approximation
as shown below,
dT
3T1 − 4T2 + T3
=
,
(5)
dx
2x
where T1, T2 and T3 are the temperatures measured by
thermocouples located at distances x = 8 mm. The
surface temperature of the microchannel, Ts, was obtained
by calculating the heat flux through the copper block, as
Characterization of SiNWs
NW height on (1 0 0) surfaces
NW height on (1 1 0) surfaces
NW diameter on (1 0 0) surfaces
NW diameter on (1 1 0) surfaces
15–20 μm
10–15 μm
50 nm
80–100 nm
well as the reading from thermocouple T1, from the following
equation:
LCu
LSi
,
(6)
+ Rt,c
+
Ts = T1 − q
KCu
KSi
where L and K represent material thickness and thermal
conductivity, respectively. Rt,c
represents the thermal contact
resistance of the interface, which is found to be repeatable at
5 × 10−6 m2 K W−1, with an uncertainty less than 4%, as
calculated in a previous study [30]. The wall superheat T is
therefore obtained by
T = Ts − Tsat .
(7)
The uncertainty analysis was conducted according to the
method proposed by Kline and McClintock [31]. The details
can be found in the previous study [4] for the same testing
assemble. Table 4 shows the uncertainty sources and values.
At low heat fluxes the uncertainty value comprises 20% of
the calculated value, while at the high heat fluxes it is only
slightly more than 4%. This is considered to be acceptable
because sample performance is evaluated mainly at elevated
heat fluxes.
3. Results and discussion
The boiling characteristics of (i) the microchannel sample
with SiNW on the all surfaces, (ii) the microchannel sample
6
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
[18]. In addition, the boiling enhancement is related to the
surface area covered by SiNWs, as suggested in figure 7. At
the low wall superheat region where only natural convection
heat transfer occurs, the microchannels with SiNWs on
the all surfaces have similar heat transfer characteristics
as the one coated with SiNWs on the top/bottom surfaces.
Once the boiling behavior reaches the nucleate boiling
stage, bubble dynamics is greatly affected by the sidewall
SiNW structures; the microchannels with SiNWs on all
the surfaces experience a dramatic heat flux increase as
the wall superheat increases. Moreover, the SiNWs on the
sidewall surfaces enhance heat transfer area, nucleation effects
and liquid transport resulting in an improvement in heat
transfer and critical heat flux (CHF). The surface cavities
in between bundled SiNWs provide great amount of active
bubble nucleation sites. The sidewall SiNW structure promotes
bubble detachment from the surfaces, intensify the flow
turbulence and therefore increase the HTC during the nucleate
boiling stage. All these factors contribute to the boiling
enhancement. At 24 K wall superheat, the calculated HTC
of the microchannel chip with SiNW on all the surfaces
is 69 kW m–2 K–1, thereby indicating a 42% improvement
against the surface without sidewall SiNW at the same
superheat region. This finding suggests that the boiling
enhancement induced by SiNW is directly related to the
area covered by SiNW, especially for the sidewall surfaces.
Finally, it is worth mentioning that the chosen microchannel
pattern and SiNW array configuration may not represent the
best combination for boiling heat transfer; optimizing the
microchannel configuration and SiNW parameters, the boiling
heat transfer performance can be further improved.
It is worth mentioning that the CHF values were not
obtained during the tests. Therefore, the maximum heat
flux values shown in figure 7 were lower than actual CHF.
The estimated CHF would be over 200 W cm−2 for the
microchannel with SiNW samples.
Figure 7. Boiling characterization of the samples: (i) microchannel
with SiNW on the all surfaces, (ii) microchannel with SiNW on the
top/bottom surfaces, (iii) microchannel without SiNW (or
microchannel-only) and (iv) plain silicon substrate.
Table 4. Uncertainty sources and values.
Source
Uncertainty
T-type thermal couple reading
Thermal conductivity of Cu
Thermal conductivity of Si
Surface temperature reading
Thermal contact resistance
Heat flux
± 0.25 K
± 2%
± 3.7%
± 4.5%
± 4%
± 2 kW cm−2 at lowest heat flux,
± 6 kW cm−2 at highest heat flux
with SiNW only on the top and bottom surfaces, (iii) the
microchannel sample without SiNW and (iv) the plain silicon
substrate (without microchannel) are depicted in figure 7.
The heat flux value was calculated based on the projected
microchannel area. The plain silicon substrate served as the
primary control for boiling performance comparison, with
results being consistent with experimental results previously
reported [32]. For the microchannel-only without the SiNW
sample, the maximum heat flux recorded is 110 W cm−2 at 35 K
wall superheat. By incorporating SiNW on the top and bottom
surfaces of the microchannel heat sink, the boiling incipient
wall superheat was found to be much lower than that on the
plain silicon substrate as well as on the microchannel-only
sample and the maximum heat flux reached 135 W cm−2 at
28 K wall superheat. When the entire microchannel surface
was covered by SiNW, significant enhancement was found
at intermediate wall superheat region, yielding a peak heat
flux value of 165 W cm−2 at 24 K superheat, demonstrating
an improvement of 60% over the microchannel with SiNW
on the top/bottom surfaces, 150% over the microchannel-only
sample and 400% over a plain silicon surface at given superheat
region.
The boiling test results suggest that the heat dissipation
ability of the microchannel heat sink through pool boiling
can be greatly enhanced by embedding SiNW. This result is
consistent with the previous study on SiNW on plain surfaces
4. Summary and outlook
This study demonstrates that uniform SiNW structures can
be created on microchannel heat sink surfaces by a two-step
electroless etching process. The pool boiling heat transfer with
water on microchannel surfaces can be significantly enhanced
by the nanowire structure and the enhancement is directly
related to the surface area covered by SiNW. The main findings
of this study are summarized as follows.
1. A two-step synthesis process is developed to create
uniform SiNW structures on the orthogonal surfaces of
the microchannels, including the (1 0 0) surface on the
top and bottom, as well as the (1 1 0) surfaces on the
sidewalls. The average height of the SiNWs is around
15–20 μm, with a diameter between 50 and 80 nm.
2. The SiNW synthesis mechanism indicates that uniform
SiNW can be created on the surfaces at their own
crystalline directions, with controllable morphology by
growing SiNW on the surfaces of the microchannel heat
sink for pool boiling applications; the total effective
7
J. Micromech. Microeng. 22 (2012) 115005
Z Yao et al
heat transfer surface area increases and the heat transfer
performance is significantly enhanced.
3. The microchannel sidewall structure directly affects the
boiling behavior, as the incorporation of SiNW on the
sidewall surfaces results in a 42% improvement in the
HTC compared to the microchannel sidewalls without
SiNW.
4. The current silicon microchannel with SiNW on all
surfaces yielded a heat flux of 165 W cm−2 at 24 K wall
superheat. This result represents a 400% improvement
over a plain silicon substrate at the same wall superheat;
it is the highest heat flux reported in the literature on pool
boiling with water on a silicon substrate.
[10]
[11]
[12]
[13]
[14]
Silicon is the most commonly used material in
the semiconductor industry. The metal-assisted electroless
etching method introduced here is simple and cost-effective.
This method can create uniform nanowire structures on
multiple surfaces with different crystalline planes of the
silicon microchannel in a two-step process. Utilizing the
microchannels with SiNW on all surfaces to study their pool
boiling behavior can provide a new insight into enhancing
boiling heat transfer more effectively. Furthermore, the
technique to incorporate SiNW and microchannel can be
applied for semiconductor cooling, thermal management and
high-heat-flux energy conversion applications at microscale.
[15]
[16]
[17]
[18]
[19]
Acknowledgement
We thank PC Kao at National Taiwan University for the
microchannel fabrication. The collaborative project has been
supported by National Science Council (NSC98-2218-E002023-MY3, NSC101-2221-E-002-080-MY2) and National
Science Foundation EPDT grant (# 0802100).
[20]
[21]
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